2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/delay.h>
16 #include <linux/err.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/slab.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
29 #include <linux/spinlock.h>
30 #include <linux/reboot.h>
33 #include "../pinconf.h"
34 #include "pinctrl-msm.h"
35 #include "../pinctrl-utils.h"
37 #define MAX_NR_GPIO 300
38 #define PS_HOLD_OFFSET 0x820
41 * struct msm_pinctrl - state for a pinctrl-msm device
42 * @dev: device handle.
43 * @pctrl: pinctrl handle.
44 * @chip: gpiochip handle.
45 * @restart_nb: restart notifier block.
46 * @irq: parent irq for the TLMM irq_chip.
47 * @lock: Spinlock to protect register resources as well
48 * as msm_pinctrl data structures.
49 * @enabled_irqs: Bitmap of currently enabled irqs.
50 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
52 * @soc; Reference to soc_data of platform specific data.
53 * @regs: Base address for the TLMM register map.
57 struct pinctrl_dev *pctrl;
58 struct gpio_chip chip;
59 struct notifier_block restart_nb;
64 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
65 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
67 const struct msm_pinctrl_soc_data *soc;
71 static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc)
73 return container_of(gc, struct msm_pinctrl, chip);
76 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
78 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
80 return pctrl->soc->ngroups;
83 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
86 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
88 return pctrl->soc->groups[group].name;
91 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
93 const unsigned **pins,
96 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
98 *pins = pctrl->soc->groups[group].pins;
99 *num_pins = pctrl->soc->groups[group].npins;
103 static const struct pinctrl_ops msm_pinctrl_ops = {
104 .get_groups_count = msm_get_groups_count,
105 .get_group_name = msm_get_group_name,
106 .get_group_pins = msm_get_group_pins,
107 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
108 .dt_free_map = pinctrl_utils_dt_free_map,
111 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
113 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
115 return pctrl->soc->nfunctions;
118 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
121 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
123 return pctrl->soc->functions[function].name;
126 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
128 const char * const **groups,
129 unsigned * const num_groups)
131 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
133 *groups = pctrl->soc->functions[function].groups;
134 *num_groups = pctrl->soc->functions[function].ngroups;
138 static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
142 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
143 const struct msm_pingroup *g;
148 g = &pctrl->soc->groups[group];
150 for (i = 0; i < g->nfuncs; i++) {
151 if (g->funcs[i] == function)
155 if (WARN_ON(i == g->nfuncs))
158 spin_lock_irqsave(&pctrl->lock, flags);
160 val = readl(pctrl->regs + g->ctl_reg);
161 val &= ~(0x7 << g->mux_bit);
162 val |= i << g->mux_bit;
163 writel(val, pctrl->regs + g->ctl_reg);
165 spin_unlock_irqrestore(&pctrl->lock, flags);
170 static const struct pinmux_ops msm_pinmux_ops = {
171 .get_functions_count = msm_get_functions_count,
172 .get_function_name = msm_get_function_name,
173 .get_function_groups = msm_get_function_groups,
174 .set_mux = msm_pinmux_set_mux,
177 static int msm_config_reg(struct msm_pinctrl *pctrl,
178 const struct msm_pingroup *g,
184 case PIN_CONFIG_BIAS_DISABLE:
185 case PIN_CONFIG_BIAS_PULL_DOWN:
186 case PIN_CONFIG_BIAS_BUS_HOLD:
187 case PIN_CONFIG_BIAS_PULL_UP:
191 case PIN_CONFIG_DRIVE_STRENGTH:
195 case PIN_CONFIG_OUTPUT:
200 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
207 #define MSM_NO_PULL 0
208 #define MSM_PULL_DOWN 1
210 #define MSM_PULL_UP 3
212 static unsigned msm_regval_to_drive(u32 val)
214 return (val + 1) * 2;
217 static int msm_config_group_get(struct pinctrl_dev *pctldev,
219 unsigned long *config)
221 const struct msm_pingroup *g;
222 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
223 unsigned param = pinconf_to_config_param(*config);
230 g = &pctrl->soc->groups[group];
232 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
236 val = readl(pctrl->regs + g->ctl_reg);
237 arg = (val >> bit) & mask;
239 /* Convert register value to pinconf value */
241 case PIN_CONFIG_BIAS_DISABLE:
242 arg = arg == MSM_NO_PULL;
244 case PIN_CONFIG_BIAS_PULL_DOWN:
245 arg = arg == MSM_PULL_DOWN;
247 case PIN_CONFIG_BIAS_BUS_HOLD:
248 arg = arg == MSM_KEEPER;
250 case PIN_CONFIG_BIAS_PULL_UP:
251 arg = arg == MSM_PULL_UP;
253 case PIN_CONFIG_DRIVE_STRENGTH:
254 arg = msm_regval_to_drive(arg);
256 case PIN_CONFIG_OUTPUT:
257 /* Pin is not output */
261 val = readl(pctrl->regs + g->io_reg);
262 arg = !!(val & BIT(g->in_bit));
265 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
270 *config = pinconf_to_config_packed(param, arg);
275 static int msm_config_group_set(struct pinctrl_dev *pctldev,
277 unsigned long *configs,
278 unsigned num_configs)
280 const struct msm_pingroup *g;
281 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
291 g = &pctrl->soc->groups[group];
293 for (i = 0; i < num_configs; i++) {
294 param = pinconf_to_config_param(configs[i]);
295 arg = pinconf_to_config_argument(configs[i]);
297 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
301 /* Convert pinconf values to register values */
303 case PIN_CONFIG_BIAS_DISABLE:
306 case PIN_CONFIG_BIAS_PULL_DOWN:
309 case PIN_CONFIG_BIAS_BUS_HOLD:
312 case PIN_CONFIG_BIAS_PULL_UP:
315 case PIN_CONFIG_DRIVE_STRENGTH:
316 /* Check for invalid values */
317 if (arg > 16 || arg < 2 || (arg % 2) != 0)
322 case PIN_CONFIG_OUTPUT:
323 /* set output value */
324 spin_lock_irqsave(&pctrl->lock, flags);
325 val = readl(pctrl->regs + g->io_reg);
327 val |= BIT(g->out_bit);
329 val &= ~BIT(g->out_bit);
330 writel(val, pctrl->regs + g->io_reg);
331 spin_unlock_irqrestore(&pctrl->lock, flags);
337 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
342 /* Range-check user-supplied value */
344 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
348 spin_lock_irqsave(&pctrl->lock, flags);
349 val = readl(pctrl->regs + g->ctl_reg);
350 val &= ~(mask << bit);
352 writel(val, pctrl->regs + g->ctl_reg);
353 spin_unlock_irqrestore(&pctrl->lock, flags);
359 static const struct pinconf_ops msm_pinconf_ops = {
360 .pin_config_group_get = msm_config_group_get,
361 .pin_config_group_set = msm_config_group_set,
364 static struct pinctrl_desc msm_pinctrl_desc = {
365 .pctlops = &msm_pinctrl_ops,
366 .pmxops = &msm_pinmux_ops,
367 .confops = &msm_pinconf_ops,
368 .owner = THIS_MODULE,
371 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
373 const struct msm_pingroup *g;
374 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
378 g = &pctrl->soc->groups[offset];
380 spin_lock_irqsave(&pctrl->lock, flags);
382 val = readl(pctrl->regs + g->ctl_reg);
383 val &= ~BIT(g->oe_bit);
384 writel(val, pctrl->regs + g->ctl_reg);
386 spin_unlock_irqrestore(&pctrl->lock, flags);
391 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
393 const struct msm_pingroup *g;
394 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
398 g = &pctrl->soc->groups[offset];
400 spin_lock_irqsave(&pctrl->lock, flags);
402 val = readl(pctrl->regs + g->io_reg);
404 val |= BIT(g->out_bit);
406 val &= ~BIT(g->out_bit);
407 writel(val, pctrl->regs + g->io_reg);
409 val = readl(pctrl->regs + g->ctl_reg);
410 val |= BIT(g->oe_bit);
411 writel(val, pctrl->regs + g->ctl_reg);
413 spin_unlock_irqrestore(&pctrl->lock, flags);
418 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
420 const struct msm_pingroup *g;
421 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
424 g = &pctrl->soc->groups[offset];
426 val = readl(pctrl->regs + g->io_reg);
427 return !!(val & BIT(g->in_bit));
430 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
432 const struct msm_pingroup *g;
433 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
437 g = &pctrl->soc->groups[offset];
439 spin_lock_irqsave(&pctrl->lock, flags);
441 val = readl(pctrl->regs + g->io_reg);
443 val |= BIT(g->out_bit);
445 val &= ~BIT(g->out_bit);
446 writel(val, pctrl->regs + g->io_reg);
448 spin_unlock_irqrestore(&pctrl->lock, flags);
451 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
453 int gpio = chip->base + offset;
454 return pinctrl_request_gpio(gpio);
457 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
459 int gpio = chip->base + offset;
460 return pinctrl_free_gpio(gpio);
463 #ifdef CONFIG_DEBUG_FS
464 #include <linux/seq_file.h>
466 static void msm_gpio_dbg_show_one(struct seq_file *s,
467 struct pinctrl_dev *pctldev,
468 struct gpio_chip *chip,
472 const struct msm_pingroup *g;
473 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
480 static const char * const pulls[] = {
487 g = &pctrl->soc->groups[offset];
488 ctl_reg = readl(pctrl->regs + g->ctl_reg);
490 is_out = !!(ctl_reg & BIT(g->oe_bit));
491 func = (ctl_reg >> g->mux_bit) & 7;
492 drive = (ctl_reg >> g->drv_bit) & 7;
493 pull = (ctl_reg >> g->pull_bit) & 3;
495 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
496 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
497 seq_printf(s, " %s", pulls[pull]);
500 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
502 unsigned gpio = chip->base;
505 for (i = 0; i < chip->ngpio; i++, gpio++) {
506 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
512 #define msm_gpio_dbg_show NULL
515 static struct gpio_chip msm_gpio_template = {
516 .direction_input = msm_gpio_direction_input,
517 .direction_output = msm_gpio_direction_output,
520 .request = msm_gpio_request,
521 .free = msm_gpio_free,
522 .dbg_show = msm_gpio_dbg_show,
525 /* For dual-edge interrupts in software, since some hardware has no
528 * At appropriate moments, this function may be called to flip the polarity
529 * settings of both-edge irq lines to try and catch the next edge.
531 * The attempt is considered successful if:
532 * - the status bit goes high, indicating that an edge was caught, or
533 * - the input value of the gpio doesn't change during the attempt.
534 * If the value changes twice during the process, that would cause the first
535 * test to fail but would force the second, as two opposite
536 * transitions would cause a detection no matter the polarity setting.
538 * The do-loop tries to sledge-hammer closed the timing hole between
539 * the initial value-read and the polarity-write - if the line value changes
540 * during that window, an interrupt is lost, the new polarity setting is
541 * incorrect, and the first success test will fail, causing a retry.
543 * Algorithm comes from Google's msmgpio driver.
545 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
546 const struct msm_pingroup *g,
549 int loop_limit = 100;
550 unsigned val, val2, intstat;
554 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
556 pol = readl(pctrl->regs + g->intr_cfg_reg);
557 pol ^= BIT(g->intr_polarity_bit);
558 writel(pol, pctrl->regs + g->intr_cfg_reg);
560 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
561 intstat = readl(pctrl->regs + g->intr_status_reg);
562 if (intstat || (val == val2))
564 } while (loop_limit-- > 0);
565 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
569 static void msm_gpio_irq_mask(struct irq_data *d)
571 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
572 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
573 const struct msm_pingroup *g;
577 g = &pctrl->soc->groups[d->hwirq];
579 spin_lock_irqsave(&pctrl->lock, flags);
581 val = readl(pctrl->regs + g->intr_cfg_reg);
582 val &= ~BIT(g->intr_enable_bit);
583 writel(val, pctrl->regs + g->intr_cfg_reg);
585 clear_bit(d->hwirq, pctrl->enabled_irqs);
587 spin_unlock_irqrestore(&pctrl->lock, flags);
590 static void msm_gpio_irq_unmask(struct irq_data *d)
592 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
593 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
594 const struct msm_pingroup *g;
598 g = &pctrl->soc->groups[d->hwirq];
600 spin_lock_irqsave(&pctrl->lock, flags);
602 val = readl(pctrl->regs + g->intr_status_reg);
603 val &= ~BIT(g->intr_status_bit);
604 writel(val, pctrl->regs + g->intr_status_reg);
606 val = readl(pctrl->regs + g->intr_cfg_reg);
607 val |= BIT(g->intr_enable_bit);
608 writel(val, pctrl->regs + g->intr_cfg_reg);
610 set_bit(d->hwirq, pctrl->enabled_irqs);
612 spin_unlock_irqrestore(&pctrl->lock, flags);
615 static void msm_gpio_irq_ack(struct irq_data *d)
617 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
618 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
619 const struct msm_pingroup *g;
623 g = &pctrl->soc->groups[d->hwirq];
625 spin_lock_irqsave(&pctrl->lock, flags);
627 val = readl(pctrl->regs + g->intr_status_reg);
628 if (g->intr_ack_high)
629 val |= BIT(g->intr_status_bit);
631 val &= ~BIT(g->intr_status_bit);
632 writel(val, pctrl->regs + g->intr_status_reg);
634 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
635 msm_gpio_update_dual_edge_pos(pctrl, g, d);
637 spin_unlock_irqrestore(&pctrl->lock, flags);
640 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
642 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
643 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
644 const struct msm_pingroup *g;
648 g = &pctrl->soc->groups[d->hwirq];
650 spin_lock_irqsave(&pctrl->lock, flags);
653 * For hw without possibility of detecting both edges
655 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
656 set_bit(d->hwirq, pctrl->dual_edge_irqs);
658 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
660 /* Route interrupts to application cpu */
661 val = readl(pctrl->regs + g->intr_target_reg);
662 val &= ~(7 << g->intr_target_bit);
663 val |= g->intr_target_kpss_val << g->intr_target_bit;
664 writel(val, pctrl->regs + g->intr_target_reg);
666 /* Update configuration for gpio.
667 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
668 * internal circuitry of TLMM, toggling the RAW_STATUS
669 * could cause the INTR_STATUS to be set for EDGE interrupts.
671 val = readl(pctrl->regs + g->intr_cfg_reg);
672 val |= BIT(g->intr_raw_status_bit);
673 if (g->intr_detection_width == 2) {
674 val &= ~(3 << g->intr_detection_bit);
675 val &= ~(1 << g->intr_polarity_bit);
677 case IRQ_TYPE_EDGE_RISING:
678 val |= 1 << g->intr_detection_bit;
679 val |= BIT(g->intr_polarity_bit);
681 case IRQ_TYPE_EDGE_FALLING:
682 val |= 2 << g->intr_detection_bit;
683 val |= BIT(g->intr_polarity_bit);
685 case IRQ_TYPE_EDGE_BOTH:
686 val |= 3 << g->intr_detection_bit;
687 val |= BIT(g->intr_polarity_bit);
689 case IRQ_TYPE_LEVEL_LOW:
691 case IRQ_TYPE_LEVEL_HIGH:
692 val |= BIT(g->intr_polarity_bit);
695 } else if (g->intr_detection_width == 1) {
696 val &= ~(1 << g->intr_detection_bit);
697 val &= ~(1 << g->intr_polarity_bit);
699 case IRQ_TYPE_EDGE_RISING:
700 val |= BIT(g->intr_detection_bit);
701 val |= BIT(g->intr_polarity_bit);
703 case IRQ_TYPE_EDGE_FALLING:
704 val |= BIT(g->intr_detection_bit);
706 case IRQ_TYPE_EDGE_BOTH:
707 val |= BIT(g->intr_detection_bit);
708 val |= BIT(g->intr_polarity_bit);
710 case IRQ_TYPE_LEVEL_LOW:
712 case IRQ_TYPE_LEVEL_HIGH:
713 val |= BIT(g->intr_polarity_bit);
719 writel(val, pctrl->regs + g->intr_cfg_reg);
721 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
722 msm_gpio_update_dual_edge_pos(pctrl, g, d);
724 spin_unlock_irqrestore(&pctrl->lock, flags);
726 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
727 __irq_set_handler_locked(d->irq, handle_level_irq);
728 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
729 __irq_set_handler_locked(d->irq, handle_edge_irq);
734 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
736 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
737 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
740 spin_lock_irqsave(&pctrl->lock, flags);
742 irq_set_irq_wake(pctrl->irq, on);
744 spin_unlock_irqrestore(&pctrl->lock, flags);
749 static struct irq_chip msm_gpio_irq_chip = {
751 .irq_mask = msm_gpio_irq_mask,
752 .irq_unmask = msm_gpio_irq_unmask,
753 .irq_ack = msm_gpio_irq_ack,
754 .irq_set_type = msm_gpio_irq_set_type,
755 .irq_set_wake = msm_gpio_irq_set_wake,
758 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
760 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
761 const struct msm_pingroup *g;
762 struct msm_pinctrl *pctrl = to_msm_pinctrl(gc);
763 struct irq_chip *chip = irq_get_chip(irq);
769 chained_irq_enter(chip, desc);
772 * Each pin has it's own IRQ status register, so use
773 * enabled_irq bitmap to limit the number of reads.
775 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
776 g = &pctrl->soc->groups[i];
777 val = readl(pctrl->regs + g->intr_status_reg);
778 if (val & BIT(g->intr_status_bit)) {
779 irq_pin = irq_find_mapping(gc->irqdomain, i);
780 generic_handle_irq(irq_pin);
785 /* No interrupts were flagged */
787 handle_bad_irq(irq, desc);
789 chained_irq_exit(chip, desc);
792 static int msm_gpio_init(struct msm_pinctrl *pctrl)
794 struct gpio_chip *chip;
796 unsigned ngpio = pctrl->soc->ngpios;
798 if (WARN_ON(ngpio > MAX_NR_GPIO))
804 chip->label = dev_name(pctrl->dev);
805 chip->dev = pctrl->dev;
806 chip->owner = THIS_MODULE;
807 chip->of_node = pctrl->dev->of_node;
809 ret = gpiochip_add(&pctrl->chip);
811 dev_err(pctrl->dev, "Failed register gpiochip\n");
815 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
817 dev_err(pctrl->dev, "Failed to add pin range\n");
818 gpiochip_remove(&pctrl->chip);
822 ret = gpiochip_irqchip_add(chip,
828 dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
829 gpiochip_remove(&pctrl->chip);
833 gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq,
834 msm_gpio_irq_handler);
839 static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
842 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
844 writel(0, pctrl->regs + PS_HOLD_OFFSET);
849 static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
852 const struct msm_function *func = pctrl->soc->functions;
854 for (i = 0; i < pctrl->soc->nfunctions; i++)
855 if (!strcmp(func[i].name, "ps_hold")) {
856 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
857 pctrl->restart_nb.priority = 128;
858 if (register_restart_handler(&pctrl->restart_nb))
860 "failed to setup restart handler.\n");
865 int msm_pinctrl_probe(struct platform_device *pdev,
866 const struct msm_pinctrl_soc_data *soc_data)
868 struct msm_pinctrl *pctrl;
869 struct resource *res;
872 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
874 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
877 pctrl->dev = &pdev->dev;
878 pctrl->soc = soc_data;
879 pctrl->chip = msm_gpio_template;
881 spin_lock_init(&pctrl->lock);
883 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
884 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
885 if (IS_ERR(pctrl->regs))
886 return PTR_ERR(pctrl->regs);
888 msm_pinctrl_setup_pm_reset(pctrl);
890 pctrl->irq = platform_get_irq(pdev, 0);
891 if (pctrl->irq < 0) {
892 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
896 msm_pinctrl_desc.name = dev_name(&pdev->dev);
897 msm_pinctrl_desc.pins = pctrl->soc->pins;
898 msm_pinctrl_desc.npins = pctrl->soc->npins;
899 pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
901 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
905 ret = msm_gpio_init(pctrl);
907 pinctrl_unregister(pctrl->pctrl);
911 platform_set_drvdata(pdev, pctrl);
913 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
917 EXPORT_SYMBOL(msm_pinctrl_probe);
919 int msm_pinctrl_remove(struct platform_device *pdev)
921 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
923 gpiochip_remove(&pctrl->chip);
924 pinctrl_unregister(pctrl->pctrl);
926 unregister_restart_handler(&pctrl->restart_nb);
930 EXPORT_SYMBOL(msm_pinctrl_remove);