2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
16 #include <linux/slab.h>
17 #include <linux/err.h>
18 #include <linux/gpio.h>
19 #include <linux/device.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_irq.h>
28 /* EXYNOS5440 GPIO and Pinctrl register offsets */
32 #define GPIO_TYPE 0x0C
42 #define EXYNOS5440_MAX_PINS 23
43 #define EXYNOS5440_MAX_GPIO_INT 8
44 #define PIN_NAME_LENGTH 10
46 #define GROUP_SUFFIX "-grp"
47 #define FUNCTION_SUFFIX "-mux"
50 * pin configuration type and its value are packed together into a 16-bits.
51 * The upper 8-bits represent the configuration type and the lower 8-bits
52 * hold the value of the configuration type.
54 #define PINCFG_TYPE_MASK 0xFF
55 #define PINCFG_VALUE_SHIFT 8
56 #define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
57 #define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
58 #define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
59 #define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
63 * enum pincfg_type - possible pin configuration types supported.
64 * @PINCFG_TYPE_PUD: Pull up/down configuration.
65 * @PINCFG_TYPE_DRV: Drive strength configuration.
66 * @PINCFG_TYPE_SKEW_RATE: Skew rate configuration.
67 * @PINCFG_TYPE_INPUT_TYPE: Pin input type configuration.
72 PINCFG_TYPE_SKEW_RATE,
73 PINCFG_TYPE_INPUT_TYPE
77 * struct exynos5440_pin_group: represent group of pins for pincfg setting.
78 * @name: name of the pin group, used to lookup the group.
79 * @pins: the pins included in this group.
80 * @num_pins: number of pins included in this group.
82 struct exynos5440_pin_group {
84 const unsigned int *pins;
89 * struct exynos5440_pmx_func: represent a pin function.
90 * @name: name of the pin function, used to lookup the function.
91 * @groups: one or more names of pin groups that provide this function.
92 * @num_groups: number of groups included in @groups.
93 * @function: the function number to be programmed when selected.
95 struct exynos5440_pmx_func {
99 unsigned long function;
103 * struct exynos5440_pinctrl_priv_data: driver's private runtime data.
104 * @reg_base: ioremapped based address of the register space.
105 * @gc: gpio chip registered with gpiolib.
106 * @pin_groups: list of pin groups parsed from device tree.
107 * @nr_groups: number of pin groups available.
108 * @pmx_functions: list of pin functions parsed from device tree.
109 * @nr_functions: number of pin functions available.
111 struct exynos5440_pinctrl_priv_data {
112 void __iomem *reg_base;
113 struct gpio_chip *gc;
114 struct irq_domain *irq_domain;
116 const struct exynos5440_pin_group *pin_groups;
117 unsigned int nr_groups;
118 const struct exynos5440_pmx_func *pmx_functions;
119 unsigned int nr_functions;
123 * struct exynos5440_gpio_intr_data: private data for gpio interrupts.
124 * @priv: driver's private runtime data.
125 * @gpio_int: gpio interrupt number.
127 struct exynos5440_gpio_intr_data {
128 struct exynos5440_pinctrl_priv_data *priv;
129 unsigned int gpio_int;
132 /* list of all possible config options supported */
133 static struct pin_config {
135 unsigned int cfg_type;
137 { "samsung,exynos5440-pin-pud", PINCFG_TYPE_PUD },
138 { "samsung,exynos5440-pin-drv", PINCFG_TYPE_DRV },
139 { "samsung,exynos5440-pin-skew-rate", PINCFG_TYPE_SKEW_RATE },
140 { "samsung,exynos5440-pin-input-type", PINCFG_TYPE_INPUT_TYPE },
143 /* check if the selector is a valid pin group selector */
144 static int exynos5440_get_group_count(struct pinctrl_dev *pctldev)
146 struct exynos5440_pinctrl_priv_data *priv;
148 priv = pinctrl_dev_get_drvdata(pctldev);
149 return priv->nr_groups;
152 /* return the name of the group selected by the group selector */
153 static const char *exynos5440_get_group_name(struct pinctrl_dev *pctldev,
156 struct exynos5440_pinctrl_priv_data *priv;
158 priv = pinctrl_dev_get_drvdata(pctldev);
159 return priv->pin_groups[selector].name;
162 /* return the pin numbers associated with the specified group */
163 static int exynos5440_get_group_pins(struct pinctrl_dev *pctldev,
164 unsigned selector, const unsigned **pins, unsigned *num_pins)
166 struct exynos5440_pinctrl_priv_data *priv;
168 priv = pinctrl_dev_get_drvdata(pctldev);
169 *pins = priv->pin_groups[selector].pins;
170 *num_pins = priv->pin_groups[selector].num_pins;
174 /* create pinctrl_map entries by parsing device tree nodes */
175 static int exynos5440_dt_node_to_map(struct pinctrl_dev *pctldev,
176 struct device_node *np, struct pinctrl_map **maps,
179 struct device *dev = pctldev->dev;
180 struct pinctrl_map *map;
181 unsigned long *cfg = NULL;
183 int cfg_cnt = 0, map_cnt = 0, idx = 0;
185 /* count the number of config options specfied in the node */
186 for (idx = 0; idx < ARRAY_SIZE(pcfgs); idx++)
187 if (of_find_property(np, pcfgs[idx].prop_cfg, NULL))
191 * Find out the number of map entries to create. All the config options
192 * can be accomadated into a single config map entry.
196 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL))
199 dev_err(dev, "node %s does not have either config or function "
200 "configurations\n", np->name);
204 /* Allocate memory for pin-map entries */
205 map = kzalloc(sizeof(*map) * map_cnt, GFP_KERNEL);
211 * Allocate memory for pin group name. The pin group name is derived
212 * from the node name from which these map entries are be created.
214 gname = kasprintf(GFP_KERNEL, "%s%s", np->name, GROUP_SUFFIX);
219 * don't have config options? then skip over to creating function
225 /* Allocate memory for config entries */
226 cfg = kzalloc(sizeof(*cfg) * cfg_cnt, GFP_KERNEL);
230 /* Prepare a list of config settings */
231 for (idx = 0, cfg_cnt = 0; idx < ARRAY_SIZE(pcfgs); idx++) {
233 if (!of_property_read_u32(np, pcfgs[idx].prop_cfg, &value))
235 PINCFG_PACK(pcfgs[idx].cfg_type, value);
238 /* create the config map entry */
239 map[*nmaps].data.configs.group_or_pin = gname;
240 map[*nmaps].data.configs.configs = cfg;
241 map[*nmaps].data.configs.num_configs = cfg_cnt;
242 map[*nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
246 /* create the function map entry */
247 if (of_find_property(np, "samsung,exynos5440-pin-function", NULL)) {
248 fname = kasprintf(GFP_KERNEL,
249 "%s%s", np->name, FUNCTION_SUFFIX);
253 map[*nmaps].data.mux.group = gname;
254 map[*nmaps].data.mux.function = fname;
255 map[*nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
271 /* free the memory allocated to hold the pin-map table */
272 static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
273 struct pinctrl_map *map, unsigned num_maps)
277 for (idx = 0; idx < num_maps; idx++) {
278 if (map[idx].type == PIN_MAP_TYPE_MUX_GROUP) {
279 kfree(map[idx].data.mux.function);
281 kfree(map[idx].data.mux.group);
282 } else if (map->type == PIN_MAP_TYPE_CONFIGS_GROUP) {
283 kfree(map[idx].data.configs.configs);
285 kfree(map[idx].data.configs.group_or_pin);
292 /* list of pinctrl callbacks for the pinctrl core */
293 static const struct pinctrl_ops exynos5440_pctrl_ops = {
294 .get_groups_count = exynos5440_get_group_count,
295 .get_group_name = exynos5440_get_group_name,
296 .get_group_pins = exynos5440_get_group_pins,
297 .dt_node_to_map = exynos5440_dt_node_to_map,
298 .dt_free_map = exynos5440_dt_free_map,
301 /* check if the selector is a valid pin function selector */
302 static int exynos5440_get_functions_count(struct pinctrl_dev *pctldev)
304 struct exynos5440_pinctrl_priv_data *priv;
306 priv = pinctrl_dev_get_drvdata(pctldev);
307 return priv->nr_functions;
310 /* return the name of the pin function specified */
311 static const char *exynos5440_pinmux_get_fname(struct pinctrl_dev *pctldev,
314 struct exynos5440_pinctrl_priv_data *priv;
316 priv = pinctrl_dev_get_drvdata(pctldev);
317 return priv->pmx_functions[selector].name;
320 /* return the groups associated for the specified function selector */
321 static int exynos5440_pinmux_get_groups(struct pinctrl_dev *pctldev,
322 unsigned selector, const char * const **groups,
323 unsigned * const num_groups)
325 struct exynos5440_pinctrl_priv_data *priv;
327 priv = pinctrl_dev_get_drvdata(pctldev);
328 *groups = priv->pmx_functions[selector].groups;
329 *num_groups = priv->pmx_functions[selector].num_groups;
333 /* enable or disable a pinmux function */
334 static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
335 unsigned group, bool enable)
337 struct exynos5440_pinctrl_priv_data *priv;
342 priv = pinctrl_dev_get_drvdata(pctldev);
343 base = priv->reg_base;
344 function = priv->pmx_functions[selector].function;
346 data = readl(base + GPIO_MUX);
348 data |= (1 << function);
350 data &= ~(1 << function);
351 writel(data, base + GPIO_MUX);
354 /* enable a specified pinmux by writing to registers */
355 static int exynos5440_pinmux_set_mux(struct pinctrl_dev *pctldev,
359 exynos5440_pinmux_setup(pctldev, selector, group, true);
364 * The calls to gpio_direction_output() and gpio_direction_input()
365 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
366 * function called from the gpiolib interface).
368 static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
369 struct pinctrl_gpio_range *range, unsigned offset, bool input)
374 /* list of pinmux callbacks for the pinmux vertical in pinctrl core */
375 static const struct pinmux_ops exynos5440_pinmux_ops = {
376 .get_functions_count = exynos5440_get_functions_count,
377 .get_function_name = exynos5440_pinmux_get_fname,
378 .get_function_groups = exynos5440_pinmux_get_groups,
379 .set_mux = exynos5440_pinmux_set_mux,
380 .gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
383 /* set the pin config settings for a specified pin */
384 static int exynos5440_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
385 unsigned long *configs,
386 unsigned num_configs)
388 struct exynos5440_pinctrl_priv_data *priv;
390 enum pincfg_type cfg_type;
395 priv = pinctrl_dev_get_drvdata(pctldev);
396 base = priv->reg_base;
398 for (i = 0; i < num_configs; i++) {
399 cfg_type = PINCFG_UNPACK_TYPE(configs[i]);
400 cfg_value = PINCFG_UNPACK_VALUE(configs[i]);
403 case PINCFG_TYPE_PUD:
404 /* first set pull enable/disable bit */
405 data = readl(base + GPIO_PE);
409 writel(data, base + GPIO_PE);
411 /* then set pull up/down bit */
412 data = readl(base + GPIO_PS);
416 writel(data, base + GPIO_PS);
419 case PINCFG_TYPE_DRV:
420 /* set the first bit of the drive strength */
421 data = readl(base + GPIO_DS0);
423 data |= ((cfg_value & 1) << pin);
424 writel(data, base + GPIO_DS0);
427 /* set the second bit of the driver strength */
428 data = readl(base + GPIO_DS1);
430 data |= ((cfg_value & 1) << pin);
431 writel(data, base + GPIO_DS1);
433 case PINCFG_TYPE_SKEW_RATE:
434 data = readl(base + GPIO_SR);
436 data |= ((cfg_value & 1) << pin);
437 writel(data, base + GPIO_SR);
439 case PINCFG_TYPE_INPUT_TYPE:
440 data = readl(base + GPIO_TYPE);
442 data |= ((cfg_value & 1) << pin);
443 writel(data, base + GPIO_TYPE);
449 } /* for each config */
454 /* get the pin config settings for a specified pin */
455 static int exynos5440_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
456 unsigned long *config)
458 struct exynos5440_pinctrl_priv_data *priv;
460 enum pincfg_type cfg_type = PINCFG_UNPACK_TYPE(*config);
463 priv = pinctrl_dev_get_drvdata(pctldev);
464 base = priv->reg_base;
467 case PINCFG_TYPE_PUD:
468 data = readl(base + GPIO_PE);
469 data = (data >> pin) & 1;
473 *config = ((readl(base + GPIO_PS) >> pin) & 1) + 1;
475 case PINCFG_TYPE_DRV:
476 data = readl(base + GPIO_DS0);
477 data = (data >> pin) & 1;
479 data = readl(base + GPIO_DS1);
480 data = (data >> pin) & 1;
481 *config |= (data << 1);
483 case PINCFG_TYPE_SKEW_RATE:
484 data = readl(base + GPIO_SR);
485 *config = (data >> pin) & 1;
487 case PINCFG_TYPE_INPUT_TYPE:
488 data = readl(base + GPIO_TYPE);
489 *config = (data >> pin) & 1;
499 /* set the pin config settings for a specified pin group */
500 static int exynos5440_pinconf_group_set(struct pinctrl_dev *pctldev,
501 unsigned group, unsigned long *configs,
502 unsigned num_configs)
504 struct exynos5440_pinctrl_priv_data *priv;
505 const unsigned int *pins;
508 priv = pinctrl_dev_get_drvdata(pctldev);
509 pins = priv->pin_groups[group].pins;
511 for (cnt = 0; cnt < priv->pin_groups[group].num_pins; cnt++)
512 exynos5440_pinconf_set(pctldev, pins[cnt], configs,
518 /* get the pin config settings for a specified pin group */
519 static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
520 unsigned int group, unsigned long *config)
522 struct exynos5440_pinctrl_priv_data *priv;
523 const unsigned int *pins;
525 priv = pinctrl_dev_get_drvdata(pctldev);
526 pins = priv->pin_groups[group].pins;
527 exynos5440_pinconf_get(pctldev, pins[0], config);
531 /* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
532 static const struct pinconf_ops exynos5440_pinconf_ops = {
533 .pin_config_get = exynos5440_pinconf_get,
534 .pin_config_set = exynos5440_pinconf_set,
535 .pin_config_group_get = exynos5440_pinconf_group_get,
536 .pin_config_group_set = exynos5440_pinconf_group_set,
539 /* gpiolib gpio_set callback function */
540 static void exynos5440_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
542 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
543 void __iomem *base = priv->reg_base;
546 data = readl(base + GPIO_VAL);
547 data &= ~(1 << offset);
550 writel(data, base + GPIO_VAL);
553 /* gpiolib gpio_get callback function */
554 static int exynos5440_gpio_get(struct gpio_chip *gc, unsigned offset)
556 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
557 void __iomem *base = priv->reg_base;
560 data = readl(base + GPIO_IN);
566 /* gpiolib gpio_direction_input callback function */
567 static int exynos5440_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
569 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
570 void __iomem *base = priv->reg_base;
573 /* first disable the data output enable on this pin */
574 data = readl(base + GPIO_OE);
575 data &= ~(1 << offset);
576 writel(data, base + GPIO_OE);
578 /* now enable input on this pin */
579 data = readl(base + GPIO_IE);
581 writel(data, base + GPIO_IE);
585 /* gpiolib gpio_direction_output callback function */
586 static int exynos5440_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
589 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
590 void __iomem *base = priv->reg_base;
593 exynos5440_gpio_set(gc, offset, value);
595 /* first disable the data input enable on this pin */
596 data = readl(base + GPIO_IE);
597 data &= ~(1 << offset);
598 writel(data, base + GPIO_IE);
600 /* now enable output on this pin */
601 data = readl(base + GPIO_OE);
603 writel(data, base + GPIO_OE);
607 /* gpiolib gpio_to_irq callback function */
608 static int exynos5440_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
610 struct exynos5440_pinctrl_priv_data *priv = dev_get_drvdata(gc->dev);
613 if (offset < 16 || offset > 23)
616 if (!priv->irq_domain)
619 virq = irq_create_mapping(priv->irq_domain, offset - 16);
620 return virq ? : -ENXIO;
623 /* parse the pin numbers listed in the 'samsung,exynos5440-pins' property */
624 static int exynos5440_pinctrl_parse_dt_pins(struct platform_device *pdev,
625 struct device_node *cfg_np, unsigned int **pin_list,
628 struct device *dev = &pdev->dev;
629 struct property *prop;
631 prop = of_find_property(cfg_np, "samsung,exynos5440-pins", NULL);
635 *npins = prop->length / sizeof(unsigned long);
637 dev_err(dev, "invalid pin list in %s node", cfg_np->name);
641 *pin_list = devm_kzalloc(dev, *npins * sizeof(**pin_list), GFP_KERNEL);
645 return of_property_read_u32_array(cfg_np, "samsung,exynos5440-pins",
650 * Parse the information about all the available pin groups and pin functions
651 * from device node of the pin-controller.
653 static int exynos5440_pinctrl_parse_dt(struct platform_device *pdev,
654 struct exynos5440_pinctrl_priv_data *priv)
656 struct device *dev = &pdev->dev;
657 struct device_node *dev_np = dev->of_node;
658 struct device_node *cfg_np;
659 struct exynos5440_pin_group *groups, *grp;
660 struct exynos5440_pmx_func *functions, *func;
662 unsigned int npins, grp_cnt, func_idx = 0;
666 grp_cnt = of_get_child_count(dev_np);
670 groups = devm_kzalloc(dev, grp_cnt * sizeof(*groups), GFP_KERNEL);
676 functions = devm_kzalloc(dev, grp_cnt * sizeof(*functions), GFP_KERNEL);
683 * Iterate over all the child nodes of the pin controller node
684 * and create pin groups and pin function lists.
686 for_each_child_of_node(dev_np, cfg_np) {
689 ret = exynos5440_pinctrl_parse_dt_pins(pdev, cfg_np,
693 goto skip_to_pin_function;
696 /* derive pin group name from the node name */
697 gname = devm_kasprintf(dev, GFP_KERNEL,
698 "%s%s", cfg_np->name, GROUP_SUFFIX);
703 grp->pins = pin_list;
704 grp->num_pins = npins;
707 skip_to_pin_function:
708 ret = of_property_read_u32(cfg_np, "samsung,exynos5440-pin-function",
713 /* derive function name from the node name */
714 fname = devm_kasprintf(dev, GFP_KERNEL,
715 "%s%s", cfg_np->name, FUNCTION_SUFFIX);
720 func->groups = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
723 func->groups[0] = gname;
724 func->num_groups = gname ? 1 : 0;
725 func->function = function;
730 priv->pin_groups = groups;
731 priv->nr_groups = grp_cnt;
732 priv->pmx_functions = functions;
733 priv->nr_functions = func_idx;
737 /* register the pinctrl interface with the pinctrl subsystem */
738 static int exynos5440_pinctrl_register(struct platform_device *pdev,
739 struct exynos5440_pinctrl_priv_data *priv)
741 struct device *dev = &pdev->dev;
742 struct pinctrl_desc *ctrldesc;
743 struct pinctrl_dev *pctl_dev;
744 struct pinctrl_pin_desc *pindesc, *pdesc;
745 struct pinctrl_gpio_range grange;
749 ctrldesc = devm_kzalloc(dev, sizeof(*ctrldesc), GFP_KERNEL);
753 ctrldesc->name = "exynos5440-pinctrl";
754 ctrldesc->owner = THIS_MODULE;
755 ctrldesc->pctlops = &exynos5440_pctrl_ops;
756 ctrldesc->pmxops = &exynos5440_pinmux_ops;
757 ctrldesc->confops = &exynos5440_pinconf_ops;
759 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
760 EXYNOS5440_MAX_PINS, GFP_KERNEL);
763 ctrldesc->pins = pindesc;
764 ctrldesc->npins = EXYNOS5440_MAX_PINS;
766 /* dynamically populate the pin number and pin name for pindesc */
767 for (pin = 0, pdesc = pindesc; pin < ctrldesc->npins; pin++, pdesc++)
771 * allocate space for storing the dynamically generated names for all
772 * the pins which belong to this pin-controller.
774 pin_names = devm_kzalloc(&pdev->dev, sizeof(char) * PIN_NAME_LENGTH *
775 ctrldesc->npins, GFP_KERNEL);
779 /* for each pin, set the name of the pin */
780 for (pin = 0; pin < ctrldesc->npins; pin++) {
781 snprintf(pin_names, 6, "gpio%02d", pin);
782 pdesc = pindesc + pin;
783 pdesc->name = pin_names;
784 pin_names += PIN_NAME_LENGTH;
787 ret = exynos5440_pinctrl_parse_dt(pdev, priv);
791 pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, priv);
792 if (IS_ERR(pctl_dev)) {
793 dev_err(&pdev->dev, "could not register pinctrl driver\n");
794 return PTR_ERR(pctl_dev);
797 grange.name = "exynos5440-pctrl-gpio-range";
800 grange.npins = EXYNOS5440_MAX_PINS;
801 grange.gc = priv->gc;
802 pinctrl_add_gpio_range(pctl_dev, &grange);
806 /* register the gpiolib interface with the gpiolib subsystem */
807 static int exynos5440_gpiolib_register(struct platform_device *pdev,
808 struct exynos5440_pinctrl_priv_data *priv)
810 struct gpio_chip *gc;
813 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
819 gc->ngpio = EXYNOS5440_MAX_PINS;
820 gc->dev = &pdev->dev;
821 gc->set = exynos5440_gpio_set;
822 gc->get = exynos5440_gpio_get;
823 gc->direction_input = exynos5440_gpio_direction_input;
824 gc->direction_output = exynos5440_gpio_direction_output;
825 gc->to_irq = exynos5440_gpio_to_irq;
826 gc->label = "gpiolib-exynos5440";
827 gc->owner = THIS_MODULE;
828 ret = gpiochip_add(gc);
830 dev_err(&pdev->dev, "failed to register gpio_chip %s, error "
831 "code: %d\n", gc->label, ret);
838 /* unregister the gpiolib interface with the gpiolib subsystem */
839 static int exynos5440_gpiolib_unregister(struct platform_device *pdev,
840 struct exynos5440_pinctrl_priv_data *priv)
842 gpiochip_remove(priv->gc);
846 static void exynos5440_gpio_irq_unmask(struct irq_data *irqd)
848 struct exynos5440_pinctrl_priv_data *d;
849 unsigned long gpio_int;
851 d = irq_data_get_irq_chip_data(irqd);
852 gpio_int = readl(d->reg_base + GPIO_INT);
853 gpio_int |= 1 << irqd->hwirq;
854 writel(gpio_int, d->reg_base + GPIO_INT);
857 static void exynos5440_gpio_irq_mask(struct irq_data *irqd)
859 struct exynos5440_pinctrl_priv_data *d;
860 unsigned long gpio_int;
862 d = irq_data_get_irq_chip_data(irqd);
863 gpio_int = readl(d->reg_base + GPIO_INT);
864 gpio_int &= ~(1 << irqd->hwirq);
865 writel(gpio_int, d->reg_base + GPIO_INT);
868 /* irq_chip for gpio interrupts */
869 static struct irq_chip exynos5440_gpio_irq_chip = {
870 .name = "exynos5440_gpio_irq_chip",
871 .irq_unmask = exynos5440_gpio_irq_unmask,
872 .irq_mask = exynos5440_gpio_irq_mask,
875 /* interrupt handler for GPIO interrupts 0..7 */
876 static irqreturn_t exynos5440_gpio_irq(int irq, void *data)
878 struct exynos5440_gpio_intr_data *intd = data;
879 struct exynos5440_pinctrl_priv_data *d = intd->priv;
882 virq = irq_linear_revmap(d->irq_domain, intd->gpio_int);
885 generic_handle_irq(virq);
889 static int exynos5440_gpio_irq_map(struct irq_domain *h, unsigned int virq,
892 struct exynos5440_pinctrl_priv_data *d = h->host_data;
894 irq_set_chip_data(virq, d);
895 irq_set_chip_and_handler(virq, &exynos5440_gpio_irq_chip,
900 /* irq domain callbacks for gpio interrupt controller */
901 static const struct irq_domain_ops exynos5440_gpio_irqd_ops = {
902 .map = exynos5440_gpio_irq_map,
903 .xlate = irq_domain_xlate_twocell,
906 /* setup handling of gpio interrupts */
907 static int exynos5440_gpio_irq_init(struct platform_device *pdev,
908 struct exynos5440_pinctrl_priv_data *priv)
910 struct device *dev = &pdev->dev;
911 struct exynos5440_gpio_intr_data *intd;
914 intd = devm_kzalloc(dev, sizeof(*intd) * EXYNOS5440_MAX_GPIO_INT,
919 for (i = 0; i < EXYNOS5440_MAX_GPIO_INT; i++) {
920 irq = irq_of_parse_and_map(dev->of_node, i);
922 dev_err(dev, "irq parsing failed\n");
928 ret = devm_request_irq(dev, irq, exynos5440_gpio_irq,
929 0, dev_name(dev), intd++);
931 dev_err(dev, "irq request failed\n");
936 priv->irq_domain = irq_domain_add_linear(dev->of_node,
937 EXYNOS5440_MAX_GPIO_INT,
938 &exynos5440_gpio_irqd_ops, priv);
939 if (!priv->irq_domain) {
940 dev_err(dev, "failed to create irq domain\n");
947 static int exynos5440_pinctrl_probe(struct platform_device *pdev)
949 struct device *dev = &pdev->dev;
950 struct exynos5440_pinctrl_priv_data *priv;
951 struct resource *res;
955 dev_err(dev, "device tree node not found\n");
959 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
963 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
964 priv->reg_base = devm_ioremap_resource(&pdev->dev, res);
965 if (IS_ERR(priv->reg_base))
966 return PTR_ERR(priv->reg_base);
968 ret = exynos5440_gpiolib_register(pdev, priv);
972 ret = exynos5440_pinctrl_register(pdev, priv);
974 exynos5440_gpiolib_unregister(pdev, priv);
978 ret = exynos5440_gpio_irq_init(pdev, priv);
980 dev_err(dev, "failed to setup gpio interrupts\n");
984 platform_set_drvdata(pdev, priv);
985 dev_info(dev, "EXYNOS5440 pinctrl driver registered\n");
989 static const struct of_device_id exynos5440_pinctrl_dt_match[] = {
990 { .compatible = "samsung,exynos5440-pinctrl" },
993 MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match);
995 static struct platform_driver exynos5440_pinctrl_driver = {
996 .probe = exynos5440_pinctrl_probe,
998 .name = "exynos5440-pinctrl",
999 .of_match_table = exynos5440_pinctrl_dt_match,
1003 static int __init exynos5440_pinctrl_drv_register(void)
1005 return platform_driver_register(&exynos5440_pinctrl_driver);
1007 postcore_initcall(exynos5440_pinctrl_drv_register);
1009 static void __exit exynos5440_pinctrl_drv_unregister(void)
1011 platform_driver_unregister(&exynos5440_pinctrl_driver);
1013 module_exit(exynos5440_pinctrl_drv_unregister);
1015 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
1016 MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver");
1017 MODULE_LICENSE("GPL v2");