drivers/pinctrl/sh-pfc/pfc-r8a73a4.c

   1 /*
   2  * Copyright (C) 2012-2013  Renesas Solutions Corp.
   3  * Copyright (C) 2013  Magnus Damm
   4  * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of the
   9  * License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/io.h>
  21 #include <linux/kernel.h>
  22 #include <linux/pinctrl/pinconf-generic.h>
  23 #include <mach/irqs.h>
  24 #include <mach/r8a73a4.h>
  25
  26 #include "core.h"
  27 #include "sh_pfc.h"
  28
  29 #define CPU_ALL_PORT(fn, pfx, sfx)                                      \
  30         /*  Port0 - Port30 */                                           \
  31         PORT_10(fn, pfx, sfx),                                          \
  32         PORT_10(fn, pfx##1, sfx),                                       \
  33         PORT_10(fn, pfx##2, sfx),                                       \
  34         PORT_1(fn,  pfx##30, sfx),                                      \
  35         /* Port32 - Port40 */                                           \
  36         PORT_1(fn,  pfx##32, sfx),      PORT_1(fn,  pfx##33, sfx),      \
  37         PORT_1(fn,  pfx##34, sfx),      PORT_1(fn,  pfx##35, sfx),      \
  38         PORT_1(fn,  pfx##36, sfx),      PORT_1(fn,  pfx##37, sfx),      \
  39         PORT_1(fn,  pfx##38, sfx),      PORT_1(fn,  pfx##39, sfx),      \
  40         PORT_1(fn,  pfx##40, sfx),                                      \
  41         /* Port64  - Port85 */                                          \
  42         PORT_1(fn, pfx##64, sfx),       PORT_1(fn, pfx##65, sfx),       \
  43         PORT_1(fn, pfx##66, sfx),       PORT_1(fn, pfx##67, sfx),       \
  44         PORT_1(fn, pfx##68, sfx),       PORT_1(fn, pfx##69, sfx),       \
  45         PORT_10(fn, pfx##7, sfx),                                       \
  46         PORT_1(fn, pfx##80, sfx),       PORT_1(fn, pfx##81, sfx),       \
  47         PORT_1(fn, pfx##82, sfx),       PORT_1(fn, pfx##83, sfx),       \
  48         PORT_1(fn, pfx##84, sfx),       PORT_1(fn, pfx##85, sfx),       \
  49         /* Port96  - Port126 */                                         \
  50         PORT_1(fn, pfx##96, sfx),       PORT_1(fn, pfx##97, sfx),       \
  51         PORT_1(fn, pfx##98, sfx),       PORT_1(fn, pfx##99, sfx),       \
  52         PORT_10(fn, pfx##10, sfx),                                      \
  53         PORT_10(fn, pfx##11, sfx),                                      \
  54         PORT_1(fn, pfx##120, sfx),      PORT_1(fn, pfx##121, sfx),      \
  55         PORT_1(fn, pfx##122, sfx),      PORT_1(fn, pfx##123, sfx),      \
  56         PORT_1(fn, pfx##124, sfx),      PORT_1(fn, pfx##125, sfx),      \
  57         PORT_1(fn, pfx##126, sfx),                                      \
  58         /* Port128 - Port134 */                                         \
  59         PORT_1(fn, pfx##128, sfx),      PORT_1(fn, pfx##129, sfx),      \
  60         PORT_1(fn, pfx##130, sfx),      PORT_1(fn, pfx##131, sfx),      \
  61         PORT_1(fn, pfx##132, sfx),      PORT_1(fn, pfx##133, sfx),      \
  62         PORT_1(fn, pfx##134, sfx),                                      \
  63         /* Port160 - Port178 */                                         \
  64         PORT_10(fn, pfx##16, sfx),                                      \
  65         PORT_1(fn, pfx##170, sfx),      PORT_1(fn, pfx##171, sfx),      \
  66         PORT_1(fn, pfx##172, sfx),      PORT_1(fn, pfx##173, sfx),      \
  67         PORT_1(fn, pfx##174, sfx),      PORT_1(fn, pfx##175, sfx),      \
  68         PORT_1(fn, pfx##176, sfx),      PORT_1(fn, pfx##177, sfx),      \
  69         PORT_1(fn, pfx##178, sfx),                                      \
  70         /* Port192 - Port222 */                                         \
  71         PORT_1(fn, pfx##192, sfx),      PORT_1(fn, pfx##193, sfx),      \
  72         PORT_1(fn, pfx##194, sfx),      PORT_1(fn, pfx##195, sfx),      \
  73         PORT_1(fn, pfx##196, sfx),      PORT_1(fn, pfx##197, sfx),      \
  74         PORT_1(fn, pfx##198, sfx),      PORT_1(fn, pfx##199, sfx),      \
  75         PORT_10(fn, pfx##20, sfx),                                      \
  76         PORT_10(fn, pfx##21, sfx),                                      \
  77         PORT_1(fn, pfx##220, sfx),      PORT_1(fn, pfx##221, sfx),      \
  78         PORT_1(fn, pfx##222, sfx),                                      \
  79         /* Port224 - Port250 */                                         \
  80         PORT_1(fn, pfx##224, sfx),      PORT_1(fn, pfx##225, sfx),      \
  81         PORT_1(fn, pfx##226, sfx),      PORT_1(fn, pfx##227, sfx),      \
  82         PORT_1(fn, pfx##228, sfx),      PORT_1(fn, pfx##229, sfx),      \
  83         PORT_10(fn, pfx##23, sfx),                                      \
  84         PORT_10(fn, pfx##24, sfx),                                      \
  85         PORT_1(fn, pfx##250, sfx),                                      \
  86         /* Port256 - Port283 */                                         \
  87         PORT_1(fn, pfx##256, sfx),      PORT_1(fn, pfx##257, sfx),      \
  88         PORT_1(fn, pfx##258, sfx),      PORT_1(fn, pfx##259, sfx),      \
  89         PORT_10(fn, pfx##26, sfx),                                      \
  90         PORT_10(fn, pfx##27, sfx),                                      \
  91         PORT_1(fn, pfx##280, sfx),      PORT_1(fn, pfx##281, sfx),      \
  92         PORT_1(fn, pfx##282, sfx),      PORT_1(fn, pfx##283, sfx),      \
  93         /* Port288 - Port308 */                                         \
  94         PORT_1(fn, pfx##288, sfx),      PORT_1(fn, pfx##289, sfx),      \
  95         PORT_10(fn, pfx##29, sfx),                                      \
  96         PORT_1(fn, pfx##300, sfx),      PORT_1(fn, pfx##301, sfx),      \
  97         PORT_1(fn, pfx##302, sfx),      PORT_1(fn, pfx##303, sfx),      \
  98         PORT_1(fn, pfx##304, sfx),      PORT_1(fn, pfx##305, sfx),      \
  99         PORT_1(fn, pfx##306, sfx),      PORT_1(fn, pfx##307, sfx),      \
 100         PORT_1(fn, pfx##308, sfx),                                      \
 101         /* Port320 - Port329 */                                         \
 102         PORT_10(fn, pfx##32, sfx)
 103
 104
 105 enum {
 106         PINMUX_RESERVED = 0,
 107
 108         /* PORT0_DATA -> PORT329_DATA */
 109         PINMUX_DATA_BEGIN,
 110         PORT_ALL(DATA),
 111         PINMUX_DATA_END,
 112
 113         /* PORT0_IN -> PORT329_IN */
 114         PINMUX_INPUT_BEGIN,
 115         PORT_ALL(IN),
 116         PINMUX_INPUT_END,
 117
 118         /* PORT0_IN_PU -> PORT329_IN_PU */
 119         PINMUX_INPUT_PULLUP_BEGIN,
 120         PORT_ALL(IN_PU),
 121         PINMUX_INPUT_PULLUP_END,
 122
 123         /* PORT0_IN_PD -> PORT329_IN_PD */
 124         PINMUX_INPUT_PULLDOWN_BEGIN,
 125         PORT_ALL(IN_PD),
 126         PINMUX_INPUT_PULLDOWN_END,
 127
 128         /* PORT0_OUT -> PORT329_OUT */
 129         PINMUX_OUTPUT_BEGIN,
 130         PORT_ALL(OUT),
 131         PINMUX_OUTPUT_END,
 132
 133         PINMUX_FUNCTION_BEGIN,
 134         PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
 135         PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
 136         PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
 137         PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
 138         PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
 139         PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
 140         PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
 141         PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
 142         PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
 143         PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
 144
 145         MSEL1CR_31_0, MSEL1CR_31_1,
 146         MSEL1CR_27_0, MSEL1CR_27_1,
 147         MSEL1CR_25_0, MSEL1CR_25_1,
 148         MSEL1CR_24_0, MSEL1CR_24_1,
 149         MSEL1CR_22_0, MSEL1CR_22_1,
 150         MSEL1CR_21_0, MSEL1CR_21_1,
 151         MSEL1CR_20_0, MSEL1CR_20_1,
 152         MSEL1CR_19_0, MSEL1CR_19_1,
 153         MSEL1CR_18_0, MSEL1CR_18_1,
 154         MSEL1CR_17_0, MSEL1CR_17_1,
 155         MSEL1CR_16_0, MSEL1CR_16_1,
 156         MSEL1CR_15_0, MSEL1CR_15_1,
 157         MSEL1CR_14_0, MSEL1CR_14_1,
 158         MSEL1CR_13_0, MSEL1CR_13_1,
 159         MSEL1CR_12_0, MSEL1CR_12_1,
 160         MSEL1CR_11_0, MSEL1CR_11_1,
 161         MSEL1CR_10_0, MSEL1CR_10_1,
 162         MSEL1CR_09_0, MSEL1CR_09_1,
 163         MSEL1CR_08_0, MSEL1CR_08_1,
 164         MSEL1CR_07_0, MSEL1CR_07_1,
 165         MSEL1CR_06_0, MSEL1CR_06_1,
 166         MSEL1CR_05_0, MSEL1CR_05_1,
 167         MSEL1CR_04_0, MSEL1CR_04_1,
 168         MSEL1CR_03_0, MSEL1CR_03_1,
 169         MSEL1CR_02_0, MSEL1CR_02_1,
 170         MSEL1CR_01_0, MSEL1CR_01_1,
 171         MSEL1CR_00_0, MSEL1CR_00_1,
 172
 173         MSEL3CR_31_0, MSEL3CR_31_1,
 174         MSEL3CR_28_0, MSEL3CR_28_1,
 175         MSEL3CR_27_0, MSEL3CR_27_1,
 176         MSEL3CR_26_0, MSEL3CR_26_1,
 177         MSEL3CR_23_0, MSEL3CR_23_1,
 178         MSEL3CR_22_0, MSEL3CR_22_1,
 179         MSEL3CR_21_0, MSEL3CR_21_1,
 180         MSEL3CR_20_0, MSEL3CR_20_1,
 181         MSEL3CR_19_0, MSEL3CR_19_1,
 182         MSEL3CR_18_0, MSEL3CR_18_1,
 183         MSEL3CR_17_0, MSEL3CR_17_1,
 184         MSEL3CR_16_0, MSEL3CR_16_1,
 185         MSEL3CR_15_0, MSEL3CR_15_1,
 186         MSEL3CR_12_0, MSEL3CR_12_1,
 187         MSEL3CR_11_0, MSEL3CR_11_1,
 188         MSEL3CR_10_0, MSEL3CR_10_1,
 189         MSEL3CR_09_0, MSEL3CR_09_1,
 190         MSEL3CR_06_0, MSEL3CR_06_1,
 191         MSEL3CR_03_0, MSEL3CR_03_1,
 192         MSEL3CR_01_0, MSEL3CR_01_1,
 193         MSEL3CR_00_0, MSEL3CR_00_1,
 194
 195         MSEL4CR_30_0, MSEL4CR_30_1,
 196         MSEL4CR_29_0, MSEL4CR_29_1,
 197         MSEL4CR_28_0, MSEL4CR_28_1,
 198         MSEL4CR_27_0, MSEL4CR_27_1,
 199         MSEL4CR_26_0, MSEL4CR_26_1,
 200         MSEL4CR_25_0, MSEL4CR_25_1,
 201         MSEL4CR_24_0, MSEL4CR_24_1,
 202         MSEL4CR_23_0, MSEL4CR_23_1,
 203         MSEL4CR_22_0, MSEL4CR_22_1,
 204         MSEL4CR_21_0, MSEL4CR_21_1,
 205         MSEL4CR_20_0, MSEL4CR_20_1,
 206         MSEL4CR_19_0, MSEL4CR_19_1,
 207         MSEL4CR_18_0, MSEL4CR_18_1,
 208         MSEL4CR_17_0, MSEL4CR_17_1,
 209         MSEL4CR_16_0, MSEL4CR_16_1,
 210         MSEL4CR_15_0, MSEL4CR_15_1,
 211         MSEL4CR_14_0, MSEL4CR_14_1,
 212         MSEL4CR_13_0, MSEL4CR_13_1,
 213         MSEL4CR_12_0, MSEL4CR_12_1,
 214         MSEL4CR_11_0, MSEL4CR_11_1,
 215         MSEL4CR_10_0, MSEL4CR_10_1,
 216         MSEL4CR_09_0, MSEL4CR_09_1,
 217         MSEL4CR_07_0, MSEL4CR_07_1,
 218         MSEL4CR_04_0, MSEL4CR_04_1,
 219         MSEL4CR_01_0, MSEL4CR_01_1,
 220
 221         MSEL5CR_31_0, MSEL5CR_31_1,
 222         MSEL5CR_30_0, MSEL5CR_30_1,
 223         MSEL5CR_29_0, MSEL5CR_29_1,
 224         MSEL5CR_28_0, MSEL5CR_28_1,
 225         MSEL5CR_27_0, MSEL5CR_27_1,
 226         MSEL5CR_26_0, MSEL5CR_26_1,
 227         MSEL5CR_25_0, MSEL5CR_25_1,
 228         MSEL5CR_24_0, MSEL5CR_24_1,
 229         MSEL5CR_23_0, MSEL5CR_23_1,
 230         MSEL5CR_22_0, MSEL5CR_22_1,
 231         MSEL5CR_21_0, MSEL5CR_21_1,
 232         MSEL5CR_20_0, MSEL5CR_20_1,
 233         MSEL5CR_19_0, MSEL5CR_19_1,
 234         MSEL5CR_18_0, MSEL5CR_18_1,
 235         MSEL5CR_17_0, MSEL5CR_17_1,
 236         MSEL5CR_16_0, MSEL5CR_16_1,
 237         MSEL5CR_15_0, MSEL5CR_15_1,
 238         MSEL5CR_14_0, MSEL5CR_14_1,
 239         MSEL5CR_13_0, MSEL5CR_13_1,
 240         MSEL5CR_12_0, MSEL5CR_12_1,
 241         MSEL5CR_11_0, MSEL5CR_11_1,
 242         MSEL5CR_10_0, MSEL5CR_10_1,
 243         MSEL5CR_09_0, MSEL5CR_09_1,
 244         MSEL5CR_08_0, MSEL5CR_08_1,
 245         MSEL5CR_07_0, MSEL5CR_07_1,
 246         MSEL5CR_06_0, MSEL5CR_06_1,
 247
 248         MSEL8CR_16_0, MSEL8CR_16_1,
 249         MSEL8CR_01_0, MSEL8CR_01_1,
 250         MSEL8CR_00_0, MSEL8CR_00_1,
 251
 252         PINMUX_FUNCTION_END,
 253
 254         PINMUX_MARK_BEGIN,
 255
 256
 257 #define F1(a)   a##_MARK
 258 #define F2(a)   a##_MARK
 259 #define F3(a)   a##_MARK
 260 #define F4(a)   a##_MARK
 261 #define F5(a)   a##_MARK
 262 #define F6(a)   a##_MARK
 263 #define F7(a)   a##_MARK
 264 #define IRQ(a)  IRQ##a##_MARK
 265
 266         F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
 267         F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
 268         F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
 269         F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
 270         F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
 271         F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
 272         F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
 273         F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
 274         F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
 275         F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
 276         F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
 277         F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
 278         F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
 279         F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
 280         F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
 281         F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
 282         F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
 283         F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
 284         F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
 285         F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
 286         F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
 287         F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
 288         F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
 289         F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
 290         F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
 291         F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
 292         F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
 293         F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
 294         F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
 295         F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
 296         F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
 297         F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
 298
 299         F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
 300         F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
 301         F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
 302         F1(SCIFA1_RTS), F7(CSCIF1_RTS),
 303         F1(SCIFA1_CTS), F7(CSCIF1_CTS),
 304         F1(SCIFA1_SCK), F7(CSCIF1_SCK),
 305         F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
 306         F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
 307         F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
 308         F7(CHSCIF0_HSCK), /* Port40 */
 309
 310         F1(PDM0_DATA), /* Port64 */
 311         F1(PDM1_DATA),
 312         F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
 313         IRQ(40),
 314         F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
 315         F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
 316         F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
 317         F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
 318         F7(CHSCIF1_HRTS), /* Port70 */
 319         F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
 320         F7(CHSCIF1_HCTS),
 321         F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
 322         F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
 323         F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
 324         F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
 325         F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
 326
 327         F1(KEYIN0), /* Port96 */
 328         F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
 329         F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
 330         F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
 331         F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
 332         F2(KEYOUT7), F5(RFANAEN), IRQ(45),
 333         F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
 334         F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
 335         F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
 336         F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
 337         F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
 338         F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
 339         F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
 340         F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
 341         F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
 342         F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
 343         F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
 344         F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
 345         F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
 346         F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
 347         F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
 348         F5(SIM0_VOLTSEL1), /* Port130 */
 349         F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
 350         F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
 351         F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
 352         IRQ(20), /* Port160 */
 353         IRQ(21), IRQ(22), IRQ(23),
 354         F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
 355         F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
 356         F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
 357         IRQ(24), IRQ(25), IRQ(26), IRQ(27),
 358         F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
 359         F1(A9), F2(MMCD1_6), IRQ(32),
 360         F1(A8), F2(MMCD1_5), IRQ(33),
 361         F1(A7), F2(MMCD1_4), IRQ(34),
 362         F1(A6), F2(MMCD1_3), IRQ(35),
 363         F1(A5), F2(MMCD1_2), IRQ(36),
 364         F1(A4), F2(MMCD1_1), IRQ(37),
 365         F1(A3), F2(MMCD1_0), IRQ(38),
 366         F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
 367         F1(A1),
 368         F1(A0), F2(BS),
 369         F1(CKO), F2(MMCCLK1),
 370         F1(CS0_N), F5(SIM0_GPO1),
 371         F1(CS2_N), F5(SIM0_GPO2),
 372         F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
 373         F1(D15), F5(GIO_OUT15),
 374         F1(D14), F5(GIO_OUT14),
 375         F1(D13), F5(GIO_OUT13),
 376         F1(D12), F5(GIO_OUT12), /* Port210 */
 377         F1(D11), F5(WGM_TXP2),
 378         F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
 379         F1(D9), F2(VIO_D9), F5(GIO_OUT9),
 380         F1(D8), F2(VIO_D8), F5(GIO_OUT8),
 381         F1(D7), F2(VIO_D7), F5(GIO_OUT7),
 382         F1(D6), F2(VIO_D6), F5(GIO_OUT6),
 383         F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
 384         F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
 385         F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
 386         F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
 387         F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
 388         F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
 389         F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
 390         F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
 391         F1(WE0_N), F2(RDWR_227),
 392         F1(WE1_N), F5(SIM0_GPO0),
 393         F1(PWMO), F2(VIO_CKO1_229),
 394         F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
 395         F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
 396         F2(VIO_CKO3_233), F4(SF_PORT_1_233),
 397         F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
 398         F1(FSIAISLD), F2(PDM3_DATA_235),
 399         F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
 400         F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
 401         F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
 402         F1(FSIBISLD), /* Port240 */
 403         F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
 404         F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
 405         F1(FSIBCK), F3(ISP_SHUTTER0_245),
 406         F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
 407         F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
 408         F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
 409         F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
 410         F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
 411         F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
 412         F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
 413         F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
 414         F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
 415         F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
 416         F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
 417         F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
 418         F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
 419         F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
 420         F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
 421         F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
 422         F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
 423         F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
 424         F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
 425         F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
 426         F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
 427         F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
 428         F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
 429         F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
 430         F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
 431         F4(MSIOF6_SS1), /* Port300 */
 432         F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
 433         F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
 434         F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
 435         F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
 436         IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
 437         IRQ(55), IRQ(56), IRQ(57),
 438         PINMUX_MARK_END,
 439 };
 440
 441 static const pinmux_enum_t pinmux_data[] = {
 442         /* specify valid pin states for each pin in GPIO mode */
 443
 444         PORT_DATA_IO_PU_PD(0), PORT_DATA_IO_PU_PD(1),
 445         PORT_DATA_IO_PU_PD(2), PORT_DATA_IO_PU_PD(3),
 446         PORT_DATA_IO_PU_PD(4), PORT_DATA_IO_PU_PD(5),
 447         PORT_DATA_IO_PU_PD(6), PORT_DATA_IO_PU_PD(7),
 448         PORT_DATA_IO_PU_PD(8), PORT_DATA_IO_PU_PD(9),
 449
 450         PORT_DATA_IO_PU_PD(10), PORT_DATA_IO_PU_PD(11),
 451         PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PU_PD(13),
 452         PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
 453         PORT_DATA_IO_PU_PD(16), PORT_DATA_IO_PU_PD(17),
 454         PORT_DATA_IO_PU_PD(18), PORT_DATA_IO_PU_PD(19),
 455
 456         PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PU_PD(21),
 457         PORT_DATA_IO_PU_PD(22), PORT_DATA_IO_PU_PD(23),
 458         PORT_DATA_IO_PU_PD(24), PORT_DATA_IO_PU_PD(25),
 459         PORT_DATA_IO_PU_PD(26), PORT_DATA_IO_PU_PD(27),
 460         PORT_DATA_IO_PU_PD(28), PORT_DATA_IO_PU_PD(29),
 461
 462         PORT_DATA_IO_PU_PD(30), PORT_DATA_IO_PU_PD(32),
 463         PORT_DATA_IO_PU_PD(33), PORT_DATA_IO_PU_PD(34),
 464         PORT_DATA_IO_PU_PD(35), PORT_DATA_IO_PU_PD(36),
 465         PORT_DATA_IO_PU_PD(37), PORT_DATA_IO_PU_PD(38),
 466         PORT_DATA_IO_PU_PD(39), PORT_DATA_IO_PU_PD(40),
 467
 468         PORT_DATA_IO_PU_PD(64), PORT_DATA_IO_PU_PD(65),
 469         PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
 470         PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
 471
 472         PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
 473         PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
 474         PORT_DATA_O(74), PORT_DATA_IO_PU_PD(75),
 475         PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
 476         PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
 477
 478         PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
 479         PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83),
 480         PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85),
 481
 482         PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
 483         PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
 484
 485         PORT_DATA_IO_PU_PD(100), PORT_DATA_IO_PU_PD(101),
 486         PORT_DATA_IO_PU_PD(102), PORT_DATA_IO_PU_PD(103),
 487         PORT_DATA_IO_PU_PD(104), PORT_DATA_IO_PU_PD(105),
 488         PORT_DATA_IO_PU_PD(106), PORT_DATA_IO_PU_PD(107),
 489         PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
 490
 491         PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
 492         PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
 493         PORT_DATA_IO_PU_PD(114), PORT_DATA_IO_PU_PD(115),
 494         PORT_DATA_IO_PU_PD(116), PORT_DATA_IO_PU_PD(117),
 495         PORT_DATA_IO_PU_PD(118), PORT_DATA_IO_PU_PD(119),
 496
 497         PORT_DATA_IO_PU_PD(120), PORT_DATA_IO_PU_PD(121),
 498         PORT_DATA_IO_PU_PD(122), PORT_DATA_IO_PU_PD(123),
 499         PORT_DATA_IO_PU_PD(124), PORT_DATA_IO_PU_PD(125),
 500         PORT_DATA_IO_PU_PD(126),
 501         PORT_DATA_IO_PU_PD(128), PORT_DATA_IO_PU_PD(129),
 502
 503         PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131),
 504         PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133),
 505         PORT_DATA_IO_PU_PD(134),
 506
 507         PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PU_PD(161),
 508         PORT_DATA_IO_PU_PD(162), PORT_DATA_IO_PU_PD(163),
 509         PORT_DATA_IO_PU_PD(164), PORT_DATA_IO_PU_PD(165),
 510         PORT_DATA_IO_PU_PD(166), PORT_DATA_IO_PU_PD(167),
 511         PORT_DATA_IO_PU_PD(168), PORT_DATA_IO_PU_PD(169),
 512
 513         PORT_DATA_IO_PU_PD(170), PORT_DATA_IO_PU_PD(171),
 514         PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173),
 515         PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175),
 516         PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177),
 517         PORT_DATA_IO_PU_PD(178),
 518
 519         PORT_DATA_IO_PU_PD(192), PORT_DATA_IO_PU_PD(193),
 520         PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PU_PD(195),
 521         PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PU_PD(197),
 522         PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
 523
 524         PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU_PD(201),
 525         PORT_DATA_IO_PU_PD(202), PORT_DATA_IO_PU_PD(203),
 526         PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
 527         PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
 528         PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PU_PD(209),
 529
 530         PORT_DATA_IO_PU_PD(210), PORT_DATA_IO_PU_PD(211),
 531         PORT_DATA_IO_PU_PD(212), PORT_DATA_IO_PU_PD(213),
 532         PORT_DATA_IO_PU_PD(214), PORT_DATA_IO_PU_PD(215),
 533         PORT_DATA_IO_PU_PD(216), PORT_DATA_IO_PU_PD(217),
 534         PORT_DATA_IO_PU_PD(218), PORT_DATA_IO_PU_PD(219),
 535
 536         PORT_DATA_IO_PU_PD(220), PORT_DATA_IO_PU_PD(221),
 537         PORT_DATA_IO_PU_PD(222), PORT_DATA_IO_PU_PD(224),
 538         PORT_DATA_IO_PU_PD(225), PORT_DATA_IO_PU_PD(226),
 539         PORT_DATA_IO_PU_PD(227), PORT_DATA_IO_PU_PD(228),
 540         PORT_DATA_IO_PU_PD(229),
 541
 542         PORT_DATA_IO_PU_PD(230), PORT_DATA_IO_PU_PD(231),
 543         PORT_DATA_IO_PU_PD(232), PORT_DATA_IO_PU_PD(233),
 544         PORT_DATA_IO_PU_PD(234), PORT_DATA_IO_PU_PD(235),
 545         PORT_DATA_IO_PU_PD(236), PORT_DATA_IO_PU_PD(237),
 546         PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
 547
 548         PORT_DATA_IO_PU_PD(240), PORT_DATA_IO_PU_PD(241),
 549         PORT_DATA_IO_PU_PD(242), PORT_DATA_IO_PU_PD(243),
 550         PORT_DATA_IO_PU_PD(244), PORT_DATA_IO_PU_PD(245),
 551         PORT_DATA_IO_PU_PD(246), PORT_DATA_IO_PU_PD(247),
 552         PORT_DATA_IO_PU_PD(248), PORT_DATA_IO_PU_PD(249),
 553
 554         PORT_DATA_IO_PU_PD(250),
 555         PORT_DATA_IO_PU_PD(256), PORT_DATA_IO_PU_PD(257),
 556         PORT_DATA_IO_PU_PD(258), PORT_DATA_IO_PU_PD(259),
 557
 558         PORT_DATA_IO_PU_PD(260), PORT_DATA_IO_PU_PD(261),
 559         PORT_DATA_IO_PU_PD(262), PORT_DATA_IO_PU_PD(263),
 560         PORT_DATA_IO_PU_PD(264), PORT_DATA_IO_PU_PD(265),
 561         PORT_DATA_IO_PU_PD(266), PORT_DATA_IO_PU_PD(267),
 562         PORT_DATA_IO_PU_PD(268), PORT_DATA_IO_PU_PD(269),
 563
 564         PORT_DATA_IO_PU_PD(270), PORT_DATA_IO_PU_PD(271),
 565         PORT_DATA_IO_PU_PD(272), PORT_DATA_IO_PU_PD(273),
 566         PORT_DATA_IO_PU_PD(274), PORT_DATA_IO_PU_PD(275),
 567         PORT_DATA_IO_PU_PD(276), PORT_DATA_IO_PU_PD(277),
 568         PORT_DATA_IO_PU_PD(278), PORT_DATA_IO_PU_PD(279),
 569
 570         PORT_DATA_IO_PU_PD(280), PORT_DATA_IO_PU_PD(281),
 571         PORT_DATA_IO_PU_PD(282), PORT_DATA_IO_PU_PD(283),
 572         PORT_DATA_O(288), PORT_DATA_IO_PU_PD(289),
 573
 574         PORT_DATA_IO_PU_PD(290), PORT_DATA_IO_PU_PD(291),
 575         PORT_DATA_IO_PU_PD(292), PORT_DATA_IO_PU_PD(293),
 576         PORT_DATA_IO_PU_PD(294), PORT_DATA_IO_PU_PD(295),
 577         PORT_DATA_IO_PU_PD(296), PORT_DATA_IO_PU_PD(297),
 578         PORT_DATA_IO_PU_PD(298), PORT_DATA_IO_PU_PD(299),
 579
 580         PORT_DATA_IO_PU_PD(300), PORT_DATA_IO_PU_PD(301),
 581         PORT_DATA_IO_PU_PD(302), PORT_DATA_IO_PU_PD(303),
 582         PORT_DATA_IO_PU_PD(304), PORT_DATA_IO_PU_PD(305),
 583         PORT_DATA_IO_PU_PD(306), PORT_DATA_IO_PU_PD(307),
 584         PORT_DATA_IO_PU_PD(308),
 585
 586         PORT_DATA_IO_PU_PD(320), PORT_DATA_IO_PU_PD(321),
 587         PORT_DATA_IO_PU_PD(322), PORT_DATA_IO_PU_PD(323),
 588         PORT_DATA_IO_PU_PD(324), PORT_DATA_IO_PU_PD(325),
 589         PORT_DATA_IO_PU_PD(326), PORT_DATA_IO_PU_PD(327),
 590         PORT_DATA_IO_PU_PD(328), PORT_DATA_IO_PU_PD(329),
 591
 592         /* Port0 */
 593         PINMUX_DATA(LCDD0_MARK,         PORT0_FN1),
 594         PINMUX_DATA(PDM2_CLK_0_MARK,    PORT0_FN3),
 595         PINMUX_DATA(DU0_DR0_MARK,       PORT0_FN7),
 596         PINMUX_DATA(IRQ0_MARK,          PORT0_FN0),
 597
 598         /* Port1 */
 599         PINMUX_DATA(LCDD1_MARK,         PORT1_FN1),
 600         PINMUX_DATA(PDM2_DATA_1_MARK,   PORT1_FN3,      MSEL3CR_12_0),
 601         PINMUX_DATA(DU0_DR19_MARK,      PORT1_FN7),
 602         PINMUX_DATA(IRQ1_MARK,          PORT1_FN0),
 603
 604         /* Port2 */
 605         PINMUX_DATA(LCDD2_MARK,         PORT2_FN1),
 606         PINMUX_DATA(PDM3_CLK_2_MARK,    PORT2_FN3),
 607         PINMUX_DATA(DU0_DR2_MARK,       PORT2_FN7),
 608         PINMUX_DATA(IRQ2_MARK,          PORT2_FN0),
 609
 610         /* Port3 */
 611         PINMUX_DATA(LCDD3_MARK,         PORT3_FN1),
 612         PINMUX_DATA(PDM3_DATA_3_MARK,   PORT3_FN3,      MSEL3CR_12_0),
 613         PINMUX_DATA(DU0_DR3_MARK,       PORT3_FN7),
 614         PINMUX_DATA(IRQ3_MARK,          PORT3_FN0),
 615
 616         /* Port4 */
 617         PINMUX_DATA(LCDD4_MARK,         PORT4_FN1),
 618         PINMUX_DATA(PDM4_CLK_4_MARK,    PORT4_FN3),
 619         PINMUX_DATA(DU0_DR4_MARK,       PORT4_FN7),
 620         PINMUX_DATA(IRQ4_MARK,          PORT4_FN0),
 621
 622         /* Port5 */
 623         PINMUX_DATA(LCDD5_MARK,         PORT5_FN1),
 624         PINMUX_DATA(PDM4_DATA_5_MARK,   PORT5_FN3,      MSEL3CR_12_0),
 625         PINMUX_DATA(DU0_DR5_MARK,       PORT5_FN7),
 626         PINMUX_DATA(IRQ5_MARK,          PORT5_FN0),
 627
 628         /* Port6 */
 629         PINMUX_DATA(LCDD6_MARK,         PORT6_FN1),
 630         PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
 631         PINMUX_DATA(DU0_DR6_MARK,       PORT6_FN7),
 632         PINMUX_DATA(IRQ6_MARK,          PORT6_FN0),
 633
 634         /* Port7 */
 635         PINMUX_DATA(LCDD7_MARK,                 PORT7_FN1),
 636         PINMUX_DATA(PDM0_OUTDATA_7_MARK,        PORT7_FN3),
 637         PINMUX_DATA(DU0_DR7_MARK,               PORT7_FN7),
 638         PINMUX_DATA(IRQ7_MARK,                  PORT7_FN0),
 639
 640         /* Port8 */
 641         PINMUX_DATA(LCDD8_MARK,         PORT8_FN1),
 642         PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
 643         PINMUX_DATA(DU0_DG0_MARK,       PORT8_FN7),
 644         PINMUX_DATA(IRQ8_MARK,          PORT8_FN0),
 645
 646         /* Port9 */
 647         PINMUX_DATA(LCDD9_MARK,         PORT9_FN1),
 648         PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
 649         PINMUX_DATA(DU0_DG1_MARK,       PORT9_FN7),
 650         PINMUX_DATA(IRQ9_MARK,          PORT9_FN0),
 651
 652         /* Port10 */
 653         PINMUX_DATA(LCDD10_MARK,                PORT10_FN1),
 654         PINMUX_DATA(FSICCK_MARK,                PORT10_FN3),
 655         PINMUX_DATA(DU0_DG2_MARK,               PORT10_FN7),
 656         PINMUX_DATA(IRQ10_MARK,                 PORT10_FN0),
 657
 658         /* Port11 */
 659         PINMUX_DATA(LCDD11_MARK,                PORT11_FN1),
 660         PINMUX_DATA(FSICISLD_MARK,              PORT11_FN3),
 661         PINMUX_DATA(DU0_DG3_MARK,               PORT11_FN7),
 662         PINMUX_DATA(IRQ11_MARK,                 PORT11_FN0),
 663
 664         /* Port12 */
 665         PINMUX_DATA(LCDD12_MARK,                PORT12_FN1),
 666         PINMUX_DATA(FSICOMC_MARK,               PORT12_FN3),
 667         PINMUX_DATA(DU0_DG4_MARK,               PORT12_FN7),
 668         PINMUX_DATA(IRQ12_MARK,                 PORT12_FN0),
 669
 670         /* Port13 */
 671         PINMUX_DATA(LCDD13_MARK,                PORT13_FN1),
 672         PINMUX_DATA(FSICOLR_MARK,               PORT13_FN3),
 673         PINMUX_DATA(FSICILR_MARK,               PORT13_FN4),
 674         PINMUX_DATA(DU0_DG5_MARK,               PORT13_FN7),
 675         PINMUX_DATA(IRQ13_MARK,                 PORT13_FN0),
 676
 677         /* Port14 */
 678         PINMUX_DATA(LCDD14_MARK,                PORT14_FN1),
 679         PINMUX_DATA(FSICOBT_MARK,               PORT14_FN3),
 680         PINMUX_DATA(FSICIBT_MARK,               PORT14_FN4),
 681         PINMUX_DATA(DU0_DG6_MARK,               PORT14_FN7),
 682         PINMUX_DATA(IRQ14_MARK,                 PORT14_FN0),
 683
 684         /* Port15 */
 685         PINMUX_DATA(LCDD15_MARK,                PORT15_FN1),
 686         PINMUX_DATA(FSICOSLD_MARK,              PORT15_FN3),
 687         PINMUX_DATA(DU0_DG7_MARK,               PORT15_FN7),
 688         PINMUX_DATA(IRQ15_MARK,                 PORT15_FN0),
 689
 690         /* Port16 */
 691         PINMUX_DATA(LCDD16_MARK,                PORT16_FN1),
 692         PINMUX_DATA(TPU1TO1_MARK,               PORT16_FN4),
 693         PINMUX_DATA(DU0_DB0_MARK,               PORT16_FN7),
 694
 695         /* Port17 */
 696         PINMUX_DATA(LCDD17_MARK,                PORT17_FN1),
 697         PINMUX_DATA(SF_IRQ_00_MARK,             PORT17_FN4),
 698         PINMUX_DATA(DU0_DB1_MARK,               PORT17_FN7),
 699
 700         /* Port18 */
 701         PINMUX_DATA(LCDD18_MARK,                PORT18_FN1),
 702         PINMUX_DATA(SF_IRQ_01_MARK,             PORT18_FN4),
 703         PINMUX_DATA(DU0_DB2_MARK,               PORT18_FN7),
 704
 705         /* Port19 */
 706         PINMUX_DATA(LCDD19_MARK,                PORT19_FN1),
 707         PINMUX_DATA(SCIFB3_RTS_19_MARK,         PORT19_FN3),
 708         PINMUX_DATA(DU0_DB3_MARK,               PORT19_FN7),
 709
 710         /* Port20 */
 711         PINMUX_DATA(LCDD20_MARK,                PORT20_FN1),
 712         PINMUX_DATA(SCIFB3_CTS_20_MARK,         PORT20_FN3,     MSEL3CR_09_0),
 713         PINMUX_DATA(DU0_DB4_MARK,               PORT20_FN7),
 714
 715         /* Port21 */
 716         PINMUX_DATA(LCDD21_MARK,                PORT21_FN1),
 717         PINMUX_DATA(SCIFB3_TXD_21_MARK,         PORT21_FN3,     MSEL3CR_09_0),
 718         PINMUX_DATA(DU0_DB5_MARK,               PORT21_FN7),
 719
 720         /* Port22 */
 721         PINMUX_DATA(LCDD22_MARK,                PORT22_FN1),
 722         PINMUX_DATA(SCIFB3_RXD_22_MARK,         PORT22_FN3,     MSEL3CR_09_0),
 723         PINMUX_DATA(DU0_DB6_MARK,               PORT22_FN7),
 724
 725         /* Port23 */
 726         PINMUX_DATA(LCDD23_MARK,                PORT23_FN1),
 727         PINMUX_DATA(SCIFB3_SCK_23_MARK,         PORT23_FN3),
 728         PINMUX_DATA(DU0_DB7_MARK,               PORT23_FN7),
 729
 730         /* Port24 */
 731         PINMUX_DATA(LCDHSYN_MARK,                       PORT24_FN1),
 732         PINMUX_DATA(LCDCS_MARK,                         PORT24_FN2),
 733         PINMUX_DATA(SCIFB1_RTS_24_MARK,                 PORT24_FN3),
 734         PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
 735
 736         /* Port25 */
 737         PINMUX_DATA(LCDVSYN_MARK,                       PORT25_FN1),
 738         PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
 739         PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
 740
 741         /* Port26 */
 742         PINMUX_DATA(LCDDCK_MARK,                PORT26_FN1),
 743         PINMUX_DATA(LCDWR_MARK,                 PORT26_FN2),
 744         PINMUX_DATA(SCIFB1_TXD_26_MARK,         PORT26_FN3,     MSEL3CR_11_0),
 745         PINMUX_DATA(DU0_DOTCLKIN_MARK,          PORT26_FN7),
 746
 747         /* Port27 */
 748         PINMUX_DATA(LCDDISP_MARK,               PORT27_FN1),
 749         PINMUX_DATA(LCDRS_MARK,                 PORT27_FN2),
 750         PINMUX_DATA(SCIFB1_RXD_27_MARK,         PORT27_FN3,     MSEL3CR_11_0),
 751         PINMUX_DATA(DU0_DOTCLKOUT_MARK,         PORT27_FN7),
 752
 753         /* Port28 */
 754         PINMUX_DATA(LCDRD_N_MARK,               PORT28_FN1),
 755         PINMUX_DATA(SCIFB1_SCK_28_MARK,         PORT28_FN3),
 756         PINMUX_DATA(DU0_DOTCLKOUTB_MARK,        PORT28_FN7),
 757
 758         /* Port29 */
 759         PINMUX_DATA(LCDLCLK_MARK,               PORT29_FN1),
 760         PINMUX_DATA(SF_IRQ_02_MARK,             PORT29_FN4),
 761         PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK,   PORT29_FN7),
 762
 763         /* Port30 */
 764         PINMUX_DATA(LCDDON_MARK,                PORT30_FN1),
 765         PINMUX_DATA(SF_IRQ_03_MARK,             PORT30_FN4),
 766         PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK,      PORT30_FN7),
 767
 768         /* Port32 */
 769         PINMUX_DATA(SCIFA0_RTS_MARK,            PORT32_FN1),
 770         PINMUX_DATA(SIM0_DET_MARK,              PORT32_FN5),
 771         PINMUX_DATA(CSCIF0_RTS_MARK,            PORT32_FN7),
 772
 773         /* Port33 */
 774         PINMUX_DATA(SCIFA0_CTS_MARK,            PORT33_FN1),
 775         PINMUX_DATA(SIM1_DET_MARK,              PORT33_FN5),
 776         PINMUX_DATA(CSCIF0_CTS_MARK,            PORT33_FN7),
 777
 778         /* Port34 */
 779         PINMUX_DATA(SCIFA0_SCK_MARK,            PORT34_FN1),
 780         PINMUX_DATA(SIM0_PWRON_MARK,            PORT34_FN5),
 781         PINMUX_DATA(CSCIF0_SCK_MARK,            PORT34_FN7),
 782
 783         /* Port35 */
 784         PINMUX_DATA(SCIFA1_RTS_MARK,            PORT35_FN1),
 785         PINMUX_DATA(CSCIF1_RTS_MARK,            PORT35_FN7),
 786
 787         /* Port36 */
 788         PINMUX_DATA(SCIFA1_CTS_MARK,            PORT36_FN1),
 789         PINMUX_DATA(CSCIF1_CTS_MARK,            PORT36_FN7),
 790
 791         /* Port37 */
 792         PINMUX_DATA(SCIFA1_SCK_MARK,            PORT37_FN1),
 793         PINMUX_DATA(CSCIF1_SCK_MARK,            PORT37_FN7),
 794
 795         /* Port38 */
 796         PINMUX_DATA(SCIFB0_RTS_MARK,            PORT38_FN1),
 797         PINMUX_DATA(TPU0TO1_MARK,               PORT38_FN3),
 798         PINMUX_DATA(SCIFB3_RTS_38_MARK,         PORT38_FN4),
 799         PINMUX_DATA(CHSCIF0_HRTS_MARK,          PORT38_FN7),
 800
 801         /* Port39 */
 802         PINMUX_DATA(SCIFB0_CTS_MARK,            PORT39_FN1),
 803         PINMUX_DATA(TPU0TO2_MARK,               PORT39_FN3),
 804         PINMUX_DATA(SCIFB3_CTS_39_MARK,         PORT39_FN4,     MSEL3CR_09_1),
 805         PINMUX_DATA(CHSCIF0_HCTS_MARK,          PORT39_FN7),
 806
 807         /* Port40 */
 808         PINMUX_DATA(SCIFB0_SCK_MARK,            PORT40_FN1),
 809         PINMUX_DATA(TPU0TO3_MARK,               PORT40_FN3),
 810         PINMUX_DATA(SCIFB3_SCK_40_MARK,         PORT40_FN4),
 811         PINMUX_DATA(CHSCIF0_HSCK_MARK,          PORT40_FN7),
 812
 813         /* Port64 */
 814         PINMUX_DATA(PDM0_DATA_MARK,             PORT64_FN1),
 815
 816         /* Port65 */
 817         PINMUX_DATA(PDM1_DATA_MARK,             PORT65_FN1),
 818
 819         /* Port66 */
 820         PINMUX_DATA(HSI_RX_WAKE_MARK,           PORT66_FN1),
 821         PINMUX_DATA(SCIFB2_CTS_66_MARK,         PORT66_FN2,     MSEL3CR_10_0),
 822         PINMUX_DATA(MSIOF3_SYNC_MARK,           PORT66_FN3),
 823         PINMUX_DATA(GenIO4_MARK,                PORT66_FN5),
 824         PINMUX_DATA(IRQ40_MARK,                 PORT66_FN0),
 825
 826         /* Port67 */
 827         PINMUX_DATA(HSI_RX_READY_MARK,          PORT67_FN1),
 828         PINMUX_DATA(SCIFB1_TXD_67_MARK,         PORT67_FN2,     MSEL3CR_11_1),
 829         PINMUX_DATA(GIO_OUT3_67_MARK,           PORT67_FN5),
 830         PINMUX_DATA(CHSCIF1_HTX_MARK,           PORT67_FN7),
 831
 832         /* Port68 */
 833         PINMUX_DATA(HSI_RX_FLAG_MARK,           PORT68_FN1),
 834         PINMUX_DATA(SCIFB2_TXD_68_MARK,         PORT68_FN2,     MSEL3CR_10_0),
 835         PINMUX_DATA(MSIOF3_TXD_MARK,            PORT68_FN3),
 836         PINMUX_DATA(GIO_OUT4_68_MARK,           PORT68_FN5),
 837
 838         /* Port69 */
 839         PINMUX_DATA(HSI_RX_DATA_MARK,           PORT69_FN1),
 840         PINMUX_DATA(SCIFB2_RXD_69_MARK,         PORT69_FN2,     MSEL3CR_10_0),
 841         PINMUX_DATA(MSIOF3_RXD_MARK,            PORT69_FN3),
 842         PINMUX_DATA(GIO_OUT5_69_MARK,           PORT69_FN5),
 843
 844         /* Port70 */
 845         PINMUX_DATA(HSI_TX_FLAG_MARK,           PORT70_FN1),
 846         PINMUX_DATA(SCIFB1_RTS_70_MARK,         PORT70_FN2),
 847         PINMUX_DATA(GIO_OUT1_70_MARK,           PORT70_FN5),
 848         PINMUX_DATA(HSIC_TSTCLK0_MARK,          PORT70_FN6),
 849         PINMUX_DATA(CHSCIF1_HRTS_MARK,          PORT70_FN7),
 850
 851         /* Port71 */
 852         PINMUX_DATA(HSI_TX_DATA_MARK,           PORT71_FN1),
 853         PINMUX_DATA(SCIFB1_CTS_71_MARK,         PORT71_FN2,     MSEL3CR_11_1),
 854         PINMUX_DATA(GIO_OUT2_71_MARK,           PORT71_FN5),
 855         PINMUX_DATA(HSIC_TSTCLK1_MARK,          PORT71_FN6),
 856         PINMUX_DATA(CHSCIF1_HCTS_MARK,          PORT71_FN7),
 857
 858         /* Port72 */
 859         PINMUX_DATA(HSI_TX_WAKE_MARK,           PORT72_FN1),
 860         PINMUX_DATA(SCIFB1_RXD_72_MARK,         PORT72_FN2,     MSEL3CR_11_1),
 861         PINMUX_DATA(GenIO8_MARK,                PORT72_FN5),
 862         PINMUX_DATA(CHSCIF1_HRX_MARK,           PORT72_FN7),
 863
 864         /* Port73 */
 865         PINMUX_DATA(HSI_TX_READY_MARK,          PORT73_FN1),
 866         PINMUX_DATA(SCIFB2_RTS_73_MARK,         PORT73_FN2),
 867         PINMUX_DATA(MSIOF3_SCK_MARK,            PORT73_FN3),
 868         PINMUX_DATA(GIO_OUT0_73_MARK,           PORT73_FN5),
 869
 870         /* Port74 - Port85 */
 871         PINMUX_DATA(IRDA_OUT_MARK,              PORT74_FN1),
 872         PINMUX_DATA(IRDA_IN_MARK,               PORT75_FN1),
 873         PINMUX_DATA(IRDA_FIRSEL_MARK,           PORT76_FN1),
 874         PINMUX_DATA(TPU0TO0_MARK,               PORT77_FN1),
 875         PINMUX_DATA(DIGRFEN_MARK,               PORT78_FN1),
 876         PINMUX_DATA(GPS_TIMESTAMP_MARK,         PORT79_FN1),
 877         PINMUX_DATA(TXP_MARK,                   PORT80_FN1),
 878         PINMUX_DATA(TXP2_MARK,                  PORT81_FN1),
 879         PINMUX_DATA(COEX_0_MARK,                PORT82_FN1),
 880         PINMUX_DATA(COEX_1_MARK,                PORT83_FN1),
 881         PINMUX_DATA(IRQ19_MARK,                 PORT84_FN0),
 882         PINMUX_DATA(IRQ18_MARK,                 PORT85_FN0),
 883
 884         /* Port96 - Port101 */
 885         PINMUX_DATA(KEYIN0_MARK,                PORT96_FN1),
 886         PINMUX_DATA(KEYIN1_MARK,                PORT97_FN1),
 887         PINMUX_DATA(KEYIN2_MARK,                PORT98_FN1),
 888         PINMUX_DATA(KEYIN3_MARK,                PORT99_FN1),
 889         PINMUX_DATA(KEYIN4_MARK,                PORT100_FN1),
 890         PINMUX_DATA(KEYIN5_MARK,                PORT101_FN1),
 891
 892         /* Port102 */
 893         PINMUX_DATA(KEYIN6_MARK,                PORT102_FN1),
 894         PINMUX_DATA(IRQ41_MARK,                 PORT102_FN0),
 895
 896         /* Port103 */
 897         PINMUX_DATA(KEYIN7_MARK,                PORT103_FN1),
 898         PINMUX_DATA(IRQ42_MARK,                 PORT103_FN0),
 899
 900         /* Port104 - Port108 */
 901         PINMUX_DATA(KEYOUT0_MARK,               PORT104_FN2),
 902         PINMUX_DATA(KEYOUT1_MARK,               PORT105_FN2),
 903         PINMUX_DATA(KEYOUT2_MARK,               PORT106_FN2),
 904         PINMUX_DATA(KEYOUT3_MARK,               PORT107_FN2),
 905         PINMUX_DATA(KEYOUT4_MARK,               PORT108_FN2),
 906
 907         /* Port109 */
 908         PINMUX_DATA(KEYOUT5_MARK,               PORT109_FN2),
 909         PINMUX_DATA(IRQ43_MARK,                 PORT109_FN0),
 910
 911         /* Port110 */
 912         PINMUX_DATA(KEYOUT6_MARK,               PORT110_FN2),
 913         PINMUX_DATA(IRQ44_MARK,                 PORT110_FN0),
 914
 915         /* Port111 */
 916         PINMUX_DATA(KEYOUT7_MARK,               PORT111_FN2),
 917         PINMUX_DATA(RFANAEN_MARK,               PORT111_FN5),
 918         PINMUX_DATA(IRQ45_MARK,                 PORT111_FN0),
 919
 920         /* Port112 */
 921         PINMUX_DATA(KEYIN8_MARK,                PORT112_FN1),
 922         PINMUX_DATA(KEYOUT8_MARK,               PORT112_FN2),
 923         PINMUX_DATA(SF_IRQ_04_MARK,             PORT112_FN4),
 924         PINMUX_DATA(IRQ46_MARK,                 PORT112_FN0),
 925
 926         /* Port113 */
 927         PINMUX_DATA(KEYIN9_MARK,                PORT113_FN1),
 928         PINMUX_DATA(KEYOUT9_MARK,               PORT113_FN2),
 929         PINMUX_DATA(SF_IRQ_05_MARK,             PORT113_FN4),
 930         PINMUX_DATA(IRQ47_MARK,                 PORT113_FN0),
 931
 932         /* Port114 */
 933         PINMUX_DATA(KEYIN10_MARK,               PORT114_FN1),
 934         PINMUX_DATA(KEYOUT10_MARK,              PORT114_FN2),
 935         PINMUX_DATA(SF_IRQ_06_MARK,             PORT114_FN4),
 936         PINMUX_DATA(IRQ48_MARK,                 PORT114_FN0),
 937
 938         /* Port115 */
 939         PINMUX_DATA(KEYIN11_MARK,               PORT115_FN1),
 940         PINMUX_DATA(KEYOUT11_MARK,              PORT115_FN2),
 941         PINMUX_DATA(SF_IRQ_07_MARK,             PORT115_FN4),
 942         PINMUX_DATA(IRQ49_MARK,                 PORT115_FN0),
 943
 944         /* Port116 */
 945         PINMUX_DATA(SCIFA0_TXD_MARK,            PORT116_FN1),
 946         PINMUX_DATA(CSCIF0_TX_MARK,             PORT116_FN7),
 947
 948         /* Port117 */
 949         PINMUX_DATA(SCIFA0_RXD_MARK,            PORT117_FN1),
 950         PINMUX_DATA(CSCIF0_RX_MARK,             PORT117_FN7),
 951
 952         /* Port118 */
 953         PINMUX_DATA(SCIFA1_TXD_MARK,            PORT118_FN1),
 954         PINMUX_DATA(CSCIF1_TX_MARK,             PORT118_FN7),
 955
 956         /* Port119 */
 957         PINMUX_DATA(SCIFA1_RXD_MARK,            PORT119_FN1),
 958         PINMUX_DATA(CSCIF1_RX_MARK,             PORT119_FN7),
 959
 960         /* Port120 */
 961         PINMUX_DATA(SF_PORT_1_120_MARK,         PORT120_FN3),
 962         PINMUX_DATA(SCIFB3_RXD_120_MARK,        PORT120_FN4,    MSEL3CR_09_1),
 963         PINMUX_DATA(DU0_CDE_MARK,               PORT120_FN7),
 964
 965         /* Port121 */
 966         PINMUX_DATA(SF_PORT_0_121_MARK,         PORT121_FN3),
 967         PINMUX_DATA(SCIFB3_TXD_121_MARK,        PORT121_FN4,    MSEL3CR_09_1),
 968
 969         /* Port122 */
 970         PINMUX_DATA(SCIFB0_TXD_MARK,            PORT122_FN1),
 971         PINMUX_DATA(CHSCIF0_HTX_MARK,           PORT122_FN7),
 972
 973         /* Port123 */
 974         PINMUX_DATA(SCIFB0_RXD_MARK,            PORT123_FN1),
 975         PINMUX_DATA(CHSCIF0_HRX_MARK,           PORT123_FN7),
 976
 977         /* Port124 */
 978         PINMUX_DATA(ISP_STROBE_124_MARK,        PORT124_FN3),
 979
 980         /* Port125 */
 981         PINMUX_DATA(STP_ISD_0_MARK,             PORT125_FN1),
 982         PINMUX_DATA(PDM4_CLK_125_MARK,          PORT125_FN2),
 983         PINMUX_DATA(MSIOF2_TXD_MARK,            PORT125_FN3),
 984         PINMUX_DATA(SIM0_VOLTSEL0_MARK,         PORT125_FN5),
 985
 986         /* Port126 */
 987         PINMUX_DATA(TS_SDEN_MARK,               PORT126_FN1),
 988         PINMUX_DATA(MSIOF7_SYNC_MARK,           PORT126_FN2),
 989         PINMUX_DATA(STP_ISEN_1_MARK,            PORT126_FN3),
 990
 991         /* Port128 */
 992         PINMUX_DATA(STP_ISEN_0_MARK,            PORT128_FN1),
 993         PINMUX_DATA(PDM1_OUTDATA_128_MARK,      PORT128_FN2),
 994         PINMUX_DATA(MSIOF2_SYNC_MARK,           PORT128_FN3),
 995         PINMUX_DATA(SIM1_VOLTSEL1_MARK,         PORT128_FN5),
 996
 997         /* Port129 */
 998         PINMUX_DATA(TS_SPSYNC_MARK,             PORT129_FN1),
 999         PINMUX_DATA(MSIOF7_RXD_MARK,            PORT129_FN2),
1000         PINMUX_DATA(STP_ISSYNC_1_MARK,          PORT129_FN3),
1001
1002         /* Port130 */
1003         PINMUX_DATA(STP_ISSYNC_0_MARK,          PORT130_FN1),
1004         PINMUX_DATA(PDM4_DATA_130_MARK,         PORT130_FN2,    MSEL3CR_12_1),
1005         PINMUX_DATA(MSIOF2_RXD_MARK,            PORT130_FN3),
1006         PINMUX_DATA(SIM0_VOLTSEL1_MARK,         PORT130_FN5),
1007
1008         /* Port131 */
1009         PINMUX_DATA(STP_OPWM_0_MARK,            PORT131_FN1),
1010         PINMUX_DATA(SIM1_PWRON_MARK,            PORT131_FN5),
1011
1012         /* Port132 */
1013         PINMUX_DATA(TS_SCK_MARK,                PORT132_FN1),
1014         PINMUX_DATA(MSIOF7_SCK_MARK,            PORT132_FN2),
1015         PINMUX_DATA(STP_ISCLK_1_MARK,           PORT132_FN3),
1016
1017         /* Port133 */
1018         PINMUX_DATA(STP_ISCLK_0_MARK,           PORT133_FN1),
1019         PINMUX_DATA(PDM1_OUTCLK_133_MARK,       PORT133_FN2),
1020         PINMUX_DATA(MSIOF2_SCK_MARK,            PORT133_FN3),
1021         PINMUX_DATA(SIM1_VOLTSEL0_MARK,         PORT133_FN5),
1022
1023         /* Port134 */
1024         PINMUX_DATA(TS_SDAT_MARK,               PORT134_FN1),
1025         PINMUX_DATA(MSIOF7_TXD_MARK,            PORT134_FN2),
1026         PINMUX_DATA(STP_ISD_1_MARK,             PORT134_FN3),
1027
1028         /* Port160 - Port178 */
1029         PINMUX_DATA(IRQ20_MARK,                 PORT160_FN0),
1030         PINMUX_DATA(IRQ21_MARK,                 PORT161_FN0),
1031         PINMUX_DATA(IRQ22_MARK,                 PORT162_FN0),
1032         PINMUX_DATA(IRQ23_MARK,                 PORT163_FN0),
1033         PINMUX_DATA(MMCD0_0_MARK,               PORT164_FN1),
1034         PINMUX_DATA(MMCD0_1_MARK,               PORT165_FN1),
1035         PINMUX_DATA(MMCD0_2_MARK,               PORT166_FN1),
1036         PINMUX_DATA(MMCD0_3_MARK,               PORT167_FN1),
1037         PINMUX_DATA(MMCD0_4_MARK,               PORT168_FN1),
1038         PINMUX_DATA(MMCD0_5_MARK,               PORT169_FN1),
1039         PINMUX_DATA(MMCD0_6_MARK,               PORT170_FN1),
1040         PINMUX_DATA(MMCD0_7_MARK,               PORT171_FN1),
1041         PINMUX_DATA(MMCCMD0_MARK,               PORT172_FN1),
1042         PINMUX_DATA(MMCCLK0_MARK,               PORT173_FN1),
1043         PINMUX_DATA(MMCRST_MARK,                PORT174_FN1),
1044         PINMUX_DATA(IRQ24_MARK,                 PORT175_FN0),
1045         PINMUX_DATA(IRQ25_MARK,                 PORT176_FN0),
1046         PINMUX_DATA(IRQ26_MARK,                 PORT177_FN0),
1047         PINMUX_DATA(IRQ27_MARK,                 PORT178_FN0),
1048
1049         /* Port192 - Port200 FN1 */
1050         PINMUX_DATA(A10_MARK,           PORT192_FN1),
1051         PINMUX_DATA(A9_MARK,            PORT193_FN1),
1052         PINMUX_DATA(A8_MARK,            PORT194_FN1),
1053         PINMUX_DATA(A7_MARK,            PORT195_FN1),
1054         PINMUX_DATA(A6_MARK,            PORT196_FN1),
1055         PINMUX_DATA(A5_MARK,            PORT197_FN1),
1056         PINMUX_DATA(A4_MARK,            PORT198_FN1),
1057         PINMUX_DATA(A3_MARK,            PORT199_FN1),
1058         PINMUX_DATA(A2_MARK,            PORT200_FN1),
1059
1060         /* Port192 - Port200 FN2 */
1061         PINMUX_DATA(MMCD1_7_MARK,               PORT192_FN2),
1062         PINMUX_DATA(MMCD1_6_MARK,               PORT193_FN2),
1063         PINMUX_DATA(MMCD1_5_MARK,               PORT194_FN2),
1064         PINMUX_DATA(MMCD1_4_MARK,               PORT195_FN2),
1065         PINMUX_DATA(MMCD1_3_MARK,               PORT196_FN2),
1066         PINMUX_DATA(MMCD1_2_MARK,               PORT197_FN2),
1067         PINMUX_DATA(MMCD1_1_MARK,               PORT198_FN2),
1068         PINMUX_DATA(MMCD1_0_MARK,               PORT199_FN2),
1069         PINMUX_DATA(MMCCMD1_MARK,               PORT200_FN2),
1070
1071         /* Port192 - Port200 IRQ */
1072         PINMUX_DATA(IRQ31_MARK,                 PORT192_FN0),
1073         PINMUX_DATA(IRQ32_MARK,                 PORT193_FN0),
1074         PINMUX_DATA(IRQ33_MARK,                 PORT194_FN0),
1075         PINMUX_DATA(IRQ34_MARK,                 PORT195_FN0),
1076         PINMUX_DATA(IRQ35_MARK,                 PORT196_FN0),
1077         PINMUX_DATA(IRQ36_MARK,                 PORT197_FN0),
1078         PINMUX_DATA(IRQ37_MARK,                 PORT198_FN0),
1079         PINMUX_DATA(IRQ38_MARK,                 PORT199_FN0),
1080         PINMUX_DATA(IRQ39_MARK,                 PORT200_FN0),
1081
1082         /* Port201 */
1083         PINMUX_DATA(A1_MARK,            PORT201_FN1),
1084
1085         /* Port202 */
1086         PINMUX_DATA(A0_MARK,            PORT202_FN1),
1087         PINMUX_DATA(BS_MARK,            PORT202_FN2),
1088
1089         /* Port203 */
1090         PINMUX_DATA(CKO_MARK,           PORT203_FN1),
1091         PINMUX_DATA(MMCCLK1_MARK,       PORT203_FN2),
1092
1093         /* Port204 */
1094         PINMUX_DATA(CS0_N_MARK,         PORT204_FN1),
1095         PINMUX_DATA(SIM0_GPO1_MARK,     PORT204_FN5),
1096
1097         /* Port205 */
1098         PINMUX_DATA(CS2_N_MARK,         PORT205_FN1),
1099         PINMUX_DATA(SIM0_GPO2_MARK,     PORT205_FN5),
1100
1101         /* Port206 */
1102         PINMUX_DATA(CS4_N_MARK,         PORT206_FN1),
1103         PINMUX_DATA(VIO_VD_MARK,        PORT206_FN2),
1104         PINMUX_DATA(SIM1_GPO0_MARK,     PORT206_FN5),
1105
1106         /* Port207 - Port212 FN1 */
1107         PINMUX_DATA(D15_MARK,           PORT207_FN1),
1108         PINMUX_DATA(D14_MARK,           PORT208_FN1),
1109         PINMUX_DATA(D13_MARK,           PORT209_FN1),
1110         PINMUX_DATA(D12_MARK,           PORT210_FN1),
1111         PINMUX_DATA(D11_MARK,           PORT211_FN1),
1112         PINMUX_DATA(D10_MARK,           PORT212_FN1),
1113
1114         /* Port207 - Port212 FN5 */
1115         PINMUX_DATA(GIO_OUT15_MARK,                     PORT207_FN5),
1116         PINMUX_DATA(GIO_OUT14_MARK,                     PORT208_FN5),
1117         PINMUX_DATA(GIO_OUT13_MARK,                     PORT209_FN5),
1118         PINMUX_DATA(GIO_OUT12_MARK,                     PORT210_FN5),
1119         PINMUX_DATA(WGM_TXP2_MARK,                      PORT211_FN5),
1120         PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK,       PORT212_FN5),
1121
1122         /* Port213 - Port222 FN1 */
1123         PINMUX_DATA(D9_MARK,            PORT213_FN1),
1124         PINMUX_DATA(D8_MARK,            PORT214_FN1),
1125         PINMUX_DATA(D7_MARK,            PORT215_FN1),
1126         PINMUX_DATA(D6_MARK,            PORT216_FN1),
1127         PINMUX_DATA(D5_MARK,            PORT217_FN1),
1128         PINMUX_DATA(D4_MARK,            PORT218_FN1),
1129         PINMUX_DATA(D3_MARK,            PORT219_FN1),
1130         PINMUX_DATA(D2_MARK,            PORT220_FN1),
1131         PINMUX_DATA(D1_MARK,            PORT221_FN1),
1132         PINMUX_DATA(D0_MARK,            PORT222_FN1),
1133
1134         /* Port213 - Port222 FN2 */
1135         PINMUX_DATA(VIO_D9_MARK,        PORT213_FN2),
1136         PINMUX_DATA(VIO_D8_MARK,        PORT214_FN2),
1137         PINMUX_DATA(VIO_D7_MARK,        PORT215_FN2),
1138         PINMUX_DATA(VIO_D6_MARK,        PORT216_FN2),
1139         PINMUX_DATA(VIO_D5_MARK,        PORT217_FN2),
1140         PINMUX_DATA(VIO_D4_MARK,        PORT218_FN2),
1141         PINMUX_DATA(VIO_D3_MARK,        PORT219_FN2),
1142         PINMUX_DATA(VIO_D2_MARK,        PORT220_FN2),
1143         PINMUX_DATA(VIO_D1_MARK,        PORT221_FN2),
1144         PINMUX_DATA(VIO_D0_MARK,        PORT222_FN2),
1145
1146         /* Port213 - Port222 FN5 */
1147         PINMUX_DATA(GIO_OUT9_MARK,      PORT213_FN5),
1148         PINMUX_DATA(GIO_OUT8_MARK,      PORT214_FN5),
1149         PINMUX_DATA(GIO_OUT7_MARK,      PORT215_FN5),
1150         PINMUX_DATA(GIO_OUT6_MARK,      PORT216_FN5),
1151         PINMUX_DATA(GIO_OUT5_217_MARK,  PORT217_FN5),
1152         PINMUX_DATA(GIO_OUT4_218_MARK,  PORT218_FN5),
1153         PINMUX_DATA(GIO_OUT3_219_MARK,  PORT219_FN5),
1154         PINMUX_DATA(GIO_OUT2_220_MARK,  PORT220_FN5),
1155         PINMUX_DATA(GIO_OUT1_221_MARK,  PORT221_FN5),
1156         PINMUX_DATA(GIO_OUT0_222_MARK,  PORT222_FN5),
1157
1158         /* Port224 */
1159         PINMUX_DATA(RDWR_224_MARK,      PORT224_FN1),
1160         PINMUX_DATA(VIO_HD_MARK,        PORT224_FN2),
1161         PINMUX_DATA(SIM1_GPO2_MARK,     PORT224_FN5),
1162
1163         /* Port225 */
1164         PINMUX_DATA(RD_N_MARK,          PORT225_FN1),
1165
1166         /* Port226 */
1167         PINMUX_DATA(WAIT_N_MARK,        PORT226_FN1),
1168         PINMUX_DATA(VIO_CLK_MARK,       PORT226_FN2),
1169         PINMUX_DATA(SIM1_GPO1_MARK,     PORT226_FN5),
1170
1171         /* Port227 */
1172         PINMUX_DATA(WE0_N_MARK,         PORT227_FN1),
1173         PINMUX_DATA(RDWR_227_MARK,      PORT227_FN2),
1174
1175         /* Port228 */
1176         PINMUX_DATA(WE1_N_MARK,         PORT228_FN1),
1177         PINMUX_DATA(SIM0_GPO0_MARK,     PORT228_FN5),
1178
1179         /* Port229 */
1180         PINMUX_DATA(PWMO_MARK,          PORT229_FN1),
1181         PINMUX_DATA(VIO_CKO1_229_MARK,  PORT229_FN2),
1182
1183         /* Port230 */
1184         PINMUX_DATA(SLIM_CLK_MARK,      PORT230_FN1),
1185         PINMUX_DATA(VIO_CKO4_230_MARK,  PORT230_FN2),
1186
1187         /* Port231 */
1188         PINMUX_DATA(SLIM_DATA_MARK,     PORT231_FN1),
1189         PINMUX_DATA(VIO_CKO5_231_MARK,  PORT231_FN2),
1190
1191         /* Port232 */
1192         PINMUX_DATA(VIO_CKO2_232_MARK,  PORT232_FN2),
1193         PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
1194
1195         /* Port233 */
1196         PINMUX_DATA(VIO_CKO3_233_MARK,  PORT233_FN2),
1197         PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
1198
1199         /* Port234 */
1200         PINMUX_DATA(FSIACK_MARK,        PORT234_FN1),
1201         PINMUX_DATA(PDM3_CLK_234_MARK,  PORT234_FN2),
1202         PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
1203
1204         /* Port235 */
1205         PINMUX_DATA(FSIAISLD_MARK,      PORT235_FN1),
1206         PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2,    MSEL3CR_12_1),
1207
1208         /* Port236 */
1209         PINMUX_DATA(FSIAOMC_MARK,               PORT236_FN1),
1210         PINMUX_DATA(PDM0_OUTCLK_236_MARK,       PORT236_FN2),
1211         PINMUX_DATA(ISP_IRIS0_236_MARK,         PORT236_FN3),
1212
1213         /* Port237 */
1214         PINMUX_DATA(FSIAOLR_MARK,       PORT237_FN1),
1215         PINMUX_DATA(FSIAILR_MARK,       PORT237_FN2),
1216
1217         /* Port238 */
1218         PINMUX_DATA(FSIAOBT_MARK,       PORT238_FN1),
1219         PINMUX_DATA(FSIAIBT_MARK,       PORT238_FN2),
1220
1221         /* Port239 */
1222         PINMUX_DATA(FSIAOSLD_MARK,              PORT239_FN1),
1223         PINMUX_DATA(PDM0_OUTDATA_239_MARK,      PORT239_FN2),
1224
1225         /* Port240 */
1226         PINMUX_DATA(FSIBISLD_MARK,      PORT240_FN1),
1227
1228         /* Port241 */
1229         PINMUX_DATA(FSIBOLR_MARK,       PORT241_FN1),
1230         PINMUX_DATA(FSIBILR_MARK,       PORT241_FN2),
1231
1232         /* Port242 */
1233         PINMUX_DATA(FSIBOMC_MARK,               PORT242_FN1),
1234         PINMUX_DATA(ISP_SHUTTER1_242_MARK,      PORT242_FN3),
1235
1236         /* Port243 */
1237         PINMUX_DATA(FSIBOBT_MARK,       PORT243_FN1),
1238         PINMUX_DATA(FSIBIBT_MARK,       PORT243_FN2),
1239
1240         /* Port244 */
1241         PINMUX_DATA(FSIBOSLD_MARK,      PORT244_FN1),
1242         PINMUX_DATA(FSIASPDIF_MARK,     PORT244_FN2),
1243
1244         /* Port245 */
1245         PINMUX_DATA(FSIBCK_MARK,                PORT245_FN1),
1246         PINMUX_DATA(ISP_SHUTTER0_245_MARK,      PORT245_FN3),
1247
1248         /* Port246 - Port250 FN1 */
1249         PINMUX_DATA(ISP_IRIS1_246_MARK,         PORT246_FN1),
1250         PINMUX_DATA(ISP_IRIS0_247_MARK,         PORT247_FN1),
1251         PINMUX_DATA(ISP_SHUTTER1_248_MARK,      PORT248_FN1),
1252         PINMUX_DATA(ISP_SHUTTER0_249_MARK,      PORT249_FN1),
1253         PINMUX_DATA(ISP_STROBE_250_MARK,        PORT250_FN1),
1254
1255         /* Port256 - Port258 */
1256         PINMUX_DATA(MSIOF0_SYNC_MARK,           PORT256_FN1),
1257         PINMUX_DATA(MSIOF0_RXD_MARK,            PORT257_FN1),
1258         PINMUX_DATA(MSIOF0_SCK_MARK,            PORT258_FN1),
1259
1260         /* Port259 */
1261         PINMUX_DATA(MSIOF0_SS2_MARK,            PORT259_FN1),
1262         PINMUX_DATA(VIO_CKO3_259_MARK,          PORT259_FN3),
1263
1264         /* Port260 */
1265         PINMUX_DATA(MSIOF0_TXD_MARK,            PORT260_FN1),
1266
1267         /* Port261 */
1268         PINMUX_DATA(SCIFB1_SCK_261_MARK,        PORT261_FN2),
1269         PINMUX_DATA(CHSCIF1_HSCK_MARK,          PORT261_FN7),
1270
1271         /* Port262 */
1272         PINMUX_DATA(SCIFB2_SCK_262_MARK,        PORT262_FN2),
1273
1274         /* Port263 - Port266 FN1 */
1275         PINMUX_DATA(MSIOF1_SS2_MARK,            PORT263_FN1),
1276         PINMUX_DATA(MSIOF1_TXD_MARK,            PORT264_FN1),
1277         PINMUX_DATA(MSIOF1_RXD_MARK,            PORT265_FN1),
1278         PINMUX_DATA(MSIOF1_SS1_MARK,            PORT266_FN1),
1279
1280         /* Port263 - Port266 FN4 */
1281         PINMUX_DATA(MSIOF5_SS2_MARK,            PORT263_FN4),
1282         PINMUX_DATA(MSIOF5_TXD_MARK,            PORT264_FN4),
1283         PINMUX_DATA(MSIOF5_RXD_MARK,            PORT265_FN4),
1284         PINMUX_DATA(MSIOF5_SS1_MARK,            PORT266_FN4),
1285
1286         /* Port267 */
1287         PINMUX_DATA(MSIOF0_SS1_MARK,            PORT267_FN1),
1288
1289         /* Port268 */
1290         PINMUX_DATA(MSIOF1_SCK_MARK,            PORT268_FN1),
1291         PINMUX_DATA(MSIOF5_SCK_MARK,            PORT268_FN4),
1292
1293         /* Port269 */
1294         PINMUX_DATA(MSIOF1_SYNC_MARK,           PORT269_FN1),
1295         PINMUX_DATA(MSIOF5_SYNC_MARK,           PORT269_FN4),
1296
1297         /* Port270 - Port273 FN1 */
1298         PINMUX_DATA(MSIOF2_SS1_MARK,            PORT270_FN1),
1299         PINMUX_DATA(MSIOF2_SS2_MARK,            PORT271_FN1),
1300         PINMUX_DATA(MSIOF3_SS2_MARK,            PORT272_FN1),
1301         PINMUX_DATA(MSIOF3_SS1_MARK,            PORT273_FN1),
1302
1303         /* Port270 - Port273 FN3 */
1304         PINMUX_DATA(VIO_CKO5_270_MARK,          PORT270_FN3),
1305         PINMUX_DATA(VIO_CKO2_271_MARK,          PORT271_FN3),
1306         PINMUX_DATA(VIO_CKO1_272_MARK,          PORT272_FN3),
1307         PINMUX_DATA(VIO_CKO4_273_MARK,          PORT273_FN3),
1308
1309         /* Port274 */
1310         PINMUX_DATA(MSIOF4_SS2_MARK,            PORT274_FN1),
1311         PINMUX_DATA(TPU1TO0_MARK,               PORT274_FN4),
1312
1313         /* Port275 - Port280 */
1314         PINMUX_DATA(IC_DP_MARK,                 PORT275_FN1),
1315         PINMUX_DATA(SIM0_RST_MARK,              PORT276_FN1),
1316         PINMUX_DATA(IC_DM_MARK,                 PORT277_FN1),
1317         PINMUX_DATA(SIM0_BSICOMP_MARK,          PORT278_FN1),
1318         PINMUX_DATA(SIM0_CLK_MARK,              PORT279_FN1),
1319         PINMUX_DATA(SIM0_IO_MARK,               PORT280_FN1),
1320
1321         /* Port281 */
1322         PINMUX_DATA(SIM1_IO_MARK,               PORT281_FN1),
1323         PINMUX_DATA(PDM2_DATA_281_MARK,         PORT281_FN2,    MSEL3CR_12_1),
1324
1325         /* Port282 */
1326         PINMUX_DATA(SIM1_CLK_MARK,              PORT282_FN1),
1327         PINMUX_DATA(PDM2_CLK_282_MARK,          PORT282_FN2),
1328
1329         /* Port283 */
1330         PINMUX_DATA(SIM1_RST_MARK,              PORT283_FN1),
1331
1332         /* Port289 */
1333         PINMUX_DATA(SDHID1_0_MARK,              PORT289_FN1),
1334         PINMUX_DATA(STMDATA0_2_MARK,            PORT289_FN3),
1335
1336         /* Port290 */
1337         PINMUX_DATA(SDHID1_1_MARK,              PORT290_FN1),
1338         PINMUX_DATA(STMDATA1_2_MARK,            PORT290_FN3),
1339         PINMUX_DATA(IRQ51_MARK,                 PORT290_FN0),
1340
1341         /* Port291 - Port294 FN1 */
1342         PINMUX_DATA(SDHID1_2_MARK,              PORT291_FN1),
1343         PINMUX_DATA(SDHID1_3_MARK,              PORT292_FN1),
1344         PINMUX_DATA(SDHICLK1_MARK,              PORT293_FN1),
1345         PINMUX_DATA(SDHICMD1_MARK,              PORT294_FN1),
1346
1347         /* Port291 - Port294 FN3 */
1348         PINMUX_DATA(STMDATA2_2_MARK,            PORT291_FN3),
1349         PINMUX_DATA(STMDATA3_2_MARK,            PORT292_FN3),
1350         PINMUX_DATA(STMCLK_2_MARK,              PORT293_FN3),
1351         PINMUX_DATA(STMSIDI_2_MARK,             PORT294_FN3),
1352
1353         /* Port295 */
1354         PINMUX_DATA(SDHID2_0_MARK,              PORT295_FN1),
1355         PINMUX_DATA(MSIOF4_TXD_MARK,            PORT295_FN2),
1356         PINMUX_DATA(SCIFB2_TXD_295_MARK,        PORT295_FN3,    MSEL3CR_10_1),
1357         PINMUX_DATA(MSIOF6_TXD_MARK,            PORT295_FN4),
1358
1359         /* Port296 */
1360         PINMUX_DATA(SDHID2_1_MARK,              PORT296_FN1),
1361         PINMUX_DATA(MSIOF6_SS2_MARK,            PORT296_FN4),
1362         PINMUX_DATA(IRQ52_MARK,                 PORT296_FN0),
1363
1364         /* Port297 - Port300 FN1 */
1365         PINMUX_DATA(SDHID2_2_MARK,              PORT297_FN1),
1366         PINMUX_DATA(SDHID2_3_MARK,              PORT298_FN1),
1367         PINMUX_DATA(SDHICLK2_MARK,              PORT299_FN1),
1368         PINMUX_DATA(SDHICMD2_MARK,              PORT300_FN1),
1369
1370         /* Port297 - Port300 FN2 */
1371         PINMUX_DATA(MSIOF4_RXD_MARK,            PORT297_FN2),
1372         PINMUX_DATA(MSIOF4_SYNC_MARK,           PORT298_FN2),
1373         PINMUX_DATA(MSIOF4_SCK_MARK,            PORT299_FN2),
1374         PINMUX_DATA(MSIOF4_SS1_MARK,            PORT300_FN2),
1375
1376         /* Port297 - Port300 FN3 */
1377         PINMUX_DATA(SCIFB2_RXD_297_MARK,        PORT297_FN3,    MSEL3CR_10_1),
1378         PINMUX_DATA(SCIFB2_CTS_298_MARK,        PORT298_FN3,    MSEL3CR_10_1),
1379         PINMUX_DATA(SCIFB2_SCK_299_MARK,        PORT299_FN3),
1380         PINMUX_DATA(SCIFB2_RTS_300_MARK,        PORT300_FN3),
1381
1382         /* Port297 - Port300 FN4 */
1383         PINMUX_DATA(MSIOF6_RXD_MARK,            PORT297_FN4),
1384         PINMUX_DATA(MSIOF6_SYNC_MARK,           PORT298_FN4),
1385         PINMUX_DATA(MSIOF6_SCK_MARK,            PORT299_FN4),
1386         PINMUX_DATA(MSIOF6_SS1_MARK,            PORT300_FN4),
1387
1388         /* Port301 */
1389         PINMUX_DATA(SDHICD0_MARK,               PORT301_FN1),
1390         PINMUX_DATA(IRQ50_MARK,                 PORT301_FN0),
1391
1392         /* Port302 - Port306 FN1 */
1393         PINMUX_DATA(SDHID0_0_MARK,              PORT302_FN1),
1394         PINMUX_DATA(SDHID0_1_MARK,              PORT303_FN1),
1395         PINMUX_DATA(SDHID0_2_MARK,              PORT304_FN1),
1396         PINMUX_DATA(SDHID0_3_MARK,              PORT305_FN1),
1397         PINMUX_DATA(SDHICMD0_MARK,              PORT306_FN1),
1398
1399         /* Port302 - Port306 FN3 */
1400         PINMUX_DATA(STMDATA0_1_MARK,            PORT302_FN3),
1401         PINMUX_DATA(STMDATA1_1_MARK,            PORT303_FN3),
1402         PINMUX_DATA(STMDATA2_1_MARK,            PORT304_FN3),
1403         PINMUX_DATA(STMDATA3_1_MARK,            PORT305_FN3),
1404         PINMUX_DATA(STMSIDI_1_MARK,             PORT306_FN3),
1405
1406         /* Port307 */
1407         PINMUX_DATA(SDHIWP0_MARK,               PORT307_FN1),
1408
1409         /* Port308 */
1410         PINMUX_DATA(SDHICLK0_MARK,              PORT308_FN1),
1411         PINMUX_DATA(STMCLK_1_MARK,              PORT308_FN3),
1412
1413         /* Port320 - Port329 */
1414         PINMUX_DATA(IRQ16_MARK,                 PORT320_FN0),
1415         PINMUX_DATA(IRQ17_MARK,                 PORT321_FN0),
1416         PINMUX_DATA(IRQ28_MARK,                 PORT322_FN0),
1417         PINMUX_DATA(IRQ29_MARK,                 PORT323_FN0),
1418         PINMUX_DATA(IRQ30_MARK,                 PORT324_FN0),
1419         PINMUX_DATA(IRQ53_MARK,                 PORT325_FN0),
1420         PINMUX_DATA(IRQ54_MARK,                 PORT326_FN0),
1421         PINMUX_DATA(IRQ55_MARK,                 PORT327_FN0),
1422         PINMUX_DATA(IRQ56_MARK,                 PORT328_FN0),
1423         PINMUX_DATA(IRQ57_MARK,                 PORT329_FN0),
1424 };
1425
1426 #define R8A73A4_PIN(pin, cfgs)                  \
1427         {                                       \
1428                 .name = __stringify(PORT##pin), \
1429                 .enum_id = PORT##pin##_DATA,    \
1430                 .configs = cfgs,                \
1431         }
1432
1433 #define __O     (SH_PFC_PIN_CFG_OUTPUT)
1434 #define __IO    (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1435 #define __PUD   (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1436
1437 #define R8A73A4_PIN_IO_PU_PD(pin)       R8A73A4_PIN(pin, __IO | __PUD)
1438 #define R8A73A4_PIN_O(pin)              R8A73A4_PIN(pin, __O)
1439
1440 static struct sh_pfc_pin pinmux_pins[] = {
1441         R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1442         R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1443         R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1444         R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1445         R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1446         R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1447         R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1448         R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1449         R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1450         R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1451         R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1452         R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1453         R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1454         R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1455         R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1456         R8A73A4_PIN_IO_PU_PD(30),
1457         R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1458         R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1459         R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1460         R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1461         R8A73A4_PIN_IO_PU_PD(40),
1462         R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1463         R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1464         R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1465         R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1466         R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1467         R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1468         R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1469         R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1470         R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1471         R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1472         R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1473         R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1474         R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1475         R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1476         R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1477         R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1478         R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1479         R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1480         R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1481         R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1482         R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1483         R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1484         R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1485         R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1486         R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1487         R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1488         R8A73A4_PIN_IO_PU_PD(126),
1489         R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1490         R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1491         R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1492         R8A73A4_PIN_IO_PU_PD(134),
1493         R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1494         R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1495         R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1496         R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1497         R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1498         R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1499         R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1500         R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1501         R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1502         R8A73A4_PIN_IO_PU_PD(178),
1503         R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1504         R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1505         R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1506         R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1507         R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1508         R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1509         R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1510         R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1511         R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1512         R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1513         R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1514         R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1515         R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1516         R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1517         R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1518         R8A73A4_PIN_IO_PU_PD(222),
1519         R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1520         R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1521         R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1522         R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1523         R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1524         R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1525         R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1526         R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1527         R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1528         R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1529         R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1530         R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1531         R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1532         R8A73A4_PIN_IO_PU_PD(250),
1533         R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1534         R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1535         R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1536         R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1537         R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1538         R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1539         R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1540         R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1541         R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1542         R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1543         R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1544         R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1545         R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1546         R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1547         R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1548         R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1549         R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1550         R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1551         R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1552         R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1553         R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1554         R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1555         R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1556         R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1557         R8A73A4_PIN_IO_PU_PD(308),
1558         R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1559         R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1560         R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1561         R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1562         R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
1563 };
1564
1565 static const struct pinmux_range pinmux_ranges[] = {
1566         {.begin = 0, .end = 30,},
1567         {.begin = 32, .end = 40,},
1568         {.begin = 64, .end = 85,},
1569         {.begin = 96, .end = 126,},
1570         {.begin = 128, .end = 134,},
1571         {.begin = 160, .end = 178,},
1572         {.begin = 192, .end = 222,},
1573         {.begin = 224, .end = 250,},
1574         {.begin = 256, .end = 283,},
1575         {.begin = 288, .end = 308,},
1576         {.begin = 320, .end = 329,},
1577 };
1578
1579 /* - IRQC ------------------------------------------------------------------- */
1580 #define IRQC_PINS_MUX(pin, irq_mark)                            \
1581 static const unsigned int irqc_irq##irq_mark##_pins[] = {       \
1582         pin,                                                    \
1583 };                                                              \
1584 static const unsigned int irqc_irq##irq_mark##_mux[] = {        \
1585         IRQ##irq_mark##_MARK,                                   \
1586 }
1587 IRQC_PINS_MUX(0, 0);
1588 IRQC_PINS_MUX(1, 1);
1589 IRQC_PINS_MUX(2, 2);
1590 IRQC_PINS_MUX(3, 3);
1591 IRQC_PINS_MUX(4, 4);
1592 IRQC_PINS_MUX(5, 5);
1593 IRQC_PINS_MUX(6, 6);
1594 IRQC_PINS_MUX(7, 7);
1595 IRQC_PINS_MUX(8, 8);
1596 IRQC_PINS_MUX(9, 9);
1597 IRQC_PINS_MUX(10, 10);
1598 IRQC_PINS_MUX(11, 11);
1599 IRQC_PINS_MUX(12, 12);
1600 IRQC_PINS_MUX(13, 13);
1601 IRQC_PINS_MUX(14, 14);
1602 IRQC_PINS_MUX(15, 15);
1603 IRQC_PINS_MUX(66, 40);
1604 IRQC_PINS_MUX(84, 19);
1605 IRQC_PINS_MUX(85, 18);
1606 IRQC_PINS_MUX(102, 41);
1607 IRQC_PINS_MUX(103, 42);
1608 IRQC_PINS_MUX(109, 43);
1609 IRQC_PINS_MUX(110, 44);
1610 IRQC_PINS_MUX(111, 45);
1611 IRQC_PINS_MUX(112, 46);
1612 IRQC_PINS_MUX(113, 47);
1613 IRQC_PINS_MUX(114, 48);
1614 IRQC_PINS_MUX(115, 49);
1615 IRQC_PINS_MUX(160, 20);
1616 IRQC_PINS_MUX(161, 21);
1617 IRQC_PINS_MUX(162, 22);
1618 IRQC_PINS_MUX(163, 23);
1619 IRQC_PINS_MUX(175, 24);
1620 IRQC_PINS_MUX(176, 25);
1621 IRQC_PINS_MUX(177, 26);
1622 IRQC_PINS_MUX(178, 27);
1623 IRQC_PINS_MUX(192, 31);
1624 IRQC_PINS_MUX(193, 32);
1625 IRQC_PINS_MUX(194, 33);
1626 IRQC_PINS_MUX(195, 34);
1627 IRQC_PINS_MUX(196, 35);
1628 IRQC_PINS_MUX(197, 36);
1629 IRQC_PINS_MUX(198, 37);
1630 IRQC_PINS_MUX(199, 38);
1631 IRQC_PINS_MUX(200, 39);
1632 IRQC_PINS_MUX(290, 51);
1633 IRQC_PINS_MUX(296, 52);
1634 IRQC_PINS_MUX(301, 50);
1635 IRQC_PINS_MUX(320, 16);
1636 IRQC_PINS_MUX(321, 17);
1637 IRQC_PINS_MUX(322, 28);
1638 IRQC_PINS_MUX(323, 29);
1639 IRQC_PINS_MUX(324, 30);
1640 IRQC_PINS_MUX(325, 53);
1641 IRQC_PINS_MUX(326, 54);
1642 IRQC_PINS_MUX(327, 55);
1643 IRQC_PINS_MUX(328, 56);
1644 IRQC_PINS_MUX(329, 57);
1645 /* - SCIFA0 ----------------------------------------------------------------- */
1646 static const unsigned int scifa0_data_pins[] = {
1647         /* SCIFA0_RXD, SCIFA0_TXD */
1648         117, 116,
1649 };
1650 static const unsigned int scifa0_data_mux[] = {
1651         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1652 };
1653 static const unsigned int scifa0_clk_pins[] = {
1654         /* SCIFA0_SCK */
1655         34,
1656 };
1657 static const unsigned int scifa0_clk_mux[] = {
1658         SCIFA0_SCK_MARK,
1659 };
1660 static const unsigned int scifa0_ctrl_pins[] = {
1661         /* SCIFA0_RTS, SCIFA0_CTS */
1662         32, 33,
1663 };
1664 static const unsigned int scifa0_ctrl_mux[] = {
1665         SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1666 };
1667 /* - SCIFA1 ----------------------------------------------------------------- */
1668 static const unsigned int scifa1_data_pins[] = {
1669         /* SCIFA1_RXD, SCIFA1_TXD */
1670         119, 118,
1671 };
1672 static const unsigned int scifa1_data_mux[] = {
1673         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1674 };
1675 static const unsigned int scifa1_clk_pins[] = {
1676         /* SCIFA1_SCK */
1677         37,
1678 };
1679 static const unsigned int scifa1_clk_mux[] = {
1680         SCIFA1_SCK_MARK,
1681 };
1682 static const unsigned int scifa1_ctrl_pins[] = {
1683         /* SCIFA1_RTS, SCIFA1_CTS */
1684         35, 36,
1685 };
1686 static const unsigned int scifa1_ctrl_mux[] = {
1687         SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1688 };
1689 /* - SCIFB0 ----------------------------------------------------------------- */
1690 static const unsigned int scifb0_data_pins[] = {
1691         /* SCIFB0_RXD, SCIFB0_TXD */
1692         123, 122,
1693 };
1694 static const unsigned int scifb0_data_mux[] = {
1695         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1696 };
1697 static const unsigned int scifb0_clk_pins[] = {
1698         /* SCIFB0_SCK */
1699         40,
1700 };
1701 static const unsigned int scifb0_clk_mux[] = {
1702         SCIFB0_SCK_MARK,
1703 };
1704 static const unsigned int scifb0_ctrl_pins[] = {
1705         /* SCIFB0_RTS, SCIFB0_CTS */
1706         38, 39,
1707 };
1708 static const unsigned int scifb0_ctrl_mux[] = {
1709         SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1710 };
1711 /* - SCIFB1 ----------------------------------------------------------------- */
1712 static const unsigned int scifb1_data_pins[] = {
1713         /* SCIFB1_RXD, SCIFB1_TXD */
1714         27, 26,
1715 };
1716 static const unsigned int scifb1_data_mux[] = {
1717         SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1718 };
1719 static const unsigned int scifb1_clk_pins[] = {
1720         /* SCIFB1_SCK */
1721         28,
1722 };
1723 static const unsigned int scifb1_clk_mux[] = {
1724         SCIFB1_SCK_28_MARK,
1725 };
1726 static const unsigned int scifb1_ctrl_pins[] = {
1727         /* SCIFB1_RTS, SCIFB1_CTS */
1728         24, 25,
1729 };
1730 static const unsigned int scifb1_ctrl_mux[] = {
1731         SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1732 };
1733 static const unsigned int scifb1_data_b_pins[] = {
1734         /* SCIFB1_RXD, SCIFB1_TXD */
1735         72, 67,
1736 };
1737 static const unsigned int scifb1_data_b_mux[] = {
1738         SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1739 };
1740 static const unsigned int scifb1_clk_b_pins[] = {
1741         /* SCIFB1_SCK */
1742         261,
1743 };
1744 static const unsigned int scifb1_clk_b_mux[] = {
1745         SCIFB1_SCK_261_MARK,
1746 };
1747 static const unsigned int scifb1_ctrl_b_pins[] = {
1748         /* SCIFB1_RTS, SCIFB1_CTS */
1749         70, 71,
1750 };
1751 static const unsigned int scifb1_ctrl_b_mux[] = {
1752         SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1753 };
1754 /* - SCIFB2 ----------------------------------------------------------------- */
1755 static const unsigned int scifb2_data_pins[] = {
1756         /* SCIFB2_RXD, SCIFB2_TXD */
1757         69, 68,
1758 };
1759 static const unsigned int scifb2_data_mux[] = {
1760         SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1761 };
1762 static const unsigned int scifb2_clk_pins[] = {
1763         /* SCIFB2_SCK */
1764         262,
1765 };
1766 static const unsigned int scifb2_clk_mux[] = {
1767         SCIFB2_SCK_262_MARK,
1768 };
1769 static const unsigned int scifb2_ctrl_pins[] = {
1770         /* SCIFB2_RTS, SCIFB2_CTS */
1771         73, 66,
1772 };
1773 static const unsigned int scifb2_ctrl_mux[] = {
1774         SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1775 };
1776 static const unsigned int scifb2_data_b_pins[] = {
1777         /* SCIFB2_RXD, SCIFB2_TXD */
1778         297, 295,
1779 };
1780 static const unsigned int scifb2_data_b_mux[] = {
1781         SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1782 };
1783 static const unsigned int scifb2_clk_b_pins[] = {
1784         /* SCIFB2_SCK */
1785         299,
1786 };
1787 static const unsigned int scifb2_clk_b_mux[] = {
1788         SCIFB2_SCK_299_MARK,
1789 };
1790 static const unsigned int scifb2_ctrl_b_pins[] = {
1791         /* SCIFB2_RTS, SCIFB2_CTS */
1792         300, 298,
1793 };
1794 static const unsigned int scifb2_ctrl_b_mux[] = {
1795         SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1796 };
1797 /* - SCIFB3 ----------------------------------------------------------------- */
1798 static const unsigned int scifb3_data_pins[] = {
1799         /* SCIFB3_RXD, SCIFB3_TXD */
1800         22, 21,
1801 };
1802 static const unsigned int scifb3_data_mux[] = {
1803         SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1804 };
1805 static const unsigned int scifb3_clk_pins[] = {
1806         /* SCIFB3_SCK */
1807         23,
1808 };
1809 static const unsigned int scifb3_clk_mux[] = {
1810         SCIFB3_SCK_23_MARK,
1811 };
1812 static const unsigned int scifb3_ctrl_pins[] = {
1813         /* SCIFB3_RTS, SCIFB3_CTS */
1814         19, 20,
1815 };
1816 static const unsigned int scifb3_ctrl_mux[] = {
1817         SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1818 };
1819 static const unsigned int scifb3_data_b_pins[] = {
1820         /* SCIFB3_RXD, SCIFB3_TXD */
1821         120, 121,
1822 };
1823 static const unsigned int scifb3_data_b_mux[] = {
1824         SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1825 };
1826 static const unsigned int scifb3_clk_b_pins[] = {
1827         /* SCIFB3_SCK */
1828         40,
1829 };
1830 static const unsigned int scifb3_clk_b_mux[] = {
1831         SCIFB3_SCK_40_MARK,
1832 };
1833 static const unsigned int scifb3_ctrl_b_pins[] = {
1834         /* SCIFB3_RTS, SCIFB3_CTS */
1835         38, 39,
1836 };
1837 static const unsigned int scifb3_ctrl_b_mux[] = {
1838         SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1839 };
1840
1841 static const struct sh_pfc_pin_group pinmux_groups[] = {
1842         SH_PFC_PIN_GROUP(irqc_irq0),
1843         SH_PFC_PIN_GROUP(irqc_irq1),
1844         SH_PFC_PIN_GROUP(irqc_irq2),
1845         SH_PFC_PIN_GROUP(irqc_irq3),
1846         SH_PFC_PIN_GROUP(irqc_irq4),
1847         SH_PFC_PIN_GROUP(irqc_irq5),
1848         SH_PFC_PIN_GROUP(irqc_irq6),
1849         SH_PFC_PIN_GROUP(irqc_irq7),
1850         SH_PFC_PIN_GROUP(irqc_irq8),
1851         SH_PFC_PIN_GROUP(irqc_irq9),
1852         SH_PFC_PIN_GROUP(irqc_irq10),
1853         SH_PFC_PIN_GROUP(irqc_irq11),
1854         SH_PFC_PIN_GROUP(irqc_irq12),
1855         SH_PFC_PIN_GROUP(irqc_irq13),
1856         SH_PFC_PIN_GROUP(irqc_irq14),
1857         SH_PFC_PIN_GROUP(irqc_irq15),
1858         SH_PFC_PIN_GROUP(irqc_irq16),
1859         SH_PFC_PIN_GROUP(irqc_irq17),
1860         SH_PFC_PIN_GROUP(irqc_irq18),
1861         SH_PFC_PIN_GROUP(irqc_irq19),
1862         SH_PFC_PIN_GROUP(irqc_irq20),
1863         SH_PFC_PIN_GROUP(irqc_irq21),
1864         SH_PFC_PIN_GROUP(irqc_irq22),
1865         SH_PFC_PIN_GROUP(irqc_irq23),
1866         SH_PFC_PIN_GROUP(irqc_irq24),
1867         SH_PFC_PIN_GROUP(irqc_irq25),
1868         SH_PFC_PIN_GROUP(irqc_irq26),
1869         SH_PFC_PIN_GROUP(irqc_irq27),
1870         SH_PFC_PIN_GROUP(irqc_irq28),
1871         SH_PFC_PIN_GROUP(irqc_irq29),
1872         SH_PFC_PIN_GROUP(irqc_irq30),
1873         SH_PFC_PIN_GROUP(irqc_irq31),
1874         SH_PFC_PIN_GROUP(irqc_irq32),
1875         SH_PFC_PIN_GROUP(irqc_irq33),
1876         SH_PFC_PIN_GROUP(irqc_irq34),
1877         SH_PFC_PIN_GROUP(irqc_irq35),
1878         SH_PFC_PIN_GROUP(irqc_irq36),
1879         SH_PFC_PIN_GROUP(irqc_irq37),
1880         SH_PFC_PIN_GROUP(irqc_irq38),
1881         SH_PFC_PIN_GROUP(irqc_irq39),
1882         SH_PFC_PIN_GROUP(irqc_irq40),
1883         SH_PFC_PIN_GROUP(irqc_irq41),
1884         SH_PFC_PIN_GROUP(irqc_irq42),
1885         SH_PFC_PIN_GROUP(irqc_irq43),
1886         SH_PFC_PIN_GROUP(irqc_irq44),
1887         SH_PFC_PIN_GROUP(irqc_irq45),
1888         SH_PFC_PIN_GROUP(irqc_irq46),
1889         SH_PFC_PIN_GROUP(irqc_irq47),
1890         SH_PFC_PIN_GROUP(irqc_irq48),
1891         SH_PFC_PIN_GROUP(irqc_irq49),
1892         SH_PFC_PIN_GROUP(irqc_irq50),
1893         SH_PFC_PIN_GROUP(irqc_irq51),
1894         SH_PFC_PIN_GROUP(irqc_irq52),
1895         SH_PFC_PIN_GROUP(irqc_irq53),
1896         SH_PFC_PIN_GROUP(irqc_irq54),
1897         SH_PFC_PIN_GROUP(irqc_irq55),
1898         SH_PFC_PIN_GROUP(irqc_irq56),
1899         SH_PFC_PIN_GROUP(irqc_irq57),
1900         SH_PFC_PIN_GROUP(scifa0_data),
1901         SH_PFC_PIN_GROUP(scifa0_clk),
1902         SH_PFC_PIN_GROUP(scifa0_ctrl),
1903         SH_PFC_PIN_GROUP(scifa1_data),
1904         SH_PFC_PIN_GROUP(scifa1_clk),
1905         SH_PFC_PIN_GROUP(scifa1_ctrl),
1906         SH_PFC_PIN_GROUP(scifb0_data),
1907         SH_PFC_PIN_GROUP(scifb0_clk),
1908         SH_PFC_PIN_GROUP(scifb0_ctrl),
1909         SH_PFC_PIN_GROUP(scifb1_data),
1910         SH_PFC_PIN_GROUP(scifb1_clk),
1911         SH_PFC_PIN_GROUP(scifb1_ctrl),
1912         SH_PFC_PIN_GROUP(scifb1_data_b),
1913         SH_PFC_PIN_GROUP(scifb1_clk_b),
1914         SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1915         SH_PFC_PIN_GROUP(scifb2_data),
1916         SH_PFC_PIN_GROUP(scifb2_clk),
1917         SH_PFC_PIN_GROUP(scifb2_ctrl),
1918         SH_PFC_PIN_GROUP(scifb2_data_b),
1919         SH_PFC_PIN_GROUP(scifb2_clk_b),
1920         SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1921         SH_PFC_PIN_GROUP(scifb3_data),
1922         SH_PFC_PIN_GROUP(scifb3_clk),
1923         SH_PFC_PIN_GROUP(scifb3_ctrl),
1924         SH_PFC_PIN_GROUP(scifb3_data_b),
1925         SH_PFC_PIN_GROUP(scifb3_clk_b),
1926         SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1927 };
1928
1929 static const char * const irqc_groups[] = {
1930         "irqc_irq0",
1931         "irqc_irq1",
1932         "irqc_irq2",
1933         "irqc_irq3",
1934         "irqc_irq4",
1935         "irqc_irq5",
1936         "irqc_irq6",
1937         "irqc_irq7",
1938         "irqc_irq8",
1939         "irqc_irq9",
1940         "irqc_irq10",
1941         "irqc_irq11",
1942         "irqc_irq12",
1943         "irqc_irq13",
1944         "irqc_irq14",
1945         "irqc_irq15",
1946         "irqc_irq16",
1947         "irqc_irq17",
1948         "irqc_irq18",
1949         "irqc_irq19",
1950         "irqc_irq20",
1951         "irqc_irq21",
1952         "irqc_irq22",
1953         "irqc_irq23",
1954         "irqc_irq24",
1955         "irqc_irq25",
1956         "irqc_irq26",
1957         "irqc_irq27",
1958         "irqc_irq28",
1959         "irqc_irq29",
1960         "irqc_irq30",
1961         "irqc_irq31",
1962         "irqc_irq32",
1963         "irqc_irq33",
1964         "irqc_irq34",
1965         "irqc_irq35",
1966         "irqc_irq36",
1967         "irqc_irq37",
1968         "irqc_irq38",
1969         "irqc_irq39",
1970         "irqc_irq40",
1971         "irqc_irq41",
1972         "irqc_irq42",
1973         "irqc_irq43",
1974         "irqc_irq44",
1975         "irqc_irq45",
1976         "irqc_irq46",
1977         "irqc_irq47",
1978         "irqc_irq48",
1979         "irqc_irq49",
1980         "irqc_irq50",
1981         "irqc_irq51",
1982         "irqc_irq52",
1983         "irqc_irq53",
1984         "irqc_irq54",
1985         "irqc_irq55",
1986         "irqc_irq56",
1987         "irqc_irq57",
1988 };
1989
1990 static const char * const scifa0_groups[] = {
1991         "scifa0_data",
1992         "scifa0_clk",
1993         "scifa0_ctrl",
1994 };
1995
1996 static const char * const scifa1_groups[] = {
1997         "scifa1_data",
1998         "scifa1_clk",
1999         "scifa1_ctrl",
2000 };
2001
2002 static const char * const scifb0_groups[] = {
2003         "scifb0_data",
2004         "scifb0_clk",
2005         "scifb0_ctrl",
2006 };
2007
2008 static const char * const scifb1_groups[] = {
2009         "scifb1_data",
2010         "scifb1_clk",
2011         "scifb1_ctrl",
2012         "scifb1_data_b",
2013         "scifb1_clk_b",
2014         "scifb1_ctrl_b",
2015 };
2016
2017 static const char * const scifb2_groups[] = {
2018         "scifb2_data",
2019         "scifb2_clk",
2020         "scifb2_ctrl",
2021         "scifb2_data_b",
2022         "scifb2_clk_b",
2023         "scifb2_ctrl_b",
2024 };
2025
2026 static const char * const scifb3_groups[] = {
2027         "scifb3_data",
2028         "scifb3_clk",
2029         "scifb3_ctrl",
2030         "scifb3_data_b",
2031         "scifb3_clk_b",
2032         "scifb3_ctrl_b",
2033 };
2034
2035 static const struct sh_pfc_function pinmux_functions[] = {
2036         SH_PFC_FUNCTION(irqc),
2037         SH_PFC_FUNCTION(scifa0),
2038         SH_PFC_FUNCTION(scifa1),
2039         SH_PFC_FUNCTION(scifb0),
2040         SH_PFC_FUNCTION(scifb1),
2041         SH_PFC_FUNCTION(scifb2),
2042         SH_PFC_FUNCTION(scifb3),
2043 };
2044
2045 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2046
2047         PORTCR(0, 0xe6050000),
2048         PORTCR(1, 0xe6050001),
2049         PORTCR(2, 0xe6050002),
2050         PORTCR(3, 0xe6050003),
2051         PORTCR(4, 0xe6050004),
2052         PORTCR(5, 0xe6050005),
2053         PORTCR(6, 0xe6050006),
2054         PORTCR(7, 0xe6050007),
2055         PORTCR(8, 0xe6050008),
2056         PORTCR(9, 0xe6050009),
2057         PORTCR(10, 0xe605000A),
2058         PORTCR(11, 0xe605000B),
2059         PORTCR(12, 0xe605000C),
2060         PORTCR(13, 0xe605000D),
2061         PORTCR(14, 0xe605000E),
2062         PORTCR(15, 0xe605000F),
2063         PORTCR(16, 0xe6050010),
2064         PORTCR(17, 0xe6050011),
2065         PORTCR(18, 0xe6050012),
2066         PORTCR(19, 0xe6050013),
2067         PORTCR(20, 0xe6050014),
2068         PORTCR(21, 0xe6050015),
2069         PORTCR(22, 0xe6050016),
2070         PORTCR(23, 0xe6050017),
2071         PORTCR(24, 0xe6050018),
2072         PORTCR(25, 0xe6050019),
2073         PORTCR(26, 0xe605001A),
2074         PORTCR(27, 0xe605001B),
2075         PORTCR(28, 0xe605001C),
2076         PORTCR(29, 0xe605001D),
2077         PORTCR(30, 0xe605001E),
2078         PORTCR(32, 0xe6051020),
2079         PORTCR(33, 0xe6051021),
2080         PORTCR(34, 0xe6051022),
2081         PORTCR(35, 0xe6051023),
2082         PORTCR(36, 0xe6051024),
2083         PORTCR(37, 0xe6051025),
2084         PORTCR(38, 0xe6051026),
2085         PORTCR(39, 0xe6051027),
2086         PORTCR(40, 0xe6051028),
2087         PORTCR(64, 0xe6050040),
2088         PORTCR(65, 0xe6050041),
2089         PORTCR(66, 0xe6050042),
2090         PORTCR(67, 0xe6050043),
2091         PORTCR(68, 0xe6050044),
2092         PORTCR(69, 0xe6050045),
2093         PORTCR(70, 0xe6050046),
2094         PORTCR(71, 0xe6050047),
2095         PORTCR(72, 0xe6050048),
2096         PORTCR(73, 0xe6050049),
2097         PORTCR(74, 0xe605004A),
2098         PORTCR(75, 0xe605004B),
2099         PORTCR(76, 0xe605004C),
2100         PORTCR(77, 0xe605004D),
2101         PORTCR(78, 0xe605004E),
2102         PORTCR(79, 0xe605004F),
2103         PORTCR(80, 0xe6050050),
2104         PORTCR(81, 0xe6050051),
2105         PORTCR(82, 0xe6050052),
2106         PORTCR(83, 0xe6050053),
2107         PORTCR(84, 0xe6050054),
2108         PORTCR(85, 0xe6050055),
2109         PORTCR(96, 0xe6051060),
2110         PORTCR(97, 0xe6051061),
2111         PORTCR(98, 0xe6051062),
2112         PORTCR(99, 0xe6051063),
2113         PORTCR(100, 0xe6051064),
2114         PORTCR(101, 0xe6051065),
2115         PORTCR(102, 0xe6051066),
2116         PORTCR(103, 0xe6051067),
2117         PORTCR(104, 0xe6051068),
2118         PORTCR(105, 0xe6051069),
2119         PORTCR(106, 0xe605106A),
2120         PORTCR(107, 0xe605106B),
2121         PORTCR(108, 0xe605106C),
2122         PORTCR(109, 0xe605106D),
2123         PORTCR(110, 0xe605106E),
2124         PORTCR(111, 0xe605106F),
2125         PORTCR(112, 0xe6051070),
2126         PORTCR(113, 0xe6051071),
2127         PORTCR(114, 0xe6051072),
2128         PORTCR(115, 0xe6051073),
2129         PORTCR(116, 0xe6051074),
2130         PORTCR(117, 0xe6051075),
2131         PORTCR(118, 0xe6051076),
2132         PORTCR(119, 0xe6051077),
2133         PORTCR(120, 0xe6051078),
2134         PORTCR(121, 0xe6051079),
2135         PORTCR(122, 0xe605107A),
2136         PORTCR(123, 0xe605107B),
2137         PORTCR(124, 0xe605107C),
2138         PORTCR(125, 0xe605107D),
2139         PORTCR(126, 0xe605107E),
2140         PORTCR(128, 0xe6051080),
2141         PORTCR(129, 0xe6051081),
2142         PORTCR(130, 0xe6051082),
2143         PORTCR(131, 0xe6051083),
2144         PORTCR(132, 0xe6051084),
2145         PORTCR(133, 0xe6051085),
2146         PORTCR(134, 0xe6051086),
2147         PORTCR(160, 0xe60520A0),
2148         PORTCR(161, 0xe60520A1),
2149         PORTCR(162, 0xe60520A2),
2150         PORTCR(163, 0xe60520A3),
2151         PORTCR(164, 0xe60520A4),
2152         PORTCR(165, 0xe60520A5),
2153         PORTCR(166, 0xe60520A6),
2154         PORTCR(167, 0xe60520A7),
2155         PORTCR(168, 0xe60520A8),
2156         PORTCR(169, 0xe60520A9),
2157         PORTCR(170, 0xe60520AA),
2158         PORTCR(171, 0xe60520AB),
2159         PORTCR(172, 0xe60520AC),
2160         PORTCR(173, 0xe60520AD),
2161         PORTCR(174, 0xe60520AE),
2162         PORTCR(175, 0xe60520AF),
2163         PORTCR(176, 0xe60520B0),
2164         PORTCR(177, 0xe60520B1),
2165         PORTCR(178, 0xe60520B2),
2166         PORTCR(192, 0xe60520C0),
2167         PORTCR(193, 0xe60520C1),
2168         PORTCR(194, 0xe60520C2),
2169         PORTCR(195, 0xe60520C3),
2170         PORTCR(196, 0xe60520C4),
2171         PORTCR(197, 0xe60520C5),
2172         PORTCR(198, 0xe60520C6),
2173         PORTCR(199, 0xe60520C7),
2174         PORTCR(200, 0xe60520C8),
2175         PORTCR(201, 0xe60520C9),
2176         PORTCR(202, 0xe60520CA),
2177         PORTCR(203, 0xe60520CB),
2178         PORTCR(204, 0xe60520CC),
2179         PORTCR(205, 0xe60520CD),
2180         PORTCR(206, 0xe60520CE),
2181         PORTCR(207, 0xe60520CF),
2182         PORTCR(208, 0xe60520D0),
2183         PORTCR(209, 0xe60520D1),
2184         PORTCR(210, 0xe60520D2),
2185         PORTCR(211, 0xe60520D3),
2186         PORTCR(212, 0xe60520D4),
2187         PORTCR(213, 0xe60520D5),
2188         PORTCR(214, 0xe60520D6),
2189         PORTCR(215, 0xe60520D7),
2190         PORTCR(216, 0xe60520D8),
2191         PORTCR(217, 0xe60520D9),
2192         PORTCR(218, 0xe60520DA),
2193         PORTCR(219, 0xe60520DB),
2194         PORTCR(220, 0xe60520DC),
2195         PORTCR(221, 0xe60520DD),
2196         PORTCR(222, 0xe60520DE),
2197         PORTCR(224, 0xe60520E0),
2198         PORTCR(225, 0xe60520E1),
2199         PORTCR(226, 0xe60520E2),
2200         PORTCR(227, 0xe60520E3),
2201         PORTCR(228, 0xe60520E4),
2202         PORTCR(229, 0xe60520E5),
2203         PORTCR(230, 0xe60520e6),
2204         PORTCR(231, 0xe60520E7),
2205         PORTCR(232, 0xe60520E8),
2206         PORTCR(233, 0xe60520E9),
2207         PORTCR(234, 0xe60520EA),
2208         PORTCR(235, 0xe60520EB),
2209         PORTCR(236, 0xe60520EC),
2210         PORTCR(237, 0xe60520ED),
2211         PORTCR(238, 0xe60520EE),
2212         PORTCR(239, 0xe60520EF),
2213         PORTCR(240, 0xe60520F0),
2214         PORTCR(241, 0xe60520F1),
2215         PORTCR(242, 0xe60520F2),
2216         PORTCR(243, 0xe60520F3),
2217         PORTCR(244, 0xe60520F4),
2218         PORTCR(245, 0xe60520F5),
2219         PORTCR(246, 0xe60520F6),
2220         PORTCR(247, 0xe60520F7),
2221         PORTCR(248, 0xe60520F8),
2222         PORTCR(249, 0xe60520F9),
2223         PORTCR(250, 0xe60520FA),
2224         PORTCR(256, 0xe6052100),
2225         PORTCR(257, 0xe6052101),
2226         PORTCR(258, 0xe6052102),
2227         PORTCR(259, 0xe6052103),
2228         PORTCR(260, 0xe6052104),
2229         PORTCR(261, 0xe6052105),
2230         PORTCR(262, 0xe6052106),
2231         PORTCR(263, 0xe6052107),
2232         PORTCR(264, 0xe6052108),
2233         PORTCR(265, 0xe6052109),
2234         PORTCR(266, 0xe605210A),
2235         PORTCR(267, 0xe605210B),
2236         PORTCR(268, 0xe605210C),
2237         PORTCR(269, 0xe605210D),
2238         PORTCR(270, 0xe605210E),
2239         PORTCR(271, 0xe605210F),
2240         PORTCR(272, 0xe6052110),
2241         PORTCR(273, 0xe6052111),
2242         PORTCR(274, 0xe6052112),
2243         PORTCR(275, 0xe6052113),
2244         PORTCR(276, 0xe6052114),
2245         PORTCR(277, 0xe6052115),
2246         PORTCR(278, 0xe6052116),
2247         PORTCR(279, 0xe6052117),
2248         PORTCR(280, 0xe6052118),
2249         PORTCR(281, 0xe6052119),
2250         PORTCR(282, 0xe605211A),
2251         PORTCR(283, 0xe605211B),
2252         PORTCR(288, 0xe6053120),
2253         PORTCR(289, 0xe6053121),
2254         PORTCR(290, 0xe6053122),
2255         PORTCR(291, 0xe6053123),
2256         PORTCR(292, 0xe6053124),
2257         PORTCR(293, 0xe6053125),
2258         PORTCR(294, 0xe6053126),
2259         PORTCR(295, 0xe6053127),
2260         PORTCR(296, 0xe6053128),
2261         PORTCR(297, 0xe6053129),
2262         PORTCR(298, 0xe605312A),
2263         PORTCR(299, 0xe605312B),
2264         PORTCR(300, 0xe605312C),
2265         PORTCR(301, 0xe605312D),
2266         PORTCR(302, 0xe605312E),
2267         PORTCR(303, 0xe605312F),
2268         PORTCR(304, 0xe6053130),
2269         PORTCR(305, 0xe6053131),
2270         PORTCR(306, 0xe6053132),
2271         PORTCR(307, 0xe6053133),
2272         PORTCR(308, 0xe6053134),
2273         PORTCR(320, 0xe6053140),
2274         PORTCR(321, 0xe6053141),
2275         PORTCR(322, 0xe6053142),
2276         PORTCR(323, 0xe6053143),
2277         PORTCR(324, 0xe6053144),
2278         PORTCR(325, 0xe6053145),
2279         PORTCR(326, 0xe6053146),
2280         PORTCR(327, 0xe6053147),
2281         PORTCR(328, 0xe6053148),
2282         PORTCR(329, 0xe6053149),
2283
2284         { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2285                         MSEL1CR_31_0, MSEL1CR_31_1,
2286                         0, 0,
2287                         0, 0,
2288                         0, 0,
2289                         MSEL1CR_27_0, MSEL1CR_27_1,
2290                         0, 0,
2291                         MSEL1CR_25_0, MSEL1CR_25_1,
2292                         MSEL1CR_24_0, MSEL1CR_24_1,
2293                         0, 0,
2294                         MSEL1CR_22_0, MSEL1CR_22_1,
2295                         MSEL1CR_21_0, MSEL1CR_21_1,
2296                         MSEL1CR_20_0, MSEL1CR_20_1,
2297                         MSEL1CR_19_0, MSEL1CR_19_1,
2298                         MSEL1CR_18_0, MSEL1CR_18_1,
2299                         MSEL1CR_17_0, MSEL1CR_17_1,
2300                         MSEL1CR_16_0, MSEL1CR_16_1,
2301                         MSEL1CR_15_0, MSEL1CR_15_1,
2302                         MSEL1CR_14_0, MSEL1CR_14_1,
2303                         MSEL1CR_13_0, MSEL1CR_13_1,
2304                         MSEL1CR_12_0, MSEL1CR_12_1,
2305                         MSEL1CR_11_0, MSEL1CR_11_1,
2306                         MSEL1CR_10_0, MSEL1CR_10_1,
2307                         MSEL1CR_09_0, MSEL1CR_09_1,
2308                         MSEL1CR_08_0, MSEL1CR_08_1,
2309                         MSEL1CR_07_0, MSEL1CR_07_1,
2310                         MSEL1CR_06_0, MSEL1CR_06_1,
2311                         MSEL1CR_05_0, MSEL1CR_05_1,
2312                         MSEL1CR_04_0, MSEL1CR_04_1,
2313                         MSEL1CR_03_0, MSEL1CR_03_1,
2314                         MSEL1CR_02_0, MSEL1CR_02_1,
2315                         MSEL1CR_01_0, MSEL1CR_01_1,
2316                         MSEL1CR_00_0, MSEL1CR_00_1,
2317                 }
2318         },
2319         { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
2320                         MSEL3CR_31_0, MSEL3CR_31_1,
2321                         0, 0,
2322                         0, 0,
2323                         MSEL3CR_28_0, MSEL3CR_28_1,
2324                         MSEL3CR_27_0, MSEL3CR_27_1,
2325                         MSEL3CR_26_0, MSEL3CR_26_1,
2326                         0, 0,
2327                         0, 0,
2328                         MSEL3CR_23_0, MSEL3CR_23_1,
2329                         MSEL3CR_22_0, MSEL3CR_22_1,
2330                         MSEL3CR_21_0, MSEL3CR_21_1,
2331                         MSEL3CR_20_0, MSEL3CR_20_1,
2332                         MSEL3CR_19_0, MSEL3CR_19_1,
2333                         MSEL3CR_18_0, MSEL3CR_18_1,
2334                         MSEL3CR_17_0, MSEL3CR_17_1,
2335                         MSEL3CR_16_0, MSEL3CR_16_1,
2336                         MSEL3CR_15_0, MSEL3CR_15_1,
2337                         0, 0,
2338                         0, 0,
2339                         MSEL3CR_12_0, MSEL3CR_12_1,
2340                         MSEL3CR_11_0, MSEL3CR_11_1,
2341                         MSEL3CR_10_0, MSEL3CR_10_1,
2342                         MSEL3CR_09_0, MSEL3CR_09_1,
2343                         0, 0,
2344                         0, 0,
2345                         MSEL3CR_06_0, MSEL3CR_06_1,
2346                         0, 0,
2347                         0, 0,
2348                         MSEL3CR_03_0, MSEL3CR_03_1,
2349                         0, 0,
2350                         MSEL3CR_01_0, MSEL3CR_01_1,
2351                         MSEL3CR_00_0, MSEL3CR_00_1,
2352                         }
2353         },
2354         { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
2355                         0, 0,
2356                         MSEL4CR_30_0, MSEL4CR_30_1,
2357                         MSEL4CR_29_0, MSEL4CR_29_1,
2358                         MSEL4CR_28_0, MSEL4CR_28_1,
2359                         MSEL4CR_27_0, MSEL4CR_27_1,
2360                         MSEL4CR_26_0, MSEL4CR_26_1,
2361                         MSEL4CR_25_0, MSEL4CR_25_1,
2362                         MSEL4CR_24_0, MSEL4CR_24_1,
2363                         MSEL4CR_23_0, MSEL4CR_23_1,
2364                         MSEL4CR_22_0, MSEL4CR_22_1,
2365                         MSEL4CR_21_0, MSEL4CR_21_1,
2366                         MSEL4CR_20_0, MSEL4CR_20_1,
2367                         MSEL4CR_19_0, MSEL4CR_19_1,
2368                         MSEL4CR_18_0, MSEL4CR_18_1,
2369                         MSEL4CR_17_0, MSEL4CR_17_1,
2370                         MSEL4CR_16_0, MSEL4CR_16_1,
2371                         MSEL4CR_15_0, MSEL4CR_15_1,
2372                         MSEL4CR_14_0, MSEL4CR_14_1,
2373                         MSEL4CR_13_0, MSEL4CR_13_1,
2374                         MSEL4CR_12_0, MSEL4CR_12_1,
2375                         MSEL4CR_11_0, MSEL4CR_11_1,
2376                         MSEL4CR_10_0, MSEL4CR_10_1,
2377                         MSEL4CR_09_0, MSEL4CR_09_1,
2378                         0, 0,
2379                         MSEL4CR_07_0, MSEL4CR_07_1,
2380                         0, 0,
2381                         0, 0,
2382                         MSEL4CR_04_0, MSEL4CR_04_1,
2383                         0, 0,
2384                         0, 0,
2385                         MSEL4CR_01_0, MSEL4CR_01_1,
2386                         0, 0,
2387                 }
2388         },
2389         { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
2390                         MSEL5CR_31_0, MSEL5CR_31_1,
2391                         MSEL5CR_30_0, MSEL5CR_30_1,
2392                         MSEL5CR_29_0, MSEL5CR_29_1,
2393                         MSEL5CR_28_0, MSEL5CR_28_1,
2394                         MSEL5CR_27_0, MSEL5CR_27_1,
2395                         MSEL5CR_26_0, MSEL5CR_26_1,
2396                         MSEL5CR_25_0, MSEL5CR_25_1,
2397                         MSEL5CR_24_0, MSEL5CR_24_1,
2398                         MSEL5CR_23_0, MSEL5CR_23_1,
2399                         MSEL5CR_22_0, MSEL5CR_22_1,
2400                         MSEL5CR_21_0, MSEL5CR_21_1,
2401                         MSEL5CR_20_0, MSEL5CR_20_1,
2402                         MSEL5CR_19_0, MSEL5CR_19_1,
2403                         MSEL5CR_18_0, MSEL5CR_18_1,
2404                         MSEL5CR_17_0, MSEL5CR_17_1,
2405                         MSEL5CR_16_0, MSEL5CR_16_1,
2406                         MSEL5CR_15_0, MSEL5CR_15_1,
2407                         MSEL5CR_14_0, MSEL5CR_14_1,
2408                         MSEL5CR_13_0, MSEL5CR_13_1,
2409                         MSEL5CR_12_0, MSEL5CR_12_1,
2410                         MSEL5CR_11_0, MSEL5CR_11_1,
2411                         MSEL5CR_10_0, MSEL5CR_10_1,
2412                         MSEL5CR_09_0, MSEL5CR_09_1,
2413                         MSEL5CR_08_0, MSEL5CR_08_1,
2414                         MSEL5CR_07_0, MSEL5CR_07_1,
2415                         MSEL5CR_06_0, MSEL5CR_06_1,
2416                         0, 0,
2417                         0, 0,
2418                         0, 0,
2419                         0, 0,
2420                         0, 0,
2421                         0, 0,
2422                 }
2423         },
2424         { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
2425                         0, 0,
2426                         0, 0,
2427                         0, 0,
2428                         0, 0,
2429                         0, 0,
2430                         0, 0,
2431                         0, 0,
2432                         0, 0,
2433                         0, 0,
2434                         0, 0,
2435                         0, 0,
2436                         0, 0,
2437                         0, 0,
2438                         0, 0,
2439                         0, 0,
2440                         MSEL8CR_16_0, MSEL8CR_16_1,
2441                         0, 0,
2442                         0, 0,
2443                         0, 0,
2444                         0, 0,
2445                         0, 0,
2446                         0, 0,
2447                         0, 0,
2448                         0, 0,
2449                         0, 0,
2450                         0, 0,
2451                         0, 0,
2452                         0, 0,
2453                         0, 0,
2454                         0, 0,
2455                         MSEL8CR_01_0, MSEL8CR_01_1,
2456                         MSEL8CR_00_0, MSEL8CR_00_1,
2457                 }
2458         },
2459         { },
2460 };
2461
2462 static const struct pinmux_data_reg pinmux_data_regs[] = {
2463
2464         { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
2465                         0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2466                         PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2467                         PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2468                         PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2469                         PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2470                         PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2471                         PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2472                         PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2473                 }
2474         },
2475         { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
2476                         0, 0, 0, 0,
2477                         0, 0, 0, 0,
2478                         0, 0, 0, 0,
2479                         0, 0, 0, 0,
2480                         0, 0, 0, 0,
2481                         0, 0, 0, PORT40_DATA,
2482                         PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2483                         PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2484                 }
2485         },
2486         { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
2487                         0, 0, 0, 0,
2488                         0, 0, 0, 0,
2489                         0, 0, PORT85_DATA, PORT84_DATA,
2490                         PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2491                         PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2492                         PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2493                         PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2494                         PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2495                 }
2496         },
2497         { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
2498                         0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2499                         PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2500                         PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2501                         PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2502                         PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2503                         PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2504                         PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2505                         PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2506                 }
2507         },
2508         { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
2509                         0, 0, 0, 0,
2510                         0, 0, 0, 0,
2511                         0, 0, 0, 0,
2512                         0, 0, 0, 0,
2513                         0, 0, 0, 0,
2514                         0, 0, 0, 0,
2515                         0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2516                         PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2517                 }
2518         },
2519         { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
2520                         0, 0, 0, 0,
2521                         0, 0, 0, 0,
2522                         0, 0, 0, 0,
2523                         0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2524                         PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2525                         PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2526                         PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2527                         PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2528                 }
2529         },
2530         { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
2531                         0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
2532                         PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
2533                         PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
2534                         PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
2535                         PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2536                         PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2537                         PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2538                         PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
2539                 }
2540         },
2541         { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
2542                         0, 0, 0, 0,
2543                         0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
2544                         PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
2545                         PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
2546                         PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
2547                         PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
2548                         PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
2549                         PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
2550                 }
2551         },
2552         { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
2553                         0, 0, 0, 0,
2554                         PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
2555                         PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
2556                         PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
2557                         PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
2558                         PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
2559                         PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
2560                         PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
2561                 }
2562         },
2563         { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
2564                         0, 0, 0, 0,
2565                         0, 0, 0, 0,
2566                         0, 0, 0, PORT308_DATA,
2567                         PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
2568                         PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
2569                         PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
2570                         PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
2571                         PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
2572                 }
2573         },
2574         { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
2575                         0, 0, 0, 0,
2576                         0, 0, 0, 0,
2577                         0, 0, 0, 0,
2578                         0, 0, 0, 0,
2579                         0, 0, 0, 0,
2580                         0, 0, PORT329_DATA, PORT328_DATA,
2581                         PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
2582                         PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
2583                 }
2584         },
2585         { },
2586 };
2587
2588 static const struct pinmux_irq pinmux_irqs[] = {
2589         PINMUX_IRQ(irq_pin(0), 0),
2590         PINMUX_IRQ(irq_pin(1), 1),
2591         PINMUX_IRQ(irq_pin(2), 2),
2592         PINMUX_IRQ(irq_pin(3), 3),
2593         PINMUX_IRQ(irq_pin(4), 4),
2594         PINMUX_IRQ(irq_pin(5), 5),
2595         PINMUX_IRQ(irq_pin(6), 6),
2596         PINMUX_IRQ(irq_pin(7), 7),
2597         PINMUX_IRQ(irq_pin(8), 8),
2598         PINMUX_IRQ(irq_pin(9), 9),
2599         PINMUX_IRQ(irq_pin(10), 10),
2600         PINMUX_IRQ(irq_pin(11), 11),
2601         PINMUX_IRQ(irq_pin(12), 12),
2602         PINMUX_IRQ(irq_pin(13), 13),
2603         PINMUX_IRQ(irq_pin(14), 14),
2604         PINMUX_IRQ(irq_pin(15), 15),
2605         PINMUX_IRQ(irq_pin(16), 320),
2606         PINMUX_IRQ(irq_pin(17), 321),
2607         PINMUX_IRQ(irq_pin(18), 85),
2608         PINMUX_IRQ(irq_pin(19), 84),
2609         PINMUX_IRQ(irq_pin(20), 160),
2610         PINMUX_IRQ(irq_pin(21), 161),
2611         PINMUX_IRQ(irq_pin(22), 162),
2612         PINMUX_IRQ(irq_pin(23), 163),
2613         PINMUX_IRQ(irq_pin(24), 175),
2614         PINMUX_IRQ(irq_pin(25), 176),
2615         PINMUX_IRQ(irq_pin(26), 177),
2616         PINMUX_IRQ(irq_pin(27), 178),
2617         PINMUX_IRQ(irq_pin(28), 322),
2618         PINMUX_IRQ(irq_pin(29), 323),
2619         PINMUX_IRQ(irq_pin(30), 324),
2620         PINMUX_IRQ(irq_pin(31), 192),
2621         PINMUX_IRQ(irq_pin(32), 193),
2622         PINMUX_IRQ(irq_pin(33), 194),
2623         PINMUX_IRQ(irq_pin(34), 195),
2624         PINMUX_IRQ(irq_pin(35), 196),
2625         PINMUX_IRQ(irq_pin(36), 197),
2626         PINMUX_IRQ(irq_pin(37), 198),
2627         PINMUX_IRQ(irq_pin(38), 199),
2628         PINMUX_IRQ(irq_pin(39), 200),
2629         PINMUX_IRQ(irq_pin(40), 66),
2630         PINMUX_IRQ(irq_pin(41), 102),
2631         PINMUX_IRQ(irq_pin(42), 103),
2632         PINMUX_IRQ(irq_pin(43), 109),
2633         PINMUX_IRQ(irq_pin(44), 110),
2634         PINMUX_IRQ(irq_pin(45), 111),
2635         PINMUX_IRQ(irq_pin(46), 112),
2636         PINMUX_IRQ(irq_pin(47), 113),
2637         PINMUX_IRQ(irq_pin(48), 114),
2638         PINMUX_IRQ(irq_pin(49), 115),
2639         PINMUX_IRQ(irq_pin(50), 301),
2640         PINMUX_IRQ(irq_pin(51), 290),
2641         PINMUX_IRQ(irq_pin(52), 296),
2642         PINMUX_IRQ(irq_pin(53), 325),
2643         PINMUX_IRQ(irq_pin(54), 326),
2644         PINMUX_IRQ(irq_pin(55), 327),
2645         PINMUX_IRQ(irq_pin(56), 328),
2646         PINMUX_IRQ(irq_pin(57), 329),
2647 };
2648
2649 #define PORTCR_PULMD_OFF (0 << 6)
2650 #define PORTCR_PULMD_DOWN (2 << 6)
2651 #define PORTCR_PULMD_UP (3 << 6)
2652 #define PORTCR_PULMD_MASK (3 << 6)
2653
2654 static const unsigned int r8a73a4_portcr_offsets[] = {
2655         0x00000000, 0x00001000, 0x00000000, 0x00001000,
2656         0x00001000, 0x00002000, 0x00002000, 0x00002000,
2657         0x00002000, 0x00003000, 0x00003000,
2658 };
2659
2660 static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
2661                                             unsigned int pin)
2662 {
2663         void __iomem *addr;
2664
2665         addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2666
2667         switch (ioread8(addr) & PORTCR_PULMD_MASK) {
2668         case PORTCR_PULMD_UP:
2669                 return PIN_CONFIG_BIAS_PULL_UP;
2670         case PORTCR_PULMD_DOWN:
2671                 return PIN_CONFIG_BIAS_PULL_DOWN;
2672         case PORTCR_PULMD_OFF:
2673         default:
2674                 return PIN_CONFIG_BIAS_DISABLE;
2675         }
2676 }
2677
2678 static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2679                                    unsigned int bias)
2680 {
2681         void __iomem *addr;
2682         u32 value;
2683
2684         addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2685         value = ioread8(addr) & ~PORTCR_PULMD_MASK;
2686
2687         switch (bias) {
2688         case PIN_CONFIG_BIAS_PULL_UP:
2689                 value |= PORTCR_PULMD_UP;
2690                 break;
2691         case PIN_CONFIG_BIAS_PULL_DOWN:
2692                 value |= PORTCR_PULMD_DOWN;
2693                 break;
2694         }
2695
2696         iowrite8(value, addr);
2697 }
2698
2699 static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
2700         .get_bias = r8a73a4_pinmux_get_bias,
2701         .set_bias = r8a73a4_pinmux_set_bias,
2702 };
2703
2704 const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2705         .name           = "r8a73a4_pfc",
2706         .ops            = &r8a73a4_pinmux_ops,
2707
2708         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2709         .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
2710         .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
2711         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2712         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2713
2714         .pins = pinmux_pins,
2715         .nr_pins = ARRAY_SIZE(pinmux_pins),
2716
2717         .ranges = pinmux_ranges,
2718         .nr_ranges = ARRAY_SIZE(pinmux_ranges),
2719
2720         .groups = pinmux_groups,
2721         .nr_groups = ARRAY_SIZE(pinmux_groups),
2722         .functions = pinmux_functions,
2723         .nr_functions = ARRAY_SIZE(pinmux_functions),
2724
2725         .cfg_regs       = pinmux_config_regs,
2726         .data_regs      = pinmux_data_regs,
2727
2728         .gpio_data      = pinmux_data,
2729         .gpio_data_size = ARRAY_SIZE(pinmux_data),
2730
2731         .gpio_irq = pinmux_irqs,
2732         .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2733 };