drivers/pinctrl/sh-pfc/pfc-r8a7740.c

   1 /*
   2  * R8A7740 processor support
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of the
  10  * License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/pinctrl/pinconf-generic.h>
  24
  25 #include <mach/r8a7740.h>
  26 #include <mach/irqs.h>
  27
  28 #include "core.h"
  29 #include "sh_pfc.h"
  30
  31 #define CPU_ALL_PORT(fn, pfx, sfx)                                      \
  32         PORT_10(fn, pfx, sfx),          PORT_90(fn, pfx, sfx),          \
  33         PORT_10(fn, pfx##10, sfx),      PORT_90(fn, pfx##1, sfx),       \
  34         PORT_10(fn, pfx##20, sfx),                                      \
  35         PORT_1(fn, pfx##210, sfx),      PORT_1(fn, pfx##211, sfx)
  36
  37 #undef _GPIO_PORT
  38 #define _GPIO_PORT(gpio, sfx)                                           \
  39         [gpio] = {                                                      \
  40                 .name = __stringify(PORT##gpio),                        \
  41                 .enum_id = PORT##gpio##_DATA,                           \
  42         }
  43
  44 #define IRQC_PIN_MUX(irq, pin)                                          \
  45 static const unsigned int intc_irq##irq##_pins[] = {                    \
  46         pin,                                                            \
  47 };                                                                      \
  48 static const unsigned int intc_irq##irq##_mux[] = {                     \
  49         IRQ##irq##_MARK,                                                \
  50 }
  51
  52 #define IRQC_PINS_MUX(irq, idx, pin)                                    \
  53 static const unsigned int intc_irq##irq##_##idx##_pins[] = {            \
  54         pin,                                                            \
  55 };                                                                      \
  56 static const unsigned int intc_irq##irq##_##idx##_mux[] = {             \
  57         IRQ##irq##_PORT##pin##_MARK,                                    \
  58 }
  59
  60 enum {
  61         PINMUX_RESERVED = 0,
  62
  63         /* PORT0_DATA -> PORT211_DATA */
  64         PINMUX_DATA_BEGIN,
  65         PORT_ALL(DATA),
  66         PINMUX_DATA_END,
  67
  68         /* PORT0_IN -> PORT211_IN */
  69         PINMUX_INPUT_BEGIN,
  70         PORT_ALL(IN),
  71         PINMUX_INPUT_END,
  72
  73         /* PORT0_OUT -> PORT211_OUT */
  74         PINMUX_OUTPUT_BEGIN,
  75         PORT_ALL(OUT),
  76         PINMUX_OUTPUT_END,
  77
  78         PINMUX_FUNCTION_BEGIN,
  79         PORT_ALL(FN_IN),        /* PORT0_FN_IN -> PORT211_FN_IN */
  80         PORT_ALL(FN_OUT),       /* PORT0_FN_OUT -> PORT211_FN_OUT */
  81         PORT_ALL(FN0),          /* PORT0_FN0 -> PORT211_FN0 */
  82         PORT_ALL(FN1),          /* PORT0_FN1 -> PORT211_FN1 */
  83         PORT_ALL(FN2),          /* PORT0_FN2 -> PORT211_FN2 */
  84         PORT_ALL(FN3),          /* PORT0_FN3 -> PORT211_FN3 */
  85         PORT_ALL(FN4),          /* PORT0_FN4 -> PORT211_FN4 */
  86         PORT_ALL(FN5),          /* PORT0_FN5 -> PORT211_FN5 */
  87         PORT_ALL(FN6),          /* PORT0_FN6 -> PORT211_FN6 */
  88         PORT_ALL(FN7),          /* PORT0_FN7 -> PORT211_FN7 */
  89
  90         MSEL1CR_31_0,   MSEL1CR_31_1,
  91         MSEL1CR_30_0,   MSEL1CR_30_1,
  92         MSEL1CR_29_0,   MSEL1CR_29_1,
  93         MSEL1CR_28_0,   MSEL1CR_28_1,
  94         MSEL1CR_27_0,   MSEL1CR_27_1,
  95         MSEL1CR_26_0,   MSEL1CR_26_1,
  96         MSEL1CR_16_0,   MSEL1CR_16_1,
  97         MSEL1CR_15_0,   MSEL1CR_15_1,
  98         MSEL1CR_14_0,   MSEL1CR_14_1,
  99         MSEL1CR_13_0,   MSEL1CR_13_1,
 100         MSEL1CR_12_0,   MSEL1CR_12_1,
 101         MSEL1CR_9_0,    MSEL1CR_9_1,
 102         MSEL1CR_7_0,    MSEL1CR_7_1,
 103         MSEL1CR_6_0,    MSEL1CR_6_1,
 104         MSEL1CR_5_0,    MSEL1CR_5_1,
 105         MSEL1CR_4_0,    MSEL1CR_4_1,
 106         MSEL1CR_3_0,    MSEL1CR_3_1,
 107         MSEL1CR_2_0,    MSEL1CR_2_1,
 108         MSEL1CR_0_0,    MSEL1CR_0_1,
 109
 110         MSEL3CR_15_0,   MSEL3CR_15_1, /* Trace / Debug ? */
 111         MSEL3CR_6_0,    MSEL3CR_6_1,
 112
 113         MSEL4CR_19_0,   MSEL4CR_19_1,
 114         MSEL4CR_18_0,   MSEL4CR_18_1,
 115         MSEL4CR_15_0,   MSEL4CR_15_1,
 116         MSEL4CR_10_0,   MSEL4CR_10_1,
 117         MSEL4CR_6_0,    MSEL4CR_6_1,
 118         MSEL4CR_4_0,    MSEL4CR_4_1,
 119         MSEL4CR_1_0,    MSEL4CR_1_1,
 120
 121         MSEL5CR_31_0,   MSEL5CR_31_1, /* irq/fiq output */
 122         MSEL5CR_30_0,   MSEL5CR_30_1,
 123         MSEL5CR_29_0,   MSEL5CR_29_1,
 124         MSEL5CR_27_0,   MSEL5CR_27_1,
 125         MSEL5CR_25_0,   MSEL5CR_25_1,
 126         MSEL5CR_23_0,   MSEL5CR_23_1,
 127         MSEL5CR_21_0,   MSEL5CR_21_1,
 128         MSEL5CR_19_0,   MSEL5CR_19_1,
 129         MSEL5CR_17_0,   MSEL5CR_17_1,
 130         MSEL5CR_15_0,   MSEL5CR_15_1,
 131         MSEL5CR_14_0,   MSEL5CR_14_1,
 132         MSEL5CR_13_0,   MSEL5CR_13_1,
 133         MSEL5CR_12_0,   MSEL5CR_12_1,
 134         MSEL5CR_11_0,   MSEL5CR_11_1,
 135         MSEL5CR_10_0,   MSEL5CR_10_1,
 136         MSEL5CR_8_0,    MSEL5CR_8_1,
 137         MSEL5CR_7_0,    MSEL5CR_7_1,
 138         MSEL5CR_6_0,    MSEL5CR_6_1,
 139         MSEL5CR_5_0,    MSEL5CR_5_1,
 140         MSEL5CR_4_0,    MSEL5CR_4_1,
 141         MSEL5CR_3_0,    MSEL5CR_3_1,
 142         MSEL5CR_2_0,    MSEL5CR_2_1,
 143         MSEL5CR_0_0,    MSEL5CR_0_1,
 144         PINMUX_FUNCTION_END,
 145
 146         PINMUX_MARK_BEGIN,
 147
 148         /* IRQ */
 149         IRQ0_PORT2_MARK,        IRQ0_PORT13_MARK,
 150         IRQ1_MARK,
 151         IRQ2_PORT11_MARK,       IRQ2_PORT12_MARK,
 152         IRQ3_PORT10_MARK,       IRQ3_PORT14_MARK,
 153         IRQ4_PORT15_MARK,       IRQ4_PORT172_MARK,
 154         IRQ5_PORT0_MARK,        IRQ5_PORT1_MARK,
 155         IRQ6_PORT121_MARK,      IRQ6_PORT173_MARK,
 156         IRQ7_PORT120_MARK,      IRQ7_PORT209_MARK,
 157         IRQ8_MARK,
 158         IRQ9_PORT118_MARK,      IRQ9_PORT210_MARK,
 159         IRQ10_MARK,
 160         IRQ11_MARK,
 161         IRQ12_PORT42_MARK,      IRQ12_PORT97_MARK,
 162         IRQ13_PORT64_MARK,      IRQ13_PORT98_MARK,
 163         IRQ14_PORT63_MARK,      IRQ14_PORT99_MARK,
 164         IRQ15_PORT62_MARK,      IRQ15_PORT100_MARK,
 165         IRQ16_PORT68_MARK,      IRQ16_PORT211_MARK,
 166         IRQ17_MARK,
 167         IRQ18_MARK,
 168         IRQ19_MARK,
 169         IRQ20_MARK,
 170         IRQ21_MARK,
 171         IRQ22_MARK,
 172         IRQ23_MARK,
 173         IRQ24_MARK,
 174         IRQ25_MARK,
 175         IRQ26_PORT58_MARK,      IRQ26_PORT81_MARK,
 176         IRQ27_PORT57_MARK,      IRQ27_PORT168_MARK,
 177         IRQ28_PORT56_MARK,      IRQ28_PORT169_MARK,
 178         IRQ29_PORT50_MARK,      IRQ29_PORT170_MARK,
 179         IRQ30_PORT49_MARK,      IRQ30_PORT171_MARK,
 180         IRQ31_PORT41_MARK,      IRQ31_PORT167_MARK,
 181
 182         /* Function */
 183
 184         /* DBGT */
 185         DBGMDT2_MARK,   DBGMDT1_MARK,   DBGMDT0_MARK,
 186         DBGMD10_MARK,   DBGMD11_MARK,   DBGMD20_MARK,
 187         DBGMD21_MARK,
 188
 189         /* FSI-A */
 190         FSIAISLD_PORT0_MARK,    /* FSIAISLD Port 0/5 */
 191         FSIAISLD_PORT5_MARK,
 192         FSIASPDIF_PORT9_MARK,   /* FSIASPDIF Port 9/18 */
 193         FSIASPDIF_PORT18_MARK,
 194         FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
 195         FSIAOBT_MARK,   FSIAOSLD_MARK,  FSIAOMC_MARK,
 196         FSIACK_MARK,    FSIAILR_MARK,   FSIAIBT_MARK,
 197
 198         /* FSI-B */
 199         FSIBCK_MARK,
 200
 201         /* FMSI */
 202         FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
 203         FMSISLD_PORT6_MARK,
 204         FMSIILR_MARK,   FMSIIBT_MARK,   FMSIOLR_MARK,   FMSIOBT_MARK,
 205         FMSICK_MARK,    FMSOILR_MARK,   FMSOIBT_MARK,   FMSOOLR_MARK,
 206         FMSOOBT_MARK,   FMSOSLD_MARK,   FMSOCK_MARK,
 207
 208         /* SCIFA0 */
 209         SCIFA0_SCK_MARK,        SCIFA0_CTS_MARK,        SCIFA0_RTS_MARK,
 210         SCIFA0_RXD_MARK,        SCIFA0_TXD_MARK,
 211
 212         /* SCIFA1 */
 213         SCIFA1_CTS_MARK,        SCIFA1_SCK_MARK,        SCIFA1_RXD_MARK,
 214         SCIFA1_TXD_MARK,        SCIFA1_RTS_MARK,
 215
 216         /* SCIFA2 */
 217         SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
 218         SCIFA2_SCK_PORT199_MARK,
 219         SCIFA2_RXD_MARK,        SCIFA2_TXD_MARK,
 220         SCIFA2_CTS_MARK,        SCIFA2_RTS_MARK,
 221
 222         /* SCIFA3 */
 223         SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
 224         SCIFA3_SCK_PORT116_MARK,
 225         SCIFA3_CTS_PORT117_MARK,
 226         SCIFA3_RXD_PORT174_MARK,
 227         SCIFA3_TXD_PORT175_MARK,
 228
 229         SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
 230         SCIFA3_SCK_PORT158_MARK,
 231         SCIFA3_CTS_PORT162_MARK,
 232         SCIFA3_RXD_PORT159_MARK,
 233         SCIFA3_TXD_PORT160_MARK,
 234
 235         /* SCIFA4 */
 236         SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
 237         SCIFA4_TXD_PORT13_MARK,
 238
 239         SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
 240         SCIFA4_TXD_PORT203_MARK,
 241
 242         SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
 243         SCIFA4_TXD_PORT93_MARK,
 244
 245         SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
 246         SCIFA4_SCK_PORT205_MARK,
 247
 248         /* SCIFA5 */
 249         SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
 250         SCIFA5_RXD_PORT10_MARK,
 251
 252         SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
 253         SCIFA5_TXD_PORT208_MARK,
 254
 255         SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
 256         SCIFA5_RXD_PORT92_MARK,
 257
 258         SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
 259         SCIFA5_SCK_PORT206_MARK,
 260
 261         /* SCIFA6 */
 262         SCIFA6_SCK_MARK,        SCIFA6_RXD_MARK,        SCIFA6_TXD_MARK,
 263
 264         /* SCIFA7 */
 265         SCIFA7_TXD_MARK,        SCIFA7_RXD_MARK,
 266
 267         /* SCIFAB */
 268         SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
 269         SCIFB_RXD_PORT191_MARK,
 270         SCIFB_TXD_PORT192_MARK,
 271         SCIFB_RTS_PORT186_MARK,
 272         SCIFB_CTS_PORT187_MARK,
 273
 274         SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
 275         SCIFB_RXD_PORT3_MARK,
 276         SCIFB_TXD_PORT4_MARK,
 277         SCIFB_RTS_PORT172_MARK,
 278         SCIFB_CTS_PORT173_MARK,
 279
 280         /* LCD0 */
 281         LCD0_D0_MARK,   LCD0_D1_MARK,   LCD0_D2_MARK,   LCD0_D3_MARK,
 282         LCD0_D4_MARK,   LCD0_D5_MARK,   LCD0_D6_MARK,   LCD0_D7_MARK,
 283         LCD0_D8_MARK,   LCD0_D9_MARK,   LCD0_D10_MARK,  LCD0_D11_MARK,
 284         LCD0_D12_MARK,  LCD0_D13_MARK,  LCD0_D14_MARK,  LCD0_D15_MARK,
 285         LCD0_D16_MARK,  LCD0_D17_MARK,
 286         LCD0_DON_MARK,  LCD0_VCPWC_MARK,        LCD0_VEPWC_MARK,
 287         LCD0_DCK_MARK,  LCD0_VSYN_MARK, /* for RGB */
 288         LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
 289         LCD0_WR_MARK,   LCD0_RD_MARK,   /* for SYS */
 290         LCD0_CS_MARK,   LCD0_RS_MARK,   /* for SYS */
 291
 292         LCD0_D21_PORT158_MARK,  LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
 293         LCD0_D22_PORT160_MARK,  LCD0_D20_PORT161_MARK,
 294         LCD0_D19_PORT162_MARK,  LCD0_D18_PORT163_MARK,
 295         LCD0_LCLK_PORT165_MARK,
 296
 297         LCD0_D18_PORT40_MARK,   LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
 298         LCD0_D23_PORT1_MARK,    LCD0_D21_PORT2_MARK,
 299         LCD0_D20_PORT3_MARK,    LCD0_D19_PORT4_MARK,
 300         LCD0_LCLK_PORT102_MARK,
 301
 302         /* LCD1 */
 303         LCD1_D0_MARK,   LCD1_D1_MARK,   LCD1_D2_MARK,   LCD1_D3_MARK,
 304         LCD1_D4_MARK,   LCD1_D5_MARK,   LCD1_D6_MARK,   LCD1_D7_MARK,
 305         LCD1_D8_MARK,   LCD1_D9_MARK,   LCD1_D10_MARK,  LCD1_D11_MARK,
 306         LCD1_D12_MARK,  LCD1_D13_MARK,  LCD1_D14_MARK,  LCD1_D15_MARK,
 307         LCD1_D16_MARK,  LCD1_D17_MARK,  LCD1_D18_MARK,  LCD1_D19_MARK,
 308         LCD1_D20_MARK,  LCD1_D21_MARK,  LCD1_D22_MARK,  LCD1_D23_MARK,
 309         LCD1_DON_MARK,  LCD1_VCPWC_MARK,
 310         LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
 311
 312         LCD1_DCK_MARK,  LCD1_VSYN_MARK, /* for RGB */
 313         LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
 314         LCD1_RS_MARK,   LCD1_CS_MARK,   /* for SYS */
 315         LCD1_RD_MARK,   LCD1_WR_MARK,   /* for SYS */
 316
 317         /* RSPI */
 318         RSPI_SSL0_A_MARK,       RSPI_SSL1_A_MARK,       RSPI_SSL2_A_MARK,
 319         RSPI_SSL3_A_MARK,       RSPI_CK_A_MARK,         RSPI_MOSI_A_MARK,
 320         RSPI_MISO_A_MARK,
 321
 322         /* VIO CKO */
 323         VIO_CKO1_MARK, /* needs fixup */
 324         VIO_CKO2_MARK,
 325         VIO_CKO_1_MARK,
 326         VIO_CKO_MARK,
 327
 328         /* VIO0 */
 329         VIO0_D0_MARK,   VIO0_D1_MARK,   VIO0_D2_MARK,   VIO0_D3_MARK,
 330         VIO0_D4_MARK,   VIO0_D5_MARK,   VIO0_D6_MARK,   VIO0_D7_MARK,
 331         VIO0_D8_MARK,   VIO0_D9_MARK,   VIO0_D10_MARK,  VIO0_D11_MARK,
 332         VIO0_D12_MARK,  VIO0_VD_MARK,   VIO0_HD_MARK,   VIO0_CLK_MARK,
 333         VIO0_FIELD_MARK,
 334
 335         VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
 336         VIO0_D14_PORT25_MARK,
 337         VIO0_D15_PORT24_MARK,
 338
 339         VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
 340         VIO0_D14_PORT95_MARK,
 341         VIO0_D15_PORT96_MARK,
 342
 343         /* VIO1 */
 344         VIO1_D0_MARK,   VIO1_D1_MARK,   VIO1_D2_MARK,   VIO1_D3_MARK,
 345         VIO1_D4_MARK,   VIO1_D5_MARK,   VIO1_D6_MARK,   VIO1_D7_MARK,
 346         VIO1_VD_MARK,   VIO1_HD_MARK,   VIO1_CLK_MARK,  VIO1_FIELD_MARK,
 347
 348         /* TPU0 */
 349         TPU0TO0_MARK,   TPU0TO1_MARK,   TPU0TO3_MARK,
 350         TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
 351         TPU0TO2_PORT202_MARK,
 352
 353         /* SSP1 0 */
 354         STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
 355         STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
 356         STP0_IPEN_MARK, STP0_IPCLK_MARK,        STP0_IPSYNC_MARK,
 357
 358         /* SSP1 1 */
 359         STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
 360         STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
 361         STP1_IPSYNC_MARK,
 362
 363         STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
 364         STP1_IPEN_PORT187_MARK,
 365
 366         STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
 367         STP1_IPEN_PORT193_MARK,
 368
 369         /* SIM */
 370         SIM_RST_MARK,   SIM_CLK_MARK,
 371         SIM_D_PORT22_MARK, /* SIM_D  Port 22/199 */
 372         SIM_D_PORT199_MARK,
 373
 374         /* SDHI0 */
 375         SDHI0_D0_MARK,  SDHI0_D1_MARK,  SDHI0_D2_MARK,  SDHI0_D3_MARK,
 376         SDHI0_CD_MARK,  SDHI0_WP_MARK,  SDHI0_CMD_MARK, SDHI0_CLK_MARK,
 377
 378         /* SDHI1 */
 379         SDHI1_D0_MARK,  SDHI1_D1_MARK,  SDHI1_D2_MARK,  SDHI1_D3_MARK,
 380         SDHI1_CD_MARK,  SDHI1_WP_MARK,  SDHI1_CMD_MARK, SDHI1_CLK_MARK,
 381
 382         /* SDHI2 */
 383         SDHI2_D0_MARK,  SDHI2_D1_MARK,  SDHI2_D2_MARK,  SDHI2_D3_MARK,
 384         SDHI2_CLK_MARK, SDHI2_CMD_MARK,
 385
 386         SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
 387         SDHI2_WP_PORT25_MARK,
 388
 389         SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
 390         SDHI2_CD_PORT202_MARK,
 391
 392         /* MSIOF2 */
 393         MSIOF2_TXD_MARK,        MSIOF2_RXD_MARK,        MSIOF2_TSCK_MARK,
 394         MSIOF2_SS2_MARK,        MSIOF2_TSYNC_MARK,      MSIOF2_SS1_MARK,
 395         MSIOF2_MCK1_MARK,       MSIOF2_MCK0_MARK,       MSIOF2_RSYNC_MARK,
 396         MSIOF2_RSCK_MARK,
 397
 398         /* KEYSC */
 399         KEYIN4_MARK,    KEYIN5_MARK,    KEYIN6_MARK,    KEYIN7_MARK,
 400         KEYOUT0_MARK,   KEYOUT1_MARK,   KEYOUT2_MARK,   KEYOUT3_MARK,
 401         KEYOUT4_MARK,   KEYOUT5_MARK,   KEYOUT6_MARK,   KEYOUT7_MARK,
 402
 403         KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
 404         KEYIN1_PORT44_MARK,
 405         KEYIN2_PORT45_MARK,
 406         KEYIN3_PORT46_MARK,
 407
 408         KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
 409         KEYIN1_PORT57_MARK,
 410         KEYIN2_PORT56_MARK,
 411         KEYIN3_PORT55_MARK,
 412
 413         /* VOU */
 414         DV_D0_MARK,     DV_D1_MARK,     DV_D2_MARK,     DV_D3_MARK,
 415         DV_D4_MARK,     DV_D5_MARK,     DV_D6_MARK,     DV_D7_MARK,
 416         DV_D8_MARK,     DV_D9_MARK,     DV_D10_MARK,    DV_D11_MARK,
 417         DV_D12_MARK,    DV_D13_MARK,    DV_D14_MARK,    DV_D15_MARK,
 418         DV_CLK_MARK,    DV_VSYNC_MARK,  DV_HSYNC_MARK,
 419
 420         /* MEMC */
 421         MEMC_AD0_MARK,  MEMC_AD1_MARK,  MEMC_AD2_MARK,  MEMC_AD3_MARK,
 422         MEMC_AD4_MARK,  MEMC_AD5_MARK,  MEMC_AD6_MARK,  MEMC_AD7_MARK,
 423         MEMC_AD8_MARK,  MEMC_AD9_MARK,  MEMC_AD10_MARK, MEMC_AD11_MARK,
 424         MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
 425         MEMC_CS0_MARK,  MEMC_INT_MARK,  MEMC_NWE_MARK,  MEMC_NOE_MARK,
 426
 427         MEMC_CS1_MARK, /* MSEL4CR_6_0 */
 428         MEMC_ADV_MARK,
 429         MEMC_WAIT_MARK,
 430         MEMC_BUSCLK_MARK,
 431
 432         MEMC_A1_MARK, /* MSEL4CR_6_1 */
 433         MEMC_DREQ0_MARK,
 434         MEMC_DREQ1_MARK,
 435         MEMC_A0_MARK,
 436
 437         /* MMC */
 438         MMC0_D0_PORT68_MARK,    MMC0_D1_PORT69_MARK,    MMC0_D2_PORT70_MARK,
 439         MMC0_D3_PORT71_MARK,    MMC0_D4_PORT72_MARK,    MMC0_D5_PORT73_MARK,
 440         MMC0_D6_PORT74_MARK,    MMC0_D7_PORT75_MARK,    MMC0_CLK_PORT66_MARK,
 441         MMC0_CMD_PORT67_MARK,   /* MSEL4CR_15_0 */
 442
 443         MMC1_D0_PORT149_MARK,   MMC1_D1_PORT148_MARK,   MMC1_D2_PORT147_MARK,
 444         MMC1_D3_PORT146_MARK,   MMC1_D4_PORT145_MARK,   MMC1_D5_PORT144_MARK,
 445         MMC1_D6_PORT143_MARK,   MMC1_D7_PORT142_MARK,   MMC1_CLK_PORT103_MARK,
 446         MMC1_CMD_PORT104_MARK,  /* MSEL4CR_15_1 */
 447
 448         /* MSIOF0 */
 449         MSIOF0_SS1_MARK,        MSIOF0_SS2_MARK,        MSIOF0_RXD_MARK,
 450         MSIOF0_TXD_MARK,        MSIOF0_MCK0_MARK,       MSIOF0_MCK1_MARK,
 451         MSIOF0_RSYNC_MARK,      MSIOF0_RSCK_MARK,       MSIOF0_TSCK_MARK,
 452         MSIOF0_TSYNC_MARK,
 453
 454         /* MSIOF1 */
 455         MSIOF1_RSCK_MARK,       MSIOF1_RSYNC_MARK,
 456         MSIOF1_MCK0_MARK,       MSIOF1_MCK1_MARK,
 457
 458         MSIOF1_SS2_PORT116_MARK,        MSIOF1_SS1_PORT117_MARK,
 459         MSIOF1_RXD_PORT118_MARK,        MSIOF1_TXD_PORT119_MARK,
 460         MSIOF1_TSYNC_PORT120_MARK,
 461         MSIOF1_TSCK_PORT121_MARK,       /* MSEL4CR_10_0 */
 462
 463         MSIOF1_SS1_PORT67_MARK,         MSIOF1_TSCK_PORT72_MARK,
 464         MSIOF1_TSYNC_PORT73_MARK,       MSIOF1_TXD_PORT74_MARK,
 465         MSIOF1_RXD_PORT75_MARK,
 466         MSIOF1_SS2_PORT202_MARK,        /* MSEL4CR_10_1 */
 467
 468         /* GPIO */
 469         GPO0_MARK,      GPI0_MARK,      GPO1_MARK,      GPI1_MARK,
 470
 471         /* USB0 */
 472         USB0_OCI_MARK,  USB0_PPON_MARK, VBUS_MARK,
 473
 474         /* USB1 */
 475         USB1_OCI_MARK,  USB1_PPON_MARK,
 476
 477         /* BBIF1 */
 478         BBIF1_RXD_MARK,         BBIF1_TXD_MARK,         BBIF1_TSYNC_MARK,
 479         BBIF1_TSCK_MARK,        BBIF1_RSCK_MARK,        BBIF1_RSYNC_MARK,
 480         BBIF1_FLOW_MARK,        BBIF1_RX_FLOW_N_MARK,
 481
 482         /* BBIF2 */
 483         BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
 484         BBIF2_RXD2_PORT60_MARK,
 485         BBIF2_TSYNC2_PORT6_MARK,
 486         BBIF2_TSCK2_PORT59_MARK,
 487
 488         BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
 489         BBIF2_TXD2_PORT183_MARK,
 490         BBIF2_TSCK2_PORT89_MARK,
 491         BBIF2_TSYNC2_PORT184_MARK,
 492
 493         /* BSC / FLCTL / PCMCIA */
 494         CS0_MARK,       CS2_MARK,       CS4_MARK,
 495         CS5B_MARK,      CS6A_MARK,
 496         CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
 497         CS5A_PORT19_MARK,
 498         IOIS16_MARK, /* ? */
 499
 500         A0_MARK,        A1_MARK,        A2_MARK,        A3_MARK,
 501         A4_FOE_MARK,    /* share with FLCTL */
 502         A5_FCDE_MARK,   /* share with FLCTL */
 503         A6_MARK,        A7_MARK,        A8_MARK,        A9_MARK,
 504         A10_MARK,       A11_MARK,       A12_MARK,       A13_MARK,
 505         A14_MARK,       A15_MARK,       A16_MARK,       A17_MARK,
 506         A18_MARK,       A19_MARK,       A20_MARK,       A21_MARK,
 507         A22_MARK,       A23_MARK,       A24_MARK,       A25_MARK,
 508         A26_MARK,
 509
 510         D0_NAF0_MARK,   D1_NAF1_MARK,   D2_NAF2_MARK,   /* share with FLCTL */
 511         D3_NAF3_MARK,   D4_NAF4_MARK,   D5_NAF5_MARK,   /* share with FLCTL */
 512         D6_NAF6_MARK,   D7_NAF7_MARK,   D8_NAF8_MARK,   /* share with FLCTL */
 513         D9_NAF9_MARK,   D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
 514         D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
 515         D15_NAF15_MARK,                                 /* share with FLCTL */
 516         D16_MARK,       D17_MARK,       D18_MARK,       D19_MARK,
 517         D20_MARK,       D21_MARK,       D22_MARK,       D23_MARK,
 518         D24_MARK,       D25_MARK,       D26_MARK,       D27_MARK,
 519         D28_MARK,       D29_MARK,       D30_MARK,       D31_MARK,
 520
 521         WE0_FWE_MARK,   /* share with FLCTL */
 522         WE1_MARK,
 523         WE2_ICIORD_MARK,        /* share with PCMCIA */
 524         WE3_ICIOWR_MARK,        /* share with PCMCIA */
 525         CKO_MARK,       BS_MARK,        RDWR_MARK,
 526         RD_FSC_MARK,    /* share with FLCTL */
 527         WAIT_PORT177_MARK, /* WAIT Port 90/177 */
 528         WAIT_PORT90_MARK,
 529
 530         FCE0_MARK,      FCE1_MARK,      FRB_MARK, /* FLCTL */
 531
 532         /* IRDA */
 533         IRDA_FIRSEL_MARK,       IRDA_IN_MARK,   IRDA_OUT_MARK,
 534
 535         /* ATAPI */
 536         IDE_D0_MARK,    IDE_D1_MARK,    IDE_D2_MARK,    IDE_D3_MARK,
 537         IDE_D4_MARK,    IDE_D5_MARK,    IDE_D6_MARK,    IDE_D7_MARK,
 538         IDE_D8_MARK,    IDE_D9_MARK,    IDE_D10_MARK,   IDE_D11_MARK,
 539         IDE_D12_MARK,   IDE_D13_MARK,   IDE_D14_MARK,   IDE_D15_MARK,
 540         IDE_A0_MARK,    IDE_A1_MARK,    IDE_A2_MARK,    IDE_CS0_MARK,
 541         IDE_CS1_MARK,   IDE_IOWR_MARK,  IDE_IORD_MARK,  IDE_IORDY_MARK,
 542         IDE_INT_MARK,           IDE_RST_MARK,           IDE_DIRECTION_MARK,
 543         IDE_EXBUF_ENB_MARK,     IDE_IODACK_MARK,        IDE_IODREQ_MARK,
 544
 545         /* RMII */
 546         RMII_CRS_DV_MARK,       RMII_RX_ER_MARK,        RMII_RXD0_MARK,
 547         RMII_RXD1_MARK,         RMII_TX_EN_MARK,        RMII_TXD0_MARK,
 548         RMII_MDC_MARK,          RMII_TXD1_MARK,         RMII_MDIO_MARK,
 549         RMII_REF50CK_MARK,      /* for RMII */
 550         RMII_REF125CK_MARK,     /* for GMII */
 551
 552         /* GEther */
 553         ET_TX_CLK_MARK, ET_TX_EN_MARK,  ET_ETXD0_MARK,  ET_ETXD1_MARK,
 554         ET_ETXD2_MARK,  ET_ETXD3_MARK,
 555         ET_ETXD4_MARK,  ET_ETXD5_MARK, /* for GEther */
 556         ET_ETXD6_MARK,  ET_ETXD7_MARK, /* for GEther */
 557         ET_COL_MARK,    ET_TX_ER_MARK,  ET_RX_CLK_MARK, ET_RX_DV_MARK,
 558         ET_ERXD0_MARK,  ET_ERXD1_MARK,  ET_ERXD2_MARK,  ET_ERXD3_MARK,
 559         ET_ERXD4_MARK,  ET_ERXD5_MARK, /* for GEther */
 560         ET_ERXD6_MARK,  ET_ERXD7_MARK, /* for GEther */
 561         ET_RX_ER_MARK,  ET_CRS_MARK,            ET_MDC_MARK,    ET_MDIO_MARK,
 562         ET_LINK_MARK,   ET_PHY_INT_MARK,        ET_WOL_MARK,    ET_GTX_CLK_MARK,
 563
 564         /* DMA0 */
 565         DREQ0_MARK,     DACK0_MARK,
 566
 567         /* DMA1 */
 568         DREQ1_MARK,     DACK1_MARK,
 569
 570         /* SYSC */
 571         RESETOUTS_MARK,         RESETP_PULLUP_MARK,     RESETP_PLAIN_MARK,
 572
 573         /* IRREM */
 574         IROUT_MARK,
 575
 576         /* SDENC */
 577         SDENC_CPG_MARK,         SDENC_DV_CLKI_MARK,
 578
 579         /* HDMI */
 580         HDMI_HPD_MARK, HDMI_CEC_MARK,
 581
 582         /* DEBUG */
 583         EDEBGREQ_PULLUP_MARK,   /* for JTAG */
 584         EDEBGREQ_PULLDOWN_MARK,
 585
 586         TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
 587         TRACEAUD_FROM_LCDC0_MARK,
 588         TRACEAUD_FROM_MEMC_MARK,
 589
 590         PINMUX_MARK_END,
 591 };
 592
 593 #define _PORT_DATA(pfx, sfx)    PORT_DATA_IO(pfx)
 594 #define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)
 595
 596 static const pinmux_enum_t pinmux_data[] = {
 597         PINMUX_DATA_GP_ALL(),
 598
 599         /* Port0 */
 600         PINMUX_DATA(DBGMDT2_MARK,               PORT0_FN1),
 601         PINMUX_DATA(FSIAISLD_PORT0_MARK,        PORT0_FN2,      MSEL5CR_3_0),
 602         PINMUX_DATA(FSIAOSLD1_MARK,             PORT0_FN3),
 603         PINMUX_DATA(LCD0_D22_PORT0_MARK,        PORT0_FN4,      MSEL5CR_6_0),
 604         PINMUX_DATA(SCIFA7_RXD_MARK,            PORT0_FN6),
 605         PINMUX_DATA(LCD1_D4_MARK,               PORT0_FN7),
 606         PINMUX_DATA(IRQ5_PORT0_MARK,            PORT0_FN0,      MSEL1CR_5_0),
 607
 608         /* Port1 */
 609         PINMUX_DATA(DBGMDT1_MARK,               PORT1_FN1),
 610         PINMUX_DATA(FMSISLD_PORT1_MARK,         PORT1_FN2,      MSEL5CR_5_0),
 611         PINMUX_DATA(FSIAOSLD2_MARK,             PORT1_FN3),
 612         PINMUX_DATA(LCD0_D23_PORT1_MARK,        PORT1_FN4,      MSEL5CR_6_0),
 613         PINMUX_DATA(SCIFA7_TXD_MARK,            PORT1_FN6),
 614         PINMUX_DATA(LCD1_D3_MARK,               PORT1_FN7),
 615         PINMUX_DATA(IRQ5_PORT1_MARK,            PORT1_FN0,      MSEL1CR_5_1),
 616
 617         /* Port2 */
 618         PINMUX_DATA(DBGMDT0_MARK,               PORT2_FN1),
 619         PINMUX_DATA(SCIFB_SCK_PORT2_MARK,       PORT2_FN2,      MSEL5CR_17_1),
 620         PINMUX_DATA(LCD0_D21_PORT2_MARK,        PORT2_FN4,      MSEL5CR_6_0),
 621         PINMUX_DATA(LCD1_D2_MARK,               PORT2_FN7),
 622         PINMUX_DATA(IRQ0_PORT2_MARK,            PORT2_FN0,      MSEL1CR_0_1),
 623
 624         /* Port3 */
 625         PINMUX_DATA(DBGMD21_MARK,               PORT3_FN1),
 626         PINMUX_DATA(SCIFB_RXD_PORT3_MARK,       PORT3_FN2,      MSEL5CR_17_1),
 627         PINMUX_DATA(LCD0_D20_PORT3_MARK,        PORT3_FN4,      MSEL5CR_6_0),
 628         PINMUX_DATA(LCD1_D1_MARK,               PORT3_FN7),
 629
 630         /* Port4 */
 631         PINMUX_DATA(DBGMD20_MARK,               PORT4_FN1),
 632         PINMUX_DATA(SCIFB_TXD_PORT4_MARK,       PORT4_FN2,      MSEL5CR_17_1),
 633         PINMUX_DATA(LCD0_D19_PORT4_MARK,        PORT4_FN4,      MSEL5CR_6_0),
 634         PINMUX_DATA(LCD1_D0_MARK,               PORT4_FN7),
 635
 636         /* Port5 */
 637         PINMUX_DATA(DBGMD11_MARK,               PORT5_FN1),
 638         PINMUX_DATA(BBIF2_TXD2_PORT5_MARK,      PORT5_FN2,      MSEL5CR_0_0),
 639         PINMUX_DATA(FSIAISLD_PORT5_MARK,        PORT5_FN4,      MSEL5CR_3_1),
 640         PINMUX_DATA(RSPI_SSL0_A_MARK,           PORT5_FN6),
 641         PINMUX_DATA(LCD1_VCPWC_MARK,            PORT5_FN7),
 642
 643         /* Port6 */
 644         PINMUX_DATA(DBGMD10_MARK,               PORT6_FN1),
 645         PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK,    PORT6_FN2,      MSEL5CR_0_0),
 646         PINMUX_DATA(FMSISLD_PORT6_MARK,         PORT6_FN4,      MSEL5CR_5_1),
 647         PINMUX_DATA(RSPI_SSL1_A_MARK,           PORT6_FN6),
 648         PINMUX_DATA(LCD1_VEPWC_MARK,            PORT6_FN7),
 649
 650         /* Port7 */
 651         PINMUX_DATA(FSIAOLR_MARK,               PORT7_FN1),
 652
 653         /* Port8 */
 654         PINMUX_DATA(FSIAOBT_MARK,               PORT8_FN1),
 655
 656         /* Port9 */
 657         PINMUX_DATA(FSIAOSLD_MARK,              PORT9_FN1),
 658         PINMUX_DATA(FSIASPDIF_PORT9_MARK,       PORT9_FN2,      MSEL5CR_4_0),
 659
 660         /* Port10 */
 661         PINMUX_DATA(FSIAOMC_MARK,               PORT10_FN1),
 662         PINMUX_DATA(SCIFA5_RXD_PORT10_MARK,     PORT10_FN3,     MSEL5CR_14_0,   MSEL5CR_15_0),
 663         PINMUX_DATA(IRQ3_PORT10_MARK,           PORT10_FN0,     MSEL1CR_3_0),
 664
 665         /* Port11 */
 666         PINMUX_DATA(FSIACK_MARK,                PORT11_FN1),
 667         PINMUX_DATA(FSIBCK_MARK,                PORT11_FN2),
 668         PINMUX_DATA(IRQ2_PORT11_MARK,           PORT11_FN0,     MSEL1CR_2_0),
 669
 670         /* Port12 */
 671         PINMUX_DATA(FSIAILR_MARK,               PORT12_FN1),
 672         PINMUX_DATA(SCIFA4_RXD_PORT12_MARK,     PORT12_FN2,     MSEL5CR_12_0,   MSEL5CR_11_0),
 673         PINMUX_DATA(LCD1_RS_MARK,               PORT12_FN6),
 674         PINMUX_DATA(LCD1_DISP_MARK,             PORT12_FN7),
 675         PINMUX_DATA(IRQ2_PORT12_MARK,           PORT12_FN0,     MSEL1CR_2_1),
 676
 677         /* Port13 */
 678         PINMUX_DATA(FSIAIBT_MARK,               PORT13_FN1),
 679         PINMUX_DATA(SCIFA4_TXD_PORT13_MARK,     PORT13_FN2,     MSEL5CR_12_0,   MSEL5CR_11_0),
 680         PINMUX_DATA(LCD1_RD_MARK,               PORT13_FN7),
 681         PINMUX_DATA(IRQ0_PORT13_MARK,           PORT13_FN0,     MSEL1CR_0_0),
 682
 683         /* Port14 */
 684         PINMUX_DATA(FMSOILR_MARK,               PORT14_FN1),
 685         PINMUX_DATA(FMSIILR_MARK,               PORT14_FN2),
 686         PINMUX_DATA(VIO_CKO1_MARK,              PORT14_FN3),
 687         PINMUX_DATA(LCD1_D23_MARK,              PORT14_FN7),
 688         PINMUX_DATA(IRQ3_PORT14_MARK,           PORT14_FN0,     MSEL1CR_3_1),
 689
 690         /* Port15 */
 691         PINMUX_DATA(FMSOIBT_MARK,               PORT15_FN1),
 692         PINMUX_DATA(FMSIIBT_MARK,               PORT15_FN2),
 693         PINMUX_DATA(VIO_CKO2_MARK,              PORT15_FN3),
 694         PINMUX_DATA(LCD1_D22_MARK,              PORT15_FN7),
 695         PINMUX_DATA(IRQ4_PORT15_MARK,           PORT15_FN0,     MSEL1CR_4_0),
 696
 697         /* Port16 */
 698         PINMUX_DATA(FMSOOLR_MARK,               PORT16_FN1),
 699         PINMUX_DATA(FMSIOLR_MARK,               PORT16_FN2),
 700
 701         /* Port17 */
 702         PINMUX_DATA(FMSOOBT_MARK,               PORT17_FN1),
 703         PINMUX_DATA(FMSIOBT_MARK,               PORT17_FN2),
 704
 705         /* Port18 */
 706         PINMUX_DATA(FMSOSLD_MARK,               PORT18_FN1),
 707         PINMUX_DATA(FSIASPDIF_PORT18_MARK,      PORT18_FN2,     MSEL5CR_4_1),
 708
 709         /* Port19 */
 710         PINMUX_DATA(FMSICK_MARK,                PORT19_FN1),
 711         PINMUX_DATA(CS5A_PORT19_MARK,           PORT19_FN7,     MSEL5CR_2_1),
 712         PINMUX_DATA(IRQ10_MARK,                 PORT19_FN0),
 713
 714         /* Port20 */
 715         PINMUX_DATA(FMSOCK_MARK,                PORT20_FN1),
 716         PINMUX_DATA(SCIFA5_TXD_PORT20_MARK,     PORT20_FN3,     MSEL5CR_15_0,   MSEL5CR_14_0),
 717         PINMUX_DATA(IRQ1_MARK,                  PORT20_FN0),
 718
 719         /* Port21 */
 720         PINMUX_DATA(SCIFA1_CTS_MARK,            PORT21_FN1),
 721         PINMUX_DATA(SCIFA4_SCK_PORT21_MARK,     PORT21_FN2,     MSEL5CR_10_0),
 722         PINMUX_DATA(TPU0TO1_MARK,               PORT21_FN4),
 723         PINMUX_DATA(VIO1_FIELD_MARK,            PORT21_FN5),
 724         PINMUX_DATA(STP0_IPD5_MARK,             PORT21_FN6),
 725         PINMUX_DATA(LCD1_D10_MARK,              PORT21_FN7),
 726
 727         /* Port22 */
 728         PINMUX_DATA(SCIFA2_SCK_PORT22_MARK,     PORT22_FN1,     MSEL5CR_7_0),
 729         PINMUX_DATA(SIM_D_PORT22_MARK,          PORT22_FN4,     MSEL5CR_21_0),
 730         PINMUX_DATA(VIO0_D13_PORT22_MARK,       PORT22_FN7,     MSEL5CR_27_1),
 731
 732         /* Port23 */
 733         PINMUX_DATA(SCIFA1_RTS_MARK,            PORT23_FN1),
 734         PINMUX_DATA(SCIFA5_SCK_PORT23_MARK,     PORT23_FN3,     MSEL5CR_13_0),
 735         PINMUX_DATA(TPU0TO0_MARK,               PORT23_FN4),
 736         PINMUX_DATA(VIO_CKO_1_MARK,             PORT23_FN5),
 737         PINMUX_DATA(STP0_IPD2_MARK,             PORT23_FN6),
 738         PINMUX_DATA(LCD1_D7_MARK,               PORT23_FN7),
 739
 740         /* Port24 */
 741         PINMUX_DATA(VIO0_D15_PORT24_MARK,       PORT24_FN1,     MSEL5CR_27_0),
 742         PINMUX_DATA(VIO1_D7_MARK,               PORT24_FN5),
 743         PINMUX_DATA(SCIFA6_SCK_MARK,            PORT24_FN6),
 744         PINMUX_DATA(SDHI2_CD_PORT24_MARK,       PORT24_FN7,     MSEL5CR_19_0),
 745
 746         /* Port25 */
 747         PINMUX_DATA(VIO0_D14_PORT25_MARK,       PORT25_FN1,     MSEL5CR_27_0),
 748         PINMUX_DATA(VIO1_D6_MARK,               PORT25_FN5),
 749         PINMUX_DATA(SCIFA6_RXD_MARK,            PORT25_FN6),
 750         PINMUX_DATA(SDHI2_WP_PORT25_MARK,       PORT25_FN7,     MSEL5CR_19_0),
 751
 752         /* Port26 */
 753         PINMUX_DATA(VIO0_D13_PORT26_MARK,       PORT26_FN1,     MSEL5CR_27_0),
 754         PINMUX_DATA(VIO1_D5_MARK,               PORT26_FN5),
 755         PINMUX_DATA(SCIFA6_TXD_MARK,            PORT26_FN6),
 756
 757         /* Port27 - Port39 Function */
 758         PINMUX_DATA(VIO0_D7_MARK,               PORT27_FN1),
 759         PINMUX_DATA(VIO0_D6_MARK,               PORT28_FN1),
 760         PINMUX_DATA(VIO0_D5_MARK,               PORT29_FN1),
 761         PINMUX_DATA(VIO0_D4_MARK,               PORT30_FN1),
 762         PINMUX_DATA(VIO0_D3_MARK,               PORT31_FN1),
 763         PINMUX_DATA(VIO0_D2_MARK,               PORT32_FN1),
 764         PINMUX_DATA(VIO0_D1_MARK,               PORT33_FN1),
 765         PINMUX_DATA(VIO0_D0_MARK,               PORT34_FN1),
 766         PINMUX_DATA(VIO0_CLK_MARK,              PORT35_FN1),
 767         PINMUX_DATA(VIO_CKO_MARK,               PORT36_FN1),
 768         PINMUX_DATA(VIO0_HD_MARK,               PORT37_FN1),
 769         PINMUX_DATA(VIO0_FIELD_MARK,            PORT38_FN1),
 770         PINMUX_DATA(VIO0_VD_MARK,               PORT39_FN1),
 771
 772         /* Port38 IRQ */
 773         PINMUX_DATA(IRQ25_MARK,                 PORT38_FN0),
 774
 775         /* Port40 */
 776         PINMUX_DATA(LCD0_D18_PORT40_MARK,       PORT40_FN4,     MSEL5CR_6_0),
 777         PINMUX_DATA(RSPI_CK_A_MARK,             PORT40_FN6),
 778         PINMUX_DATA(LCD1_LCLK_MARK,             PORT40_FN7),
 779
 780         /* Port41 */
 781         PINMUX_DATA(LCD0_D17_MARK,              PORT41_FN1),
 782         PINMUX_DATA(MSIOF2_SS1_MARK,            PORT41_FN2),
 783         PINMUX_DATA(IRQ31_PORT41_MARK,          PORT41_FN0,     MSEL1CR_31_1),
 784
 785         /* Port42 */
 786         PINMUX_DATA(LCD0_D16_MARK,              PORT42_FN1),
 787         PINMUX_DATA(MSIOF2_MCK1_MARK,           PORT42_FN2),
 788         PINMUX_DATA(IRQ12_PORT42_MARK,          PORT42_FN0,     MSEL1CR_12_1),
 789
 790         /* Port43 */
 791         PINMUX_DATA(LCD0_D15_MARK,              PORT43_FN1),
 792         PINMUX_DATA(MSIOF2_MCK0_MARK,           PORT43_FN2),
 793         PINMUX_DATA(KEYIN0_PORT43_MARK,         PORT43_FN3,     MSEL4CR_18_0),
 794         PINMUX_DATA(DV_D15_MARK,                PORT43_FN6),
 795
 796         /* Port44 */
 797         PINMUX_DATA(LCD0_D14_MARK,              PORT44_FN1),
 798         PINMUX_DATA(MSIOF2_RSYNC_MARK,          PORT44_FN2),
 799         PINMUX_DATA(KEYIN1_PORT44_MARK,         PORT44_FN3,     MSEL4CR_18_0),
 800         PINMUX_DATA(DV_D14_MARK,                PORT44_FN6),
 801
 802         /* Port45 */
 803         PINMUX_DATA(LCD0_D13_MARK,              PORT45_FN1),
 804         PINMUX_DATA(MSIOF2_RSCK_MARK,           PORT45_FN2),
 805         PINMUX_DATA(KEYIN2_PORT45_MARK,         PORT45_FN3,     MSEL4CR_18_0),
 806         PINMUX_DATA(DV_D13_MARK,                PORT45_FN6),
 807
 808         /* Port46 */
 809         PINMUX_DATA(LCD0_D12_MARK,              PORT46_FN1),
 810         PINMUX_DATA(KEYIN3_PORT46_MARK,         PORT46_FN3,     MSEL4CR_18_0),
 811         PINMUX_DATA(DV_D12_MARK,                PORT46_FN6),
 812
 813         /* Port47 */
 814         PINMUX_DATA(LCD0_D11_MARK,              PORT47_FN1),
 815         PINMUX_DATA(KEYIN4_MARK,                PORT47_FN3),
 816         PINMUX_DATA(DV_D11_MARK,                PORT47_FN6),
 817
 818         /* Port48 */
 819         PINMUX_DATA(LCD0_D10_MARK,              PORT48_FN1),
 820         PINMUX_DATA(KEYIN5_MARK,                PORT48_FN3),
 821         PINMUX_DATA(DV_D10_MARK,                PORT48_FN6),
 822
 823         /* Port49 */
 824         PINMUX_DATA(LCD0_D9_MARK,               PORT49_FN1),
 825         PINMUX_DATA(KEYIN6_MARK,                PORT49_FN3),
 826         PINMUX_DATA(DV_D9_MARK,                 PORT49_FN6),
 827         PINMUX_DATA(IRQ30_PORT49_MARK,          PORT49_FN0,     MSEL1CR_30_1),
 828
 829         /* Port50 */
 830         PINMUX_DATA(LCD0_D8_MARK,               PORT50_FN1),
 831         PINMUX_DATA(KEYIN7_MARK,                PORT50_FN3),
 832         PINMUX_DATA(DV_D8_MARK,                 PORT50_FN6),
 833         PINMUX_DATA(IRQ29_PORT50_MARK,          PORT50_FN0,     MSEL1CR_29_1),
 834
 835         /* Port51 */
 836         PINMUX_DATA(LCD0_D7_MARK,               PORT51_FN1),
 837         PINMUX_DATA(KEYOUT0_MARK,               PORT51_FN3),
 838         PINMUX_DATA(DV_D7_MARK,                 PORT51_FN6),
 839
 840         /* Port52 */
 841         PINMUX_DATA(LCD0_D6_MARK,               PORT52_FN1),
 842         PINMUX_DATA(KEYOUT1_MARK,               PORT52_FN3),
 843         PINMUX_DATA(DV_D6_MARK,                 PORT52_FN6),
 844
 845         /* Port53 */
 846         PINMUX_DATA(LCD0_D5_MARK,               PORT53_FN1),
 847         PINMUX_DATA(KEYOUT2_MARK,               PORT53_FN3),
 848         PINMUX_DATA(DV_D5_MARK,                 PORT53_FN6),
 849
 850         /* Port54 */
 851         PINMUX_DATA(LCD0_D4_MARK,               PORT54_FN1),
 852         PINMUX_DATA(KEYOUT3_MARK,               PORT54_FN3),
 853         PINMUX_DATA(DV_D4_MARK,                 PORT54_FN6),
 854
 855         /* Port55 */
 856         PINMUX_DATA(LCD0_D3_MARK,               PORT55_FN1),
 857         PINMUX_DATA(KEYOUT4_MARK,               PORT55_FN3),
 858         PINMUX_DATA(KEYIN3_PORT55_MARK,         PORT55_FN4,     MSEL4CR_18_1),
 859         PINMUX_DATA(DV_D3_MARK,                 PORT55_FN6),
 860
 861         /* Port56 */
 862         PINMUX_DATA(LCD0_D2_MARK,               PORT56_FN1),
 863         PINMUX_DATA(KEYOUT5_MARK,               PORT56_FN3),
 864         PINMUX_DATA(KEYIN2_PORT56_MARK,         PORT56_FN4,     MSEL4CR_18_1),
 865         PINMUX_DATA(DV_D2_MARK,                 PORT56_FN6),
 866         PINMUX_DATA(IRQ28_PORT56_MARK,          PORT56_FN0,     MSEL1CR_28_1),
 867
 868         /* Port57 */
 869         PINMUX_DATA(LCD0_D1_MARK,               PORT57_FN1),
 870         PINMUX_DATA(KEYOUT6_MARK,               PORT57_FN3),
 871         PINMUX_DATA(KEYIN1_PORT57_MARK,         PORT57_FN4,     MSEL4CR_18_1),
 872         PINMUX_DATA(DV_D1_MARK,                 PORT57_FN6),
 873         PINMUX_DATA(IRQ27_PORT57_MARK,          PORT57_FN0,     MSEL1CR_27_1),
 874
 875         /* Port58 */
 876         PINMUX_DATA(LCD0_D0_MARK,               PORT58_FN1,     MSEL3CR_6_0),
 877         PINMUX_DATA(KEYOUT7_MARK,               PORT58_FN3),
 878         PINMUX_DATA(KEYIN0_PORT58_MARK,         PORT58_FN4,     MSEL4CR_18_1),
 879         PINMUX_DATA(DV_D0_MARK,                 PORT58_FN6),
 880         PINMUX_DATA(IRQ26_PORT58_MARK,          PORT58_FN0,     MSEL1CR_26_1),
 881
 882         /* Port59 */
 883         PINMUX_DATA(LCD0_VCPWC_MARK,            PORT59_FN1),
 884         PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK,    PORT59_FN2,     MSEL5CR_0_0),
 885         PINMUX_DATA(RSPI_MOSI_A_MARK,           PORT59_FN6),
 886
 887         /* Port60 */
 888         PINMUX_DATA(LCD0_VEPWC_MARK,            PORT60_FN1),
 889         PINMUX_DATA(BBIF2_RXD2_PORT60_MARK,     PORT60_FN2,     MSEL5CR_0_0),
 890         PINMUX_DATA(RSPI_MISO_A_MARK,           PORT60_FN6),
 891
 892         /* Port61 */
 893         PINMUX_DATA(LCD0_DON_MARK,              PORT61_FN1),
 894         PINMUX_DATA(MSIOF2_TXD_MARK,            PORT61_FN2),
 895
 896         /* Port62 */
 897         PINMUX_DATA(LCD0_DCK_MARK,              PORT62_FN1),
 898         PINMUX_DATA(LCD0_WR_MARK,               PORT62_FN4),
 899         PINMUX_DATA(DV_CLK_MARK,                PORT62_FN6),
 900         PINMUX_DATA(IRQ15_PORT62_MARK,          PORT62_FN0,     MSEL1CR_15_1),
 901
 902         /* Port63 */
 903         PINMUX_DATA(LCD0_VSYN_MARK,             PORT63_FN1),
 904         PINMUX_DATA(DV_VSYNC_MARK,              PORT63_FN6),
 905         PINMUX_DATA(IRQ14_PORT63_MARK,          PORT63_FN0,     MSEL1CR_14_1),
 906
 907         /* Port64 */
 908         PINMUX_DATA(LCD0_HSYN_MARK,             PORT64_FN1),
 909         PINMUX_DATA(LCD0_CS_MARK,               PORT64_FN4),
 910         PINMUX_DATA(DV_HSYNC_MARK,              PORT64_FN6),
 911         PINMUX_DATA(IRQ13_PORT64_MARK,          PORT64_FN0,     MSEL1CR_13_1),
 912
 913         /* Port65 */
 914         PINMUX_DATA(LCD0_DISP_MARK,             PORT65_FN1),
 915         PINMUX_DATA(MSIOF2_TSCK_MARK,           PORT65_FN2),
 916         PINMUX_DATA(LCD0_RS_MARK,               PORT65_FN4),
 917
 918         /* Port66 */
 919         PINMUX_DATA(MEMC_INT_MARK,              PORT66_FN1),
 920         PINMUX_DATA(TPU0TO2_PORT66_MARK,        PORT66_FN3,     MSEL5CR_25_0),
 921         PINMUX_DATA(MMC0_CLK_PORT66_MARK,       PORT66_FN4,     MSEL4CR_15_0),
 922         PINMUX_DATA(SDHI1_CLK_MARK,             PORT66_FN6),
 923
 924         /* Port67 - Port73 Function1 */
 925         PINMUX_DATA(MEMC_CS0_MARK,              PORT67_FN1),
 926         PINMUX_DATA(MEMC_AD8_MARK,              PORT68_FN1),
 927         PINMUX_DATA(MEMC_AD9_MARK,              PORT69_FN1),
 928         PINMUX_DATA(MEMC_AD10_MARK,             PORT70_FN1),
 929         PINMUX_DATA(MEMC_AD11_MARK,             PORT71_FN1),
 930         PINMUX_DATA(MEMC_AD12_MARK,             PORT72_FN1),
 931         PINMUX_DATA(MEMC_AD13_MARK,             PORT73_FN1),
 932
 933         /* Port67 - Port73 Function2 */
 934         PINMUX_DATA(MSIOF1_SS1_PORT67_MARK,     PORT67_FN2,     MSEL4CR_10_1),
 935         PINMUX_DATA(MSIOF1_RSCK_MARK,           PORT68_FN2),
 936         PINMUX_DATA(MSIOF1_RSYNC_MARK,          PORT69_FN2),
 937         PINMUX_DATA(MSIOF1_MCK0_MARK,           PORT70_FN2),
 938         PINMUX_DATA(MSIOF1_MCK1_MARK,           PORT71_FN2),
 939         PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK,    PORT72_FN2,     MSEL4CR_10_1),
 940         PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK,   PORT73_FN2,     MSEL4CR_10_1),
 941
 942         /* Port67 - Port73 Function4 */
 943         PINMUX_DATA(MMC0_CMD_PORT67_MARK,       PORT67_FN4,     MSEL4CR_15_0),
 944         PINMUX_DATA(MMC0_D0_PORT68_MARK,        PORT68_FN4,     MSEL4CR_15_0),
 945         PINMUX_DATA(MMC0_D1_PORT69_MARK,        PORT69_FN4,     MSEL4CR_15_0),
 946         PINMUX_DATA(MMC0_D2_PORT70_MARK,        PORT70_FN4,     MSEL4CR_15_0),
 947         PINMUX_DATA(MMC0_D3_PORT71_MARK,        PORT71_FN4,     MSEL4CR_15_0),
 948         PINMUX_DATA(MMC0_D4_PORT72_MARK,        PORT72_FN4,     MSEL4CR_15_0),
 949         PINMUX_DATA(MMC0_D5_PORT73_MARK,        PORT73_FN4,     MSEL4CR_15_0),
 950
 951         /* Port67 - Port73 Function6 */
 952         PINMUX_DATA(SDHI1_CMD_MARK,             PORT67_FN6),
 953         PINMUX_DATA(SDHI1_D0_MARK,              PORT68_FN6),
 954         PINMUX_DATA(SDHI1_D1_MARK,              PORT69_FN6),
 955         PINMUX_DATA(SDHI1_D2_MARK,              PORT70_FN6),
 956         PINMUX_DATA(SDHI1_D3_MARK,              PORT71_FN6),
 957         PINMUX_DATA(SDHI1_CD_MARK,              PORT72_FN6),
 958         PINMUX_DATA(SDHI1_WP_MARK,              PORT73_FN6),
 959
 960         /* Port67 - Port71 IRQ */
 961         PINMUX_DATA(IRQ20_MARK,                 PORT67_FN0),
 962         PINMUX_DATA(IRQ16_PORT68_MARK,          PORT68_FN0,     MSEL1CR_16_0),
 963         PINMUX_DATA(IRQ17_MARK,                 PORT69_FN0),
 964         PINMUX_DATA(IRQ18_MARK,                 PORT70_FN0),
 965         PINMUX_DATA(IRQ19_MARK,                 PORT71_FN0),
 966
 967         /* Port74 */
 968         PINMUX_DATA(MEMC_AD14_MARK,             PORT74_FN1),
 969         PINMUX_DATA(MSIOF1_TXD_PORT74_MARK,     PORT74_FN2,     MSEL4CR_10_1),
 970         PINMUX_DATA(MMC0_D6_PORT74_MARK,        PORT74_FN4,     MSEL4CR_15_0),
 971         PINMUX_DATA(STP1_IPD7_MARK,             PORT74_FN6),
 972         PINMUX_DATA(LCD1_D21_MARK,              PORT74_FN7),
 973
 974         /* Port75 */
 975         PINMUX_DATA(MEMC_AD15_MARK,             PORT75_FN1),
 976         PINMUX_DATA(MSIOF1_RXD_PORT75_MARK,     PORT75_FN2,     MSEL4CR_10_1),
 977         PINMUX_DATA(MMC0_D7_PORT75_MARK,        PORT75_FN4,     MSEL4CR_15_0),
 978         PINMUX_DATA(STP1_IPD6_MARK,             PORT75_FN6),
 979         PINMUX_DATA(LCD1_D20_MARK,              PORT75_FN7),
 980
 981         /* Port76 - Port80 Function */
 982         PINMUX_DATA(SDHI0_CMD_MARK,             PORT76_FN1),
 983         PINMUX_DATA(SDHI0_D0_MARK,              PORT77_FN1),
 984         PINMUX_DATA(SDHI0_D1_MARK,              PORT78_FN1),
 985         PINMUX_DATA(SDHI0_D2_MARK,              PORT79_FN1),
 986         PINMUX_DATA(SDHI0_D3_MARK,              PORT80_FN1),
 987
 988         /* Port81 */
 989         PINMUX_DATA(SDHI0_CD_MARK,              PORT81_FN1),
 990         PINMUX_DATA(IRQ26_PORT81_MARK,          PORT81_FN0,     MSEL1CR_26_0),
 991
 992         /* Port82 - Port88 Function */
 993         PINMUX_DATA(SDHI0_CLK_MARK,             PORT82_FN1),
 994         PINMUX_DATA(SDHI0_WP_MARK,              PORT83_FN1),
 995         PINMUX_DATA(RESETOUTS_MARK,             PORT84_FN1),
 996         PINMUX_DATA(USB0_PPON_MARK,             PORT85_FN1),
 997         PINMUX_DATA(USB0_OCI_MARK,              PORT86_FN1),
 998         PINMUX_DATA(USB1_PPON_MARK,             PORT87_FN1),
 999         PINMUX_DATA(USB1_OCI_MARK,              PORT88_FN1),
1000
1001         /* Port89 */
1002         PINMUX_DATA(DREQ0_MARK,                 PORT89_FN1),
1003         PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK,    PORT89_FN2,     MSEL5CR_0_1),
1004         PINMUX_DATA(RSPI_SSL3_A_MARK,           PORT89_FN6),
1005
1006         /* Port90 */
1007         PINMUX_DATA(DACK0_MARK,                 PORT90_FN1),
1008         PINMUX_DATA(BBIF2_RXD2_PORT90_MARK,     PORT90_FN2,     MSEL5CR_0_1),
1009         PINMUX_DATA(RSPI_SSL2_A_MARK,           PORT90_FN6),
1010         PINMUX_DATA(WAIT_PORT90_MARK,           PORT90_FN7,     MSEL5CR_2_1),
1011
1012         /* Port91 */
1013         PINMUX_DATA(MEMC_AD0_MARK,              PORT91_FN1),
1014         PINMUX_DATA(BBIF1_RXD_MARK,             PORT91_FN2),
1015         PINMUX_DATA(SCIFA5_TXD_PORT91_MARK,     PORT91_FN3,     MSEL5CR_15_1,   MSEL5CR_14_0),
1016         PINMUX_DATA(LCD1_D5_MARK,               PORT91_FN7),
1017
1018         /* Port92 */
1019         PINMUX_DATA(MEMC_AD1_MARK,              PORT92_FN1),
1020         PINMUX_DATA(BBIF1_TSYNC_MARK,           PORT92_FN2),
1021         PINMUX_DATA(SCIFA5_RXD_PORT92_MARK,     PORT92_FN3,     MSEL5CR_15_1,   MSEL5CR_14_0),
1022         PINMUX_DATA(STP0_IPD1_MARK,             PORT92_FN6),
1023         PINMUX_DATA(LCD1_D6_MARK,               PORT92_FN7),
1024
1025         /* Port93 */
1026         PINMUX_DATA(MEMC_AD2_MARK,              PORT93_FN1),
1027         PINMUX_DATA(BBIF1_TSCK_MARK,            PORT93_FN2),
1028         PINMUX_DATA(SCIFA4_TXD_PORT93_MARK,     PORT93_FN3,     MSEL5CR_12_1,   MSEL5CR_11_0),
1029         PINMUX_DATA(STP0_IPD3_MARK,             PORT93_FN6),
1030         PINMUX_DATA(LCD1_D8_MARK,               PORT93_FN7),
1031
1032         /* Port94 */
1033         PINMUX_DATA(MEMC_AD3_MARK,              PORT94_FN1),
1034         PINMUX_DATA(BBIF1_TXD_MARK,             PORT94_FN2),
1035         PINMUX_DATA(SCIFA4_RXD_PORT94_MARK,     PORT94_FN3,     MSEL5CR_12_1,   MSEL5CR_11_0),
1036         PINMUX_DATA(STP0_IPD4_MARK,             PORT94_FN6),
1037         PINMUX_DATA(LCD1_D9_MARK,               PORT94_FN7),
1038
1039         /* Port95 */
1040         PINMUX_DATA(MEMC_CS1_MARK,              PORT95_FN1,     MSEL4CR_6_0),
1041         PINMUX_DATA(MEMC_A1_MARK,               PORT95_FN1,     MSEL4CR_6_1),
1042
1043         PINMUX_DATA(SCIFA2_CTS_MARK,            PORT95_FN2),
1044         PINMUX_DATA(SIM_RST_MARK,               PORT95_FN4),
1045         PINMUX_DATA(VIO0_D14_PORT95_MARK,       PORT95_FN7,     MSEL5CR_27_1),
1046         PINMUX_DATA(IRQ22_MARK,                 PORT95_FN0),
1047
1048         /* Port96 */
1049         PINMUX_DATA(MEMC_ADV_MARK,              PORT96_FN1,     MSEL4CR_6_0),
1050         PINMUX_DATA(MEMC_DREQ0_MARK,            PORT96_FN1,     MSEL4CR_6_1),
1051
1052         PINMUX_DATA(SCIFA2_RTS_MARK,            PORT96_FN2),
1053         PINMUX_DATA(SIM_CLK_MARK,               PORT96_FN4),
1054         PINMUX_DATA(VIO0_D15_PORT96_MARK,       PORT96_FN7,     MSEL5CR_27_1),
1055         PINMUX_DATA(IRQ23_MARK,                 PORT96_FN0),
1056
1057         /* Port97 */
1058         PINMUX_DATA(MEMC_AD4_MARK,              PORT97_FN1),
1059         PINMUX_DATA(BBIF1_RSCK_MARK,            PORT97_FN2),
1060         PINMUX_DATA(LCD1_CS_MARK,               PORT97_FN6),
1061         PINMUX_DATA(LCD1_HSYN_MARK,             PORT97_FN7),
1062         PINMUX_DATA(IRQ12_PORT97_MARK,          PORT97_FN0,     MSEL1CR_12_0),
1063
1064         /* Port98 */
1065         PINMUX_DATA(MEMC_AD5_MARK,              PORT98_FN1),
1066         PINMUX_DATA(BBIF1_RSYNC_MARK,           PORT98_FN2),
1067         PINMUX_DATA(LCD1_VSYN_MARK,             PORT98_FN7),
1068         PINMUX_DATA(IRQ13_PORT98_MARK,          PORT98_FN0,     MSEL1CR_13_0),
1069
1070         /* Port99 */
1071         PINMUX_DATA(MEMC_AD6_MARK,              PORT99_FN1),
1072         PINMUX_DATA(BBIF1_FLOW_MARK,            PORT99_FN2),
1073         PINMUX_DATA(LCD1_WR_MARK,               PORT99_FN6),
1074         PINMUX_DATA(LCD1_DCK_MARK,              PORT99_FN7),
1075         PINMUX_DATA(IRQ14_PORT99_MARK,          PORT99_FN0,     MSEL1CR_14_0),
1076
1077         /* Port100 */
1078         PINMUX_DATA(MEMC_AD7_MARK,              PORT100_FN1),
1079         PINMUX_DATA(BBIF1_RX_FLOW_N_MARK,       PORT100_FN2),
1080         PINMUX_DATA(LCD1_DON_MARK,              PORT100_FN7),
1081         PINMUX_DATA(IRQ15_PORT100_MARK,         PORT100_FN0,    MSEL1CR_15_0),
1082
1083         /* Port101 */
1084         PINMUX_DATA(FCE0_MARK,                  PORT101_FN1),
1085
1086         /* Port102 */
1087         PINMUX_DATA(FRB_MARK,                   PORT102_FN1),
1088         PINMUX_DATA(LCD0_LCLK_PORT102_MARK,     PORT102_FN4,    MSEL5CR_6_0),
1089
1090         /* Port103 */
1091         PINMUX_DATA(CS5B_MARK,                  PORT103_FN1),
1092         PINMUX_DATA(FCE1_MARK,                  PORT103_FN2),
1093         PINMUX_DATA(MMC1_CLK_PORT103_MARK,      PORT103_FN3,    MSEL4CR_15_1),
1094
1095         /* Port104 */
1096         PINMUX_DATA(CS6A_MARK,                  PORT104_FN1),
1097         PINMUX_DATA(MMC1_CMD_PORT104_MARK,      PORT104_FN3,    MSEL4CR_15_1),
1098         PINMUX_DATA(IRQ11_MARK,                 PORT104_FN0),
1099
1100         /* Port105 */
1101         PINMUX_DATA(CS5A_PORT105_MARK,          PORT105_FN1,    MSEL5CR_2_0),
1102         PINMUX_DATA(SCIFA3_RTS_PORT105_MARK,    PORT105_FN4,    MSEL5CR_8_0),
1103
1104         /* Port106 */
1105         PINMUX_DATA(IOIS16_MARK,                PORT106_FN1),
1106         PINMUX_DATA(IDE_EXBUF_ENB_MARK,         PORT106_FN6),
1107
1108         /* Port107 - Port115 Function */
1109         PINMUX_DATA(WE3_ICIOWR_MARK,            PORT107_FN1),
1110         PINMUX_DATA(WE2_ICIORD_MARK,            PORT108_FN1),
1111         PINMUX_DATA(CS0_MARK,                   PORT109_FN1),
1112         PINMUX_DATA(CS2_MARK,                   PORT110_FN1),
1113         PINMUX_DATA(CS4_MARK,                   PORT111_FN1),
1114         PINMUX_DATA(WE1_MARK,                   PORT112_FN1),
1115         PINMUX_DATA(WE0_FWE_MARK,               PORT113_FN1),
1116         PINMUX_DATA(RDWR_MARK,                  PORT114_FN1),
1117         PINMUX_DATA(RD_FSC_MARK,                PORT115_FN1),
1118
1119         /* Port116 */
1120         PINMUX_DATA(A25_MARK,                   PORT116_FN1),
1121         PINMUX_DATA(MSIOF0_SS2_MARK,            PORT116_FN2),
1122         PINMUX_DATA(MSIOF1_SS2_PORT116_MARK,    PORT116_FN3,    MSEL4CR_10_0),
1123         PINMUX_DATA(SCIFA3_SCK_PORT116_MARK,    PORT116_FN4,    MSEL5CR_8_0),
1124         PINMUX_DATA(GPO1_MARK,                  PORT116_FN5),
1125
1126         /* Port117 */
1127         PINMUX_DATA(A24_MARK,                   PORT117_FN1),
1128         PINMUX_DATA(MSIOF0_SS1_MARK,            PORT117_FN2),
1129         PINMUX_DATA(MSIOF1_SS1_PORT117_MARK,    PORT117_FN3,    MSEL4CR_10_0),
1130         PINMUX_DATA(SCIFA3_CTS_PORT117_MARK,    PORT117_FN4,    MSEL5CR_8_0),
1131         PINMUX_DATA(GPO0_MARK,                  PORT117_FN5),
1132
1133         /* Port118 */
1134         PINMUX_DATA(A23_MARK,                   PORT118_FN1),
1135         PINMUX_DATA(MSIOF0_MCK1_MARK,           PORT118_FN2),
1136         PINMUX_DATA(MSIOF1_RXD_PORT118_MARK,    PORT118_FN3,    MSEL4CR_10_0),
1137         PINMUX_DATA(GPI1_MARK,                  PORT118_FN5),
1138         PINMUX_DATA(IRQ9_PORT118_MARK,          PORT118_FN0,    MSEL1CR_9_0),
1139
1140         /* Port119 */
1141         PINMUX_DATA(A22_MARK,                   PORT119_FN1),
1142         PINMUX_DATA(MSIOF0_MCK0_MARK,           PORT119_FN2),
1143         PINMUX_DATA(MSIOF1_TXD_PORT119_MARK,    PORT119_FN3,    MSEL4CR_10_0),
1144         PINMUX_DATA(GPI0_MARK,                  PORT119_FN5),
1145         PINMUX_DATA(IRQ8_MARK,                  PORT119_FN0),
1146
1147         /* Port120 */
1148         PINMUX_DATA(A21_MARK,                   PORT120_FN1),
1149         PINMUX_DATA(MSIOF0_RSYNC_MARK,          PORT120_FN2),
1150         PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK,  PORT120_FN3,    MSEL4CR_10_0),
1151         PINMUX_DATA(IRQ7_PORT120_MARK,          PORT120_FN0,    MSEL1CR_7_1),
1152
1153         /* Port121 */
1154         PINMUX_DATA(A20_MARK,                   PORT121_FN1),
1155         PINMUX_DATA(MSIOF0_RSCK_MARK,           PORT121_FN2),
1156         PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK,   PORT121_FN3,    MSEL4CR_10_0),
1157         PINMUX_DATA(IRQ6_PORT121_MARK,          PORT121_FN0,    MSEL1CR_6_0),
1158
1159         /* Port122 */
1160         PINMUX_DATA(A19_MARK,                   PORT122_FN1),
1161         PINMUX_DATA(MSIOF0_RXD_MARK,            PORT122_FN2),
1162
1163         /* Port123 */
1164         PINMUX_DATA(A18_MARK,                   PORT123_FN1),
1165         PINMUX_DATA(MSIOF0_TSCK_MARK,           PORT123_FN2),
1166
1167         /* Port124 */
1168         PINMUX_DATA(A17_MARK,                   PORT124_FN1),
1169         PINMUX_DATA(MSIOF0_TSYNC_MARK,          PORT124_FN2),
1170
1171         /* Port125 - Port141 Function */
1172         PINMUX_DATA(A16_MARK,                   PORT125_FN1),
1173         PINMUX_DATA(A15_MARK,                   PORT126_FN1),
1174         PINMUX_DATA(A14_MARK,                   PORT127_FN1),
1175         PINMUX_DATA(A13_MARK,                   PORT128_FN1),
1176         PINMUX_DATA(A12_MARK,                   PORT129_FN1),
1177         PINMUX_DATA(A11_MARK,                   PORT130_FN1),
1178         PINMUX_DATA(A10_MARK,                   PORT131_FN1),
1179         PINMUX_DATA(A9_MARK,                    PORT132_FN1),
1180         PINMUX_DATA(A8_MARK,                    PORT133_FN1),
1181         PINMUX_DATA(A7_MARK,                    PORT134_FN1),
1182         PINMUX_DATA(A6_MARK,                    PORT135_FN1),
1183         PINMUX_DATA(A5_FCDE_MARK,               PORT136_FN1),
1184         PINMUX_DATA(A4_FOE_MARK,                PORT137_FN1),
1185         PINMUX_DATA(A3_MARK,                    PORT138_FN1),
1186         PINMUX_DATA(A2_MARK,                    PORT139_FN1),
1187         PINMUX_DATA(A1_MARK,                    PORT140_FN1),
1188         PINMUX_DATA(CKO_MARK,                   PORT141_FN1),
1189
1190         /* Port142 - Port157 Function1 */
1191         PINMUX_DATA(D15_NAF15_MARK,             PORT142_FN1),
1192         PINMUX_DATA(D14_NAF14_MARK,             PORT143_FN1),
1193         PINMUX_DATA(D13_NAF13_MARK,             PORT144_FN1),
1194         PINMUX_DATA(D12_NAF12_MARK,             PORT145_FN1),
1195         PINMUX_DATA(D11_NAF11_MARK,             PORT146_FN1),
1196         PINMUX_DATA(D10_NAF10_MARK,             PORT147_FN1),
1197         PINMUX_DATA(D9_NAF9_MARK,               PORT148_FN1),
1198         PINMUX_DATA(D8_NAF8_MARK,               PORT149_FN1),
1199         PINMUX_DATA(D7_NAF7_MARK,               PORT150_FN1),
1200         PINMUX_DATA(D6_NAF6_MARK,               PORT151_FN1),
1201         PINMUX_DATA(D5_NAF5_MARK,               PORT152_FN1),
1202         PINMUX_DATA(D4_NAF4_MARK,               PORT153_FN1),
1203         PINMUX_DATA(D3_NAF3_MARK,               PORT154_FN1),
1204         PINMUX_DATA(D2_NAF2_MARK,               PORT155_FN1),
1205         PINMUX_DATA(D1_NAF1_MARK,               PORT156_FN1),
1206         PINMUX_DATA(D0_NAF0_MARK,               PORT157_FN1),
1207
1208         /* Port142 - Port149 Function3 */
1209         PINMUX_DATA(MMC1_D7_PORT142_MARK,       PORT142_FN3,    MSEL4CR_15_1),
1210         PINMUX_DATA(MMC1_D6_PORT143_MARK,       PORT143_FN3,    MSEL4CR_15_1),
1211         PINMUX_DATA(MMC1_D5_PORT144_MARK,       PORT144_FN3,    MSEL4CR_15_1),
1212         PINMUX_DATA(MMC1_D4_PORT145_MARK,       PORT145_FN3,    MSEL4CR_15_1),
1213         PINMUX_DATA(MMC1_D3_PORT146_MARK,       PORT146_FN3,    MSEL4CR_15_1),
1214         PINMUX_DATA(MMC1_D2_PORT147_MARK,       PORT147_FN3,    MSEL4CR_15_1),
1215         PINMUX_DATA(MMC1_D1_PORT148_MARK,       PORT148_FN3,    MSEL4CR_15_1),
1216         PINMUX_DATA(MMC1_D0_PORT149_MARK,       PORT149_FN3,    MSEL4CR_15_1),
1217
1218         /* Port158 */
1219         PINMUX_DATA(D31_MARK,                   PORT158_FN1),
1220         PINMUX_DATA(SCIFA3_SCK_PORT158_MARK,    PORT158_FN2,    MSEL5CR_8_1),
1221         PINMUX_DATA(RMII_REF125CK_MARK,         PORT158_FN3),
1222         PINMUX_DATA(LCD0_D21_PORT158_MARK,      PORT158_FN4,    MSEL5CR_6_1),
1223         PINMUX_DATA(IRDA_FIRSEL_MARK,           PORT158_FN5),
1224         PINMUX_DATA(IDE_D15_MARK,               PORT158_FN6),
1225
1226         /* Port159 */
1227         PINMUX_DATA(D30_MARK,                   PORT159_FN1),
1228         PINMUX_DATA(SCIFA3_RXD_PORT159_MARK,    PORT159_FN2,    MSEL5CR_8_1),
1229         PINMUX_DATA(RMII_REF50CK_MARK,          PORT159_FN3),
1230         PINMUX_DATA(LCD0_D23_PORT159_MARK,      PORT159_FN4,    MSEL5CR_6_1),
1231         PINMUX_DATA(IDE_D14_MARK,               PORT159_FN6),
1232
1233         /* Port160 */
1234         PINMUX_DATA(D29_MARK,                   PORT160_FN1),
1235         PINMUX_DATA(SCIFA3_TXD_PORT160_MARK,    PORT160_FN2,    MSEL5CR_8_1),
1236         PINMUX_DATA(LCD0_D22_PORT160_MARK,      PORT160_FN4,    MSEL5CR_6_1),
1237         PINMUX_DATA(VIO1_HD_MARK,               PORT160_FN5),
1238         PINMUX_DATA(IDE_D13_MARK,               PORT160_FN6),
1239
1240         /* Port161 */
1241         PINMUX_DATA(D28_MARK,                   PORT161_FN1),
1242         PINMUX_DATA(SCIFA3_RTS_PORT161_MARK,    PORT161_FN2,    MSEL5CR_8_1),
1243         PINMUX_DATA(ET_RX_DV_MARK,              PORT161_FN3),
1244         PINMUX_DATA(LCD0_D20_PORT161_MARK,      PORT161_FN4,    MSEL5CR_6_1),
1245         PINMUX_DATA(IRDA_IN_MARK,               PORT161_FN5),
1246         PINMUX_DATA(IDE_D12_MARK,               PORT161_FN6),
1247
1248         /* Port162 */
1249         PINMUX_DATA(D27_MARK,                   PORT162_FN1),
1250         PINMUX_DATA(SCIFA3_CTS_PORT162_MARK,    PORT162_FN2,    MSEL5CR_8_1),
1251         PINMUX_DATA(LCD0_D19_PORT162_MARK,      PORT162_FN4,    MSEL5CR_6_1),
1252         PINMUX_DATA(IRDA_OUT_MARK,              PORT162_FN5),
1253         PINMUX_DATA(IDE_D11_MARK,               PORT162_FN6),
1254
1255         /* Port163 */
1256         PINMUX_DATA(D26_MARK,                   PORT163_FN1),
1257         PINMUX_DATA(MSIOF2_SS2_MARK,            PORT163_FN2),
1258         PINMUX_DATA(ET_COL_MARK,                PORT163_FN3),
1259         PINMUX_DATA(LCD0_D18_PORT163_MARK,      PORT163_FN4,    MSEL5CR_6_1),
1260         PINMUX_DATA(IROUT_MARK,                 PORT163_FN5),
1261         PINMUX_DATA(IDE_D10_MARK,               PORT163_FN6),
1262
1263         /* Port164 */
1264         PINMUX_DATA(D25_MARK,                   PORT164_FN1),
1265         PINMUX_DATA(MSIOF2_TSYNC_MARK,          PORT164_FN2),
1266         PINMUX_DATA(ET_PHY_INT_MARK,            PORT164_FN3),
1267         PINMUX_DATA(LCD0_RD_MARK,               PORT164_FN4),
1268         PINMUX_DATA(IDE_D9_MARK,                PORT164_FN6),
1269
1270         /* Port165 */
1271         PINMUX_DATA(D24_MARK,                   PORT165_FN1),
1272         PINMUX_DATA(MSIOF2_RXD_MARK,            PORT165_FN2),
1273         PINMUX_DATA(LCD0_LCLK_PORT165_MARK,     PORT165_FN4,    MSEL5CR_6_1),
1274         PINMUX_DATA(IDE_D8_MARK,                PORT165_FN6),
1275
1276         /* Port166 - Port171 Function1 */
1277         PINMUX_DATA(D21_MARK,                   PORT166_FN1),
1278         PINMUX_DATA(D20_MARK,                   PORT167_FN1),
1279         PINMUX_DATA(D19_MARK,                   PORT168_FN1),
1280         PINMUX_DATA(D18_MARK,                   PORT169_FN1),
1281         PINMUX_DATA(D17_MARK,                   PORT170_FN1),
1282         PINMUX_DATA(D16_MARK,                   PORT171_FN1),
1283
1284         /* Port166 - Port171 Function3 */
1285         PINMUX_DATA(ET_ETXD5_MARK,              PORT166_FN3),
1286         PINMUX_DATA(ET_ETXD4_MARK,              PORT167_FN3),
1287         PINMUX_DATA(ET_ETXD3_MARK,              PORT168_FN3),
1288         PINMUX_DATA(ET_ETXD2_MARK,              PORT169_FN3),
1289         PINMUX_DATA(ET_ETXD1_MARK,              PORT170_FN3),
1290         PINMUX_DATA(ET_ETXD0_MARK,              PORT171_FN3),
1291
1292         /* Port166 - Port171 Function6 */
1293         PINMUX_DATA(IDE_D5_MARK,                PORT166_FN6),
1294         PINMUX_DATA(IDE_D4_MARK,                PORT167_FN6),
1295         PINMUX_DATA(IDE_D3_MARK,                PORT168_FN6),
1296         PINMUX_DATA(IDE_D2_MARK,                PORT169_FN6),
1297         PINMUX_DATA(IDE_D1_MARK,                PORT170_FN6),
1298         PINMUX_DATA(IDE_D0_MARK,                PORT171_FN6),
1299
1300         /* Port167 - Port171 IRQ */
1301         PINMUX_DATA(IRQ31_PORT167_MARK,         PORT167_FN0,    MSEL1CR_31_0),
1302         PINMUX_DATA(IRQ27_PORT168_MARK,         PORT168_FN0,    MSEL1CR_27_0),
1303         PINMUX_DATA(IRQ28_PORT169_MARK,         PORT169_FN0,    MSEL1CR_28_0),
1304         PINMUX_DATA(IRQ29_PORT170_MARK,         PORT170_FN0,    MSEL1CR_29_0),
1305         PINMUX_DATA(IRQ30_PORT171_MARK,         PORT171_FN0,    MSEL1CR_30_0),
1306
1307         /* Port172 */
1308         PINMUX_DATA(D23_MARK,                   PORT172_FN1),
1309         PINMUX_DATA(SCIFB_RTS_PORT172_MARK,     PORT172_FN2,    MSEL5CR_17_1),
1310         PINMUX_DATA(ET_ETXD7_MARK,              PORT172_FN3),
1311         PINMUX_DATA(IDE_D7_MARK,                PORT172_FN6),
1312         PINMUX_DATA(IRQ4_PORT172_MARK,          PORT172_FN0,    MSEL1CR_4_1),
1313
1314         /* Port173 */
1315         PINMUX_DATA(D22_MARK,                   PORT173_FN1),
1316         PINMUX_DATA(SCIFB_CTS_PORT173_MARK,     PORT173_FN2,    MSEL5CR_17_1),
1317         PINMUX_DATA(ET_ETXD6_MARK,              PORT173_FN3),
1318         PINMUX_DATA(IDE_D6_MARK,                PORT173_FN6),
1319         PINMUX_DATA(IRQ6_PORT173_MARK,          PORT173_FN0,    MSEL1CR_6_1),
1320
1321         /* Port174 */
1322         PINMUX_DATA(A26_MARK,                   PORT174_FN1),
1323         PINMUX_DATA(MSIOF0_TXD_MARK,            PORT174_FN2),
1324         PINMUX_DATA(ET_RX_CLK_MARK,             PORT174_FN3),
1325         PINMUX_DATA(SCIFA3_RXD_PORT174_MARK,    PORT174_FN4,    MSEL5CR_8_0),
1326
1327         /* Port175 */
1328         PINMUX_DATA(A0_MARK,                    PORT175_FN1),
1329         PINMUX_DATA(BS_MARK,                    PORT175_FN2),
1330         PINMUX_DATA(ET_WOL_MARK,                PORT175_FN3),
1331         PINMUX_DATA(SCIFA3_TXD_PORT175_MARK,    PORT175_FN4,    MSEL5CR_8_0),
1332
1333         /* Port176 */
1334         PINMUX_DATA(ET_GTX_CLK_MARK,            PORT176_FN3),
1335
1336         /* Port177 */
1337         PINMUX_DATA(WAIT_PORT177_MARK,          PORT177_FN1,    MSEL5CR_2_0),
1338         PINMUX_DATA(ET_LINK_MARK,               PORT177_FN3),
1339         PINMUX_DATA(IDE_IOWR_MARK,              PORT177_FN6),
1340         PINMUX_DATA(SDHI2_WP_PORT177_MARK,      PORT177_FN7,    MSEL5CR_19_1),
1341
1342         /* Port178 */
1343         PINMUX_DATA(VIO0_D12_MARK,              PORT178_FN1),
1344         PINMUX_DATA(VIO1_D4_MARK,               PORT178_FN5),
1345         PINMUX_DATA(IDE_IORD_MARK,              PORT178_FN6),
1346
1347         /* Port179 */
1348         PINMUX_DATA(VIO0_D11_MARK,              PORT179_FN1),
1349         PINMUX_DATA(VIO1_D3_MARK,               PORT179_FN5),
1350         PINMUX_DATA(IDE_IORDY_MARK,             PORT179_FN6),
1351
1352         /* Port180 */
1353         PINMUX_DATA(VIO0_D10_MARK,              PORT180_FN1),
1354         PINMUX_DATA(TPU0TO3_MARK,               PORT180_FN4),
1355         PINMUX_DATA(VIO1_D2_MARK,               PORT180_FN5),
1356         PINMUX_DATA(IDE_INT_MARK,               PORT180_FN6),
1357         PINMUX_DATA(IRQ24_MARK,                 PORT180_FN0),
1358
1359         /* Port181 */
1360         PINMUX_DATA(VIO0_D9_MARK,               PORT181_FN1),
1361         PINMUX_DATA(VIO1_D1_MARK,               PORT181_FN5),
1362         PINMUX_DATA(IDE_RST_MARK,               PORT181_FN6),
1363
1364         /* Port182 */
1365         PINMUX_DATA(VIO0_D8_MARK,               PORT182_FN1),
1366         PINMUX_DATA(VIO1_D0_MARK,               PORT182_FN5),
1367         PINMUX_DATA(IDE_DIRECTION_MARK,         PORT182_FN6),
1368
1369         /* Port183 */
1370         PINMUX_DATA(DREQ1_MARK,                 PORT183_FN1),
1371         PINMUX_DATA(BBIF2_TXD2_PORT183_MARK,    PORT183_FN2,    MSEL5CR_0_1),
1372         PINMUX_DATA(ET_TX_EN_MARK,              PORT183_FN3),
1373
1374         /* Port184 */
1375         PINMUX_DATA(DACK1_MARK,                 PORT184_FN1),
1376         PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK,  PORT184_FN2,    MSEL5CR_0_1),
1377         PINMUX_DATA(ET_TX_CLK_MARK,             PORT184_FN3),
1378
1379         /* Port185 - Port192 Function1 */
1380         PINMUX_DATA(SCIFA1_SCK_MARK,            PORT185_FN1),
1381         PINMUX_DATA(SCIFB_RTS_PORT186_MARK,     PORT186_FN1,    MSEL5CR_17_0),
1382         PINMUX_DATA(SCIFB_CTS_PORT187_MARK,     PORT187_FN1,    MSEL5CR_17_0),
1383         PINMUX_DATA(SCIFA0_SCK_MARK,            PORT188_FN1),
1384         PINMUX_DATA(SCIFB_SCK_PORT190_MARK,     PORT190_FN1,    MSEL5CR_17_0),
1385         PINMUX_DATA(SCIFB_RXD_PORT191_MARK,     PORT191_FN1,    MSEL5CR_17_0),
1386         PINMUX_DATA(SCIFB_TXD_PORT192_MARK,     PORT192_FN1,    MSEL5CR_17_0),
1387
1388         /* Port185 - Port192 Function3 */
1389         PINMUX_DATA(ET_ERXD0_MARK,              PORT185_FN3),
1390         PINMUX_DATA(ET_ERXD1_MARK,              PORT186_FN3),
1391         PINMUX_DATA(ET_ERXD2_MARK,              PORT187_FN3),
1392         PINMUX_DATA(ET_ERXD3_MARK,              PORT188_FN3),
1393         PINMUX_DATA(ET_ERXD4_MARK,              PORT189_FN3),
1394         PINMUX_DATA(ET_ERXD5_MARK,              PORT190_FN3),
1395         PINMUX_DATA(ET_ERXD6_MARK,              PORT191_FN3),
1396         PINMUX_DATA(ET_ERXD7_MARK,              PORT192_FN3),
1397
1398         /* Port185 - Port192 Function6 */
1399         PINMUX_DATA(STP1_IPCLK_MARK,            PORT185_FN6),
1400         PINMUX_DATA(STP1_IPD0_PORT186_MARK,     PORT186_FN6,    MSEL5CR_23_0),
1401         PINMUX_DATA(STP1_IPEN_PORT187_MARK,     PORT187_FN6,    MSEL5CR_23_0),
1402         PINMUX_DATA(STP1_IPSYNC_MARK,           PORT188_FN6),
1403         PINMUX_DATA(STP0_IPCLK_MARK,            PORT189_FN6),
1404         PINMUX_DATA(STP0_IPD0_MARK,             PORT190_FN6),
1405         PINMUX_DATA(STP0_IPEN_MARK,             PORT191_FN6),
1406         PINMUX_DATA(STP0_IPSYNC_MARK,           PORT192_FN6),
1407
1408         /* Port193 */
1409         PINMUX_DATA(SCIFA0_CTS_MARK,            PORT193_FN1),
1410         PINMUX_DATA(RMII_CRS_DV_MARK,           PORT193_FN3),
1411         PINMUX_DATA(STP1_IPEN_PORT193_MARK,     PORT193_FN6,    MSEL5CR_23_1), /* ? */
1412         PINMUX_DATA(LCD1_D17_MARK,              PORT193_FN7),
1413
1414         /* Port194 */
1415         PINMUX_DATA(SCIFA0_RTS_MARK,            PORT194_FN1),
1416         PINMUX_DATA(RMII_RX_ER_MARK,            PORT194_FN3),
1417         PINMUX_DATA(STP1_IPD0_PORT194_MARK,     PORT194_FN6,    MSEL5CR_23_1), /* ? */
1418         PINMUX_DATA(LCD1_D16_MARK,              PORT194_FN7),
1419
1420         /* Port195 */
1421         PINMUX_DATA(SCIFA1_RXD_MARK,            PORT195_FN1),
1422         PINMUX_DATA(RMII_RXD0_MARK,             PORT195_FN3),
1423         PINMUX_DATA(STP1_IPD3_MARK,             PORT195_FN6),
1424         PINMUX_DATA(LCD1_D15_MARK,              PORT195_FN7),
1425
1426         /* Port196 */
1427         PINMUX_DATA(SCIFA1_TXD_MARK,            PORT196_FN1),
1428         PINMUX_DATA(RMII_RXD1_MARK,             PORT196_FN3),
1429         PINMUX_DATA(STP1_IPD2_MARK,             PORT196_FN6),
1430         PINMUX_DATA(LCD1_D14_MARK,              PORT196_FN7),
1431
1432         /* Port197 */
1433         PINMUX_DATA(SCIFA0_RXD_MARK,            PORT197_FN1),
1434         PINMUX_DATA(VIO1_CLK_MARK,              PORT197_FN5),
1435         PINMUX_DATA(STP1_IPD5_MARK,             PORT197_FN6),
1436         PINMUX_DATA(LCD1_D19_MARK,              PORT197_FN7),
1437
1438         /* Port198 */
1439         PINMUX_DATA(SCIFA0_TXD_MARK,            PORT198_FN1),
1440         PINMUX_DATA(VIO1_VD_MARK,               PORT198_FN5),
1441         PINMUX_DATA(STP1_IPD4_MARK,             PORT198_FN6),
1442         PINMUX_DATA(LCD1_D18_MARK,              PORT198_FN7),
1443
1444         /* Port199 */
1445         PINMUX_DATA(MEMC_NWE_MARK,              PORT199_FN1),
1446         PINMUX_DATA(SCIFA2_SCK_PORT199_MARK,    PORT199_FN2,    MSEL5CR_7_1),
1447         PINMUX_DATA(RMII_TX_EN_MARK,            PORT199_FN3),
1448         PINMUX_DATA(SIM_D_PORT199_MARK,         PORT199_FN4,    MSEL5CR_21_1),
1449         PINMUX_DATA(STP1_IPD1_MARK,             PORT199_FN6),
1450         PINMUX_DATA(LCD1_D13_MARK,              PORT199_FN7),
1451
1452         /* Port200 */
1453         PINMUX_DATA(MEMC_NOE_MARK,              PORT200_FN1),
1454         PINMUX_DATA(SCIFA2_RXD_MARK,            PORT200_FN2),
1455         PINMUX_DATA(RMII_TXD0_MARK,             PORT200_FN3),
1456         PINMUX_DATA(STP0_IPD7_MARK,             PORT200_FN6),
1457         PINMUX_DATA(LCD1_D12_MARK,              PORT200_FN7),
1458
1459         /* Port201 */
1460         PINMUX_DATA(MEMC_WAIT_MARK,             PORT201_FN1,    MSEL4CR_6_0),
1461         PINMUX_DATA(MEMC_DREQ1_MARK,            PORT201_FN1,    MSEL4CR_6_1),
1462
1463         PINMUX_DATA(SCIFA2_TXD_MARK,            PORT201_FN2),
1464         PINMUX_DATA(RMII_TXD1_MARK,             PORT201_FN3),
1465         PINMUX_DATA(STP0_IPD6_MARK,             PORT201_FN6),
1466         PINMUX_DATA(LCD1_D11_MARK,              PORT201_FN7),
1467
1468         /* Port202 */
1469         PINMUX_DATA(MEMC_BUSCLK_MARK,           PORT202_FN1,    MSEL4CR_6_0),
1470         PINMUX_DATA(MEMC_A0_MARK,               PORT202_FN1,    MSEL4CR_6_1),
1471
1472         PINMUX_DATA(MSIOF1_SS2_PORT202_MARK,    PORT202_FN2,    MSEL4CR_10_1),
1473         PINMUX_DATA(RMII_MDC_MARK,              PORT202_FN3),
1474         PINMUX_DATA(TPU0TO2_PORT202_MARK,       PORT202_FN4,    MSEL5CR_25_1),
1475         PINMUX_DATA(IDE_CS0_MARK,               PORT202_FN6),
1476         PINMUX_DATA(SDHI2_CD_PORT202_MARK,      PORT202_FN7,    MSEL5CR_19_1),
1477         PINMUX_DATA(IRQ21_MARK,                 PORT202_FN0),
1478
1479         /* Port203 - Port208 Function1 */
1480         PINMUX_DATA(SDHI2_CLK_MARK,             PORT203_FN1),
1481         PINMUX_DATA(SDHI2_CMD_MARK,             PORT204_FN1),
1482         PINMUX_DATA(SDHI2_D0_MARK,              PORT205_FN1),
1483         PINMUX_DATA(SDHI2_D1_MARK,              PORT206_FN1),
1484         PINMUX_DATA(SDHI2_D2_MARK,              PORT207_FN1),
1485         PINMUX_DATA(SDHI2_D3_MARK,              PORT208_FN1),
1486
1487         /* Port203 - Port208 Function3 */
1488         PINMUX_DATA(ET_TX_ER_MARK,              PORT203_FN3),
1489         PINMUX_DATA(ET_RX_ER_MARK,              PORT204_FN3),
1490         PINMUX_DATA(ET_CRS_MARK,                PORT205_FN3),
1491         PINMUX_DATA(ET_MDC_MARK,                PORT206_FN3),
1492         PINMUX_DATA(ET_MDIO_MARK,               PORT207_FN3),
1493         PINMUX_DATA(RMII_MDIO_MARK,             PORT208_FN3),
1494
1495         /* Port203 - Port208 Function6 */
1496         PINMUX_DATA(IDE_A2_MARK,                PORT203_FN6),
1497         PINMUX_DATA(IDE_A1_MARK,                PORT204_FN6),
1498         PINMUX_DATA(IDE_A0_MARK,                PORT205_FN6),
1499         PINMUX_DATA(IDE_IODACK_MARK,            PORT206_FN6),
1500         PINMUX_DATA(IDE_IODREQ_MARK,            PORT207_FN6),
1501         PINMUX_DATA(IDE_CS1_MARK,               PORT208_FN6),
1502
1503         /* Port203 - Port208 Function7 */
1504         PINMUX_DATA(SCIFA4_TXD_PORT203_MARK,    PORT203_FN7,    MSEL5CR_12_0,   MSEL5CR_11_1),
1505         PINMUX_DATA(SCIFA4_RXD_PORT204_MARK,    PORT204_FN7,    MSEL5CR_12_0,   MSEL5CR_11_1),
1506         PINMUX_DATA(SCIFA4_SCK_PORT205_MARK,    PORT205_FN7,    MSEL5CR_10_1),
1507         PINMUX_DATA(SCIFA5_SCK_PORT206_MARK,    PORT206_FN7,    MSEL5CR_13_1),
1508         PINMUX_DATA(SCIFA5_RXD_PORT207_MARK,    PORT207_FN7,    MSEL5CR_15_0,   MSEL5CR_14_1),
1509         PINMUX_DATA(SCIFA5_TXD_PORT208_MARK,    PORT208_FN7,    MSEL5CR_15_0,   MSEL5CR_14_1),
1510
1511         /* Port209 */
1512         PINMUX_DATA(VBUS_MARK,                  PORT209_FN1),
1513         PINMUX_DATA(IRQ7_PORT209_MARK,          PORT209_FN0,    MSEL1CR_7_0),
1514
1515         /* Port210 */
1516         PINMUX_DATA(IRQ9_PORT210_MARK,          PORT210_FN0,    MSEL1CR_9_1),
1517         PINMUX_DATA(HDMI_HPD_MARK,              PORT210_FN1),
1518
1519         /* Port211 */
1520         PINMUX_DATA(IRQ16_PORT211_MARK,         PORT211_FN0,    MSEL1CR_16_1),
1521         PINMUX_DATA(HDMI_CEC_MARK,              PORT211_FN1),
1522
1523         /* SDENC */
1524         PINMUX_DATA(SDENC_CPG_MARK,                             MSEL4CR_19_0),
1525         PINMUX_DATA(SDENC_DV_CLKI_MARK,                         MSEL4CR_19_1),
1526
1527         /* SYSC */
1528         PINMUX_DATA(RESETP_PULLUP_MARK,                         MSEL4CR_4_0),
1529         PINMUX_DATA(RESETP_PLAIN_MARK,                          MSEL4CR_4_1),
1530
1531         /* DEBUG */
1532         PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK,                     MSEL4CR_1_0),
1533         PINMUX_DATA(EDEBGREQ_PULLUP_MARK,                       MSEL4CR_1_1),
1534
1535         PINMUX_DATA(TRACEAUD_FROM_VIO_MARK,                     MSEL5CR_30_0,   MSEL5CR_29_0),
1536         PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK,                   MSEL5CR_30_0,   MSEL5CR_29_1),
1537         PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK,                    MSEL5CR_30_1,   MSEL5CR_29_0),
1538 };
1539
1540 #define R8A7740_PIN(pin, cfgs)                                          \
1541         {                                                               \
1542                 .name = __stringify(PORT##pin),                         \
1543                 .enum_id = PORT##pin##_DATA,                            \
1544                 .configs = cfgs,                                        \
1545         }
1546
1547 #define __I             (SH_PFC_PIN_CFG_INPUT)
1548 #define __O             (SH_PFC_PIN_CFG_OUTPUT)
1549 #define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1550 #define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
1551 #define __PU            (SH_PFC_PIN_CFG_PULL_UP)
1552 #define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1553
1554 #define R8A7740_PIN_I_PD(pin)           R8A7740_PIN(pin, __I | __PD)
1555 #define R8A7740_PIN_I_PU(pin)           R8A7740_PIN(pin, __I | __PU)
1556 #define R8A7740_PIN_I_PU_PD(pin)                R8A7740_PIN(pin, __I | __PUD)
1557 #define R8A7740_PIN_IO(pin)             R8A7740_PIN(pin, __IO)
1558 #define R8A7740_PIN_IO_PD(pin)          R8A7740_PIN(pin, __IO | __PD)
1559 #define R8A7740_PIN_IO_PU(pin)          R8A7740_PIN(pin, __IO | __PU)
1560 #define R8A7740_PIN_IO_PU_PD(pin)       R8A7740_PIN(pin, __IO | __PUD)
1561 #define R8A7740_PIN_O(pin)              R8A7740_PIN(pin, __O)
1562 #define R8A7740_PIN_O_PU_PD(pin)                R8A7740_PIN(pin, __O | __PUD)
1563
1564 static struct sh_pfc_pin pinmux_pins[] = {
1565         /* Table 56-1 (I/O and Pull U/D) */
1566         R8A7740_PIN_IO_PD(0),           R8A7740_PIN_IO_PD(1),
1567         R8A7740_PIN_IO_PD(2),           R8A7740_PIN_IO_PD(3),
1568         R8A7740_PIN_IO_PD(4),           R8A7740_PIN_IO_PD(5),
1569         R8A7740_PIN_IO_PD(6),           R8A7740_PIN_IO(7),
1570         R8A7740_PIN_IO(8),              R8A7740_PIN_IO(9),
1571         R8A7740_PIN_IO_PD(10),          R8A7740_PIN_IO_PD(11),
1572         R8A7740_PIN_IO_PD(12),          R8A7740_PIN_IO_PU_PD(13),
1573         R8A7740_PIN_IO_PD(14),          R8A7740_PIN_IO_PD(15),
1574         R8A7740_PIN_IO_PD(16),          R8A7740_PIN_IO_PD(17),
1575         R8A7740_PIN_IO(18),             R8A7740_PIN_IO_PU(19),
1576         R8A7740_PIN_IO_PU_PD(20),       R8A7740_PIN_IO_PD(21),
1577         R8A7740_PIN_IO_PU_PD(22),       R8A7740_PIN_IO(23),
1578         R8A7740_PIN_IO_PU(24),          R8A7740_PIN_IO_PU(25),
1579         R8A7740_PIN_IO_PU(26),          R8A7740_PIN_IO_PU(27),
1580         R8A7740_PIN_IO_PU(28),          R8A7740_PIN_IO_PU(29),
1581         R8A7740_PIN_IO_PU(30),          R8A7740_PIN_IO_PD(31),
1582         R8A7740_PIN_IO_PD(32),          R8A7740_PIN_IO_PD(33),
1583         R8A7740_PIN_IO_PD(34),          R8A7740_PIN_IO_PU(35),
1584         R8A7740_PIN_IO_PU(36),          R8A7740_PIN_IO_PD(37),
1585         R8A7740_PIN_IO_PU(38),          R8A7740_PIN_IO_PD(39),
1586         R8A7740_PIN_IO_PU_PD(40),       R8A7740_PIN_IO_PD(41),
1587         R8A7740_PIN_IO_PD(42),          R8A7740_PIN_IO_PU_PD(43),
1588         R8A7740_PIN_IO_PU_PD(44),       R8A7740_PIN_IO_PU_PD(45),
1589         R8A7740_PIN_IO_PU_PD(46),       R8A7740_PIN_IO_PU_PD(47),
1590         R8A7740_PIN_IO_PU_PD(48),       R8A7740_PIN_IO_PU_PD(49),
1591         R8A7740_PIN_IO_PU_PD(50),       R8A7740_PIN_IO_PD(51),
1592         R8A7740_PIN_IO_PD(52),          R8A7740_PIN_IO_PD(53),
1593         R8A7740_PIN_IO_PD(54),          R8A7740_PIN_IO_PU_PD(55),
1594         R8A7740_PIN_IO_PU_PD(56),       R8A7740_PIN_IO_PU_PD(57),
1595         R8A7740_PIN_IO_PU_PD(58),       R8A7740_PIN_IO_PU_PD(59),
1596         R8A7740_PIN_IO_PU_PD(60),       R8A7740_PIN_IO_PD(61),
1597         R8A7740_PIN_IO_PD(62),          R8A7740_PIN_IO_PD(63),
1598         R8A7740_PIN_IO_PD(64),          R8A7740_PIN_IO_PD(65),
1599         R8A7740_PIN_IO_PU_PD(66),       R8A7740_PIN_IO_PU_PD(67),
1600         R8A7740_PIN_IO_PU_PD(68),       R8A7740_PIN_IO_PU_PD(69),
1601         R8A7740_PIN_IO_PU_PD(70),       R8A7740_PIN_IO_PU_PD(71),
1602         R8A7740_PIN_IO_PU_PD(72),       R8A7740_PIN_IO_PU_PD(73),
1603         R8A7740_PIN_IO_PU_PD(74),       R8A7740_PIN_IO_PU_PD(75),
1604         R8A7740_PIN_IO_PU_PD(76),       R8A7740_PIN_IO_PU_PD(77),
1605         R8A7740_PIN_IO_PU_PD(78),       R8A7740_PIN_IO_PU_PD(79),
1606         R8A7740_PIN_IO_PU_PD(80),       R8A7740_PIN_IO_PU_PD(81),
1607         R8A7740_PIN_IO(82),             R8A7740_PIN_IO_PU_PD(83),
1608         R8A7740_PIN_IO(84),             R8A7740_PIN_IO_PD(85),
1609         R8A7740_PIN_IO_PD(86),          R8A7740_PIN_IO_PD(87),
1610         R8A7740_PIN_IO_PD(88),          R8A7740_PIN_IO_PD(89),
1611         R8A7740_PIN_IO_PD(90),          R8A7740_PIN_IO_PU_PD(91),
1612         R8A7740_PIN_IO_PU_PD(92),       R8A7740_PIN_IO_PU_PD(93),
1613         R8A7740_PIN_IO_PU_PD(94),       R8A7740_PIN_IO_PU_PD(95),
1614         R8A7740_PIN_IO_PU_PD(96),       R8A7740_PIN_IO_PU_PD(97),
1615         R8A7740_PIN_IO_PU_PD(98),       R8A7740_PIN_IO_PU_PD(99),
1616         R8A7740_PIN_IO_PU_PD(100),      R8A7740_PIN_IO(101),
1617         R8A7740_PIN_IO_PU(102),         R8A7740_PIN_IO_PU_PD(103),
1618         R8A7740_PIN_IO_PU(104),         R8A7740_PIN_IO_PU(105),
1619         R8A7740_PIN_IO_PU_PD(106),      R8A7740_PIN_IO(107),
1620         R8A7740_PIN_IO(108),            R8A7740_PIN_IO(109),
1621         R8A7740_PIN_IO(110),            R8A7740_PIN_IO(111),
1622         R8A7740_PIN_IO(112),            R8A7740_PIN_IO(113),
1623         R8A7740_PIN_IO_PU_PD(114),      R8A7740_PIN_IO(115),
1624         R8A7740_PIN_IO_PD(116),         R8A7740_PIN_IO_PD(117),
1625         R8A7740_PIN_IO_PD(118),         R8A7740_PIN_IO_PD(119),
1626         R8A7740_PIN_IO_PD(120),         R8A7740_PIN_IO_PD(121),
1627         R8A7740_PIN_IO_PD(122),         R8A7740_PIN_IO_PD(123),
1628         R8A7740_PIN_IO_PD(124),         R8A7740_PIN_IO(125),
1629         R8A7740_PIN_IO(126),            R8A7740_PIN_IO(127),
1630         R8A7740_PIN_IO(128),            R8A7740_PIN_IO(129),
1631         R8A7740_PIN_IO(130),            R8A7740_PIN_IO(131),
1632         R8A7740_PIN_IO(132),            R8A7740_PIN_IO(133),
1633         R8A7740_PIN_IO(134),            R8A7740_PIN_IO(135),
1634         R8A7740_PIN_IO(136),            R8A7740_PIN_IO(137),
1635         R8A7740_PIN_IO(138),            R8A7740_PIN_IO(139),
1636         R8A7740_PIN_IO(140),            R8A7740_PIN_IO(141),
1637         R8A7740_PIN_IO_PU(142),         R8A7740_PIN_IO_PU(143),
1638         R8A7740_PIN_IO_PU(144),         R8A7740_PIN_IO_PU(145),
1639         R8A7740_PIN_IO_PU(146),         R8A7740_PIN_IO_PU(147),
1640         R8A7740_PIN_IO_PU(148),         R8A7740_PIN_IO_PU(149),
1641         R8A7740_PIN_IO_PU(150),         R8A7740_PIN_IO_PU(151),
1642         R8A7740_PIN_IO_PU(152),         R8A7740_PIN_IO_PU(153),
1643         R8A7740_PIN_IO_PU(154),         R8A7740_PIN_IO_PU(155),
1644         R8A7740_PIN_IO_PU(156),         R8A7740_PIN_IO_PU(157),
1645         R8A7740_PIN_IO_PD(158),         R8A7740_PIN_IO_PD(159),
1646         R8A7740_PIN_IO_PU_PD(160),      R8A7740_PIN_IO_PD(161),
1647         R8A7740_PIN_IO_PD(162),         R8A7740_PIN_IO_PD(163),
1648         R8A7740_PIN_IO_PD(164),         R8A7740_PIN_IO_PD(165),
1649         R8A7740_PIN_IO_PU(166),         R8A7740_PIN_IO_PU(167),
1650         R8A7740_PIN_IO_PU(168),         R8A7740_PIN_IO_PU(169),
1651         R8A7740_PIN_IO_PU(170),         R8A7740_PIN_IO_PU(171),
1652         R8A7740_PIN_IO_PD(172),         R8A7740_PIN_IO_PD(173),
1653         R8A7740_PIN_IO_PD(174),         R8A7740_PIN_IO_PD(175),
1654         R8A7740_PIN_IO_PU(176),         R8A7740_PIN_IO_PU_PD(177),
1655         R8A7740_PIN_IO_PU(178),         R8A7740_PIN_IO_PD(179),
1656         R8A7740_PIN_IO_PD(180),         R8A7740_PIN_IO_PU(181),
1657         R8A7740_PIN_IO_PU(182),         R8A7740_PIN_IO(183),
1658         R8A7740_PIN_IO_PD(184),         R8A7740_PIN_IO_PD(185),
1659         R8A7740_PIN_IO_PD(186),         R8A7740_PIN_IO_PD(187),
1660         R8A7740_PIN_IO_PD(188),         R8A7740_PIN_IO_PD(189),
1661         R8A7740_PIN_IO_PD(190),         R8A7740_PIN_IO_PD(191),
1662         R8A7740_PIN_IO_PD(192),         R8A7740_PIN_IO_PU_PD(193),
1663         R8A7740_PIN_IO_PU_PD(194),      R8A7740_PIN_IO_PD(195),
1664         R8A7740_PIN_IO_PU_PD(196),      R8A7740_PIN_IO_PD(197),
1665         R8A7740_PIN_IO_PU_PD(198),      R8A7740_PIN_IO_PU_PD(199),
1666         R8A7740_PIN_IO_PU_PD(200),      R8A7740_PIN_IO_PU(201),
1667         R8A7740_PIN_IO_PU_PD(202),      R8A7740_PIN_IO(203),
1668         R8A7740_PIN_IO_PU_PD(204),      R8A7740_PIN_IO_PU_PD(205),
1669         R8A7740_PIN_IO_PU_PD(206),      R8A7740_PIN_IO_PU_PD(207),
1670         R8A7740_PIN_IO_PU_PD(208),      R8A7740_PIN_IO_PD(209),
1671         R8A7740_PIN_IO_PD(210),         R8A7740_PIN_IO_PD(211),
1672 };
1673
1674 /* - BSC -------------------------------------------------------------------- */
1675 static const unsigned int bsc_data8_pins[] = {
1676         /* D[0:7] */
1677         157, 156, 155, 154, 153, 152, 151, 150,
1678 };
1679 static const unsigned int bsc_data8_mux[] = {
1680         D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1681         D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1682 };
1683 static const unsigned int bsc_data16_pins[] = {
1684         /* D[0:15] */
1685         157, 156, 155, 154, 153, 152, 151, 150,
1686         149, 148, 147, 146, 145, 144, 143, 142,
1687 };
1688 static const unsigned int bsc_data16_mux[] = {
1689         D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1690         D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1691         D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1692         D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1693 };
1694 static const unsigned int bsc_data32_pins[] = {
1695         /* D[0:31] */
1696         157, 156, 155, 154, 153, 152, 151, 150,
1697         149, 148, 147, 146, 145, 144, 143, 142,
1698         171, 170, 169, 168, 167, 166, 173, 172,
1699         165, 164, 163, 162, 161, 160, 159, 158,
1700 };
1701 static const unsigned int bsc_data32_mux[] = {
1702         D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1703         D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1704         D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1705         D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1706         D16_MARK, D17_MARK, D18_MARK, D19_MARK,
1707         D20_MARK, D21_MARK, D22_MARK, D23_MARK,
1708         D24_MARK, D25_MARK, D26_MARK, D27_MARK,
1709         D28_MARK, D29_MARK, D30_MARK, D31_MARK,
1710 };
1711 static const unsigned int bsc_cs0_pins[] = {
1712         /* CS */
1713         109,
1714 };
1715 static const unsigned int bsc_cs0_mux[] = {
1716         CS0_MARK,
1717 };
1718 static const unsigned int bsc_cs2_pins[] = {
1719         /* CS */
1720         110,
1721 };
1722 static const unsigned int bsc_cs2_mux[] = {
1723         CS2_MARK,
1724 };
1725 static const unsigned int bsc_cs4_pins[] = {
1726         /* CS */
1727         111,
1728 };
1729 static const unsigned int bsc_cs4_mux[] = {
1730         CS4_MARK,
1731 };
1732 static const unsigned int bsc_cs5a_0_pins[] = {
1733         /* CS */
1734         105,
1735 };
1736 static const unsigned int bsc_cs5a_0_mux[] = {
1737         CS5A_PORT105_MARK,
1738 };
1739 static const unsigned int bsc_cs5a_1_pins[] = {
1740         /* CS */
1741         19,
1742 };
1743 static const unsigned int bsc_cs5a_1_mux[] = {
1744         CS5A_PORT19_MARK,
1745 };
1746 static const unsigned int bsc_cs5b_pins[] = {
1747         /* CS */
1748         103,
1749 };
1750 static const unsigned int bsc_cs5b_mux[] = {
1751         CS5B_MARK,
1752 };
1753 static const unsigned int bsc_cs6a_pins[] = {
1754         /* CS */
1755         104,
1756 };
1757 static const unsigned int bsc_cs6a_mux[] = {
1758         CS6A_MARK,
1759 };
1760 static const unsigned int bsc_rd_we8_pins[] = {
1761         /* RD, WE[0] */
1762         115, 113,
1763 };
1764 static const unsigned int bsc_rd_we8_mux[] = {
1765         RD_FSC_MARK, WE0_FWE_MARK,
1766 };
1767 static const unsigned int bsc_rd_we16_pins[] = {
1768         /* RD, WE[0:1] */
1769         115, 113, 112,
1770 };
1771 static const unsigned int bsc_rd_we16_mux[] = {
1772         RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1773 };
1774 static const unsigned int bsc_rd_we32_pins[] = {
1775         /* RD, WE[0:3] */
1776         115, 113, 112, 108, 107,
1777 };
1778 static const unsigned int bsc_rd_we32_mux[] = {
1779         RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
1780 };
1781 static const unsigned int bsc_bs_pins[] = {
1782         /* BS */
1783         175,
1784 };
1785 static const unsigned int bsc_bs_mux[] = {
1786         BS_MARK,
1787 };
1788 static const unsigned int bsc_rdwr_pins[] = {
1789         /* RDWR */
1790         114,
1791 };
1792 static const unsigned int bsc_rdwr_mux[] = {
1793         RDWR_MARK,
1794 };
1795 /* - CEU0 ------------------------------------------------------------------- */
1796 static const unsigned int ceu0_data_0_7_pins[] = {
1797         /* D[0:7] */
1798         34, 33, 32, 31, 30, 29, 28, 27,
1799 };
1800 static const unsigned int ceu0_data_0_7_mux[] = {
1801         VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
1802         VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
1803 };
1804 static const unsigned int ceu0_data_8_15_0_pins[] = {
1805         /* D[8:15] */
1806         182, 181, 180, 179, 178, 26, 25, 24,
1807 };
1808 static const unsigned int ceu0_data_8_15_0_mux[] = {
1809         VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1810         VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
1811         VIO0_D15_PORT24_MARK,
1812 };
1813 static const unsigned int ceu0_data_8_15_1_pins[] = {
1814         /* D[8:15] */
1815         182, 181, 180, 179, 178, 22, 95, 96,
1816 };
1817 static const unsigned int ceu0_data_8_15_1_mux[] = {
1818         VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1819         VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
1820         VIO0_D15_PORT96_MARK,
1821 };
1822 static const unsigned int ceu0_clk_0_pins[] = {
1823         /* CKO */
1824         36,
1825 };
1826 static const unsigned int ceu0_clk_0_mux[] = {
1827         VIO_CKO_MARK,
1828 };
1829 static const unsigned int ceu0_clk_1_pins[] = {
1830         /* CKO */
1831         14,
1832 };
1833 static const unsigned int ceu0_clk_1_mux[] = {
1834         VIO_CKO1_MARK,
1835 };
1836 static const unsigned int ceu0_clk_2_pins[] = {
1837         /* CKO */
1838         15,
1839 };
1840 static const unsigned int ceu0_clk_2_mux[] = {
1841         VIO_CKO2_MARK,
1842 };
1843 static const unsigned int ceu0_sync_pins[] = {
1844         /* CLK, VD, HD */
1845         35, 39, 37,
1846 };
1847 static const unsigned int ceu0_sync_mux[] = {
1848         VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
1849 };
1850 static const unsigned int ceu0_field_pins[] = {
1851         /* FIELD */
1852         38,
1853 };
1854 static const unsigned int ceu0_field_mux[] = {
1855         VIO0_FIELD_MARK,
1856 };
1857 /* - CEU1 ------------------------------------------------------------------- */
1858 static const unsigned int ceu1_data_pins[] = {
1859         /* D[0:7] */
1860         182, 181, 180, 179, 178, 26, 25, 24,
1861 };
1862 static const unsigned int ceu1_data_mux[] = {
1863         VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
1864         VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
1865 };
1866 static const unsigned int ceu1_clk_pins[] = {
1867         /* CKO */
1868         23,
1869 };
1870 static const unsigned int ceu1_clk_mux[] = {
1871         VIO_CKO_1_MARK,
1872 };
1873 static const unsigned int ceu1_sync_pins[] = {
1874         /* CLK, VD, HD */
1875         197, 198, 160,
1876 };
1877 static const unsigned int ceu1_sync_mux[] = {
1878         VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
1879 };
1880 static const unsigned int ceu1_field_pins[] = {
1881         /* FIELD */
1882         21,
1883 };
1884 static const unsigned int ceu1_field_mux[] = {
1885         VIO1_FIELD_MARK,
1886 };
1887 /* - FSIA ------------------------------------------------------------------- */
1888 static const unsigned int fsia_mclk_in_pins[] = {
1889         /* CK */
1890         11,
1891 };
1892 static const unsigned int fsia_mclk_in_mux[] = {
1893         FSIACK_MARK,
1894 };
1895 static const unsigned int fsia_mclk_out_pins[] = {
1896         /* OMC */
1897         10,
1898 };
1899 static const unsigned int fsia_mclk_out_mux[] = {
1900         FSIAOMC_MARK,
1901 };
1902 static const unsigned int fsia_sclk_in_pins[] = {
1903         /* ILR, IBT */
1904         12, 13,
1905 };
1906 static const unsigned int fsia_sclk_in_mux[] = {
1907         FSIAILR_MARK, FSIAIBT_MARK,
1908 };
1909 static const unsigned int fsia_sclk_out_pins[] = {
1910         /* OLR, OBT */
1911         7, 8,
1912 };
1913 static const unsigned int fsia_sclk_out_mux[] = {
1914         FSIAOLR_MARK, FSIAOBT_MARK,
1915 };
1916 static const unsigned int fsia_data_in_0_pins[] = {
1917         /* ISLD */
1918         0,
1919 };
1920 static const unsigned int fsia_data_in_0_mux[] = {
1921         FSIAISLD_PORT0_MARK,
1922 };
1923 static const unsigned int fsia_data_in_1_pins[] = {
1924         /* ISLD */
1925         5,
1926 };
1927 static const unsigned int fsia_data_in_1_mux[] = {
1928         FSIAISLD_PORT5_MARK,
1929 };
1930 static const unsigned int fsia_data_out_0_pins[] = {
1931         /* OSLD */
1932         9,
1933 };
1934 static const unsigned int fsia_data_out_0_mux[] = {
1935         FSIAOSLD_MARK,
1936 };
1937 static const unsigned int fsia_data_out_1_pins[] = {
1938         /* OSLD */
1939         0,
1940 };
1941 static const unsigned int fsia_data_out_1_mux[] = {
1942         FSIAOSLD1_MARK,
1943 };
1944 static const unsigned int fsia_data_out_2_pins[] = {
1945         /* OSLD */
1946         1,
1947 };
1948 static const unsigned int fsia_data_out_2_mux[] = {
1949         FSIAOSLD2_MARK,
1950 };
1951 static const unsigned int fsia_spdif_0_pins[] = {
1952         /* SPDIF */
1953         9,
1954 };
1955 static const unsigned int fsia_spdif_0_mux[] = {
1956         FSIASPDIF_PORT9_MARK,
1957 };
1958 static const unsigned int fsia_spdif_1_pins[] = {
1959         /* SPDIF */
1960         18,
1961 };
1962 static const unsigned int fsia_spdif_1_mux[] = {
1963         FSIASPDIF_PORT18_MARK,
1964 };
1965 /* - FSIB ------------------------------------------------------------------- */
1966 static const unsigned int fsib_mclk_in_pins[] = {
1967         /* CK */
1968         11,
1969 };
1970 static const unsigned int fsib_mclk_in_mux[] = {
1971         FSIBCK_MARK,
1972 };
1973 /* - GETHER ----------------------------------------------------------------- */
1974 static const unsigned int gether_rmii_pins[] = {
1975         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
1976         195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
1977 };
1978 static const unsigned int gether_rmii_mux[] = {
1979         RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
1980         RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
1981         RMII_MDC_MARK, RMII_MDIO_MARK,
1982 };
1983 static const unsigned int gether_mii_pins[] = {
1984         /* RXD[0:3], RX_CLK, RX_DV, RX_ER
1985          * TXD[0:3], TX_CLK, TX_EN, TX_ER
1986          * CRS, COL, MDC, MDIO,
1987          */
1988         185, 186, 187, 188, 174, 161, 204,
1989         171, 170, 169, 168, 184, 183, 203,
1990         205, 163, 206, 207,
1991 };
1992 static const unsigned int gether_mii_mux[] = {
1993         ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1994         ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1995         ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1996         ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1997         ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1998 };
1999 static const unsigned int gether_gmii_pins[] = {
2000         /* RXD[0:7], RX_CLK, RX_DV, RX_ER
2001          * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
2002          * CRS, COL, MDC, MDIO, REF125CK_MARK,
2003          */
2004         185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
2005         171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
2006         205, 163, 206, 207,
2007 };
2008 static const unsigned int gether_gmii_mux[] = {
2009         ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
2010         ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
2011         ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
2012         ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
2013         ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
2014         ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
2015         ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
2016         RMII_REF125CK_MARK,
2017 };
2018 static const unsigned int gether_int_pins[] = {
2019         /* PHY_INT */
2020         164,
2021 };
2022 static const unsigned int gether_int_mux[] = {
2023         ET_PHY_INT_MARK,
2024 };
2025 static const unsigned int gether_link_pins[] = {
2026         /* LINK */
2027         177,
2028 };
2029 static const unsigned int gether_link_mux[] = {
2030         ET_LINK_MARK,
2031 };
2032 static const unsigned int gether_wol_pins[] = {
2033         /* WOL */
2034         175,
2035 };
2036 static const unsigned int gether_wol_mux[] = {
2037         ET_WOL_MARK,
2038 };
2039 /* - HDMI ------------------------------------------------------------------- */
2040 static const unsigned int hdmi_pins[] = {
2041         /* HPD, CEC */
2042         210, 211,
2043 };
2044 static const unsigned int hdmi_mux[] = {
2045         HDMI_HPD_MARK, HDMI_CEC_MARK,
2046 };
2047 /* - INTC ------------------------------------------------------------------- */
2048 IRQC_PINS_MUX(0, 0, 2);
2049 IRQC_PINS_MUX(0, 1, 13);
2050 IRQC_PIN_MUX(1, 20);
2051 IRQC_PINS_MUX(2, 0, 11);
2052 IRQC_PINS_MUX(2, 1, 12);
2053 IRQC_PINS_MUX(3, 0, 10);
2054 IRQC_PINS_MUX(3, 1, 14);
2055 IRQC_PINS_MUX(4, 0, 15);
2056 IRQC_PINS_MUX(4, 1, 172);
2057 IRQC_PINS_MUX(5, 0, 0);
2058 IRQC_PINS_MUX(5, 1, 1);
2059 IRQC_PINS_MUX(6, 0, 121);
2060 IRQC_PINS_MUX(6, 1, 173);
2061 IRQC_PINS_MUX(7, 0, 120);
2062 IRQC_PINS_MUX(7, 1, 209);
2063 IRQC_PIN_MUX(8, 119);
2064 IRQC_PINS_MUX(9, 0, 118);
2065 IRQC_PINS_MUX(9, 1, 210);
2066 IRQC_PIN_MUX(10, 19);
2067 IRQC_PIN_MUX(11, 104);
2068 IRQC_PINS_MUX(12, 0, 42);
2069 IRQC_PINS_MUX(12, 1, 97);
2070 IRQC_PINS_MUX(13, 0, 64);
2071 IRQC_PINS_MUX(13, 1, 98);
2072 IRQC_PINS_MUX(14, 0, 63);
2073 IRQC_PINS_MUX(14, 1, 99);
2074 IRQC_PINS_MUX(15, 0, 62);
2075 IRQC_PINS_MUX(15, 1, 100);
2076 IRQC_PINS_MUX(16, 0, 68);
2077 IRQC_PINS_MUX(16, 1, 211);
2078 IRQC_PIN_MUX(17, 69);
2079 IRQC_PIN_MUX(18, 70);
2080 IRQC_PIN_MUX(19, 71);
2081 IRQC_PIN_MUX(20, 67);
2082 IRQC_PIN_MUX(21, 202);
2083 IRQC_PIN_MUX(22, 95);
2084 IRQC_PIN_MUX(23, 96);
2085 IRQC_PIN_MUX(24, 180);
2086 IRQC_PIN_MUX(25, 38);
2087 IRQC_PINS_MUX(26, 0, 58);
2088 IRQC_PINS_MUX(26, 1, 81);
2089 IRQC_PINS_MUX(27, 0, 57);
2090 IRQC_PINS_MUX(27, 1, 168);
2091 IRQC_PINS_MUX(28, 0, 56);
2092 IRQC_PINS_MUX(28, 1, 169);
2093 IRQC_PINS_MUX(29, 0, 50);
2094 IRQC_PINS_MUX(29, 1, 170);
2095 IRQC_PINS_MUX(30, 0, 49);
2096 IRQC_PINS_MUX(30, 1, 171);
2097 IRQC_PINS_MUX(31, 0, 41);
2098 IRQC_PINS_MUX(31, 1, 167);
2099
2100 /* - LCD0 ------------------------------------------------------------------- */
2101 static const unsigned int lcd0_data8_pins[] = {
2102         /* D[0:7] */
2103         58, 57, 56, 55, 54, 53, 52, 51,
2104 };
2105 static const unsigned int lcd0_data8_mux[] = {
2106         LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2107         LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2108 };
2109 static const unsigned int lcd0_data9_pins[] = {
2110         /* D[0:8] */
2111         58, 57, 56, 55, 54, 53, 52, 51,
2112         50,
2113 };
2114 static const unsigned int lcd0_data9_mux[] = {
2115         LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2116         LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2117         LCD0_D8_MARK,
2118 };
2119 static const unsigned int lcd0_data12_pins[] = {
2120         /* D[0:11] */
2121         58, 57, 56, 55, 54, 53, 52, 51,
2122         50, 49, 48, 47,
2123 };
2124 static const unsigned int lcd0_data12_mux[] = {
2125         LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2126         LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2127         LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2128 };
2129 static const unsigned int lcd0_data16_pins[] = {
2130         /* D[0:15] */
2131         58, 57, 56, 55, 54, 53, 52, 51,
2132         50, 49, 48, 47, 46, 45, 44, 43,
2133 };
2134 static const unsigned int lcd0_data16_mux[] = {
2135         LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2136         LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2137         LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2138         LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2139 };
2140 static const unsigned int lcd0_data18_pins[] = {
2141         /* D[0:17] */
2142         58, 57, 56, 55, 54, 53, 52, 51,
2143         50, 49, 48, 47, 46, 45, 44, 43,
2144         42, 41,
2145 };
2146 static const unsigned int lcd0_data18_mux[] = {
2147         LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2148         LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2149         LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2150         LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2151         LCD0_D16_MARK, LCD0_D17_MARK,
2152 };
2153 static const unsigned int lcd0_data24_0_pins[] = {
2154         /* D[0:23] */
2155         58, 57, 56, 55, 54, 53, 52, 51,
2156         50, 49, 48, 47, 46, 45, 44, 43,
2157         42, 41, 40, 4, 3, 2, 0, 1,
2158 };
2159 static const unsigned int lcd0_data24_0_mux[] = {
2160         LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2161         LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2162         LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2163         LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2164         LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
2165         LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
2166         LCD0_D23_PORT1_MARK,
2167 };
2168 static const unsigned int lcd0_data24_1_pins[] = {
2169         /* D[0:23] */
2170         58, 57, 56, 55, 54, 53, 52, 51,
2171         50, 49, 48, 47, 46, 45, 44, 43,
2172         42, 41, 163, 162, 161, 158, 160, 159,
2173 };
2174 static const unsigned int lcd0_data24_1_mux[] = {
2175         LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2176         LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2177         LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2178         LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
2179         LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
2180         LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
2181 };
2182 static const unsigned int lcd0_display_pins[] = {
2183         /* DON, VCPWC, VEPWC */
2184         61, 59, 60,
2185 };
2186 static const unsigned int lcd0_display_mux[] = {
2187         LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
2188 };
2189 static const unsigned int lcd0_lclk_0_pins[] = {
2190         /* LCLK */
2191         102,
2192 };
2193 static const unsigned int lcd0_lclk_0_mux[] = {
2194         LCD0_LCLK_PORT102_MARK,
2195 };
2196 static const unsigned int lcd0_lclk_1_pins[] = {
2197         /* LCLK */
2198         165,
2199 };
2200 static const unsigned int lcd0_lclk_1_mux[] = {
2201         LCD0_LCLK_PORT165_MARK,
2202 };
2203 static const unsigned int lcd0_sync_pins[] = {
2204         /* VSYN, HSYN, DCK, DISP */
2205         63, 64, 62, 65,
2206 };
2207 static const unsigned int lcd0_sync_mux[] = {
2208         LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
2209 };
2210 static const unsigned int lcd0_sys_pins[] = {
2211         /* CS, WR, RD, RS */
2212         64, 62, 164, 65,
2213 };
2214 static const unsigned int lcd0_sys_mux[] = {
2215         LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
2216 };
2217 /* - LCD1 ------------------------------------------------------------------- */
2218 static const unsigned int lcd1_data8_pins[] = {
2219         /* D[0:7] */
2220         4, 3, 2, 1, 0, 91, 92, 23,
2221 };
2222 static const unsigned int lcd1_data8_mux[] = {
2223         LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2224         LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2225 };
2226 static const unsigned int lcd1_data9_pins[] = {
2227         /* D[0:8] */
2228         4, 3, 2, 1, 0, 91, 92, 23,
2229         93,
2230 };
2231 static const unsigned int lcd1_data9_mux[] = {
2232         LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2233         LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2234         LCD1_D8_MARK,
2235 };
2236 static const unsigned int lcd1_data12_pins[] = {
2237         /* D[0:12] */
2238         4, 3, 2, 1, 0, 91, 92, 23,
2239         93, 94, 21, 201,
2240 };
2241 static const unsigned int lcd1_data12_mux[] = {
2242         LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2243         LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2244         LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2245 };
2246 static const unsigned int lcd1_data16_pins[] = {
2247         /* D[0:15] */
2248         4, 3, 2, 1, 0, 91, 92, 23,
2249         93, 94, 21, 201, 200, 199, 196, 195,
2250 };
2251 static const unsigned int lcd1_data16_mux[] = {
2252         LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2253         LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2254         LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2255         LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2256 };
2257 static const unsigned int lcd1_data18_pins[] = {
2258         /* D[0:17] */
2259         4, 3, 2, 1, 0, 91, 92, 23,
2260         93, 94, 21, 201, 200, 199, 196, 195,
2261         194, 193,
2262 };
2263 static const unsigned int lcd1_data18_mux[] = {
2264         LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2265         LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2266         LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2267         LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2268         LCD1_D16_MARK, LCD1_D17_MARK,
2269 };
2270 static const unsigned int lcd1_data24_pins[] = {
2271         /* D[0:23] */
2272         4, 3, 2, 1, 0, 91, 92, 23,
2273         93, 94, 21, 201, 200, 199, 196, 195,
2274         194, 193, 198, 197, 75, 74, 15, 14,
2275 };
2276 static const unsigned int lcd1_data24_mux[] = {
2277         LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2278         LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2279         LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2280         LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2281         LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
2282         LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
2283 };
2284 static const unsigned int lcd1_display_pins[] = {
2285         /* DON, VCPWC, VEPWC */
2286         100, 5, 6,
2287 };
2288 static const unsigned int lcd1_display_mux[] = {
2289         LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
2290 };
2291 static const unsigned int lcd1_lclk_pins[] = {
2292         /* LCLK */
2293         40,
2294 };
2295 static const unsigned int lcd1_lclk_mux[] = {
2296         LCD1_LCLK_MARK,
2297 };
2298 static const unsigned int lcd1_sync_pins[] = {
2299         /* VSYN, HSYN, DCK, DISP */
2300         98, 97, 99, 12,
2301 };
2302 static const unsigned int lcd1_sync_mux[] = {
2303         LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
2304 };
2305 static const unsigned int lcd1_sys_pins[] = {
2306         /* CS, WR, RD, RS */
2307         97, 99, 13, 12,
2308 };
2309 static const unsigned int lcd1_sys_mux[] = {
2310         LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
2311 };
2312 /* - MMCIF ------------------------------------------------------------------ */
2313 static const unsigned int mmc0_data1_0_pins[] = {
2314         /* D[0] */
2315         68,
2316 };
2317 static const unsigned int mmc0_data1_0_mux[] = {
2318         MMC0_D0_PORT68_MARK,
2319 };
2320 static const unsigned int mmc0_data4_0_pins[] = {
2321         /* D[0:3] */
2322         68, 69, 70, 71,
2323 };
2324 static const unsigned int mmc0_data4_0_mux[] = {
2325         MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2326 };
2327 static const unsigned int mmc0_data8_0_pins[] = {
2328         /* D[0:7] */
2329         68, 69, 70, 71, 72, 73, 74, 75,
2330 };
2331 static const unsigned int mmc0_data8_0_mux[] = {
2332         MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2333         MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
2334 };
2335 static const unsigned int mmc0_ctrl_0_pins[] = {
2336         /* CMD, CLK */
2337         67, 66,
2338 };
2339 static const unsigned int mmc0_ctrl_0_mux[] = {
2340         MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
2341 };
2342
2343 static const unsigned int mmc0_data1_1_pins[] = {
2344         /* D[0] */
2345         149,
2346 };
2347 static const unsigned int mmc0_data1_1_mux[] = {
2348         MMC1_D0_PORT149_MARK,
2349 };
2350 static const unsigned int mmc0_data4_1_pins[] = {
2351         /* D[0:3] */
2352         149, 148, 147, 146,
2353 };
2354 static const unsigned int mmc0_data4_1_mux[] = {
2355         MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2356 };
2357 static const unsigned int mmc0_data8_1_pins[] = {
2358         /* D[0:7] */
2359         149, 148, 147, 146, 145, 144, 143, 142,
2360 };
2361 static const unsigned int mmc0_data8_1_mux[] = {
2362         MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2363         MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
2364 };
2365 static const unsigned int mmc0_ctrl_1_pins[] = {
2366         /* CMD, CLK */
2367         104, 103,
2368 };
2369 static const unsigned int mmc0_ctrl_1_mux[] = {
2370         MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
2371 };
2372 /* - SCIFA0 ----------------------------------------------------------------- */
2373 static const unsigned int scifa0_data_pins[] = {
2374         /* RXD, TXD */
2375         197, 198,
2376 };
2377 static const unsigned int scifa0_data_mux[] = {
2378         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2379 };
2380 static const unsigned int scifa0_clk_pins[] = {
2381         /* SCK */
2382         188,
2383 };
2384 static const unsigned int scifa0_clk_mux[] = {
2385         SCIFA0_SCK_MARK,
2386 };
2387 static const unsigned int scifa0_ctrl_pins[] = {
2388         /* RTS, CTS */
2389         194, 193,
2390 };
2391 static const unsigned int scifa0_ctrl_mux[] = {
2392         SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
2393 };
2394 /* - SCIFA1 ----------------------------------------------------------------- */
2395 static const unsigned int scifa1_data_pins[] = {
2396         /* RXD, TXD */
2397         195, 196,
2398 };
2399 static const unsigned int scifa1_data_mux[] = {
2400         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2401 };
2402 static const unsigned int scifa1_clk_pins[] = {
2403         /* SCK */
2404         185,
2405 };
2406 static const unsigned int scifa1_clk_mux[] = {
2407         SCIFA1_SCK_MARK,
2408 };
2409 static const unsigned int scifa1_ctrl_pins[] = {
2410         /* RTS, CTS */
2411         23, 21,
2412 };
2413 static const unsigned int scifa1_ctrl_mux[] = {
2414         SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
2415 };
2416 /* - SCIFA2 ----------------------------------------------------------------- */
2417 static const unsigned int scifa2_data_pins[] = {
2418         /* RXD, TXD */
2419         200, 201,
2420 };
2421 static const unsigned int scifa2_data_mux[] = {
2422         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2423 };
2424 static const unsigned int scifa2_clk_0_pins[] = {
2425         /* SCK */
2426         22,
2427 };
2428 static const unsigned int scifa2_clk_0_mux[] = {
2429         SCIFA2_SCK_PORT22_MARK,
2430 };
2431 static const unsigned int scifa2_clk_1_pins[] = {
2432         /* SCK */
2433         199,
2434 };
2435 static const unsigned int scifa2_clk_1_mux[] = {
2436         SCIFA2_SCK_PORT199_MARK,
2437 };
2438 static const unsigned int scifa2_ctrl_pins[] = {
2439         /* RTS, CTS */
2440         96, 95,
2441 };
2442 static const unsigned int scifa2_ctrl_mux[] = {
2443         SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
2444 };
2445 /* - SCIFA3 ----------------------------------------------------------------- */
2446 static const unsigned int scifa3_data_0_pins[] = {
2447         /* RXD, TXD */
2448         174, 175,
2449 };
2450 static const unsigned int scifa3_data_0_mux[] = {
2451         SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
2452 };
2453 static const unsigned int scifa3_clk_0_pins[] = {
2454         /* SCK */
2455         116,
2456 };
2457 static const unsigned int scifa3_clk_0_mux[] = {
2458         SCIFA3_SCK_PORT116_MARK,
2459 };
2460 static const unsigned int scifa3_ctrl_0_pins[] = {
2461         /* RTS, CTS */
2462         105, 117,
2463 };
2464 static const unsigned int scifa3_ctrl_0_mux[] = {
2465         SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
2466 };
2467 static const unsigned int scifa3_data_1_pins[] = {
2468         /* RXD, TXD */
2469         159, 160,
2470 };
2471 static const unsigned int scifa3_data_1_mux[] = {
2472         SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
2473 };
2474 static const unsigned int scifa3_clk_1_pins[] = {
2475         /* SCK */
2476         158,
2477 };
2478 static const unsigned int scifa3_clk_1_mux[] = {
2479         SCIFA3_SCK_PORT158_MARK,
2480 };
2481 static const unsigned int scifa3_ctrl_1_pins[] = {
2482         /* RTS, CTS */
2483         161, 162,
2484 };
2485 static const unsigned int scifa3_ctrl_1_mux[] = {
2486         SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
2487 };
2488 /* - SCIFA4 ----------------------------------------------------------------- */
2489 static const unsigned int scifa4_data_0_pins[] = {
2490         /* RXD, TXD */
2491         12, 13,
2492 };
2493 static const unsigned int scifa4_data_0_mux[] = {
2494         SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
2495 };
2496 static const unsigned int scifa4_data_1_pins[] = {
2497         /* RXD, TXD */
2498         204, 203,
2499 };
2500 static const unsigned int scifa4_data_1_mux[] = {
2501         SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
2502 };
2503 static const unsigned int scifa4_data_2_pins[] = {
2504         /* RXD, TXD */
2505         94, 93,
2506 };
2507 static const unsigned int scifa4_data_2_mux[] = {
2508         SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
2509 };
2510 static const unsigned int scifa4_clk_0_pins[] = {
2511         /* SCK */
2512         21,
2513 };
2514 static const unsigned int scifa4_clk_0_mux[] = {
2515         SCIFA4_SCK_PORT21_MARK,
2516 };
2517 static const unsigned int scifa4_clk_1_pins[] = {
2518         /* SCK */
2519         205,
2520 };
2521 static const unsigned int scifa4_clk_1_mux[] = {
2522         SCIFA4_SCK_PORT205_MARK,
2523 };
2524 /* - SCIFA5 ----------------------------------------------------------------- */
2525 static const unsigned int scifa5_data_0_pins[] = {
2526         /* RXD, TXD */
2527         10, 20,
2528 };
2529 static const unsigned int scifa5_data_0_mux[] = {
2530         SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
2531 };
2532 static const unsigned int scifa5_data_1_pins[] = {
2533         /* RXD, TXD */
2534         207, 208,
2535 };
2536 static const unsigned int scifa5_data_1_mux[] = {
2537         SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
2538 };
2539 static const unsigned int scifa5_data_2_pins[] = {
2540         /* RXD, TXD */
2541         92, 91,
2542 };
2543 static const unsigned int scifa5_data_2_mux[] = {
2544         SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
2545 };
2546 static const unsigned int scifa5_clk_0_pins[] = {
2547         /* SCK */
2548         23,
2549 };
2550 static const unsigned int scifa5_clk_0_mux[] = {
2551         SCIFA5_SCK_PORT23_MARK,
2552 };
2553 static const unsigned int scifa5_clk_1_pins[] = {
2554         /* SCK */
2555         206,
2556 };
2557 static const unsigned int scifa5_clk_1_mux[] = {
2558         SCIFA5_SCK_PORT206_MARK,
2559 };
2560 /* - SCIFA6 ----------------------------------------------------------------- */
2561 static const unsigned int scifa6_data_pins[] = {
2562         /* RXD, TXD */
2563         25, 26,
2564 };
2565 static const unsigned int scifa6_data_mux[] = {
2566         SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
2567 };
2568 static const unsigned int scifa6_clk_pins[] = {
2569         /* SCK */
2570         24,
2571 };
2572 static const unsigned int scifa6_clk_mux[] = {
2573         SCIFA6_SCK_MARK,
2574 };
2575 /* - SCIFA7 ----------------------------------------------------------------- */
2576 static const unsigned int scifa7_data_pins[] = {
2577         /* RXD, TXD */
2578         0, 1,
2579 };
2580 static const unsigned int scifa7_data_mux[] = {
2581         SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2582 };
2583 /* - SCIFB ------------------------------------------------------------------ */
2584 static const unsigned int scifb_data_0_pins[] = {
2585         /* RXD, TXD */
2586         191, 192,
2587 };
2588 static const unsigned int scifb_data_0_mux[] = {
2589         SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
2590 };
2591 static const unsigned int scifb_clk_0_pins[] = {
2592         /* SCK */
2593         190,
2594 };
2595 static const unsigned int scifb_clk_0_mux[] = {
2596         SCIFB_SCK_PORT190_MARK,
2597 };
2598 static const unsigned int scifb_ctrl_0_pins[] = {
2599         /* RTS, CTS */
2600         186, 187,
2601 };
2602 static const unsigned int scifb_ctrl_0_mux[] = {
2603         SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
2604 };
2605 static const unsigned int scifb_data_1_pins[] = {
2606         /* RXD, TXD */
2607         3, 4,
2608 };
2609 static const unsigned int scifb_data_1_mux[] = {
2610         SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
2611 };
2612 static const unsigned int scifb_clk_1_pins[] = {
2613         /* SCK */
2614         2,
2615 };
2616 static const unsigned int scifb_clk_1_mux[] = {
2617         SCIFB_SCK_PORT2_MARK,
2618 };
2619 static const unsigned int scifb_ctrl_1_pins[] = {
2620         /* RTS, CTS */
2621         172, 173,
2622 };
2623 static const unsigned int scifb_ctrl_1_mux[] = {
2624         SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
2625 };
2626 /* - SDHI0 ------------------------------------------------------------------ */
2627 static const unsigned int sdhi0_data1_pins[] = {
2628         /* D0 */
2629         77,
2630 };
2631 static const unsigned int sdhi0_data1_mux[] = {
2632         SDHI0_D0_MARK,
2633 };
2634 static const unsigned int sdhi0_data4_pins[] = {
2635         /* D[0:3] */
2636         77, 78, 79, 80,
2637 };
2638 static const unsigned int sdhi0_data4_mux[] = {
2639         SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
2640 };
2641 static const unsigned int sdhi0_ctrl_pins[] = {
2642         /* CMD, CLK */
2643         76, 82,
2644 };
2645 static const unsigned int sdhi0_ctrl_mux[] = {
2646         SDHI0_CMD_MARK, SDHI0_CLK_MARK,
2647 };
2648 static const unsigned int sdhi0_cd_pins[] = {
2649         /* CD */
2650         81,
2651 };
2652 static const unsigned int sdhi0_cd_mux[] = {
2653         SDHI0_CD_MARK,
2654 };
2655 static const unsigned int sdhi0_wp_pins[] = {
2656         /* WP */
2657         83,
2658 };
2659 static const unsigned int sdhi0_wp_mux[] = {
2660         SDHI0_WP_MARK,
2661 };
2662 /* - SDHI1 ------------------------------------------------------------------ */
2663 static const unsigned int sdhi1_data1_pins[] = {
2664         /* D0 */
2665         68,
2666 };
2667 static const unsigned int sdhi1_data1_mux[] = {
2668         SDHI1_D0_MARK,
2669 };
2670 static const unsigned int sdhi1_data4_pins[] = {
2671         /* D[0:3] */
2672         68, 69, 70, 71,
2673 };
2674 static const unsigned int sdhi1_data4_mux[] = {
2675         SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
2676 };
2677 static const unsigned int sdhi1_ctrl_pins[] = {
2678         /* CMD, CLK */
2679         67, 66,
2680 };
2681 static const unsigned int sdhi1_ctrl_mux[] = {
2682         SDHI1_CMD_MARK, SDHI1_CLK_MARK,
2683 };
2684 static const unsigned int sdhi1_cd_pins[] = {
2685         /* CD */
2686         72,
2687 };
2688 static const unsigned int sdhi1_cd_mux[] = {
2689         SDHI1_CD_MARK,
2690 };
2691 static const unsigned int sdhi1_wp_pins[] = {
2692         /* WP */
2693         73,
2694 };
2695 static const unsigned int sdhi1_wp_mux[] = {
2696         SDHI1_WP_MARK,
2697 };
2698 /* - SDHI2 ------------------------------------------------------------------ */
2699 static const unsigned int sdhi2_data1_pins[] = {
2700         /* D0 */
2701         205,
2702 };
2703 static const unsigned int sdhi2_data1_mux[] = {
2704         SDHI2_D0_MARK,
2705 };
2706 static const unsigned int sdhi2_data4_pins[] = {
2707         /* D[0:3] */
2708         205, 206, 207, 208,
2709 };
2710 static const unsigned int sdhi2_data4_mux[] = {
2711         SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2712 };
2713 static const unsigned int sdhi2_ctrl_pins[] = {
2714         /* CMD, CLK */
2715         204, 203,
2716 };
2717 static const unsigned int sdhi2_ctrl_mux[] = {
2718         SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2719 };
2720 static const unsigned int sdhi2_cd_0_pins[] = {
2721         /* CD */
2722         202,
2723 };
2724 static const unsigned int sdhi2_cd_0_mux[] = {
2725         SDHI2_CD_PORT202_MARK,
2726 };
2727 static const unsigned int sdhi2_wp_0_pins[] = {
2728         /* WP */
2729         177,
2730 };
2731 static const unsigned int sdhi2_wp_0_mux[] = {
2732         SDHI2_WP_PORT177_MARK,
2733 };
2734 static const unsigned int sdhi2_cd_1_pins[] = {
2735         /* CD */
2736         24,
2737 };
2738 static const unsigned int sdhi2_cd_1_mux[] = {
2739         SDHI2_CD_PORT24_MARK,
2740 };
2741 static const unsigned int sdhi2_wp_1_pins[] = {
2742         /* WP */
2743         25,
2744 };
2745 static const unsigned int sdhi2_wp_1_mux[] = {
2746         SDHI2_WP_PORT25_MARK,
2747 };
2748 /* - TPU0 ------------------------------------------------------------------- */
2749 static const unsigned int tpu0_to0_pins[] = {
2750         /* TO */
2751         23,
2752 };
2753 static const unsigned int tpu0_to0_mux[] = {
2754         TPU0TO0_MARK,
2755 };
2756 static const unsigned int tpu0_to1_pins[] = {
2757         /* TO */
2758         21,
2759 };
2760 static const unsigned int tpu0_to1_mux[] = {
2761         TPU0TO1_MARK,
2762 };
2763 static const unsigned int tpu0_to2_0_pins[] = {
2764         /* TO */
2765         66,
2766 };
2767 static const unsigned int tpu0_to2_0_mux[] = {
2768         TPU0TO2_PORT66_MARK,
2769 };
2770 static const unsigned int tpu0_to2_1_pins[] = {
2771         /* TO */
2772         202,
2773 };
2774 static const unsigned int tpu0_to2_1_mux[] = {
2775         TPU0TO2_PORT202_MARK,
2776 };
2777 static const unsigned int tpu0_to3_pins[] = {
2778         /* TO */
2779         180,
2780 };
2781 static const unsigned int tpu0_to3_mux[] = {
2782         TPU0TO3_MARK,
2783 };
2784
2785 static const struct sh_pfc_pin_group pinmux_groups[] = {
2786         SH_PFC_PIN_GROUP(bsc_data8),
2787         SH_PFC_PIN_GROUP(bsc_data16),
2788         SH_PFC_PIN_GROUP(bsc_data32),
2789         SH_PFC_PIN_GROUP(bsc_cs0),
2790         SH_PFC_PIN_GROUP(bsc_cs2),
2791         SH_PFC_PIN_GROUP(bsc_cs4),
2792         SH_PFC_PIN_GROUP(bsc_cs5a_0),
2793         SH_PFC_PIN_GROUP(bsc_cs5a_1),
2794         SH_PFC_PIN_GROUP(bsc_cs5b),
2795         SH_PFC_PIN_GROUP(bsc_cs6a),
2796         SH_PFC_PIN_GROUP(bsc_rd_we8),
2797         SH_PFC_PIN_GROUP(bsc_rd_we16),
2798         SH_PFC_PIN_GROUP(bsc_rd_we32),
2799         SH_PFC_PIN_GROUP(bsc_bs),
2800         SH_PFC_PIN_GROUP(bsc_rdwr),
2801         SH_PFC_PIN_GROUP(ceu0_data_0_7),
2802         SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
2803         SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
2804         SH_PFC_PIN_GROUP(ceu0_clk_0),
2805         SH_PFC_PIN_GROUP(ceu0_clk_1),
2806         SH_PFC_PIN_GROUP(ceu0_clk_2),
2807         SH_PFC_PIN_GROUP(ceu0_sync),
2808         SH_PFC_PIN_GROUP(ceu0_field),
2809         SH_PFC_PIN_GROUP(ceu1_data),
2810         SH_PFC_PIN_GROUP(ceu1_clk),
2811         SH_PFC_PIN_GROUP(ceu1_sync),
2812         SH_PFC_PIN_GROUP(ceu1_field),
2813         SH_PFC_PIN_GROUP(fsia_mclk_in),
2814         SH_PFC_PIN_GROUP(fsia_mclk_out),
2815         SH_PFC_PIN_GROUP(fsia_sclk_in),
2816         SH_PFC_PIN_GROUP(fsia_sclk_out),
2817         SH_PFC_PIN_GROUP(fsia_data_in_0),
2818         SH_PFC_PIN_GROUP(fsia_data_in_1),
2819         SH_PFC_PIN_GROUP(fsia_data_out_0),
2820         SH_PFC_PIN_GROUP(fsia_data_out_1),
2821         SH_PFC_PIN_GROUP(fsia_data_out_2),
2822         SH_PFC_PIN_GROUP(fsia_spdif_0),
2823         SH_PFC_PIN_GROUP(fsia_spdif_1),
2824         SH_PFC_PIN_GROUP(fsib_mclk_in),
2825         SH_PFC_PIN_GROUP(gether_rmii),
2826         SH_PFC_PIN_GROUP(gether_mii),
2827         SH_PFC_PIN_GROUP(gether_gmii),
2828         SH_PFC_PIN_GROUP(gether_int),
2829         SH_PFC_PIN_GROUP(gether_link),
2830         SH_PFC_PIN_GROUP(gether_wol),
2831         SH_PFC_PIN_GROUP(hdmi),
2832         SH_PFC_PIN_GROUP(intc_irq0_0),
2833         SH_PFC_PIN_GROUP(intc_irq0_1),
2834         SH_PFC_PIN_GROUP(intc_irq1),
2835         SH_PFC_PIN_GROUP(intc_irq2_0),
2836         SH_PFC_PIN_GROUP(intc_irq2_1),
2837         SH_PFC_PIN_GROUP(intc_irq3_0),
2838         SH_PFC_PIN_GROUP(intc_irq3_1),
2839         SH_PFC_PIN_GROUP(intc_irq4_0),
2840         SH_PFC_PIN_GROUP(intc_irq4_1),
2841         SH_PFC_PIN_GROUP(intc_irq5_0),
2842         SH_PFC_PIN_GROUP(intc_irq5_1),
2843         SH_PFC_PIN_GROUP(intc_irq6_0),
2844         SH_PFC_PIN_GROUP(intc_irq6_1),
2845         SH_PFC_PIN_GROUP(intc_irq7_0),
2846         SH_PFC_PIN_GROUP(intc_irq7_1),
2847         SH_PFC_PIN_GROUP(intc_irq8),
2848         SH_PFC_PIN_GROUP(intc_irq9_0),
2849         SH_PFC_PIN_GROUP(intc_irq9_1),
2850         SH_PFC_PIN_GROUP(intc_irq10),
2851         SH_PFC_PIN_GROUP(intc_irq11),
2852         SH_PFC_PIN_GROUP(intc_irq12_0),
2853         SH_PFC_PIN_GROUP(intc_irq12_1),
2854         SH_PFC_PIN_GROUP(intc_irq13_0),
2855         SH_PFC_PIN_GROUP(intc_irq13_1),
2856         SH_PFC_PIN_GROUP(intc_irq14_0),
2857         SH_PFC_PIN_GROUP(intc_irq14_1),
2858         SH_PFC_PIN_GROUP(intc_irq15_0),
2859         SH_PFC_PIN_GROUP(intc_irq15_1),
2860         SH_PFC_PIN_GROUP(intc_irq16_0),
2861         SH_PFC_PIN_GROUP(intc_irq16_1),
2862         SH_PFC_PIN_GROUP(intc_irq17),
2863         SH_PFC_PIN_GROUP(intc_irq18),
2864         SH_PFC_PIN_GROUP(intc_irq19),
2865         SH_PFC_PIN_GROUP(intc_irq20),
2866         SH_PFC_PIN_GROUP(intc_irq21),
2867         SH_PFC_PIN_GROUP(intc_irq22),
2868         SH_PFC_PIN_GROUP(intc_irq23),
2869         SH_PFC_PIN_GROUP(intc_irq24),
2870         SH_PFC_PIN_GROUP(intc_irq25),
2871         SH_PFC_PIN_GROUP(intc_irq26_0),
2872         SH_PFC_PIN_GROUP(intc_irq26_1),
2873         SH_PFC_PIN_GROUP(intc_irq27_0),
2874         SH_PFC_PIN_GROUP(intc_irq27_1),
2875         SH_PFC_PIN_GROUP(intc_irq28_0),
2876         SH_PFC_PIN_GROUP(intc_irq28_1),
2877         SH_PFC_PIN_GROUP(intc_irq29_0),
2878         SH_PFC_PIN_GROUP(intc_irq29_1),
2879         SH_PFC_PIN_GROUP(intc_irq30_0),
2880         SH_PFC_PIN_GROUP(intc_irq30_1),
2881         SH_PFC_PIN_GROUP(intc_irq31_0),
2882         SH_PFC_PIN_GROUP(intc_irq31_1),
2883         SH_PFC_PIN_GROUP(lcd0_data8),
2884         SH_PFC_PIN_GROUP(lcd0_data9),
2885         SH_PFC_PIN_GROUP(lcd0_data12),
2886         SH_PFC_PIN_GROUP(lcd0_data16),
2887         SH_PFC_PIN_GROUP(lcd0_data18),
2888         SH_PFC_PIN_GROUP(lcd0_data24_0),
2889         SH_PFC_PIN_GROUP(lcd0_data24_1),
2890         SH_PFC_PIN_GROUP(lcd0_display),
2891         SH_PFC_PIN_GROUP(lcd0_lclk_0),
2892         SH_PFC_PIN_GROUP(lcd0_lclk_1),
2893         SH_PFC_PIN_GROUP(lcd0_sync),
2894         SH_PFC_PIN_GROUP(lcd0_sys),
2895         SH_PFC_PIN_GROUP(lcd1_data8),
2896         SH_PFC_PIN_GROUP(lcd1_data9),
2897         SH_PFC_PIN_GROUP(lcd1_data12),
2898         SH_PFC_PIN_GROUP(lcd1_data16),
2899         SH_PFC_PIN_GROUP(lcd1_data18),
2900         SH_PFC_PIN_GROUP(lcd1_data24),
2901         SH_PFC_PIN_GROUP(lcd1_display),
2902         SH_PFC_PIN_GROUP(lcd1_lclk),
2903         SH_PFC_PIN_GROUP(lcd1_sync),
2904         SH_PFC_PIN_GROUP(lcd1_sys),
2905         SH_PFC_PIN_GROUP(mmc0_data1_0),
2906         SH_PFC_PIN_GROUP(mmc0_data4_0),
2907         SH_PFC_PIN_GROUP(mmc0_data8_0),
2908         SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2909         SH_PFC_PIN_GROUP(mmc0_data1_1),
2910         SH_PFC_PIN_GROUP(mmc0_data4_1),
2911         SH_PFC_PIN_GROUP(mmc0_data8_1),
2912         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2913         SH_PFC_PIN_GROUP(scifa0_data),
2914         SH_PFC_PIN_GROUP(scifa0_clk),
2915         SH_PFC_PIN_GROUP(scifa0_ctrl),
2916         SH_PFC_PIN_GROUP(scifa1_data),
2917         SH_PFC_PIN_GROUP(scifa1_clk),
2918         SH_PFC_PIN_GROUP(scifa1_ctrl),
2919         SH_PFC_PIN_GROUP(scifa2_data),
2920         SH_PFC_PIN_GROUP(scifa2_clk_0),
2921         SH_PFC_PIN_GROUP(scifa2_clk_1),
2922         SH_PFC_PIN_GROUP(scifa2_ctrl),
2923         SH_PFC_PIN_GROUP(scifa3_data_0),
2924         SH_PFC_PIN_GROUP(scifa3_clk_0),
2925         SH_PFC_PIN_GROUP(scifa3_ctrl_0),
2926         SH_PFC_PIN_GROUP(scifa3_data_1),
2927         SH_PFC_PIN_GROUP(scifa3_clk_1),
2928         SH_PFC_PIN_GROUP(scifa3_ctrl_1),
2929         SH_PFC_PIN_GROUP(scifa4_data_0),
2930         SH_PFC_PIN_GROUP(scifa4_data_1),
2931         SH_PFC_PIN_GROUP(scifa4_data_2),
2932         SH_PFC_PIN_GROUP(scifa4_clk_0),
2933         SH_PFC_PIN_GROUP(scifa4_clk_1),
2934         SH_PFC_PIN_GROUP(scifa5_data_0),
2935         SH_PFC_PIN_GROUP(scifa5_data_1),
2936         SH_PFC_PIN_GROUP(scifa5_data_2),
2937         SH_PFC_PIN_GROUP(scifa5_clk_0),
2938         SH_PFC_PIN_GROUP(scifa5_clk_1),
2939         SH_PFC_PIN_GROUP(scifa6_data),
2940         SH_PFC_PIN_GROUP(scifa6_clk),
2941         SH_PFC_PIN_GROUP(scifa7_data),
2942         SH_PFC_PIN_GROUP(scifb_data_0),
2943         SH_PFC_PIN_GROUP(scifb_clk_0),
2944         SH_PFC_PIN_GROUP(scifb_ctrl_0),
2945         SH_PFC_PIN_GROUP(scifb_data_1),
2946         SH_PFC_PIN_GROUP(scifb_clk_1),
2947         SH_PFC_PIN_GROUP(scifb_ctrl_1),
2948         SH_PFC_PIN_GROUP(sdhi0_data1),
2949         SH_PFC_PIN_GROUP(sdhi0_data4),
2950         SH_PFC_PIN_GROUP(sdhi0_ctrl),
2951         SH_PFC_PIN_GROUP(sdhi0_cd),
2952         SH_PFC_PIN_GROUP(sdhi0_wp),
2953         SH_PFC_PIN_GROUP(sdhi1_data1),
2954         SH_PFC_PIN_GROUP(sdhi1_data4),
2955         SH_PFC_PIN_GROUP(sdhi1_ctrl),
2956         SH_PFC_PIN_GROUP(sdhi1_cd),
2957         SH_PFC_PIN_GROUP(sdhi1_wp),
2958         SH_PFC_PIN_GROUP(sdhi2_data1),
2959         SH_PFC_PIN_GROUP(sdhi2_data4),
2960         SH_PFC_PIN_GROUP(sdhi2_ctrl),
2961         SH_PFC_PIN_GROUP(sdhi2_cd_0),
2962         SH_PFC_PIN_GROUP(sdhi2_wp_0),
2963         SH_PFC_PIN_GROUP(sdhi2_cd_1),
2964         SH_PFC_PIN_GROUP(sdhi2_wp_1),
2965         SH_PFC_PIN_GROUP(tpu0_to0),
2966         SH_PFC_PIN_GROUP(tpu0_to1),
2967         SH_PFC_PIN_GROUP(tpu0_to2_0),
2968         SH_PFC_PIN_GROUP(tpu0_to2_1),
2969         SH_PFC_PIN_GROUP(tpu0_to3),
2970 };
2971
2972 static const char * const bsc_groups[] = {
2973         "bsc_data8",
2974         "bsc_data16",
2975         "bsc_data32",
2976         "bsc_cs0",
2977         "bsc_cs2",
2978         "bsc_cs4",
2979         "bsc_cs5a_0",
2980         "bsc_cs5a_1",
2981         "bsc_cs5b",
2982         "bsc_cs6a",
2983         "bsc_rd_we8",
2984         "bsc_rd_we16",
2985         "bsc_rd_we32",
2986         "bsc_bs",
2987         "bsc_rdwr",
2988 };
2989
2990 static const char * const ceu0_groups[] = {
2991         "ceu0_data_0_7",
2992         "ceu0_data_8_15_0",
2993         "ceu0_data_8_15_1",
2994         "ceu0_clk_0",
2995         "ceu0_clk_1",
2996         "ceu0_clk_2",
2997         "ceu0_sync",
2998         "ceu0_field",
2999 };
3000
3001 static const char * const ceu1_groups[] = {
3002         "ceu1_data",
3003         "ceu1_clk",
3004         "ceu1_sync",
3005         "ceu1_field",
3006 };
3007
3008 static const char * const fsia_groups[] = {
3009         "fsia_mclk_in",
3010         "fsia_mclk_out",
3011         "fsia_sclk_in",
3012         "fsia_sclk_out",
3013         "fsia_data_in_0",
3014         "fsia_data_in_1",
3015         "fsia_data_out_0",
3016         "fsia_data_out_1",
3017         "fsia_data_out_2",
3018         "fsia_spdif_0",
3019         "fsia_spdif_1",
3020 };
3021
3022 static const char * const fsib_groups[] = {
3023         "fsib_mclk_in",
3024 };
3025
3026 static const char * const gether_groups[] = {
3027         "gether_rmii",
3028         "gether_mii",
3029         "gether_gmii",
3030         "gether_int",
3031         "gether_link",
3032         "gether_wol",
3033 };
3034
3035 static const char * const hdmi_groups[] = {
3036         "hdmi",
3037 };
3038
3039 static const char * const intc_groups[] = {
3040         "intc_irq0_0",
3041         "intc_irq0_1",
3042         "intc_irq1",
3043         "intc_irq2_0",
3044         "intc_irq2_1",
3045         "intc_irq3_0",
3046         "intc_irq3_1",
3047         "intc_irq4_0",
3048         "intc_irq4_1",
3049         "intc_irq5_0",
3050         "intc_irq5_1",
3051         "intc_irq6_0",
3052         "intc_irq6_1",
3053         "intc_irq7_0",
3054         "intc_irq7_1",
3055         "intc_irq8",
3056         "intc_irq9_0",
3057         "intc_irq9_1",
3058         "intc_irq10",
3059         "intc_irq11",
3060         "intc_irq12_0",
3061         "intc_irq12_1",
3062         "intc_irq13_0",
3063         "intc_irq13_1",
3064         "intc_irq14_0",
3065         "intc_irq14_1",
3066         "intc_irq15_0",
3067         "intc_irq15_1",
3068         "intc_irq16_0",
3069         "intc_irq16_1",
3070         "intc_irq17",
3071         "intc_irq18",
3072         "intc_irq19",
3073         "intc_irq20",
3074         "intc_irq21",
3075         "intc_irq22",
3076         "intc_irq23",
3077         "intc_irq24",
3078         "intc_irq25",
3079         "intc_irq26_0",
3080         "intc_irq26_1",
3081         "intc_irq27_0",
3082         "intc_irq27_1",
3083         "intc_irq28_0",
3084         "intc_irq28_1",
3085         "intc_irq29_0",
3086         "intc_irq29_1",
3087         "intc_irq30_0",
3088         "intc_irq30_1",
3089         "intc_irq31_0",
3090         "intc_irq31_1",
3091 };
3092
3093 static const char * const lcd0_groups[] = {
3094         "lcd0_data8",
3095         "lcd0_data9",
3096         "lcd0_data12",
3097         "lcd0_data16",
3098         "lcd0_data18",
3099         "lcd0_data24_0",
3100         "lcd0_data24_1",
3101         "lcd0_display",
3102         "lcd0_lclk_0",
3103         "lcd0_lclk_1",
3104         "lcd0_sync",
3105         "lcd0_sys",
3106 };
3107
3108 static const char * const lcd1_groups[] = {
3109         "lcd1_data8",
3110         "lcd1_data9",
3111         "lcd1_data12",
3112         "lcd1_data16",
3113         "lcd1_data18",
3114         "lcd1_data24",
3115         "lcd1_display",
3116         "lcd1_lclk",
3117         "lcd1_sync",
3118         "lcd1_sys",
3119 };
3120
3121 static const char * const mmc0_groups[] = {
3122         "mmc0_data1_0",
3123         "mmc0_data4_0",
3124         "mmc0_data8_0",
3125         "mmc0_ctrl_0",
3126         "mmc0_data1_1",
3127         "mmc0_data4_1",
3128         "mmc0_data8_1",
3129         "mmc0_ctrl_1",
3130 };
3131
3132 static const char * const scifa0_groups[] = {
3133         "scifa0_data",
3134         "scifa0_clk",
3135         "scifa0_ctrl",
3136 };
3137
3138 static const char * const scifa1_groups[] = {
3139         "scifa1_data",
3140         "scifa1_clk",
3141         "scifa1_ctrl",
3142 };
3143
3144 static const char * const scifa2_groups[] = {
3145         "scifa2_data",
3146         "scifa2_clk_0",
3147         "scifa2_clk_1",
3148         "scifa2_ctrl",
3149 };
3150
3151 static const char * const scifa3_groups[] = {
3152         "scifa3_data_0",
3153         "scifa3_clk_0",
3154         "scifa3_ctrl_0",
3155         "scifa3_data_1",
3156         "scifa3_clk_1",
3157         "scifa3_ctrl_1",
3158 };
3159
3160 static const char * const scifa4_groups[] = {
3161         "scifa4_data_0",
3162         "scifa4_data_1",
3163         "scifa4_data_2",
3164         "scifa4_clk_0",
3165         "scifa4_clk_1",
3166 };
3167
3168 static const char * const scifa5_groups[] = {
3169         "scifa5_data_0",
3170         "scifa5_data_1",
3171         "scifa5_data_2",
3172         "scifa5_clk_0",
3173         "scifa5_clk_1",
3174 };
3175
3176 static const char * const scifa6_groups[] = {
3177         "scifa6_data",
3178         "scifa6_clk",
3179 };
3180
3181 static const char * const scifa7_groups[] = {
3182         "scifa7_data",
3183 };
3184
3185 static const char * const scifb_groups[] = {
3186         "scifb_data_0",
3187         "scifb_clk_0",
3188         "scifb_ctrl_0",
3189         "scifb_data_1",
3190         "scifb_clk_1",
3191         "scifb_ctrl_1",
3192 };
3193
3194 static const char * const sdhi0_groups[] = {
3195         "sdhi0_data1",
3196         "sdhi0_data4",
3197         "sdhi0_ctrl",
3198         "sdhi0_cd",
3199         "sdhi0_wp",
3200 };
3201
3202 static const char * const sdhi1_groups[] = {
3203         "sdhi1_data1",
3204         "sdhi1_data4",
3205         "sdhi1_ctrl",
3206         "sdhi1_cd",
3207         "sdhi1_wp",
3208 };
3209
3210 static const char * const sdhi2_groups[] = {
3211         "sdhi2_data1",
3212         "sdhi2_data4",
3213         "sdhi2_ctrl",
3214         "sdhi2_cd_0",
3215         "sdhi2_wp_0",
3216         "sdhi2_cd_1",
3217         "sdhi2_wp_1",
3218 };
3219
3220 static const char * const tpu0_groups[] = {
3221         "tpu0_to0",
3222         "tpu0_to1",
3223         "tpu0_to2_0",
3224         "tpu0_to2_1",
3225         "tpu0_to3",
3226 };
3227
3228 static const struct sh_pfc_function pinmux_functions[] = {
3229         SH_PFC_FUNCTION(bsc),
3230         SH_PFC_FUNCTION(ceu0),
3231         SH_PFC_FUNCTION(ceu1),
3232         SH_PFC_FUNCTION(fsia),
3233         SH_PFC_FUNCTION(fsib),
3234         SH_PFC_FUNCTION(gether),
3235         SH_PFC_FUNCTION(hdmi),
3236         SH_PFC_FUNCTION(intc),
3237         SH_PFC_FUNCTION(lcd0),
3238         SH_PFC_FUNCTION(lcd1),
3239         SH_PFC_FUNCTION(mmc0),
3240         SH_PFC_FUNCTION(scifa0),
3241         SH_PFC_FUNCTION(scifa1),
3242         SH_PFC_FUNCTION(scifa2),
3243         SH_PFC_FUNCTION(scifa3),
3244         SH_PFC_FUNCTION(scifa4),
3245         SH_PFC_FUNCTION(scifa5),
3246         SH_PFC_FUNCTION(scifa6),
3247         SH_PFC_FUNCTION(scifa7),
3248         SH_PFC_FUNCTION(scifb),
3249         SH_PFC_FUNCTION(sdhi0),
3250         SH_PFC_FUNCTION(sdhi1),
3251         SH_PFC_FUNCTION(sdhi2),
3252         SH_PFC_FUNCTION(tpu0),
3253 };
3254
3255 #undef PORTCR
3256 #define PORTCR(nr, reg)                                                 \
3257         {                                                               \
3258                 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {             \
3259                         _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),     \
3260                                 PORT##nr##_FN0, PORT##nr##_FN1,         \
3261                                 PORT##nr##_FN2, PORT##nr##_FN3,         \
3262                                 PORT##nr##_FN4, PORT##nr##_FN5,         \
3263                                 PORT##nr##_FN6, PORT##nr##_FN7 }        \
3264         }
3265
3266 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3267         PORTCR(0,       0xe6050000), /* PORT0CR */
3268         PORTCR(1,       0xe6050001), /* PORT1CR */
3269         PORTCR(2,       0xe6050002), /* PORT2CR */
3270         PORTCR(3,       0xe6050003), /* PORT3CR */
3271         PORTCR(4,       0xe6050004), /* PORT4CR */
3272         PORTCR(5,       0xe6050005), /* PORT5CR */
3273         PORTCR(6,       0xe6050006), /* PORT6CR */
3274         PORTCR(7,       0xe6050007), /* PORT7CR */
3275         PORTCR(8,       0xe6050008), /* PORT8CR */
3276         PORTCR(9,       0xe6050009), /* PORT9CR */
3277         PORTCR(10,      0xe605000a), /* PORT10CR */
3278         PORTCR(11,      0xe605000b), /* PORT11CR */
3279         PORTCR(12,      0xe605000c), /* PORT12CR */
3280         PORTCR(13,      0xe605000d), /* PORT13CR */
3281         PORTCR(14,      0xe605000e), /* PORT14CR */
3282         PORTCR(15,      0xe605000f), /* PORT15CR */
3283         PORTCR(16,      0xe6050010), /* PORT16CR */
3284         PORTCR(17,      0xe6050011), /* PORT17CR */
3285         PORTCR(18,      0xe6050012), /* PORT18CR */
3286         PORTCR(19,      0xe6050013), /* PORT19CR */
3287         PORTCR(20,      0xe6050014), /* PORT20CR */
3288         PORTCR(21,      0xe6050015), /* PORT21CR */
3289         PORTCR(22,      0xe6050016), /* PORT22CR */
3290         PORTCR(23,      0xe6050017), /* PORT23CR */
3291         PORTCR(24,      0xe6050018), /* PORT24CR */
3292         PORTCR(25,      0xe6050019), /* PORT25CR */
3293         PORTCR(26,      0xe605001a), /* PORT26CR */
3294         PORTCR(27,      0xe605001b), /* PORT27CR */
3295         PORTCR(28,      0xe605001c), /* PORT28CR */
3296         PORTCR(29,      0xe605001d), /* PORT29CR */
3297         PORTCR(30,      0xe605001e), /* PORT30CR */
3298         PORTCR(31,      0xe605001f), /* PORT31CR */
3299         PORTCR(32,      0xe6050020), /* PORT32CR */
3300         PORTCR(33,      0xe6050021), /* PORT33CR */
3301         PORTCR(34,      0xe6050022), /* PORT34CR */
3302         PORTCR(35,      0xe6050023), /* PORT35CR */
3303         PORTCR(36,      0xe6050024), /* PORT36CR */
3304         PORTCR(37,      0xe6050025), /* PORT37CR */
3305         PORTCR(38,      0xe6050026), /* PORT38CR */
3306         PORTCR(39,      0xe6050027), /* PORT39CR */
3307         PORTCR(40,      0xe6050028), /* PORT40CR */
3308         PORTCR(41,      0xe6050029), /* PORT41CR */
3309         PORTCR(42,      0xe605002a), /* PORT42CR */
3310         PORTCR(43,      0xe605002b), /* PORT43CR */
3311         PORTCR(44,      0xe605002c), /* PORT44CR */
3312         PORTCR(45,      0xe605002d), /* PORT45CR */
3313         PORTCR(46,      0xe605002e), /* PORT46CR */
3314         PORTCR(47,      0xe605002f), /* PORT47CR */
3315         PORTCR(48,      0xe6050030), /* PORT48CR */
3316         PORTCR(49,      0xe6050031), /* PORT49CR */
3317         PORTCR(50,      0xe6050032), /* PORT50CR */
3318         PORTCR(51,      0xe6050033), /* PORT51CR */
3319         PORTCR(52,      0xe6050034), /* PORT52CR */
3320         PORTCR(53,      0xe6050035), /* PORT53CR */
3321         PORTCR(54,      0xe6050036), /* PORT54CR */
3322         PORTCR(55,      0xe6050037), /* PORT55CR */
3323         PORTCR(56,      0xe6050038), /* PORT56CR */
3324         PORTCR(57,      0xe6050039), /* PORT57CR */
3325         PORTCR(58,      0xe605003a), /* PORT58CR */
3326         PORTCR(59,      0xe605003b), /* PORT59CR */
3327         PORTCR(60,      0xe605003c), /* PORT60CR */
3328         PORTCR(61,      0xe605003d), /* PORT61CR */
3329         PORTCR(62,      0xe605003e), /* PORT62CR */
3330         PORTCR(63,      0xe605003f), /* PORT63CR */
3331         PORTCR(64,      0xe6050040), /* PORT64CR */
3332         PORTCR(65,      0xe6050041), /* PORT65CR */
3333         PORTCR(66,      0xe6050042), /* PORT66CR */
3334         PORTCR(67,      0xe6050043), /* PORT67CR */
3335         PORTCR(68,      0xe6050044), /* PORT68CR */
3336         PORTCR(69,      0xe6050045), /* PORT69CR */
3337         PORTCR(70,      0xe6050046), /* PORT70CR */
3338         PORTCR(71,      0xe6050047), /* PORT71CR */
3339         PORTCR(72,      0xe6050048), /* PORT72CR */
3340         PORTCR(73,      0xe6050049), /* PORT73CR */
3341         PORTCR(74,      0xe605004a), /* PORT74CR */
3342         PORTCR(75,      0xe605004b), /* PORT75CR */
3343         PORTCR(76,      0xe605004c), /* PORT76CR */
3344         PORTCR(77,      0xe605004d), /* PORT77CR */
3345         PORTCR(78,      0xe605004e), /* PORT78CR */
3346         PORTCR(79,      0xe605004f), /* PORT79CR */
3347         PORTCR(80,      0xe6050050), /* PORT80CR */
3348         PORTCR(81,      0xe6050051), /* PORT81CR */
3349         PORTCR(82,      0xe6050052), /* PORT82CR */
3350         PORTCR(83,      0xe6050053), /* PORT83CR */
3351
3352         PORTCR(84,      0xe6051054), /* PORT84CR */
3353         PORTCR(85,      0xe6051055), /* PORT85CR */
3354         PORTCR(86,      0xe6051056), /* PORT86CR */
3355         PORTCR(87,      0xe6051057), /* PORT87CR */
3356         PORTCR(88,      0xe6051058), /* PORT88CR */
3357         PORTCR(89,      0xe6051059), /* PORT89CR */
3358         PORTCR(90,      0xe605105a), /* PORT90CR */
3359         PORTCR(91,      0xe605105b), /* PORT91CR */
3360         PORTCR(92,      0xe605105c), /* PORT92CR */
3361         PORTCR(93,      0xe605105d), /* PORT93CR */
3362         PORTCR(94,      0xe605105e), /* PORT94CR */
3363         PORTCR(95,      0xe605105f), /* PORT95CR */
3364         PORTCR(96,      0xe6051060), /* PORT96CR */
3365         PORTCR(97,      0xe6051061), /* PORT97CR */
3366         PORTCR(98,      0xe6051062), /* PORT98CR */
3367         PORTCR(99,      0xe6051063), /* PORT99CR */
3368         PORTCR(100,     0xe6051064), /* PORT100CR */
3369         PORTCR(101,     0xe6051065), /* PORT101CR */
3370         PORTCR(102,     0xe6051066), /* PORT102CR */
3371         PORTCR(103,     0xe6051067), /* PORT103CR */
3372         PORTCR(104,     0xe6051068), /* PORT104CR */
3373         PORTCR(105,     0xe6051069), /* PORT105CR */
3374         PORTCR(106,     0xe605106a), /* PORT106CR */
3375         PORTCR(107,     0xe605106b), /* PORT107CR */
3376         PORTCR(108,     0xe605106c), /* PORT108CR */
3377         PORTCR(109,     0xe605106d), /* PORT109CR */
3378         PORTCR(110,     0xe605106e), /* PORT110CR */
3379         PORTCR(111,     0xe605106f), /* PORT111CR */
3380         PORTCR(112,     0xe6051070), /* PORT112CR */
3381         PORTCR(113,     0xe6051071), /* PORT113CR */
3382         PORTCR(114,     0xe6051072), /* PORT114CR */
3383
3384         PORTCR(115,     0xe6052073), /* PORT115CR */
3385         PORTCR(116,     0xe6052074), /* PORT116CR */
3386         PORTCR(117,     0xe6052075), /* PORT117CR */
3387         PORTCR(118,     0xe6052076), /* PORT118CR */
3388         PORTCR(119,     0xe6052077), /* PORT119CR */
3389         PORTCR(120,     0xe6052078), /* PORT120CR */
3390         PORTCR(121,     0xe6052079), /* PORT121CR */
3391         PORTCR(122,     0xe605207a), /* PORT122CR */
3392         PORTCR(123,     0xe605207b), /* PORT123CR */
3393         PORTCR(124,     0xe605207c), /* PORT124CR */
3394         PORTCR(125,     0xe605207d), /* PORT125CR */
3395         PORTCR(126,     0xe605207e), /* PORT126CR */
3396         PORTCR(127,     0xe605207f), /* PORT127CR */
3397         PORTCR(128,     0xe6052080), /* PORT128CR */
3398         PORTCR(129,     0xe6052081), /* PORT129CR */
3399         PORTCR(130,     0xe6052082), /* PORT130CR */
3400         PORTCR(131,     0xe6052083), /* PORT131CR */
3401         PORTCR(132,     0xe6052084), /* PORT132CR */
3402         PORTCR(133,     0xe6052085), /* PORT133CR */
3403         PORTCR(134,     0xe6052086), /* PORT134CR */
3404         PORTCR(135,     0xe6052087), /* PORT135CR */
3405         PORTCR(136,     0xe6052088), /* PORT136CR */
3406         PORTCR(137,     0xe6052089), /* PORT137CR */
3407         PORTCR(138,     0xe605208a), /* PORT138CR */
3408         PORTCR(139,     0xe605208b), /* PORT139CR */
3409         PORTCR(140,     0xe605208c), /* PORT140CR */
3410         PORTCR(141,     0xe605208d), /* PORT141CR */
3411         PORTCR(142,     0xe605208e), /* PORT142CR */
3412         PORTCR(143,     0xe605208f), /* PORT143CR */
3413         PORTCR(144,     0xe6052090), /* PORT144CR */
3414         PORTCR(145,     0xe6052091), /* PORT145CR */
3415         PORTCR(146,     0xe6052092), /* PORT146CR */
3416         PORTCR(147,     0xe6052093), /* PORT147CR */
3417         PORTCR(148,     0xe6052094), /* PORT148CR */
3418         PORTCR(149,     0xe6052095), /* PORT149CR */
3419         PORTCR(150,     0xe6052096), /* PORT150CR */
3420         PORTCR(151,     0xe6052097), /* PORT151CR */
3421         PORTCR(152,     0xe6052098), /* PORT152CR */
3422         PORTCR(153,     0xe6052099), /* PORT153CR */
3423         PORTCR(154,     0xe605209a), /* PORT154CR */
3424         PORTCR(155,     0xe605209b), /* PORT155CR */
3425         PORTCR(156,     0xe605209c), /* PORT156CR */
3426         PORTCR(157,     0xe605209d), /* PORT157CR */
3427         PORTCR(158,     0xe605209e), /* PORT158CR */
3428         PORTCR(159,     0xe605209f), /* PORT159CR */
3429         PORTCR(160,     0xe60520a0), /* PORT160CR */
3430         PORTCR(161,     0xe60520a1), /* PORT161CR */
3431         PORTCR(162,     0xe60520a2), /* PORT162CR */
3432         PORTCR(163,     0xe60520a3), /* PORT163CR */
3433         PORTCR(164,     0xe60520a4), /* PORT164CR */
3434         PORTCR(165,     0xe60520a5), /* PORT165CR */
3435         PORTCR(166,     0xe60520a6), /* PORT166CR */
3436         PORTCR(167,     0xe60520a7), /* PORT167CR */
3437         PORTCR(168,     0xe60520a8), /* PORT168CR */
3438         PORTCR(169,     0xe60520a9), /* PORT169CR */
3439         PORTCR(170,     0xe60520aa), /* PORT170CR */
3440         PORTCR(171,     0xe60520ab), /* PORT171CR */
3441         PORTCR(172,     0xe60520ac), /* PORT172CR */
3442         PORTCR(173,     0xe60520ad), /* PORT173CR */
3443         PORTCR(174,     0xe60520ae), /* PORT174CR */
3444         PORTCR(175,     0xe60520af), /* PORT175CR */
3445         PORTCR(176,     0xe60520b0), /* PORT176CR */
3446         PORTCR(177,     0xe60520b1), /* PORT177CR */
3447         PORTCR(178,     0xe60520b2), /* PORT178CR */
3448         PORTCR(179,     0xe60520b3), /* PORT179CR */
3449         PORTCR(180,     0xe60520b4), /* PORT180CR */
3450         PORTCR(181,     0xe60520b5), /* PORT181CR */
3451         PORTCR(182,     0xe60520b6), /* PORT182CR */
3452         PORTCR(183,     0xe60520b7), /* PORT183CR */
3453         PORTCR(184,     0xe60520b8), /* PORT184CR */
3454         PORTCR(185,     0xe60520b9), /* PORT185CR */
3455         PORTCR(186,     0xe60520ba), /* PORT186CR */
3456         PORTCR(187,     0xe60520bb), /* PORT187CR */
3457         PORTCR(188,     0xe60520bc), /* PORT188CR */
3458         PORTCR(189,     0xe60520bd), /* PORT189CR */
3459         PORTCR(190,     0xe60520be), /* PORT190CR */
3460         PORTCR(191,     0xe60520bf), /* PORT191CR */
3461         PORTCR(192,     0xe60520c0), /* PORT192CR */
3462         PORTCR(193,     0xe60520c1), /* PORT193CR */
3463         PORTCR(194,     0xe60520c2), /* PORT194CR */
3464         PORTCR(195,     0xe60520c3), /* PORT195CR */
3465         PORTCR(196,     0xe60520c4), /* PORT196CR */
3466         PORTCR(197,     0xe60520c5), /* PORT197CR */
3467         PORTCR(198,     0xe60520c6), /* PORT198CR */
3468         PORTCR(199,     0xe60520c7), /* PORT199CR */
3469         PORTCR(200,     0xe60520c8), /* PORT200CR */
3470         PORTCR(201,     0xe60520c9), /* PORT201CR */
3471         PORTCR(202,     0xe60520ca), /* PORT202CR */
3472         PORTCR(203,     0xe60520cb), /* PORT203CR */
3473         PORTCR(204,     0xe60520cc), /* PORT204CR */
3474         PORTCR(205,     0xe60520cd), /* PORT205CR */
3475         PORTCR(206,     0xe60520ce), /* PORT206CR */
3476         PORTCR(207,     0xe60520cf), /* PORT207CR */
3477         PORTCR(208,     0xe60520d0), /* PORT208CR */
3478         PORTCR(209,     0xe60520d1), /* PORT209CR */
3479
3480         PORTCR(210,     0xe60530d2), /* PORT210CR */
3481         PORTCR(211,     0xe60530d3), /* PORT211CR */
3482
3483         { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
3484                         MSEL1CR_31_0,   MSEL1CR_31_1,
3485                         MSEL1CR_30_0,   MSEL1CR_30_1,
3486                         MSEL1CR_29_0,   MSEL1CR_29_1,
3487                         MSEL1CR_28_0,   MSEL1CR_28_1,
3488                         MSEL1CR_27_0,   MSEL1CR_27_1,
3489                         MSEL1CR_26_0,   MSEL1CR_26_1,
3490                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3491                         0, 0, 0, 0, 0, 0, 0, 0,
3492                         MSEL1CR_16_0,   MSEL1CR_16_1,
3493                         MSEL1CR_15_0,   MSEL1CR_15_1,
3494                         MSEL1CR_14_0,   MSEL1CR_14_1,
3495                         MSEL1CR_13_0,   MSEL1CR_13_1,
3496                         MSEL1CR_12_0,   MSEL1CR_12_1,
3497                         0, 0, 0, 0,
3498                         MSEL1CR_9_0,    MSEL1CR_9_1,
3499                         0, 0,
3500                         MSEL1CR_7_0,    MSEL1CR_7_1,
3501                         MSEL1CR_6_0,    MSEL1CR_6_1,
3502                         MSEL1CR_5_0,    MSEL1CR_5_1,
3503                         MSEL1CR_4_0,    MSEL1CR_4_1,
3504                         MSEL1CR_3_0,    MSEL1CR_3_1,
3505                         MSEL1CR_2_0,    MSEL1CR_2_1,
3506                         0, 0,
3507                         MSEL1CR_0_0,    MSEL1CR_0_1,
3508                 }
3509         },
3510         { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
3511                         0, 0, 0, 0, 0, 0, 0, 0,
3512                         0, 0, 0, 0, 0, 0, 0, 0,
3513                         0, 0, 0, 0, 0, 0, 0, 0,
3514                         0, 0, 0, 0, 0, 0, 0, 0,
3515                         MSEL3CR_15_0,   MSEL3CR_15_1,
3516                         0, 0, 0, 0, 0, 0, 0, 0,
3517                         0, 0, 0, 0, 0, 0, 0, 0,
3518                         MSEL3CR_6_0,    MSEL3CR_6_1,
3519                         0, 0, 0, 0, 0, 0, 0, 0,
3520                         0, 0, 0, 0,
3521                         }
3522         },
3523         { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
3524                         0, 0, 0, 0, 0, 0, 0, 0,
3525                         0, 0, 0, 0, 0, 0, 0, 0,
3526                         0, 0, 0, 0, 0, 0, 0, 0,
3527                         MSEL4CR_19_0,   MSEL4CR_19_1,
3528                         MSEL4CR_18_0,   MSEL4CR_18_1,
3529                         0, 0, 0, 0,
3530                         MSEL4CR_15_0,   MSEL4CR_15_1,
3531                         0, 0, 0, 0, 0, 0, 0, 0,
3532                         MSEL4CR_10_0,   MSEL4CR_10_1,
3533                         0, 0, 0, 0, 0, 0,
3534                         MSEL4CR_6_0,    MSEL4CR_6_1,
3535                         0, 0,
3536                         MSEL4CR_4_0,    MSEL4CR_4_1,
3537                         0, 0, 0, 0,
3538                         MSEL4CR_1_0,    MSEL4CR_1_1,
3539                         0, 0,
3540                 }
3541         },
3542         { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
3543                         MSEL5CR_31_0,   MSEL5CR_31_1,
3544                         MSEL5CR_30_0,   MSEL5CR_30_1,
3545                         MSEL5CR_29_0,   MSEL5CR_29_1,
3546                         0, 0,
3547                         MSEL5CR_27_0,   MSEL5CR_27_1,
3548                         0, 0,
3549                         MSEL5CR_25_0,   MSEL5CR_25_1,
3550                         0, 0,
3551                         MSEL5CR_23_0,   MSEL5CR_23_1,
3552                         0, 0,
3553                         MSEL5CR_21_0,   MSEL5CR_21_1,
3554                         0, 0,
3555                         MSEL5CR_19_0,   MSEL5CR_19_1,
3556                         0, 0,
3557                         MSEL5CR_17_0,   MSEL5CR_17_1,
3558                         0, 0,
3559                         MSEL5CR_15_0,   MSEL5CR_15_1,
3560                         MSEL5CR_14_0,   MSEL5CR_14_1,
3561                         MSEL5CR_13_0,   MSEL5CR_13_1,
3562                         MSEL5CR_12_0,   MSEL5CR_12_1,
3563                         MSEL5CR_11_0,   MSEL5CR_11_1,
3564                         MSEL5CR_10_0,   MSEL5CR_10_1,
3565                         0, 0,
3566                         MSEL5CR_8_0,    MSEL5CR_8_1,
3567                         MSEL5CR_7_0,    MSEL5CR_7_1,
3568                         MSEL5CR_6_0,    MSEL5CR_6_1,
3569                         MSEL5CR_5_0,    MSEL5CR_5_1,
3570                         MSEL5CR_4_0,    MSEL5CR_4_1,
3571                         MSEL5CR_3_0,    MSEL5CR_3_1,
3572                         MSEL5CR_2_0,    MSEL5CR_2_1,
3573                         0, 0,
3574                         MSEL5CR_0_0,    MSEL5CR_0_1,
3575                 }
3576         },
3577         { },
3578 };
3579
3580 static const struct pinmux_data_reg pinmux_data_regs[] = {
3581         { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
3582                 PORT31_DATA,    PORT30_DATA,    PORT29_DATA,    PORT28_DATA,
3583                 PORT27_DATA,    PORT26_DATA,    PORT25_DATA,    PORT24_DATA,
3584                 PORT23_DATA,    PORT22_DATA,    PORT21_DATA,    PORT20_DATA,
3585                 PORT19_DATA,    PORT18_DATA,    PORT17_DATA,    PORT16_DATA,
3586                 PORT15_DATA,    PORT14_DATA,    PORT13_DATA,    PORT12_DATA,
3587                 PORT11_DATA,    PORT10_DATA,    PORT9_DATA,     PORT8_DATA,
3588                 PORT7_DATA,     PORT6_DATA,     PORT5_DATA,     PORT4_DATA,
3589                 PORT3_DATA,     PORT2_DATA,     PORT1_DATA,     PORT0_DATA }
3590         },
3591         { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
3592                 PORT63_DATA,    PORT62_DATA,    PORT61_DATA,    PORT60_DATA,
3593                 PORT59_DATA,    PORT58_DATA,    PORT57_DATA,    PORT56_DATA,
3594                 PORT55_DATA,    PORT54_DATA,    PORT53_DATA,    PORT52_DATA,
3595                 PORT51_DATA,    PORT50_DATA,    PORT49_DATA,    PORT48_DATA,
3596                 PORT47_DATA,    PORT46_DATA,    PORT45_DATA,    PORT44_DATA,
3597                 PORT43_DATA,    PORT42_DATA,    PORT41_DATA,    PORT40_DATA,
3598                 PORT39_DATA,    PORT38_DATA,    PORT37_DATA,    PORT36_DATA,
3599                 PORT35_DATA,    PORT34_DATA,    PORT33_DATA,    PORT32_DATA }
3600         },
3601         { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
3602                 0, 0, 0, 0,
3603                 0, 0, 0, 0,
3604                 0, 0, 0, 0,
3605                 PORT83_DATA,    PORT82_DATA,    PORT81_DATA,    PORT80_DATA,
3606                 PORT79_DATA,    PORT78_DATA,    PORT77_DATA,    PORT76_DATA,
3607                 PORT75_DATA,    PORT74_DATA,    PORT73_DATA,    PORT72_DATA,
3608                 PORT71_DATA,    PORT70_DATA,    PORT69_DATA,    PORT68_DATA,
3609                 PORT67_DATA,    PORT66_DATA,    PORT65_DATA,    PORT64_DATA }
3610         },
3611         { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
3612                 PORT95_DATA,    PORT94_DATA,    PORT93_DATA,    PORT92_DATA,
3613                 PORT91_DATA,    PORT90_DATA,    PORT89_DATA,    PORT88_DATA,
3614                 PORT87_DATA,    PORT86_DATA,    PORT85_DATA,    PORT84_DATA,
3615                 0, 0, 0, 0,
3616                 0, 0, 0, 0,
3617                 0, 0, 0, 0,
3618                 0, 0, 0, 0,
3619                 0, 0, 0, 0 }
3620         },
3621         { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
3622                 0, 0, 0, 0,
3623                 0, 0, 0, 0,
3624                 0, 0, 0, 0,
3625                 0,              PORT114_DATA,   PORT113_DATA,   PORT112_DATA,
3626                 PORT111_DATA,   PORT110_DATA,   PORT109_DATA,   PORT108_DATA,
3627                 PORT107_DATA,   PORT106_DATA,   PORT105_DATA,   PORT104_DATA,
3628                 PORT103_DATA,   PORT102_DATA,   PORT101_DATA,   PORT100_DATA,
3629                 PORT99_DATA,    PORT98_DATA,    PORT97_DATA,    PORT96_DATA }
3630         },
3631         { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
3632                 PORT127_DATA,   PORT126_DATA,   PORT125_DATA,   PORT124_DATA,
3633                 PORT123_DATA,   PORT122_DATA,   PORT121_DATA,   PORT120_DATA,
3634                 PORT119_DATA,   PORT118_DATA,   PORT117_DATA,   PORT116_DATA,
3635                 PORT115_DATA,   0, 0, 0,
3636                 0, 0, 0, 0,
3637                 0, 0, 0, 0,
3638                 0, 0, 0, 0,
3639                 0, 0, 0, 0 }
3640         },
3641         { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
3642                 PORT159_DATA,   PORT158_DATA,   PORT157_DATA,   PORT156_DATA,
3643                 PORT155_DATA,   PORT154_DATA,   PORT153_DATA,   PORT152_DATA,
3644                 PORT151_DATA,   PORT150_DATA,   PORT149_DATA,   PORT148_DATA,
3645                 PORT147_DATA,   PORT146_DATA,   PORT145_DATA,   PORT144_DATA,
3646                 PORT143_DATA,   PORT142_DATA,   PORT141_DATA,   PORT140_DATA,
3647                 PORT139_DATA,   PORT138_DATA,   PORT137_DATA,   PORT136_DATA,
3648                 PORT135_DATA,   PORT134_DATA,   PORT133_DATA,   PORT132_DATA,
3649                 PORT131_DATA,   PORT130_DATA,   PORT129_DATA,   PORT128_DATA }
3650         },
3651         { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
3652                 PORT191_DATA,   PORT190_DATA,   PORT189_DATA,   PORT188_DATA,
3653                 PORT187_DATA,   PORT186_DATA,   PORT185_DATA,   PORT184_DATA,
3654                 PORT183_DATA,   PORT182_DATA,   PORT181_DATA,   PORT180_DATA,
3655                 PORT179_DATA,   PORT178_DATA,   PORT177_DATA,   PORT176_DATA,
3656                 PORT175_DATA,   PORT174_DATA,   PORT173_DATA,   PORT172_DATA,
3657                 PORT171_DATA,   PORT170_DATA,   PORT169_DATA,   PORT168_DATA,
3658                 PORT167_DATA,   PORT166_DATA,   PORT165_DATA,   PORT164_DATA,
3659                 PORT163_DATA,   PORT162_DATA,   PORT161_DATA,   PORT160_DATA }
3660         },
3661         { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
3662                 0, 0, 0, 0,
3663                 0, 0, 0, 0,
3664                 0, 0, 0, 0,
3665                 0, 0,                           PORT209_DATA,   PORT208_DATA,
3666                 PORT207_DATA,   PORT206_DATA,   PORT205_DATA,   PORT204_DATA,
3667                 PORT203_DATA,   PORT202_DATA,   PORT201_DATA,   PORT200_DATA,
3668                 PORT199_DATA,   PORT198_DATA,   PORT197_DATA,   PORT196_DATA,
3669                 PORT195_DATA,   PORT194_DATA,   PORT193_DATA,   PORT192_DATA }
3670         },
3671         { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
3672                 0, 0, 0, 0,
3673                 0, 0, 0, 0,
3674                 0, 0, 0, 0,
3675                 PORT211_DATA,   PORT210_DATA, 0, 0,
3676                 0, 0, 0, 0,
3677                 0, 0, 0, 0,
3678                 0, 0, 0, 0,
3679                 0, 0, 0, 0 }
3680         },
3681         { },
3682 };
3683
3684 static const struct pinmux_irq pinmux_irqs[] = {
3685         PINMUX_IRQ(irq_pin(0), 2,   13),        /* IRQ0A */
3686         PINMUX_IRQ(irq_pin(1), 20),             /* IRQ1A */
3687         PINMUX_IRQ(irq_pin(2), 11,  12),        /* IRQ2A */
3688         PINMUX_IRQ(irq_pin(3), 10,  14),        /* IRQ3A */
3689         PINMUX_IRQ(irq_pin(4), 15,  172),       /* IRQ4A */
3690         PINMUX_IRQ(irq_pin(5), 0,   1),         /* IRQ5A */
3691         PINMUX_IRQ(irq_pin(6), 121, 173),       /* IRQ6A */
3692         PINMUX_IRQ(irq_pin(7), 120, 209),       /* IRQ7A */
3693         PINMUX_IRQ(irq_pin(8), 119),            /* IRQ8A */
3694         PINMUX_IRQ(irq_pin(9), 118, 210),       /* IRQ9A */
3695         PINMUX_IRQ(irq_pin(10), 19),            /* IRQ10A */
3696         PINMUX_IRQ(irq_pin(11), 104),           /* IRQ11A */
3697         PINMUX_IRQ(irq_pin(12), 42,  97),       /* IRQ12A */
3698         PINMUX_IRQ(irq_pin(13), 64,  98),       /* IRQ13A */
3699         PINMUX_IRQ(irq_pin(14), 63,  99),       /* IRQ14A */
3700         PINMUX_IRQ(irq_pin(15), 62,  100),      /* IRQ15A */
3701         PINMUX_IRQ(irq_pin(16), 68,  211),      /* IRQ16A */
3702         PINMUX_IRQ(irq_pin(17), 69),            /* IRQ17A */
3703         PINMUX_IRQ(irq_pin(18), 70),            /* IRQ18A */
3704         PINMUX_IRQ(irq_pin(19), 71),            /* IRQ19A */
3705         PINMUX_IRQ(irq_pin(20), 67),            /* IRQ20A */
3706         PINMUX_IRQ(irq_pin(21), 202),           /* IRQ21A */
3707         PINMUX_IRQ(irq_pin(22), 95),            /* IRQ22A */
3708         PINMUX_IRQ(irq_pin(23), 96),            /* IRQ23A */
3709         PINMUX_IRQ(irq_pin(24), 180),           /* IRQ24A */
3710         PINMUX_IRQ(irq_pin(25), 38),            /* IRQ25A */
3711         PINMUX_IRQ(irq_pin(26), 58,  81),       /* IRQ26A */
3712         PINMUX_IRQ(irq_pin(27), 57,  168),      /* IRQ27A */
3713         PINMUX_IRQ(irq_pin(28), 56,  169),      /* IRQ28A */
3714         PINMUX_IRQ(irq_pin(29), 50,  170),      /* IRQ29A */
3715         PINMUX_IRQ(irq_pin(30), 49,  171),      /* IRQ30A */
3716         PINMUX_IRQ(irq_pin(31), 41,  167),      /* IRQ31A */
3717 };
3718
3719 #define PORTnCR_PULMD_OFF       (0 << 6)
3720 #define PORTnCR_PULMD_DOWN      (2 << 6)
3721 #define PORTnCR_PULMD_UP        (3 << 6)
3722 #define PORTnCR_PULMD_MASK      (3 << 6)
3723
3724 struct r8a7740_portcr_group {
3725         unsigned int end_pin;
3726         unsigned int offset;
3727 };
3728
3729 static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
3730         { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
3731 };
3732
3733 static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
3734 {
3735         unsigned int i;
3736
3737         for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
3738                 const struct r8a7740_portcr_group *group =
3739                         &r8a7740_portcr_offsets[i];
3740
3741                 if (i <= group->end_pin)
3742                         return pfc->window->virt + group->offset + pin;
3743         }
3744
3745         return NULL;
3746 }
3747
3748 static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3749 {
3750         void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3751         u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3752
3753         switch (value) {
3754         case PORTnCR_PULMD_UP:
3755                 return PIN_CONFIG_BIAS_PULL_UP;
3756         case PORTnCR_PULMD_DOWN:
3757                 return PIN_CONFIG_BIAS_PULL_DOWN;
3758         case PORTnCR_PULMD_OFF:
3759         default:
3760                 return PIN_CONFIG_BIAS_DISABLE;
3761         }
3762 }
3763
3764 static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3765                                    unsigned int bias)
3766 {
3767         void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3768         u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3769
3770         switch (bias) {
3771         case PIN_CONFIG_BIAS_PULL_UP:
3772                 value |= PORTnCR_PULMD_UP;
3773                 break;
3774         case PIN_CONFIG_BIAS_PULL_DOWN:
3775                 value |= PORTnCR_PULMD_DOWN;
3776                 break;
3777         }
3778
3779         iowrite8(value, addr);
3780 }
3781
3782 static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
3783         .get_bias = r8a7740_pinmux_get_bias,
3784         .set_bias = r8a7740_pinmux_set_bias,
3785 };
3786
3787 const struct sh_pfc_soc_info r8a7740_pinmux_info = {
3788         .name           = "r8a7740_pfc",
3789         .ops            = &r8a7740_pinmux_ops,
3790
3791         .input          = { PINMUX_INPUT_BEGIN,
3792                             PINMUX_INPUT_END },
3793         .output         = { PINMUX_OUTPUT_BEGIN,
3794                             PINMUX_OUTPUT_END },
3795         .function       = { PINMUX_FUNCTION_BEGIN,
3796                             PINMUX_FUNCTION_END },
3797
3798         .pins           = pinmux_pins,
3799         .nr_pins        = ARRAY_SIZE(pinmux_pins),
3800         .groups         = pinmux_groups,
3801         .nr_groups      = ARRAY_SIZE(pinmux_groups),
3802         .functions      = pinmux_functions,
3803         .nr_functions   = ARRAY_SIZE(pinmux_functions),
3804
3805         .cfg_regs       = pinmux_config_regs,
3806         .data_regs      = pinmux_data_regs,
3807
3808         .gpio_data      = pinmux_data,
3809         .gpio_data_size = ARRAY_SIZE(pinmux_data),
3810
3811         .gpio_irq       = pinmux_irqs,
3812         .gpio_irq_size  = ARRAY_SIZE(pinmux_irqs),
3813 };