drivers/pinctrl/sh-pfc/pfc-r8a7779.c

   1 /*
   2  * r8a7779 processor support - PFC hardware block
   3  *
   4  * Copyright (C) 2011  Renesas Solutions Corp.
   5  * Copyright (C) 2011  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <mach/r8a7779.h>
  23
  24 #include "sh_pfc.h"
  25
  26 #define CPU_32_PORT6(fn, pfx, sfx)                              \
  27         PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),       \
  28         PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),       \
  29         PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx),       \
  30         PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),       \
  31         PORT_1(fn, pfx##8, sfx)
  32
  33 #define CPU_ALL_PORT(fn, pfx, sfx)                              \
  34         PORT_32(fn, pfx##_0_, sfx),                             \
  35         PORT_32(fn, pfx##_1_, sfx),                             \
  36         PORT_32(fn, pfx##_2_, sfx),                             \
  37         PORT_32(fn, pfx##_3_, sfx),                             \
  38         PORT_32(fn, pfx##_4_, sfx),                             \
  39         PORT_32(fn, pfx##_5_, sfx),                             \
  40         CPU_32_PORT6(fn, pfx##_6_, sfx)
  41
  42 #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
  43 #define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,    \
  44                                        GP##pfx##_IN, GP##pfx##_OUT)
  45
  46 #define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
  47 #define _GP_INDT(pfx, sfx) GP##pfx##_DATA
  48
  49 #define GP_ALL(str)     CPU_ALL_PORT(_PORT_ALL, GP, str)
  50 #define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, , unused)
  51 #define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, , unused)
  52
  53 #define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused)
  54 #define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused)
  55
  56 #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
  57 #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
  58                                                           FN_##ipsr, FN_##fn)
  59
  60 enum {
  61         PINMUX_RESERVED = 0,
  62
  63         PINMUX_DATA_BEGIN,
  64         GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
  65         PINMUX_DATA_END,
  66
  67         PINMUX_INPUT_BEGIN,
  68         GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */
  69         PINMUX_INPUT_END,
  70
  71         PINMUX_OUTPUT_BEGIN,
  72         GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */
  73         PINMUX_OUTPUT_END,
  74
  75         PINMUX_FUNCTION_BEGIN,
  76         GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
  77
  78         /* GPSR0 */
  79         FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
  80         FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
  81         FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
  82         FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
  83         FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
  84         FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
  85         FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
  86         FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
  87
  88         /* GPSR1 */
  89         FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
  90         FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
  91         FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
  92         FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
  93         FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
  94         FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
  95         FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
  96         FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
  97
  98         /* GPSR2 */
  99         FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
 100         FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
 101         FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
 102         FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
 103         FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
 104         FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
 105         FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
 106         FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
 107
 108         /* GPSR3 */
 109         FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
 110         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
 111         FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
 112         FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
 113         FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
 114         FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
 115         FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
 116         FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
 117
 118         /* GPSR4 */
 119         FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
 120         FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
 121         FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
 122         FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
 123         FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
 124         FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
 125         FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
 126         FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
 127
 128         /* GPSR5 */
 129         FN_A1, FN_A2, FN_A3, FN_A4,
 130         FN_A5, FN_A6, FN_A7, FN_A8,
 131         FN_A9, FN_A10, FN_A11, FN_A12,
 132         FN_A13, FN_A14, FN_A15, FN_A16,
 133         FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
 134         FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
 135         FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
 136         FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
 137
 138         /* GPSR6 */
 139         FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
 140         FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
 141         FN_IP3_20,
 142
 143         /* IPSR0 */
 144         FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
 145         FN_HRTS1, FN_RX4_C,
 146         FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
 147         FN_CS0, FN_HSPI_CS2_B,
 148         FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
 149         FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
 150         FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
 151         FN_CTS0_B,
 152         FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
 153         FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
 154         FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
 155         FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
 156         FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
 157         FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
 158         FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
 159         FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
 160         FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
 161         FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
 162         FN_SCIF_CLK, FN_TCLK0_C,
 163
 164         /* IPSR1 */
 165         FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
 166         FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
 167         FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
 168         FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
 169         FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
 170         FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
 171         FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
 172         FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
 173         FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
 174         FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
 175         FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
 176         FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
 177         FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
 178         FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
 179         FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
 180         FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
 181
 182         /* IPSR2 */
 183         FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
 184         FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
 185         FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
 186         FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
 187         FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
 188         FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
 189         FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
 190         FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
 191         FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
 192         FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
 193         FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
 194         FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
 195         FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
 196         FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
 197         FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
 198         FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
 199         FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
 200         FN_DREQ1, FN_SCL2, FN_AUDATA2,
 201
 202         /* IPSR3 */
 203         FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
 204         FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
 205         FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
 206         FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
 207         FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
 208         FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
 209         FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
 210         FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
 211         FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
 212         FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
 213         FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
 214         FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
 215         FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
 216         FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
 217         FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
 218         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
 219         FN_TX2_C, FN_SCL2_C, FN_REMOCON,
 220
 221         /* IPSR4 */
 222         FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
 223         FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
 224         FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
 225         FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
 226         FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
 227         FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
 228         FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
 229         FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
 230         FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
 231         FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
 232         FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
 233         FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
 234         FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
 235         FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
 236         FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
 237         FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
 238         FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
 239         FN_SCK0_D,
 240
 241         /* IPSR5 */
 242         FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
 243         FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
 244         FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
 245         FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
 246         FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
 247         FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
 248         FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
 249         FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
 250         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
 251         FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
 252         FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
 253         FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
 254         FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
 255         FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
 256         FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
 257         FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
 258         FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
 259         FN_CAN_DEBUGOUT0, FN_MOUT0,
 260
 261         /* IPSR6 */
 262         FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
 263         FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
 264         FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
 265         FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
 266         FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
 267         FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
 268         FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
 269         FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
 270         FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
 271         FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
 272         FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
 273         FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
 274         FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
 275
 276         /* IPSR7 */
 277         FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
 278         FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
 279         FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
 280         FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
 281         FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
 282         FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
 283         FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
 284         FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
 285         FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
 286         FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
 287         FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
 288         FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
 289         FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
 290         FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
 291
 292         /* IPSR8 */
 293         FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
 294         FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
 295         FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
 296         FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
 297         FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
 298         FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
 299         FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
 300         FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
 301         FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
 302         FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
 303         FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
 304         FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
 305         FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
 306         FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
 307         FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
 308         FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
 309
 310         /* IPSR9 */
 311         FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
 312         FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
 313         FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
 314         FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
 315         FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
 316         FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
 317         FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
 318         FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
 319         FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
 320         FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
 321         FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
 322         FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
 323         FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
 324         FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
 325
 326         /* IPSR10 */
 327         FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
 328         FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
 329         FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
 330         FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
 331         FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
 332         FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
 333         FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
 334         FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
 335         FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
 336         FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
 337         FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
 338         FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
 339         FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
 340         FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
 341         FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
 342         FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
 343
 344         /* IPSR11 */
 345         FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
 346         FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
 347         FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
 348         FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
 349         FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
 350         FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
 351         FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
 352         FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
 353         FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
 354         FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
 355         FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
 356         FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
 357         FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
 358         FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
 359
 360         /* IPSR12 */
 361         FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
 362         FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
 363         FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
 364         FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
 365         FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
 366         FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
 367         FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
 368         FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
 369         FN_GPS_MAG, FN_FCE, FN_SCK4_B,
 370
 371         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
 372         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 373         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
 374         FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
 375         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
 376         FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
 377         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
 378         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 379         FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
 380         FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
 381         FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
 382         FN_SEL_VI0_0, FN_SEL_VI0_1,
 383         FN_SEL_SD2_0, FN_SEL_SD2_1,
 384         FN_SEL_INT3_0, FN_SEL_INT3_1,
 385         FN_SEL_INT2_0, FN_SEL_INT2_1,
 386         FN_SEL_INT1_0, FN_SEL_INT1_1,
 387         FN_SEL_INT0_0, FN_SEL_INT0_1,
 388         FN_SEL_IE_0, FN_SEL_IE_1,
 389         FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
 390         FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
 391         FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
 392
 393         FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
 394         FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
 395         FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
 396         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
 397         FN_SEL_CAN0_0, FN_SEL_CAN0_1,
 398         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 399         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
 400         FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
 401         FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
 402         FN_SEL_ADI_0, FN_SEL_ADI_1,
 403         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 404         FN_SEL_SIM_0, FN_SEL_SIM_1,
 405         FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
 406         FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
 407         FN_SEL_I2C3_0, FN_SEL_I2C3_1,
 408         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 409         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
 410         PINMUX_FUNCTION_END,
 411
 412         PINMUX_MARK_BEGIN,
 413         AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
 414         A19_MARK,
 415
 416         RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
 417         HRTS1_MARK, RX4_C_MARK,
 418         CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
 419         CS0_MARK, HSPI_CS2_B_MARK,
 420         CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
 421         A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
 422         HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
 423         A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
 424         HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
 425         A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
 426         A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
 427         A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
 428         A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
 429         A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
 430         BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
 431         ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
 432         USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
 433         SCIF_CLK_MARK, TCLK0_C_MARK,
 434
 435         EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
 436         FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
 437         EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
 438         ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
 439         FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
 440         HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
 441         EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
 442         ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
 443         TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
 444         SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
 445         VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
 446         SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
 447         MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
 448         PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
 449         SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
 450         CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
 451
 452         HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
 453         SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
 454         CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
 455         MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
 456         SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
 457         CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
 458         STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
 459         SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
 460         RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
 461         CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
 462         CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
 463         GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
 464         LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
 465         AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
 466         DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
 467         DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
 468         DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
 469         DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
 470
 471         DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
 472         AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
 473         LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
 474         LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
 475         LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
 476         SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
 477         LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
 478         AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
 479         DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
 480         DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
 481         DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 482         TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
 483         DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
 484         SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
 485         QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
 486         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
 487         TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
 488
 489         DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
 490         DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
 491         DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
 492         VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
 493         AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
 494         PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
 495         CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
 496         VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
 497         VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
 498         VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
 499         SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
 500         DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
 501         SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
 502         VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
 503         VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
 504         VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
 505         VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
 506         SCK0_D_MARK,
 507
 508         DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
 509         RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
 510         DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
 511         DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
 512         DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
 513         HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
 514         SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
 515         VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
 516         VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
 517         TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
 518         VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
 519         GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
 520         QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
 521         GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
 522         RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
 523         VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
 524         GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
 525         USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
 526
 527         SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
 528         CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
 529         MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
 530         SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
 531         CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
 532         SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
 533         SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
 534         CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
 535         SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
 536         ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
 537         SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
 538         SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
 539         SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
 540
 541         SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
 542         SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
 543         SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
 544         HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
 545         SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
 546         IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
 547         VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
 548         ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
 549         TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
 550         RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
 551         SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
 552         TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
 553         RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
 554         RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
 555
 556         HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
 557         CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
 558         CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
 559         AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
 560         CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
 561         CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
 562         CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
 563         CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
 564         AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
 565         CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
 566         PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
 567         VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
 568         MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
 569         VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
 570         MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
 571         RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
 572
 573         VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
 574         VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
 575         VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
 576         MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
 577         VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
 578         MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
 579         MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
 580         IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
 581         IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
 582         MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
 583         ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
 584         VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
 585         VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
 586         VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
 587         VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
 588
 589         VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
 590         ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
 591         DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
 592         VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
 593         ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
 594         IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
 595         SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
 596         TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
 597         HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
 598         VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
 599         TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
 600         ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
 601         TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
 602         VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
 603         PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
 604         SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
 605
 606         VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
 607         ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
 608         SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
 609         SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
 610         VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
 611         ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
 612         SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
 613         VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
 614         HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
 615         MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
 616         SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
 617         VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK,
 618         DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
 619         VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
 620         DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
 621
 622         VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
 623         SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
 624         SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
 625         VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
 626         SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
 627         GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
 628         VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
 629         RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
 630         GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
 631         PINMUX_MARK_END,
 632 };
 633
 634 static const pinmux_enum_t pinmux_data[] = {
 635         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 636
 637         PINMUX_DATA(AVS1_MARK, FN_AVS1),
 638         PINMUX_DATA(AVS1_MARK, FN_AVS1),
 639         PINMUX_DATA(A17_MARK, FN_A17),
 640         PINMUX_DATA(A18_MARK, FN_A18),
 641         PINMUX_DATA(A19_MARK, FN_A19),
 642
 643         PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
 644         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
 645         PINMUX_IPSR_DATA(IP0_2_0, PWM1),
 646         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
 647         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
 648         PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2),
 649         PINMUX_IPSR_DATA(IP0_5_3, BS),
 650         PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
 651         PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
 652         PINMUX_IPSR_DATA(IP0_5_3, FD2),
 653         PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
 654         PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
 655         PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0),
 656         PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
 657         PINMUX_IPSR_DATA(IP0_7_6, A0),
 658         PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
 659         PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3),
 660         PINMUX_IPSR_DATA(IP0_7_6, FD3),
 661         PINMUX_IPSR_DATA(IP0_9_8, A20),
 662         PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
 663         PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
 664         PINMUX_IPSR_DATA(IP0_11_10, A21),
 665         PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3),
 666         PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
 667         PINMUX_IPSR_DATA(IP0_13_12, A22),
 668         PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3),
 669         PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
 670         PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
 671         PINMUX_IPSR_DATA(IP0_15_14, A23),
 672         PINMUX_IPSR_DATA(IP0_15_14, FCLE),
 673         PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
 674         PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
 675         PINMUX_IPSR_DATA(IP0_18_16, A24),
 676         PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
 677         PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
 678         PINMUX_IPSR_DATA(IP0_18_16, FD4),
 679         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
 680         PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
 681         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
 682         PINMUX_IPSR_DATA(IP0_22_19, A25),
 683         PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
 684         PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
 685         PINMUX_IPSR_DATA(IP0_22_19, FD5),
 686         PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
 687         PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
 688         PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
 689         PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
 690         PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1),
 691         PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
 692         PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
 693         PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
 694         PINMUX_IPSR_DATA(IP0_25, CS0),
 695         PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
 696         PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
 697         PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
 698         PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
 699         PINMUX_IPSR_DATA(IP0_30_28, RD_WR),
 700         PINMUX_IPSR_DATA(IP0_30_28, FWE),
 701         PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
 702         PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
 703         PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0),
 704         PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2),
 705
 706         PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
 707         PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
 708         PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
 709         PINMUX_IPSR_DATA(IP1_1_0, FD6),
 710         PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
 711         PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7),
 712         PINMUX_IPSR_DATA(IP1_3_2, FD7),
 713         PINMUX_IPSR_DATA(IP1_6_4, EX_CS2),
 714         PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK),
 715         PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK),
 716         PINMUX_IPSR_DATA(IP1_6_4, FALE),
 717         PINMUX_IPSR_DATA(IP1_6_4, ATACS00),
 718         PINMUX_IPSR_DATA(IP1_10_7, EX_CS3),
 719         PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD),
 720         PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD),
 721         PINMUX_IPSR_DATA(IP1_10_7, FRE),
 722         PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
 723         PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
 724         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1),
 725         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0),
 726         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
 727         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
 728         PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
 729         PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
 730         PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
 731         PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
 732         PINMUX_IPSR_DATA(IP1_14_11, FD0),
 733         PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
 734         PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
 735         PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1),
 736         PINMUX_IPSR_DATA(IP1_14_11, HTX1),
 737         PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
 738         PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
 739         PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
 740         PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
 741         PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
 742         PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
 743         PINMUX_IPSR_DATA(IP1_18_15, FD1),
 744         PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
 745         PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
 746         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0),
 747         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4),
 748         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1),
 749         PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0),
 750         PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
 751         PINMUX_IPSR_DATA(IP1_20_19, PWM2),
 752         PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0),
 753         PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
 754         PINMUX_IPSR_DATA(IP1_22_21, PWM3),
 755         PINMUX_IPSR_DATA(IP1_22_21, TX4),
 756         PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
 757         PINMUX_IPSR_DATA(IP1_24_23, PWM4),
 758         PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0),
 759         PINMUX_IPSR_DATA(IP1_28_25, HTX0),
 760         PINMUX_IPSR_DATA(IP1_28_25, TX1),
 761         PINMUX_IPSR_DATA(IP1_28_25, SDATA),
 762         PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2),
 763         PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
 764         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
 765         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
 766         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18),
 767         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
 768         PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
 769
 770         PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0),
 771         PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0),
 772         PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
 773         PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
 774         PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
 775         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
 776         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
 777         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
 778         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
 779         PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
 780         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0),
 781         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0),
 782         PINMUX_IPSR_DATA(IP2_7_4, MTS),
 783         PINMUX_IPSR_DATA(IP2_7_4, PWM5),
 784         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2),
 785         PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
 786         PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
 787         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
 788         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
 789         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
 790         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
 791         PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
 792         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0),
 793         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0),
 794         PINMUX_IPSR_DATA(IP2_11_8, STM),
 795         PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
 796         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2),
 797         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
 798         PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
 799         PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1),
 800         PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
 801         PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0),
 802         PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
 803         PINMUX_IPSR_DATA(IP2_15_12, MDATA),
 804         PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
 805         PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
 806         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1),
 807         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9),
 808         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17),
 809         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25),
 810         PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
 811         PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
 812         PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
 813         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0),
 814         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
 815         PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
 816         PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
 817         PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
 818         PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
 819         PINMUX_IPSR_DATA(IP2_21_19, DACK0),
 820         PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
 821         PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
 822         PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
 823         PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2),
 824         PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
 825         PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
 826         PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
 827         PINMUX_IPSR_DATA(IP2_23, LCDOUT3),
 828         PINMUX_IPSR_DATA(IP2_24, DU0_DR4),
 829         PINMUX_IPSR_DATA(IP2_24, LCDOUT4),
 830         PINMUX_IPSR_DATA(IP2_25, DU0_DR5),
 831         PINMUX_IPSR_DATA(IP2_25, LCDOUT5),
 832         PINMUX_IPSR_DATA(IP2_26, DU0_DR6),
 833         PINMUX_IPSR_DATA(IP2_26, LCDOUT6),
 834         PINMUX_IPSR_DATA(IP2_27, DU0_DR7),
 835         PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
 836         PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
 837         PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
 838         PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0),
 839         PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0),
 840         PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
 841
 842         PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
 843         PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
 844         PINMUX_IPSR_DATA(IP3_2_0, DACK1),
 845         PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0),
 846         PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
 847         PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
 848         PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
 849         PINMUX_IPSR_DATA(IP3_4, DU0_DG3),
 850         PINMUX_IPSR_DATA(IP3_4, LCDOUT11),
 851         PINMUX_IPSR_DATA(IP3_5, DU0_DG4),
 852         PINMUX_IPSR_DATA(IP3_5, LCDOUT12),
 853         PINMUX_IPSR_DATA(IP3_6, DU0_DG5),
 854         PINMUX_IPSR_DATA(IP3_6, LCDOUT13),
 855         PINMUX_IPSR_DATA(IP3_7, DU0_DG6),
 856         PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
 857         PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
 858         PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
 859         PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
 860         PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
 861         PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
 862         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0),
 863         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0),
 864         PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
 865         PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
 866         PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
 867         PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
 868         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0),
 869         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
 870         PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
 871         PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2),
 872         PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
 873         PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
 874         PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
 875         PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
 876         PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
 877         PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
 878         PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
 879         PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
 880         PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
 881         PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
 882         PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
 883         PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
 884         PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
 885         PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
 886         PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
 887         PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1),
 888         PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
 889         PINMUX_IPSR_DATA(IP3_23, QCLK),
 890         PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
 891         PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
 892         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
 893         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1),
 894         PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2),
 895         PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
 896         PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
 897         PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
 898         PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
 899         PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
 900         PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
 901         PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 902         PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
 903         PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
 904         PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
 905         PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2),
 906         PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
 907
 908         PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
 909         PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
 910         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
 911         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2),
 912         PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
 913         PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
 914         PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
 915         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2),
 916         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
 917         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
 918         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1),
 919         PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
 920         PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
 921         PINMUX_IPSR_DATA(IP4_7_5, PWM6),
 922         PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
 923         PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
 924         PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
 925         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
 926         PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
 927         PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
 928         PINMUX_IPSR_DATA(IP4_10_8, PWM0),
 929         PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
 930         PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
 931         PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
 932         PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3),
 933         PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
 934         PINMUX_IPSR_DATA(IP4_11, VI2_G0),
 935         PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
 936         PINMUX_IPSR_DATA(IP4_12, VI2_G1),
 937         PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
 938         PINMUX_IPSR_DATA(IP4_13, VI2_G2),
 939         PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
 940         PINMUX_IPSR_DATA(IP4_14, VI2_G3),
 941         PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
 942         PINMUX_IPSR_DATA(IP4_15, VI2_G4),
 943         PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
 944         PINMUX_IPSR_DATA(IP4_16, VI2_G5),
 945         PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
 946         PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
 947         PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1),
 948         PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
 949         PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4),
 950         PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
 951         PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
 952         PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
 953         PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
 954         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1),
 955         PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
 956         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0),
 957         PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
 958         PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3),
 959         PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
 960         PINMUX_IPSR_DATA(IP4_23, VI2_G6),
 961         PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
 962         PINMUX_IPSR_DATA(IP4_24, VI2_G7),
 963         PINMUX_IPSR_DATA(IP4_25, DU1_DG4),
 964         PINMUX_IPSR_DATA(IP4_25, VI2_R0),
 965         PINMUX_IPSR_DATA(IP4_26, DU1_DG5),
 966         PINMUX_IPSR_DATA(IP4_26, VI2_R1),
 967         PINMUX_IPSR_DATA(IP4_27, DU1_DG6),
 968         PINMUX_IPSR_DATA(IP4_27, VI2_R2),
 969         PINMUX_IPSR_DATA(IP4_28, DU1_DG7),
 970         PINMUX_IPSR_DATA(IP4_28, VI2_R3),
 971         PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
 972         PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
 973         PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1),
 974         PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
 975         PINMUX_IPSR_DATA(IP4_31_29, TX5),
 976         PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3),
 977
 978         PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
 979         PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
 980         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1),
 981         PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
 982         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0),
 983         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
 984         PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
 985         PINMUX_IPSR_DATA(IP5_3, VI2_R4),
 986         PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
 987         PINMUX_IPSR_DATA(IP5_4, VI2_R5),
 988         PINMUX_IPSR_DATA(IP5_5, DU1_DB4),
 989         PINMUX_IPSR_DATA(IP5_5, VI2_R6),
 990         PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
 991         PINMUX_IPSR_DATA(IP5_6, VI2_R7),
 992         PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
 993         PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3),
 994         PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
 995         PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3),
 996         PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
 997         PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
 998         PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
 999         PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3),
1000         PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
1001         PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
1002         PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3),
1003         PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
1004         PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
1005         PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
1006         PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
1007         PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC),
1008         PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC),
1009         PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1010         PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK),
1011         PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B),
1012         PINMUX_IPSR_DATA(IP5_20_17, SD3_CD),
1013         PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1),
1014         PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB),
1015         PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB),
1016         PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
1017         PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
1018         PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
1019         PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
1020         PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
1021         PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
1022         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0),
1023         PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
1024         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
1025         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3),
1026         PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
1027         PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
1028         PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
1029         PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
1030         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
1031         PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
1032         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
1033         PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
1034         PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
1035         PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
1036         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3),
1037         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
1038         PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
1039         PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
1040         PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
1041         PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
1042         PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2),
1043         PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0),
1044         PINMUX_IPSR_DATA(IP5_30_29, MOUT0),
1045
1046         PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129),
1047         PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1),
1048         PINMUX_IPSR_DATA(IP6_1_0, MOUT1),
1049         PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129),
1050         PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2),
1051         PINMUX_IPSR_DATA(IP6_3_2, MOUT2),
1052         PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0),
1053         PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3),
1054         PINMUX_IPSR_DATA(IP6_5_4, MOUT5),
1055         PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1),
1056         PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4),
1057         PINMUX_IPSR_DATA(IP6_7_6, MOUT6),
1058         PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2),
1059         PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5),
1060         PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
1061         PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
1062         PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
1063         PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0),
1064         PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
1065         PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
1066         PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
1067         PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
1068         PINMUX_IPSR_DATA(IP6_14_12, IETX),
1069         PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
1070         PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
1071         PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
1072         PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
1073         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
1074         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0),
1075         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
1076         PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1),
1077         PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
1078         PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
1079         PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
1080         PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
1081         PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
1082         PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
1083         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0),
1084         PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3),
1085         PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
1086         PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
1087         PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
1088         PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
1089         PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
1090         PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0),
1091         PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
1092         PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
1093         PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
1094         PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
1095         PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
1096         PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1),
1097
1098         PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
1099         PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
1100         PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0),
1101         PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
1102         PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
1103         PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
1104         PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
1105         PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1),
1106         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
1107         PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
1108         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1),
1109         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
1110         PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
1111         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0),
1112         PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
1113         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1),
1114         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
1115         PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
1116         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
1117         PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
1118         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1),
1119         PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2),
1120         PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
1121         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
1122         PINMUX_IPSR_DATA(IP7_14_13, VSP),
1123         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1),
1124         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
1125         PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
1126         PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
1127         PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1),
1128         PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
1129         PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
1130         PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
1131         PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
1132         PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
1133         PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
1134         PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1),
1135         PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
1136         PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
1137         PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
1138         PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1),
1139         PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
1140         PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
1141         PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
1142         PINMUX_IPSR_DATA(IP7_24_23, TX2_B),
1143         PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
1144         PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
1145         PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
1146         PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1),
1147         PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
1148         PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
1149         PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0),
1150         PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
1151         PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
1152         PINMUX_IPSR_DATA(IP7_30_29, DACK2),
1153         PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1),
1154
1155         PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
1156         PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0),
1157         PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
1158         PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
1159         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
1160         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12),
1161         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20),
1162         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
1163         PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
1164         PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
1165         PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
1166         PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
1167         PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
1168         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
1169         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13),
1170         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21),
1171         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29),
1172         PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37),
1173         PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0),
1174         PINMUX_IPSR_DATA(IP8_11_8, TX0),
1175         PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
1176         PINMUX_IPSR_DATA(IP8_11_8, AD_DO),
1177         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6),
1178         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14),
1179         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22),
1180         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
1181         PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
1182         PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
1183         PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0),
1184         PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
1185         PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
1186         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
1187         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15),
1188         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23),
1189         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31),
1190         PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39),
1191         PINMUX_IPSR_DATA(IP8_17_16, FMCLK),
1192         PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK),
1193         PINMUX_IPSR_DATA(IP8_17_16, PCMOE),
1194         PINMUX_IPSR_DATA(IP8_18, BPFCLK),
1195         PINMUX_IPSR_DATA(IP8_18, PCMWE),
1196         PINMUX_IPSR_DATA(IP8_19, FMIN),
1197         PINMUX_IPSR_DATA(IP8_19, RDS_DATA),
1198         PINMUX_IPSR_DATA(IP8_20, VI0_CLK),
1199         PINMUX_IPSR_DATA(IP8_20, MMC1_CLK),
1200         PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB),
1201         PINMUX_IPSR_DATA(IP8_22_21, TX1_C),
1202         PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
1203         PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
1204         PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
1205         PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2),
1206         PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
1207         PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
1208         PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
1209         PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2),
1210         PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
1211         PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
1212         PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
1213         PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
1214         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
1215         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
1216         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3),
1217         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
1218
1219         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
1220         PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
1221         PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
1222         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
1223         PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
1224         PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
1225         PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
1226         PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
1227         PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3),
1228         PINMUX_IPSR_DATA(IP9_5, MMC1_D1),
1229         PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4),
1230         PINMUX_IPSR_DATA(IP9_6, MMC1_D2),
1231         PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5),
1232         PINMUX_IPSR_DATA(IP9_7, MMC1_D3),
1233         PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6),
1234         PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4),
1235         PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0),
1236         PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7),
1237         PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
1238         PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
1239         PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
1240         PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
1241         PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0),
1242         PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
1243         PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
1244         PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
1245         PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0),
1246         PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
1247         PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
1248         PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
1249         PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6),
1250         PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4),
1251         PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0),
1252         PINMUX_IPSR_DATA(IP9_21_19, VI0_G3),
1253         PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV),
1254         PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7),
1255         PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5),
1256         PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
1257         PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
1258         PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
1259         PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
1260         PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
1261         PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
1262         PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
1263         PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
1264         PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
1265         PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
1266         PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
1267         PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
1268         PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
1269         PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
1270         PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
1271         PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
1272         PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
1273
1274         PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
1275         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
1276         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2),
1277         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
1278         PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
1279         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
1280         PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
1281         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
1282         PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
1283         PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
1284         PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
1285         PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C),
1286         PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
1287         PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
1288         PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
1289         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0),
1290         PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
1291         PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
1292         PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
1293         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
1294         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0),
1295         PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
1296         PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
1297         PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
1298         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1),
1299         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
1300         PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
1301         PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
1302         PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
1303         PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
1304         PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
1305         PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1),
1306         PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
1307         PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
1308         PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
1309         PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
1310         PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
1311         PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
1312         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
1313         PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
1314         PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
1315         PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
1316         PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
1317         PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
1318         PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
1319         PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
1320         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
1321         PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
1322         PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
1323         PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
1324         PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
1325         PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0),
1326         PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0),
1327         PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
1328         PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
1329         PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
1330         PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
1331         PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
1332         PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
1333         PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
1334         PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
1335         PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
1336         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
1337         PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
1338         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0),
1339
1340         PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
1341         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0),
1342         PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
1343         PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
1344         PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
1345         PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
1346         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0),
1347         PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
1348         PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
1349         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
1350         PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
1351         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0),
1352         PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
1353         PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
1354         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1),
1355         PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
1356         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0),
1357         PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
1358         PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
1359         PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
1360         PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4),
1361         PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
1362         PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
1363         PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
1364         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
1365         PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
1366         PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
1367         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0),
1368         PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
1369         PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
1370         PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
1371         PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
1372         PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
1373         PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0),
1374         PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
1375         PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
1376         PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
1377         PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
1378         PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0),
1379         PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
1380         PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
1381         PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
1382         PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
1383         PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
1384         PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1),
1385         PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
1386         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
1387         PINMUX_IPSR_DATA(IP11_26_24, TX2),
1388         PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
1389         PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
1390         PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
1391         PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
1392         PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
1393         PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
1394         PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
1395         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0),
1396         PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
1397
1398         PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
1399         PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
1400         PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
1401         PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
1402         PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0),
1403         PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
1404         PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
1405         PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
1406         PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
1407         PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
1408         PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2),
1409         PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
1410         PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
1411         PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
1412         PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
1413         PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2),
1414         PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
1415         PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
1416         PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
1417         PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
1418         PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0),
1419         PINMUX_IPSR_DATA(IP12_11_9, FSE),
1420         PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
1421         PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1),
1422         PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
1423         PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
1424         PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0),
1425         PINMUX_IPSR_DATA(IP12_14_12, FRB),
1426         PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1),
1427         PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
1428         PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
1429         PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
1430         PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0),
1431         PINMUX_IPSR_DATA(IP12_17_15, FCE),
1432         PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1433 };
1434
1435 static struct sh_pfc_pin pinmux_pins[] = {
1436         PINMUX_GPIO_GP_ALL(),
1437 };
1438
1439 /* - DU0 -------------------------------------------------------------------- */
1440 static const unsigned int du0_rgb666_pins[] = {
1441         /* R[7:2], G[7:2], B[7:2] */
1442         188, 187, 186, 185, 184, 183,
1443         194, 193, 192, 191, 190, 189,
1444         200, 199, 198, 197, 196, 195,
1445 };
1446 static const unsigned int du0_rgb666_mux[] = {
1447         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1448         DU0_DR3_MARK, DU0_DR2_MARK,
1449         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1450         DU0_DG3_MARK, DU0_DG2_MARK,
1451         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1452         DU0_DB3_MARK, DU0_DB2_MARK,
1453 };
1454 static const unsigned int du0_rgb888_pins[] = {
1455         /* R[7:0], G[7:0], B[7:0] */
1456         188, 187, 186, 185, 184, 183, 24, 23,
1457         194, 193, 192, 191, 190, 189, 26, 25,
1458         200, 199, 198, 197, 196, 195, 28, 27,
1459 };
1460 static const unsigned int du0_rgb888_mux[] = {
1461         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1462         DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1463         DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1464         DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1465         DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1466         DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1467 };
1468 static const unsigned int du0_clk_0_pins[] = {
1469         /* CLKIN, CLKOUT */
1470         29, 180,
1471 };
1472 static const unsigned int du0_clk_0_mux[] = {
1473         DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT0_MARK,
1474 };
1475 static const unsigned int du0_clk_1_pins[] = {
1476         /* CLKIN, CLKOUT */
1477         29, 30,
1478 };
1479 static const unsigned int du0_clk_1_mux[] = {
1480         DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT1_MARK,
1481 };
1482 static const unsigned int du0_sync_0_pins[] = {
1483         /* VSYNC, HSYNC, DISP */
1484         182, 181, 31,
1485 };
1486 static const unsigned int du0_sync_0_mux[] = {
1487         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1488         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1489 };
1490 static const unsigned int du0_sync_1_pins[] = {
1491         /* VSYNC, HSYNC, DISP */
1492         182, 181, 32,
1493 };
1494 static const unsigned int du0_sync_1_mux[] = {
1495         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1496         DU0_DISP_MARK
1497 };
1498 static const unsigned int du0_oddf_pins[] = {
1499         /* ODDF */
1500         31,
1501 };
1502 static const unsigned int du0_oddf_mux[] = {
1503         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1504 };
1505 static const unsigned int du0_cde_pins[] = {
1506         /* CDE */
1507         33,
1508 };
1509 static const unsigned int du0_cde_mux[] = {
1510         DU0_CDE_MARK
1511 };
1512 /* - DU1 -------------------------------------------------------------------- */
1513 static const unsigned int du1_rgb666_pins[] = {
1514         /* R[7:2], G[7:2], B[7:2] */
1515         41, 40, 39, 38, 37, 36,
1516         49, 48, 47, 46, 45, 44,
1517         57, 56, 55, 54, 53, 52,
1518 };
1519 static const unsigned int du1_rgb666_mux[] = {
1520         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1521         DU1_DR3_MARK, DU1_DR2_MARK,
1522         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1523         DU1_DG3_MARK, DU1_DG2_MARK,
1524         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1525         DU1_DB3_MARK, DU1_DB2_MARK,
1526 };
1527 static const unsigned int du1_rgb888_pins[] = {
1528         /* R[7:0], G[7:0], B[7:0] */
1529         41, 40, 39, 38, 37, 36, 35, 34,
1530         49, 48, 47, 46, 45, 44, 43, 32,
1531         57, 56, 55, 54, 53, 52, 51, 50,
1532 };
1533 static const unsigned int du1_rgb888_mux[] = {
1534         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1535         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1536         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1537         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1538         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1539         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1540 };
1541 static const unsigned int du1_clk_pins[] = {
1542         /* CLKIN, CLKOUT */
1543         58, 59,
1544 };
1545 static const unsigned int du1_clk_mux[] = {
1546         DU1_DOTCLKIN_MARK, DU1_DOTCLKOUT_MARK,
1547 };
1548 static const unsigned int du1_sync_0_pins[] = {
1549         /* VSYNC, HSYNC, DISP */
1550         61, 60, 62,
1551 };
1552 static const unsigned int du1_sync_0_mux[] = {
1553         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1554         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1555 };
1556 static const unsigned int du1_sync_1_pins[] = {
1557         /* VSYNC, HSYNC, DISP */
1558         61, 60, 63,
1559 };
1560 static const unsigned int du1_sync_1_mux[] = {
1561         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1562         DU1_DISP_MARK
1563 };
1564 static const unsigned int du1_oddf_pins[] = {
1565         /* ODDF */
1566         62,
1567 };
1568 static const unsigned int du1_oddf_mux[] = {
1569         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1570 };
1571 static const unsigned int du1_cde_pins[] = {
1572         /* CDE */
1573         64,
1574 };
1575 static const unsigned int du1_cde_mux[] = {
1576         DU1_CDE_MARK
1577 };
1578 /* - HSPI0 ------------------------------------------------------------------ */
1579 static const unsigned int hspi0_pins[] = {
1580         /* CLK, CS, RX, TX */
1581         150, 151, 153, 152,
1582 };
1583 static const unsigned int hspi0_mux[] = {
1584         HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
1585 };
1586 /* - HSPI1 ------------------------------------------------------------------ */
1587 static const unsigned int hspi1_pins[] = {
1588         /* CLK, CS, RX, TX */
1589         63, 58, 64, 62,
1590 };
1591 static const unsigned int hspi1_mux[] = {
1592         HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
1593 };
1594 static const unsigned int hspi1_b_pins[] = {
1595         /* CLK, CS, RX, TX */
1596         90, 91, 93, 92,
1597 };
1598 static const unsigned int hspi1_b_mux[] = {
1599         HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
1600 };
1601 static const unsigned int hspi1_c_pins[] = {
1602         /* CLK, CS, RX, TX */
1603         141, 142, 144, 143,
1604 };
1605 static const unsigned int hspi1_c_mux[] = {
1606         HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
1607 };
1608 static const unsigned int hspi1_d_pins[] = {
1609         /* CLK, CS, RX, TX */
1610         101, 102, 104, 103,
1611 };
1612 static const unsigned int hspi1_d_mux[] = {
1613         HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
1614 };
1615 /* - HSPI2 ------------------------------------------------------------------ */
1616 static const unsigned int hspi2_pins[] = {
1617         /* CLK, CS, RX, TX */
1618         9, 10, 11, 14,
1619 };
1620 static const unsigned int hspi2_mux[] = {
1621         HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
1622 };
1623 static const unsigned int hspi2_b_pins[] = {
1624         /* CLK, CS, RX, TX */
1625         7, 13, 8, 6,
1626 };
1627 static const unsigned int hspi2_b_mux[] = {
1628         HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
1629 };
1630 /* - MMCIF ------------------------------------------------------------------ */
1631 static const unsigned int mmc0_data1_pins[] = {
1632         /* D[0] */
1633         19,
1634 };
1635 static const unsigned int mmc0_data1_mux[] = {
1636         MMC0_D0_MARK,
1637 };
1638 static const unsigned int mmc0_data4_pins[] = {
1639         /* D[0:3] */
1640         19, 20, 21, 2,
1641 };
1642 static const unsigned int mmc0_data4_mux[] = {
1643         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1644 };
1645 static const unsigned int mmc0_data8_pins[] = {
1646         /* D[0:7] */
1647         19, 20, 21, 2, 10, 11, 15, 16,
1648 };
1649 static const unsigned int mmc0_data8_mux[] = {
1650         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1651         MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
1652 };
1653 static const unsigned int mmc0_ctrl_pins[] = {
1654         /* CMD, CLK */
1655         18, 17,
1656 };
1657 static const unsigned int mmc0_ctrl_mux[] = {
1658         MMC0_CMD_MARK, MMC0_CLK_MARK,
1659 };
1660 static const unsigned int mmc1_data1_pins[] = {
1661         /* D[0] */
1662         72,
1663 };
1664 static const unsigned int mmc1_data1_mux[] = {
1665         MMC1_D0_MARK,
1666 };
1667 static const unsigned int mmc1_data4_pins[] = {
1668         /* D[0:3] */
1669         72, 73, 74, 75,
1670 };
1671 static const unsigned int mmc1_data4_mux[] = {
1672         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1673 };
1674 static const unsigned int mmc1_data8_pins[] = {
1675         /* D[0:7] */
1676         72, 73, 74, 75, 76, 77, 80, 81,
1677 };
1678 static const unsigned int mmc1_data8_mux[] = {
1679         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1680         MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
1681 };
1682 static const unsigned int mmc1_ctrl_pins[] = {
1683         /* CMD, CLK */
1684         68, 65,
1685 };
1686 static const unsigned int mmc1_ctrl_mux[] = {
1687         MMC1_CMD_MARK, MMC1_CLK_MARK,
1688 };
1689 /* - SCIF0 ------------------------------------------------------------------ */
1690 static const unsigned int scif0_data_pins[] = {
1691         /* RXD, TXD */
1692         153, 152,
1693 };
1694 static const unsigned int scif0_data_mux[] = {
1695         RX0_MARK, TX0_MARK,
1696 };
1697 static const unsigned int scif0_clk_pins[] = {
1698         /* SCK */
1699         156,
1700 };
1701 static const unsigned int scif0_clk_mux[] = {
1702         SCK0_MARK,
1703 };
1704 static const unsigned int scif0_ctrl_pins[] = {
1705         /* RTS, CTS */
1706         151, 150,
1707 };
1708 static const unsigned int scif0_ctrl_mux[] = {
1709         RTS0_TANS_MARK, CTS0_MARK,
1710 };
1711 static const unsigned int scif0_data_b_pins[] = {
1712         /* RXD, TXD */
1713         20, 19,
1714 };
1715 static const unsigned int scif0_data_b_mux[] = {
1716         RX0_B_MARK, TX0_B_MARK,
1717 };
1718 static const unsigned int scif0_clk_b_pins[] = {
1719         /* SCK */
1720         33,
1721 };
1722 static const unsigned int scif0_clk_b_mux[] = {
1723         SCK0_B_MARK,
1724 };
1725 static const unsigned int scif0_ctrl_b_pins[] = {
1726         /* RTS, CTS */
1727         18, 11,
1728 };
1729 static const unsigned int scif0_ctrl_b_mux[] = {
1730         RTS0_B_TANS_B_MARK, CTS0_B_MARK,
1731 };
1732 static const unsigned int scif0_data_c_pins[] = {
1733         /* RXD, TXD */
1734         146, 147,
1735 };
1736 static const unsigned int scif0_data_c_mux[] = {
1737         RX0_C_MARK, TX0_C_MARK,
1738 };
1739 static const unsigned int scif0_clk_c_pins[] = {
1740         /* SCK */
1741         145,
1742 };
1743 static const unsigned int scif0_clk_c_mux[] = {
1744         SCK0_C_MARK,
1745 };
1746 static const unsigned int scif0_ctrl_c_pins[] = {
1747         /* RTS, CTS */
1748         149, 148,
1749 };
1750 static const unsigned int scif0_ctrl_c_mux[] = {
1751         RTS0_C_TANS_C_MARK, CTS0_C_MARK,
1752 };
1753 static const unsigned int scif0_data_d_pins[] = {
1754         /* RXD, TXD */
1755         43, 42,
1756 };
1757 static const unsigned int scif0_data_d_mux[] = {
1758         RX0_D_MARK, TX0_D_MARK,
1759 };
1760 static const unsigned int scif0_clk_d_pins[] = {
1761         /* SCK */
1762         50,
1763 };
1764 static const unsigned int scif0_clk_d_mux[] = {
1765         SCK0_D_MARK,
1766 };
1767 static const unsigned int scif0_ctrl_d_pins[] = {
1768         /* RTS, CTS */
1769         51, 35,
1770 };
1771 static const unsigned int scif0_ctrl_d_mux[] = {
1772         RTS0_D_TANS_D_MARK, CTS0_D_MARK,
1773 };
1774 /* - SCIF1 ------------------------------------------------------------------ */
1775 static const unsigned int scif1_data_pins[] = {
1776         /* RXD, TXD */
1777         149, 148,
1778 };
1779 static const unsigned int scif1_data_mux[] = {
1780         RX1_MARK, TX1_MARK,
1781 };
1782 static const unsigned int scif1_clk_pins[] = {
1783         /* SCK */
1784         145,
1785 };
1786 static const unsigned int scif1_clk_mux[] = {
1787         SCK1_MARK,
1788 };
1789 static const unsigned int scif1_ctrl_pins[] = {
1790         /* RTS, CTS */
1791         147, 146,
1792 };
1793 static const unsigned int scif1_ctrl_mux[] = {
1794         RTS1_TANS_MARK, CTS1_MARK,
1795 };
1796 static const unsigned int scif1_data_b_pins[] = {
1797         /* RXD, TXD */
1798         117, 114,
1799 };
1800 static const unsigned int scif1_data_b_mux[] = {
1801         RX1_B_MARK, TX1_B_MARK,
1802 };
1803 static const unsigned int scif1_clk_b_pins[] = {
1804         /* SCK */
1805         113,
1806 };
1807 static const unsigned int scif1_clk_b_mux[] = {
1808         SCK1_B_MARK,
1809 };
1810 static const unsigned int scif1_ctrl_b_pins[] = {
1811         /* RTS, CTS */
1812         115, 116,
1813 };
1814 static const unsigned int scif1_ctrl_b_mux[] = {
1815         RTS1_B_TANS_B_MARK, CTS1_B_MARK,
1816 };
1817 static const unsigned int scif1_data_c_pins[] = {
1818         /* RXD, TXD */
1819         67, 66,
1820 };
1821 static const unsigned int scif1_data_c_mux[] = {
1822         RX1_C_MARK, TX1_C_MARK,
1823 };
1824 static const unsigned int scif1_clk_c_pins[] = {
1825         /* SCK */
1826         86,
1827 };
1828 static const unsigned int scif1_clk_c_mux[] = {
1829         SCK1_C_MARK,
1830 };
1831 static const unsigned int scif1_ctrl_c_pins[] = {
1832         /* RTS, CTS */
1833         69, 68,
1834 };
1835 static const unsigned int scif1_ctrl_c_mux[] = {
1836         RTS1_C_TANS_C_MARK, CTS1_C_MARK,
1837 };
1838 /* - SCIF2 ------------------------------------------------------------------ */
1839 static const unsigned int scif2_data_pins[] = {
1840         /* RXD, TXD */
1841         106, 105,
1842 };
1843 static const unsigned int scif2_data_mux[] = {
1844         RX2_MARK, TX2_MARK,
1845 };
1846 static const unsigned int scif2_clk_pins[] = {
1847         /* SCK */
1848         107,
1849 };
1850 static const unsigned int scif2_clk_mux[] = {
1851         SCK2_MARK,
1852 };
1853 static const unsigned int scif2_data_b_pins[] = {
1854         /* RXD, TXD */
1855         120, 119,
1856 };
1857 static const unsigned int scif2_data_b_mux[] = {
1858         RX2_B_MARK, TX2_B_MARK,
1859 };
1860 static const unsigned int scif2_clk_b_pins[] = {
1861         /* SCK */
1862         118,
1863 };
1864 static const unsigned int scif2_clk_b_mux[] = {
1865         SCK2_B_MARK,
1866 };
1867 static const unsigned int scif2_data_c_pins[] = {
1868         /* RXD, TXD */
1869         33, 31,
1870 };
1871 static const unsigned int scif2_data_c_mux[] = {
1872         RX2_C_MARK, TX2_C_MARK,
1873 };
1874 static const unsigned int scif2_clk_c_pins[] = {
1875         /* SCK */
1876         32,
1877 };
1878 static const unsigned int scif2_clk_c_mux[] = {
1879         SCK2_C_MARK,
1880 };
1881 static const unsigned int scif2_data_d_pins[] = {
1882         /* RXD, TXD */
1883         64, 62,
1884 };
1885 static const unsigned int scif2_data_d_mux[] = {
1886         RX2_D_MARK, TX2_D_MARK,
1887 };
1888 static const unsigned int scif2_clk_d_pins[] = {
1889         /* SCK */
1890         63,
1891 };
1892 static const unsigned int scif2_clk_d_mux[] = {
1893         SCK2_D_MARK,
1894 };
1895 static const unsigned int scif2_data_e_pins[] = {
1896         /* RXD, TXD */
1897         20, 19,
1898 };
1899 static const unsigned int scif2_data_e_mux[] = {
1900         RX2_E_MARK, TX2_E_MARK,
1901 };
1902 /* - SCIF3 ------------------------------------------------------------------ */
1903 static const unsigned int scif3_data_pins[] = {
1904         /* RXD, TXD */
1905         137, 136,
1906 };
1907 static const unsigned int scif3_data_mux[] = {
1908         RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
1909 };
1910 static const unsigned int scif3_clk_pins[] = {
1911         /* SCK */
1912         135,
1913 };
1914 static const unsigned int scif3_clk_mux[] = {
1915         SCK3_MARK,
1916 };
1917
1918 static const unsigned int scif3_data_b_pins[] = {
1919         /* RXD, TXD */
1920         64, 62,
1921 };
1922 static const unsigned int scif3_data_b_mux[] = {
1923         RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
1924 };
1925 static const unsigned int scif3_data_c_pins[] = {
1926         /* RXD, TXD */
1927         15, 12,
1928 };
1929 static const unsigned int scif3_data_c_mux[] = {
1930         RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
1931 };
1932 static const unsigned int scif3_data_d_pins[] = {
1933         /* RXD, TXD */
1934         30, 29,
1935 };
1936 static const unsigned int scif3_data_d_mux[] = {
1937         RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
1938 };
1939 static const unsigned int scif3_data_e_pins[] = {
1940         /* RXD, TXD */
1941         35, 34,
1942 };
1943 static const unsigned int scif3_data_e_mux[] = {
1944         RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
1945 };
1946 static const unsigned int scif3_clk_e_pins[] = {
1947         /* SCK */
1948         42,
1949 };
1950 static const unsigned int scif3_clk_e_mux[] = {
1951         SCK3_E_MARK,
1952 };
1953 /* - SCIF4 ------------------------------------------------------------------ */
1954 static const unsigned int scif4_data_pins[] = {
1955         /* RXD, TXD */
1956         123, 122,
1957 };
1958 static const unsigned int scif4_data_mux[] = {
1959         RX4_MARK, TX4_MARK,
1960 };
1961 static const unsigned int scif4_clk_pins[] = {
1962         /* SCK */
1963         121,
1964 };
1965 static const unsigned int scif4_clk_mux[] = {
1966         SCK4_MARK,
1967 };
1968 static const unsigned int scif4_data_b_pins[] = {
1969         /* RXD, TXD */
1970         111, 110,
1971 };
1972 static const unsigned int scif4_data_b_mux[] = {
1973         RX4_B_MARK, TX4_B_MARK,
1974 };
1975 static const unsigned int scif4_clk_b_pins[] = {
1976         /* SCK */
1977         112,
1978 };
1979 static const unsigned int scif4_clk_b_mux[] = {
1980         SCK4_B_MARK,
1981 };
1982 static const unsigned int scif4_data_c_pins[] = {
1983         /* RXD, TXD */
1984         22, 21,
1985 };
1986 static const unsigned int scif4_data_c_mux[] = {
1987         RX4_C_MARK, TX4_C_MARK,
1988 };
1989 static const unsigned int scif4_data_d_pins[] = {
1990         /* RXD, TXD */
1991         69, 68,
1992 };
1993 static const unsigned int scif4_data_d_mux[] = {
1994         RX4_D_MARK, TX4_D_MARK,
1995 };
1996 /* - SCIF5 ------------------------------------------------------------------ */
1997 static const unsigned int scif5_data_pins[] = {
1998         /* RXD, TXD */
1999         51, 50,
2000 };
2001 static const unsigned int scif5_data_mux[] = {
2002         RX5_MARK, TX5_MARK,
2003 };
2004 static const unsigned int scif5_clk_pins[] = {
2005         /* SCK */
2006         43,
2007 };
2008 static const unsigned int scif5_clk_mux[] = {
2009         SCK5_MARK,
2010 };
2011 static const unsigned int scif5_data_b_pins[] = {
2012         /* RXD, TXD */
2013         18, 11,
2014 };
2015 static const unsigned int scif5_data_b_mux[] = {
2016         RX5_B_MARK, TX5_B_MARK,
2017 };
2018 static const unsigned int scif5_clk_b_pins[] = {
2019         /* SCK */
2020         19,
2021 };
2022 static const unsigned int scif5_clk_b_mux[] = {
2023         SCK5_B_MARK,
2024 };
2025 static const unsigned int scif5_data_c_pins[] = {
2026         /* RXD, TXD */
2027         24, 23,
2028 };
2029 static const unsigned int scif5_data_c_mux[] = {
2030         RX5_C_MARK, TX5_C_MARK,
2031 };
2032 static const unsigned int scif5_clk_c_pins[] = {
2033         /* SCK */
2034         28,
2035 };
2036 static const unsigned int scif5_clk_c_mux[] = {
2037         SCK5_C_MARK,
2038 };
2039 static const unsigned int scif5_data_d_pins[] = {
2040         /* RXD, TXD */
2041         8, 6,
2042 };
2043 static const unsigned int scif5_data_d_mux[] = {
2044         RX5_D_MARK, TX5_D_MARK,
2045 };
2046 static const unsigned int scif5_clk_d_pins[] = {
2047         /* SCK */
2048         7,
2049 };
2050 static const unsigned int scif5_clk_d_mux[] = {
2051         SCK5_D_MARK,
2052 };
2053 /* - SDHI0 ------------------------------------------------------------------ */
2054 static const unsigned int sdhi0_data1_pins[] = {
2055         /* D0 */
2056         117,
2057 };
2058 static const unsigned int sdhi0_data1_mux[] = {
2059         SD0_DAT0_MARK,
2060 };
2061 static const unsigned int sdhi0_data4_pins[] = {
2062         /* D[0:3] */
2063         117, 118, 119, 120,
2064 };
2065 static const unsigned int sdhi0_data4_mux[] = {
2066         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2067 };
2068 static const unsigned int sdhi0_ctrl_pins[] = {
2069         /* CMD, CLK */
2070         114, 113,
2071 };
2072 static const unsigned int sdhi0_ctrl_mux[] = {
2073         SD0_CMD_MARK, SD0_CLK_MARK,
2074 };
2075 static const unsigned int sdhi0_cd_pins[] = {
2076         /* CD */
2077         115,
2078 };
2079 static const unsigned int sdhi0_cd_mux[] = {
2080         SD0_CD_MARK,
2081 };
2082 static const unsigned int sdhi0_wp_pins[] = {
2083         /* WP */
2084         116,
2085 };
2086 static const unsigned int sdhi0_wp_mux[] = {
2087         SD0_WP_MARK,
2088 };
2089 /* - SDHI1 ------------------------------------------------------------------ */
2090 static const unsigned int sdhi1_data1_pins[] = {
2091         /* D0 */
2092         19,
2093 };
2094 static const unsigned int sdhi1_data1_mux[] = {
2095         SD1_DAT0_MARK,
2096 };
2097 static const unsigned int sdhi1_data4_pins[] = {
2098         /* D[0:3] */
2099         19, 20, 21, 2,
2100 };
2101 static const unsigned int sdhi1_data4_mux[] = {
2102         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2103 };
2104 static const unsigned int sdhi1_ctrl_pins[] = {
2105         /* CMD, CLK */
2106         18, 17,
2107 };
2108 static const unsigned int sdhi1_ctrl_mux[] = {
2109         SD1_CMD_MARK, SD1_CLK_MARK,
2110 };
2111 static const unsigned int sdhi1_cd_pins[] = {
2112         /* CD */
2113         10,
2114 };
2115 static const unsigned int sdhi1_cd_mux[] = {
2116         SD1_CD_MARK,
2117 };
2118 static const unsigned int sdhi1_wp_pins[] = {
2119         /* WP */
2120         11,
2121 };
2122 static const unsigned int sdhi1_wp_mux[] = {
2123         SD1_WP_MARK,
2124 };
2125 /* - SDHI2 ------------------------------------------------------------------ */
2126 static const unsigned int sdhi2_data1_pins[] = {
2127         /* D0 */
2128         97,
2129 };
2130 static const unsigned int sdhi2_data1_mux[] = {
2131         SD2_DAT0_MARK,
2132 };
2133 static const unsigned int sdhi2_data4_pins[] = {
2134         /* D[0:3] */
2135         97, 98, 99, 100,
2136 };
2137 static const unsigned int sdhi2_data4_mux[] = {
2138         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2139 };
2140 static const unsigned int sdhi2_ctrl_pins[] = {
2141         /* CMD, CLK */
2142         102, 101,
2143 };
2144 static const unsigned int sdhi2_ctrl_mux[] = {
2145         SD2_CMD_MARK, SD2_CLK_MARK,
2146 };
2147 static const unsigned int sdhi2_cd_pins[] = {
2148         /* CD */
2149         103,
2150 };
2151 static const unsigned int sdhi2_cd_mux[] = {
2152         SD2_CD_MARK,
2153 };
2154 static const unsigned int sdhi2_wp_pins[] = {
2155         /* WP */
2156         104,
2157 };
2158 static const unsigned int sdhi2_wp_mux[] = {
2159         SD2_WP_MARK,
2160 };
2161 /* - SDHI3 ------------------------------------------------------------------ */
2162 static const unsigned int sdhi3_data1_pins[] = {
2163         /* D0 */
2164         50,
2165 };
2166 static const unsigned int sdhi3_data1_mux[] = {
2167         SD3_DAT0_MARK,
2168 };
2169 static const unsigned int sdhi3_data4_pins[] = {
2170         /* D[0:3] */
2171         50, 51, 52, 53,
2172 };
2173 static const unsigned int sdhi3_data4_mux[] = {
2174         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2175 };
2176 static const unsigned int sdhi3_ctrl_pins[] = {
2177         /* CMD, CLK */
2178         35, 34,
2179 };
2180 static const unsigned int sdhi3_ctrl_mux[] = {
2181         SD3_CMD_MARK, SD3_CLK_MARK,
2182 };
2183 static const unsigned int sdhi3_cd_pins[] = {
2184         /* CD */
2185         62,
2186 };
2187 static const unsigned int sdhi3_cd_mux[] = {
2188         SD3_CD_MARK,
2189 };
2190 static const unsigned int sdhi3_wp_pins[] = {
2191         /* WP */
2192         64,
2193 };
2194 static const unsigned int sdhi3_wp_mux[] = {
2195         SD3_WP_MARK,
2196 };
2197
2198 static const struct sh_pfc_pin_group pinmux_groups[] = {
2199         SH_PFC_PIN_GROUP(du0_rgb666),
2200         SH_PFC_PIN_GROUP(du0_rgb888),
2201         SH_PFC_PIN_GROUP(du0_clk_0),
2202         SH_PFC_PIN_GROUP(du0_clk_1),
2203         SH_PFC_PIN_GROUP(du0_sync_0),
2204         SH_PFC_PIN_GROUP(du0_sync_1),
2205         SH_PFC_PIN_GROUP(du0_oddf),
2206         SH_PFC_PIN_GROUP(du0_cde),
2207         SH_PFC_PIN_GROUP(du1_rgb666),
2208         SH_PFC_PIN_GROUP(du1_rgb888),
2209         SH_PFC_PIN_GROUP(du1_clk),
2210         SH_PFC_PIN_GROUP(du1_sync_0),
2211         SH_PFC_PIN_GROUP(du1_sync_1),
2212         SH_PFC_PIN_GROUP(du1_oddf),
2213         SH_PFC_PIN_GROUP(du1_cde),
2214         SH_PFC_PIN_GROUP(hspi0),
2215         SH_PFC_PIN_GROUP(hspi1),
2216         SH_PFC_PIN_GROUP(hspi1_b),
2217         SH_PFC_PIN_GROUP(hspi1_c),
2218         SH_PFC_PIN_GROUP(hspi1_d),
2219         SH_PFC_PIN_GROUP(hspi2),
2220         SH_PFC_PIN_GROUP(hspi2_b),
2221         SH_PFC_PIN_GROUP(mmc0_data1),
2222         SH_PFC_PIN_GROUP(mmc0_data4),
2223         SH_PFC_PIN_GROUP(mmc0_data8),
2224         SH_PFC_PIN_GROUP(mmc0_ctrl),
2225         SH_PFC_PIN_GROUP(mmc1_data1),
2226         SH_PFC_PIN_GROUP(mmc1_data4),
2227         SH_PFC_PIN_GROUP(mmc1_data8),
2228         SH_PFC_PIN_GROUP(mmc1_ctrl),
2229         SH_PFC_PIN_GROUP(scif0_data),
2230         SH_PFC_PIN_GROUP(scif0_clk),
2231         SH_PFC_PIN_GROUP(scif0_ctrl),
2232         SH_PFC_PIN_GROUP(scif0_data_b),
2233         SH_PFC_PIN_GROUP(scif0_clk_b),
2234         SH_PFC_PIN_GROUP(scif0_ctrl_b),
2235         SH_PFC_PIN_GROUP(scif0_data_c),
2236         SH_PFC_PIN_GROUP(scif0_clk_c),
2237         SH_PFC_PIN_GROUP(scif0_ctrl_c),
2238         SH_PFC_PIN_GROUP(scif0_data_d),
2239         SH_PFC_PIN_GROUP(scif0_clk_d),
2240         SH_PFC_PIN_GROUP(scif0_ctrl_d),
2241         SH_PFC_PIN_GROUP(scif1_data),
2242         SH_PFC_PIN_GROUP(scif1_clk),
2243         SH_PFC_PIN_GROUP(scif1_ctrl),
2244         SH_PFC_PIN_GROUP(scif1_data_b),
2245         SH_PFC_PIN_GROUP(scif1_clk_b),
2246         SH_PFC_PIN_GROUP(scif1_ctrl_b),
2247         SH_PFC_PIN_GROUP(scif1_data_c),
2248         SH_PFC_PIN_GROUP(scif1_clk_c),
2249         SH_PFC_PIN_GROUP(scif1_ctrl_c),
2250         SH_PFC_PIN_GROUP(scif2_data),
2251         SH_PFC_PIN_GROUP(scif2_clk),
2252         SH_PFC_PIN_GROUP(scif2_data_b),
2253         SH_PFC_PIN_GROUP(scif2_clk_b),
2254         SH_PFC_PIN_GROUP(scif2_data_c),
2255         SH_PFC_PIN_GROUP(scif2_clk_c),
2256         SH_PFC_PIN_GROUP(scif2_data_d),
2257         SH_PFC_PIN_GROUP(scif2_clk_d),
2258         SH_PFC_PIN_GROUP(scif2_data_e),
2259         SH_PFC_PIN_GROUP(scif3_data),
2260         SH_PFC_PIN_GROUP(scif3_clk),
2261         SH_PFC_PIN_GROUP(scif3_data_b),
2262         SH_PFC_PIN_GROUP(scif3_data_c),
2263         SH_PFC_PIN_GROUP(scif3_data_d),
2264         SH_PFC_PIN_GROUP(scif3_data_e),
2265         SH_PFC_PIN_GROUP(scif3_clk_e),
2266         SH_PFC_PIN_GROUP(scif4_data),
2267         SH_PFC_PIN_GROUP(scif4_clk),
2268         SH_PFC_PIN_GROUP(scif4_data_b),
2269         SH_PFC_PIN_GROUP(scif4_clk_b),
2270         SH_PFC_PIN_GROUP(scif4_data_c),
2271         SH_PFC_PIN_GROUP(scif4_data_d),
2272         SH_PFC_PIN_GROUP(scif5_data),
2273         SH_PFC_PIN_GROUP(scif5_clk),
2274         SH_PFC_PIN_GROUP(scif5_data_b),
2275         SH_PFC_PIN_GROUP(scif5_clk_b),
2276         SH_PFC_PIN_GROUP(scif5_data_c),
2277         SH_PFC_PIN_GROUP(scif5_clk_c),
2278         SH_PFC_PIN_GROUP(scif5_data_d),
2279         SH_PFC_PIN_GROUP(scif5_clk_d),
2280         SH_PFC_PIN_GROUP(sdhi0_data1),
2281         SH_PFC_PIN_GROUP(sdhi0_data4),
2282         SH_PFC_PIN_GROUP(sdhi0_ctrl),
2283         SH_PFC_PIN_GROUP(sdhi0_cd),
2284         SH_PFC_PIN_GROUP(sdhi0_wp),
2285         SH_PFC_PIN_GROUP(sdhi1_data1),
2286         SH_PFC_PIN_GROUP(sdhi1_data4),
2287         SH_PFC_PIN_GROUP(sdhi1_ctrl),
2288         SH_PFC_PIN_GROUP(sdhi1_cd),
2289         SH_PFC_PIN_GROUP(sdhi1_wp),
2290         SH_PFC_PIN_GROUP(sdhi2_data1),
2291         SH_PFC_PIN_GROUP(sdhi2_data4),
2292         SH_PFC_PIN_GROUP(sdhi2_ctrl),
2293         SH_PFC_PIN_GROUP(sdhi2_cd),
2294         SH_PFC_PIN_GROUP(sdhi2_wp),
2295         SH_PFC_PIN_GROUP(sdhi3_data1),
2296         SH_PFC_PIN_GROUP(sdhi3_data4),
2297         SH_PFC_PIN_GROUP(sdhi3_ctrl),
2298         SH_PFC_PIN_GROUP(sdhi3_cd),
2299         SH_PFC_PIN_GROUP(sdhi3_wp),
2300 };
2301
2302 static const char * const du0_groups[] = {
2303         "du0_rgb666",
2304         "du0_rgb888",
2305         "du0_clk_0",
2306         "du0_clk_1",
2307         "du0_sync_0",
2308         "du0_sync_1",
2309         "du0_oddf",
2310         "du0_cde",
2311 };
2312
2313 static const char * const du1_groups[] = {
2314         "du1_rgb666",
2315         "du1_rgb888",
2316         "du1_clk",
2317         "du1_sync_0",
2318         "du1_sync_1",
2319         "du1_oddf",
2320         "du1_cde",
2321 };
2322
2323 static const char * const hspi0_groups[] = {
2324         "hspi0",
2325 };
2326
2327 static const char * const hspi1_groups[] = {
2328         "hspi1",
2329         "hspi1_b",
2330         "hspi1_c",
2331         "hspi1_d",
2332 };
2333
2334 static const char * const hspi2_groups[] = {
2335         "hspi2",
2336         "hspi2_b",
2337 };
2338
2339 static const char * const mmc0_groups[] = {
2340         "mmc0_data1",
2341         "mmc0_data4",
2342         "mmc0_data8",
2343         "mmc0_ctrl",
2344 };
2345
2346 static const char * const mmc1_groups[] = {
2347         "mmc1_data1",
2348         "mmc1_data4",
2349         "mmc1_data8",
2350         "mmc1_ctrl",
2351 };
2352
2353 static const char * const scif0_groups[] = {
2354         "scif0_data",
2355         "scif0_clk",
2356         "scif0_ctrl",
2357         "scif0_data_b",
2358         "scif0_clk_b",
2359         "scif0_ctrl_b",
2360         "scif0_data_c",
2361         "scif0_clk_c",
2362         "scif0_ctrl_c",
2363         "scif0_data_d",
2364         "scif0_clk_d",
2365         "scif0_ctrl_d",
2366 };
2367
2368 static const char * const scif1_groups[] = {
2369         "scif1_data",
2370         "scif1_clk",
2371         "scif1_ctrl",
2372         "scif1_data_b",
2373         "scif1_clk_b",
2374         "scif1_ctrl_b",
2375         "scif1_data_c",
2376         "scif1_clk_c",
2377         "scif1_ctrl_c",
2378 };
2379
2380 static const char * const scif2_groups[] = {
2381         "scif2_data",
2382         "scif2_clk",
2383         "scif2_data_b",
2384         "scif2_clk_b",
2385         "scif2_data_c",
2386         "scif2_clk_c",
2387         "scif2_data_d",
2388         "scif2_clk_d",
2389         "scif2_data_e",
2390 };
2391
2392 static const char * const scif3_groups[] = {
2393         "scif3_data",
2394         "scif3_clk",
2395         "scif3_data_b",
2396         "scif3_data_c",
2397         "scif3_data_d",
2398         "scif3_data_e",
2399         "scif3_clk_e",
2400 };
2401
2402 static const char * const scif4_groups[] = {
2403         "scif4_data",
2404         "scif4_clk",
2405         "scif4_data_b",
2406         "scif4_clk_b",
2407         "scif4_data_c",
2408         "scif4_data_d",
2409 };
2410
2411 static const char * const scif5_groups[] = {
2412         "scif5_data",
2413         "scif5_clk",
2414         "scif5_data_b",
2415         "scif5_clk_b",
2416         "scif5_data_c",
2417         "scif5_clk_c",
2418         "scif5_data_d",
2419         "scif5_clk_d",
2420 };
2421
2422 static const char * const sdhi0_groups[] = {
2423         "sdhi0_data1",
2424         "sdhi0_data4",
2425         "sdhi0_ctrl",
2426         "sdhi0_cd",
2427         "sdhi0_wp",
2428 };
2429
2430 static const char * const sdhi1_groups[] = {
2431         "sdhi1_data1",
2432         "sdhi1_data4",
2433         "sdhi1_ctrl",
2434         "sdhi1_cd",
2435         "sdhi1_wp",
2436 };
2437
2438 static const char * const sdhi2_groups[] = {
2439         "sdhi2_data1",
2440         "sdhi2_data4",
2441         "sdhi2_ctrl",
2442         "sdhi2_cd",
2443         "sdhi2_wp",
2444 };
2445
2446 static const char * const sdhi3_groups[] = {
2447         "sdhi3_data1",
2448         "sdhi3_data4",
2449         "sdhi3_ctrl",
2450         "sdhi3_cd",
2451         "sdhi3_wp",
2452 };
2453
2454 static const struct sh_pfc_function pinmux_functions[] = {
2455         SH_PFC_FUNCTION(du0),
2456         SH_PFC_FUNCTION(du1),
2457         SH_PFC_FUNCTION(hspi0),
2458         SH_PFC_FUNCTION(hspi1),
2459         SH_PFC_FUNCTION(hspi2),
2460         SH_PFC_FUNCTION(mmc0),
2461         SH_PFC_FUNCTION(mmc1),
2462         SH_PFC_FUNCTION(sdhi0),
2463         SH_PFC_FUNCTION(sdhi1),
2464         SH_PFC_FUNCTION(sdhi2),
2465         SH_PFC_FUNCTION(sdhi3),
2466         SH_PFC_FUNCTION(scif0),
2467         SH_PFC_FUNCTION(scif1),
2468         SH_PFC_FUNCTION(scif2),
2469         SH_PFC_FUNCTION(scif3),
2470         SH_PFC_FUNCTION(scif4),
2471         SH_PFC_FUNCTION(scif5),
2472 };
2473
2474 #define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
2475
2476 static const struct pinmux_func pinmux_func_gpios[] = {
2477         GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
2478         GPIO_FN(A19),
2479
2480         /* IPSR0 */
2481         GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
2482         GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
2483         GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
2484         GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
2485         GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D),
2486         GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D),
2487         GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D),
2488         GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
2489         GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD),
2490         GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2),
2491         GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5),
2492         GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B),
2493         GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT),
2494         GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0),
2495         GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2),
2496         GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
2497         GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C),
2498
2499         /* IPSR1 */
2500         GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6),
2501         GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7),
2502         GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE),
2503         GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD),
2504         GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B),
2505         GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B),
2506         GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0),
2507         GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
2508         GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B),
2509         GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1),
2510         GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
2511         GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9),
2512         GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG),
2513         GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
2514         GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA),
2515         GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
2516         GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
2517         GPIO_FN(CC5_STATE34),
2518
2519         /* IPSR2 */
2520         GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C),
2521         GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
2522         GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
2523         GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5),
2524         GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
2525         GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
2526         GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
2527         GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C),
2528         GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
2529         GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS),
2530         GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
2531         GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
2532         GPIO_FN(CC5_STATE33), GPIO_FN(LCDOUT0),
2533         GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
2534         GPIO_FN(TX5_C), GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
2535         GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C),
2536         GPIO_FN(LCDOUT2), GPIO_FN(LCDOUT3),
2537         GPIO_FN(LCDOUT4), GPIO_FN(LCDOUT5),
2538         GPIO_FN(LCDOUT6), GPIO_FN(LCDOUT7),
2539         GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
2540         GPIO_FN(AUDATA2),
2541
2542         /* IPSR3 */
2543         GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
2544         GPIO_FN(AUDATA3), GPIO_FN(LCDOUT10),
2545         GPIO_FN(LCDOUT11),
2546         GPIO_FN(LCDOUT12), GPIO_FN(LCDOUT13),
2547         GPIO_FN(LCDOUT14),
2548         GPIO_FN(LCDOUT15), GPIO_FN(LCDOUT16),
2549         GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
2550         GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
2551         GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C),
2552         GPIO_FN(LCDOUT18),
2553         GPIO_FN(LCDOUT19), GPIO_FN(LCDOUT20),
2554         GPIO_FN(LCDOUT21),
2555         GPIO_FN(LCDOUT22), GPIO_FN(LCDOUT23),
2556         GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D),
2557         GPIO_FN(SCL3_B), GPIO_FN(QCLK),
2558         GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D),
2559         GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
2560         GPIO_FN(QSTH_QHS),
2561         GPIO_FN(QSTB_QHE),
2562         GPIO_FN(QCPV_QDE),
2563         GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
2564
2565         /* IPSR4 */
2566         GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C),
2567         GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C),
2568         GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B),
2569         GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
2570         GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK),
2571         GPIO_FN(PWMFSW0_B), GPIO_FN(VI2_DATA1_VI2_B1),
2572         GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E),
2573         GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(VI2_G0),
2574         GPIO_FN(VI2_G1), GPIO_FN(VI2_G2),
2575         GPIO_FN(VI2_G3), GPIO_FN(VI2_G4),
2576         GPIO_FN(VI2_G5),
2577         GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2),
2578         GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D),
2579         GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3),
2580         GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D),
2581         GPIO_FN(VI2_G6), GPIO_FN(VI2_G7),
2582         GPIO_FN(VI2_R0), GPIO_FN(VI2_R1),
2583         GPIO_FN(VI2_R2), GPIO_FN(VI2_R3),
2584         GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0),
2585         GPIO_FN(TX5), GPIO_FN(SCK0_D),
2586
2587         /* IPSR5 */
2588         GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
2589         GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D),
2590         GPIO_FN(VI2_R4), GPIO_FN(VI2_R5),
2591         GPIO_FN(VI2_R6), GPIO_FN(VI2_R7),
2592         GPIO_FN(SCL2_D), GPIO_FN(SDA2_D),
2593         GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1),
2594         GPIO_FN(SCL1_D), GPIO_FN(VI2_FIELD),
2595         GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC),
2596         GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC),
2597         GPIO_FN(VI3_VSYNC),
2598         GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD),
2599         GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
2600         GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN),
2601         GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6),
2602         GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
2603         GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
2604         GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
2605         GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
2606         GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
2607         GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
2608         GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
2609         GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
2610
2611         /* IPSR6 */
2612         GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1),
2613         GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2),
2614         GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5),
2615         GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6),
2616         GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34),
2617         GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX),
2618         GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7),
2619         GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C),
2620         GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8),
2621         GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
2622         GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
2623         GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
2624         GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D),
2625         GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
2626         GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
2627         GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6),
2628         GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
2629
2630         /* IPSR7 */
2631         GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
2632         GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
2633         GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
2634         GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C),
2635         GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B),
2636         GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7),
2637         GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
2638         GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
2639         GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK),
2640         GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11),
2641         GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1),
2642         GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1),
2643         GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1),
2644         GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1),
2645         GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2),
2646         GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2),
2647         GPIO_FN(CTS1_B),
2648
2649         /* IPSR8 */
2650         GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
2651         GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
2652         GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0),
2653         GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI),
2654         GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
2655         GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0),
2656         GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
2657         GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
2658         GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0),
2659         GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
2660         GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
2661         GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
2662         GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
2663         GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB),
2664         GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
2665         GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B),
2666         GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C),
2667         GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B),
2668         GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
2669         GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C),
2670
2671         /* IPSR9 */
2672         GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
2673         GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
2674         GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3),
2675         GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2),
2676         GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6),
2677         GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
2678         GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
2679         GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2),
2680         GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1),
2681         GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
2682         GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
2683         GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7),
2684         GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
2685         GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6),
2686         GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B),
2687         GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
2688         GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
2689         GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9),
2690
2691         /* IPSR10 */
2692         GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C),
2693         GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
2694         GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
2695         GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
2696         GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2),
2697         GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
2698         GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
2699         GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B),
2700         GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
2701         GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
2702         GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15),
2703         GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
2704         GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK),
2705         GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
2706         GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B),
2707         GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
2708         GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
2709         GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
2710         GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C),
2711         GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C),
2712         GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
2713
2714         /* IPSR11 */
2715         GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST),
2716         GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
2717         GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
2718         GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2),
2719         GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
2720         GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN),
2721         GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
2722         GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
2723         GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
2724         GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
2725         GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
2726         GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
2727         GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP),
2728         GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
2729         GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1),
2730         GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO),
2731         GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
2732         GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2),
2733         GPIO_FN(HRTS0_B),
2734
2735         /* IPSR12 */
2736         GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
2737         GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
2738         GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
2739         GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
2740         GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
2741         GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
2742         GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B),
2743         GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
2744         GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
2745         GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B),
2746 };
2747
2748 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2749         { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
2750                 GP_0_31_FN, FN_IP3_31_29,
2751                 GP_0_30_FN, FN_IP3_26_24,
2752                 GP_0_29_FN, FN_IP3_22_21,
2753                 GP_0_28_FN, FN_IP3_14_12,
2754                 GP_0_27_FN, FN_IP3_11_9,
2755                 GP_0_26_FN, FN_IP3_2_0,
2756                 GP_0_25_FN, FN_IP2_30_28,
2757                 GP_0_24_FN, FN_IP2_21_19,
2758                 GP_0_23_FN, FN_IP2_18_16,
2759                 GP_0_22_FN, FN_IP0_30_28,
2760                 GP_0_21_FN, FN_IP0_5_3,
2761                 GP_0_20_FN, FN_IP1_18_15,
2762                 GP_0_19_FN, FN_IP1_14_11,
2763                 GP_0_18_FN, FN_IP1_10_7,
2764                 GP_0_17_FN, FN_IP1_6_4,
2765                 GP_0_16_FN, FN_IP1_3_2,
2766                 GP_0_15_FN, FN_IP1_1_0,
2767                 GP_0_14_FN, FN_IP0_27_26,
2768                 GP_0_13_FN, FN_IP0_25,
2769                 GP_0_12_FN, FN_IP0_24_23,
2770                 GP_0_11_FN, FN_IP0_22_19,
2771                 GP_0_10_FN, FN_IP0_18_16,
2772                 GP_0_9_FN, FN_IP0_15_14,
2773                 GP_0_8_FN, FN_IP0_13_12,
2774                 GP_0_7_FN, FN_IP0_11_10,
2775                 GP_0_6_FN, FN_IP0_9_8,
2776                 GP_0_5_FN, FN_A19,
2777                 GP_0_4_FN, FN_A18,
2778                 GP_0_3_FN, FN_A17,
2779                 GP_0_2_FN, FN_IP0_7_6,
2780                 GP_0_1_FN, FN_AVS2,
2781                 GP_0_0_FN, FN_AVS1 }
2782         },
2783         { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
2784                 GP_1_31_FN, FN_IP5_23_21,
2785                 GP_1_30_FN, FN_IP5_20_17,
2786                 GP_1_29_FN, FN_IP5_16_15,
2787                 GP_1_28_FN, FN_IP5_14_13,
2788                 GP_1_27_FN, FN_IP5_12_11,
2789                 GP_1_26_FN, FN_IP5_10_9,
2790                 GP_1_25_FN, FN_IP5_8,
2791                 GP_1_24_FN, FN_IP5_7,
2792                 GP_1_23_FN, FN_IP5_6,
2793                 GP_1_22_FN, FN_IP5_5,
2794                 GP_1_21_FN, FN_IP5_4,
2795                 GP_1_20_FN, FN_IP5_3,
2796                 GP_1_19_FN, FN_IP5_2_0,
2797                 GP_1_18_FN, FN_IP4_31_29,
2798                 GP_1_17_FN, FN_IP4_28,
2799                 GP_1_16_FN, FN_IP4_27,
2800                 GP_1_15_FN, FN_IP4_26,
2801                 GP_1_14_FN, FN_IP4_25,
2802                 GP_1_13_FN, FN_IP4_24,
2803                 GP_1_12_FN, FN_IP4_23,
2804                 GP_1_11_FN, FN_IP4_22_20,
2805                 GP_1_10_FN, FN_IP4_19_17,
2806                 GP_1_9_FN, FN_IP4_16,
2807                 GP_1_8_FN, FN_IP4_15,
2808                 GP_1_7_FN, FN_IP4_14,
2809                 GP_1_6_FN, FN_IP4_13,
2810                 GP_1_5_FN, FN_IP4_12,
2811                 GP_1_4_FN, FN_IP4_11,
2812                 GP_1_3_FN, FN_IP4_10_8,
2813                 GP_1_2_FN, FN_IP4_7_5,
2814                 GP_1_1_FN, FN_IP4_4_2,
2815                 GP_1_0_FN, FN_IP4_1_0 }
2816         },
2817         { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
2818                 GP_2_31_FN, FN_IP10_28_26,
2819                 GP_2_30_FN, FN_IP10_25_24,
2820                 GP_2_29_FN, FN_IP10_23_21,
2821                 GP_2_28_FN, FN_IP10_20_18,
2822                 GP_2_27_FN, FN_IP10_17_15,
2823                 GP_2_26_FN, FN_IP10_14_12,
2824                 GP_2_25_FN, FN_IP10_11_9,
2825                 GP_2_24_FN, FN_IP10_8_6,
2826                 GP_2_23_FN, FN_IP10_5_3,
2827                 GP_2_22_FN, FN_IP10_2_0,
2828                 GP_2_21_FN, FN_IP9_29_28,
2829                 GP_2_20_FN, FN_IP9_27_26,
2830                 GP_2_19_FN, FN_IP9_25_24,
2831                 GP_2_18_FN, FN_IP9_23_22,
2832                 GP_2_17_FN, FN_IP9_21_19,
2833                 GP_2_16_FN, FN_IP9_18_16,
2834                 GP_2_15_FN, FN_IP9_15_14,
2835                 GP_2_14_FN, FN_IP9_13_12,
2836                 GP_2_13_FN, FN_IP9_11_10,
2837                 GP_2_12_FN, FN_IP9_9_8,
2838                 GP_2_11_FN, FN_IP9_7,
2839                 GP_2_10_FN, FN_IP9_6,
2840                 GP_2_9_FN, FN_IP9_5,
2841                 GP_2_8_FN, FN_IP9_4,
2842                 GP_2_7_FN, FN_IP9_3_2,
2843                 GP_2_6_FN, FN_IP9_1_0,
2844                 GP_2_5_FN, FN_IP8_30_28,
2845                 GP_2_4_FN, FN_IP8_27_25,
2846                 GP_2_3_FN, FN_IP8_24_23,
2847                 GP_2_2_FN, FN_IP8_22_21,
2848                 GP_2_1_FN, FN_IP8_20,
2849                 GP_2_0_FN, FN_IP5_27_24 }
2850         },
2851         { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
2852                 GP_3_31_FN, FN_IP6_3_2,
2853                 GP_3_30_FN, FN_IP6_1_0,
2854                 GP_3_29_FN, FN_IP5_30_29,
2855                 GP_3_28_FN, FN_IP5_28,
2856                 GP_3_27_FN, FN_IP1_24_23,
2857                 GP_3_26_FN, FN_IP1_22_21,
2858                 GP_3_25_FN, FN_IP1_20_19,
2859                 GP_3_24_FN, FN_IP7_26_25,
2860                 GP_3_23_FN, FN_IP7_24_23,
2861                 GP_3_22_FN, FN_IP7_22_21,
2862                 GP_3_21_FN, FN_IP7_20_19,
2863                 GP_3_20_FN, FN_IP7_30_29,
2864                 GP_3_19_FN, FN_IP7_28_27,
2865                 GP_3_18_FN, FN_IP7_18_17,
2866                 GP_3_17_FN, FN_IP7_16_15,
2867                 GP_3_16_FN, FN_IP12_17_15,
2868                 GP_3_15_FN, FN_IP12_14_12,
2869                 GP_3_14_FN, FN_IP12_11_9,
2870                 GP_3_13_FN, FN_IP12_8_6,
2871                 GP_3_12_FN, FN_IP12_5_3,
2872                 GP_3_11_FN, FN_IP12_2_0,
2873                 GP_3_10_FN, FN_IP11_29_27,
2874                 GP_3_9_FN, FN_IP11_26_24,
2875                 GP_3_8_FN, FN_IP11_23_21,
2876                 GP_3_7_FN, FN_IP11_20_18,
2877                 GP_3_6_FN, FN_IP11_17_15,
2878                 GP_3_5_FN, FN_IP11_14_12,
2879                 GP_3_4_FN, FN_IP11_11_9,
2880                 GP_3_3_FN, FN_IP11_8_6,
2881                 GP_3_2_FN, FN_IP11_5_3,
2882                 GP_3_1_FN, FN_IP11_2_0,
2883                 GP_3_0_FN, FN_IP10_31_29 }
2884         },
2885         { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
2886                 GP_4_31_FN, FN_IP8_19,
2887                 GP_4_30_FN, FN_IP8_18,
2888                 GP_4_29_FN, FN_IP8_17_16,
2889                 GP_4_28_FN, FN_IP0_2_0,
2890                 GP_4_27_FN, FN_USB_PENC1,
2891                 GP_4_26_FN, FN_USB_PENC0,
2892                 GP_4_25_FN, FN_IP8_15_12,
2893                 GP_4_24_FN, FN_IP8_11_8,
2894                 GP_4_23_FN, FN_IP8_7_4,
2895                 GP_4_22_FN, FN_IP8_3_0,
2896                 GP_4_21_FN, FN_IP2_3_0,
2897                 GP_4_20_FN, FN_IP1_28_25,
2898                 GP_4_19_FN, FN_IP2_15_12,
2899                 GP_4_18_FN, FN_IP2_11_8,
2900                 GP_4_17_FN, FN_IP2_7_4,
2901                 GP_4_16_FN, FN_IP7_14_13,
2902                 GP_4_15_FN, FN_IP7_12_10,
2903                 GP_4_14_FN, FN_IP7_9_7,
2904                 GP_4_13_FN, FN_IP7_6_4,
2905                 GP_4_12_FN, FN_IP7_3_2,
2906                 GP_4_11_FN, FN_IP7_1_0,
2907                 GP_4_10_FN, FN_IP6_30_29,
2908                 GP_4_9_FN, FN_IP6_26_25,
2909                 GP_4_8_FN, FN_IP6_24_23,
2910                 GP_4_7_FN, FN_IP6_22_20,
2911                 GP_4_6_FN, FN_IP6_19_18,
2912                 GP_4_5_FN, FN_IP6_17_15,
2913                 GP_4_4_FN, FN_IP6_14_12,
2914                 GP_4_3_FN, FN_IP6_11_9,
2915                 GP_4_2_FN, FN_IP6_8,
2916                 GP_4_1_FN, FN_IP6_7_6,
2917                 GP_4_0_FN, FN_IP6_5_4 }
2918         },
2919         { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
2920                 GP_5_31_FN, FN_IP3_5,
2921                 GP_5_30_FN, FN_IP3_4,
2922                 GP_5_29_FN, FN_IP3_3,
2923                 GP_5_28_FN, FN_IP2_27,
2924                 GP_5_27_FN, FN_IP2_26,
2925                 GP_5_26_FN, FN_IP2_25,
2926                 GP_5_25_FN, FN_IP2_24,
2927                 GP_5_24_FN, FN_IP2_23,
2928                 GP_5_23_FN, FN_IP2_22,
2929                 GP_5_22_FN, FN_IP3_28,
2930                 GP_5_21_FN, FN_IP3_27,
2931                 GP_5_20_FN, FN_IP3_23,
2932                 GP_5_19_FN, FN_EX_WAIT0,
2933                 GP_5_18_FN, FN_WE1,
2934                 GP_5_17_FN, FN_WE0,
2935                 GP_5_16_FN, FN_RD,
2936                 GP_5_15_FN, FN_A16,
2937                 GP_5_14_FN, FN_A15,
2938                 GP_5_13_FN, FN_A14,
2939                 GP_5_12_FN, FN_A13,
2940                 GP_5_11_FN, FN_A12,
2941                 GP_5_10_FN, FN_A11,
2942                 GP_5_9_FN, FN_A10,
2943                 GP_5_8_FN, FN_A9,
2944                 GP_5_7_FN, FN_A8,
2945                 GP_5_6_FN, FN_A7,
2946                 GP_5_5_FN, FN_A6,
2947                 GP_5_4_FN, FN_A5,
2948                 GP_5_3_FN, FN_A4,
2949                 GP_5_2_FN, FN_A3,
2950                 GP_5_1_FN, FN_A2,
2951                 GP_5_0_FN, FN_A1 }
2952         },
2953         { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) {
2954                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2955                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2956                 0, 0, 0, 0, 0, 0, 0, 0,
2957                 0, 0,
2958                 0, 0,
2959                 0, 0,
2960                 GP_6_8_FN, FN_IP3_20,
2961                 GP_6_7_FN, FN_IP3_19,
2962                 GP_6_6_FN, FN_IP3_18,
2963                 GP_6_5_FN, FN_IP3_17,
2964                 GP_6_4_FN, FN_IP3_16,
2965                 GP_6_3_FN, FN_IP3_15,
2966                 GP_6_2_FN, FN_IP3_8,
2967                 GP_6_1_FN, FN_IP3_7,
2968                 GP_6_0_FN, FN_IP3_6 }
2969         },
2970
2971         { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2972                              1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) {
2973                 /* IP0_31 [1] */
2974                 0, 0,
2975                 /* IP0_30_28 [3] */
2976                 FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
2977                 FN_HRTS1, FN_RX4_C, 0, 0,
2978                 /* IP0_27_26 [2] */
2979                 FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0,
2980                 /* IP0_25 [1] */
2981                 FN_CS0, FN_HSPI_CS2_B,
2982                 /* IP0_24_23 [2] */
2983                 FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0,
2984                 /* IP0_22_19 [4] */
2985                 FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
2986                 FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
2987                 FN_CTS0_B, 0, 0, 0,
2988                 0, 0, 0, 0,
2989                 /* IP0_18_16 [3] */
2990                 FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
2991                 FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0,
2992                 /* IP0_15_14 [2] */
2993                 FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
2994                 /* IP0_13_12 [2] */
2995                 FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
2996                 /* IP0_11_10 [2] */
2997                 FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0,
2998                 /* IP0_9_8 [2] */
2999                 FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0,
3000                 /* IP0_7_6 [2] */
3001                 FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
3002                 /* IP0_5_3 [3] */
3003                 FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
3004                 FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
3005                 /* IP0_2_0 [3] */
3006                 FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
3007                 FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
3008         },
3009         { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3010                              3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) {
3011                 /* IP1_31_29 [3] */
3012                 0, 0, 0, 0, 0, 0, 0, 0,
3013                 /* IP1_28_25 [4] */
3014                 FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
3015                 FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
3016                 FN_CC5_STATE26, FN_CC5_STATE34, 0, 0,
3017                 0, 0, 0, 0,
3018                 /* IP1_24_23 [2] */
3019                 FN_MLB_DAT, FN_PWM4, FN_RX4, 0,
3020                 /* IP1_22_21 [2] */
3021                 FN_MLB_SIG, FN_PWM3, FN_TX4, 0,
3022                 /* IP1_20_19 [2] */
3023                 FN_MLB_CLK, FN_PWM2, FN_SCK4, 0,
3024                 /* IP1_18_15 [4] */
3025                 FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1,
3026                 FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E,
3027                 FN_RX0_B, FN_SSI_WS9, 0, 0,
3028                 0, 0, 0, 0,
3029                 /* IP1_14_11 [4] */
3030                 FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
3031                 FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
3032                 FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0,
3033                 0, 0, 0, 0,
3034                 /* IP1_10_7 [4] */
3035                 FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE,
3036                 FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1,
3037                 FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0,
3038                 0, 0, 0, 0,
3039                 /* IP1_6_4 [3] */
3040                 FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
3041                 FN_ATACS00, 0, 0, 0,
3042                 /* IP1_3_2 [2] */
3043                 FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
3044                 /* IP1_1_0 [2] */
3045                 FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 }
3046         },
3047         { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3048                              1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) {
3049                 /* IP2_31 [1] */
3050                 0, 0,
3051                 /* IP2_30_28 [3] */
3052                 FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
3053                 FN_AUDATA2, 0, 0, 0,
3054                 /* IP2_27 [1] */
3055                 FN_DU0_DR7, FN_LCDOUT7,
3056                 /* IP2_26 [1] */
3057                 FN_DU0_DR6, FN_LCDOUT6,
3058                 /* IP2_25 [1] */
3059                 FN_DU0_DR5, FN_LCDOUT5,
3060                 /* IP2_24 [1] */
3061                 FN_DU0_DR4, FN_LCDOUT4,
3062                 /* IP2_23 [1] */
3063                 FN_DU0_DR3, FN_LCDOUT3,
3064                 /* IP2_22 [1] */
3065                 FN_DU0_DR2, FN_LCDOUT2,
3066                 /* IP2_21_19 [3] */
3067                 FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0,
3068                 FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0,
3069                 /* IP2_18_16 [3] */
3070                 FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B,
3071                 FN_AUDATA0, FN_TX5_C, 0, 0,
3072                 /* IP2_15_12 [4] */
3073                 FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C,
3074                 FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17,
3075                 FN_CC5_STATE25, FN_CC5_STATE33, 0, 0,
3076                 0, 0, 0, 0,
3077                 /* IP2_11_8 [4] */
3078                 FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D,
3079                 FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B,
3080                 FN_CC5_OSCOUT, 0, 0, 0,
3081                 0, 0, 0, 0,
3082                 /* IP2_7_4 [4] */
3083                 FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5,
3084                 FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0,
3085                 FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32,
3086                 0, 0, 0, 0,
3087                 /* IP2_3_0 [4] */
3088                 FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
3089                 FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
3090                 FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
3091                 0, 0, 0, 0 }
3092         },
3093         { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3094                              3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1,
3095                              1, 3, 3, 1, 1, 1, 1, 1, 1, 3) {
3096             /* IP3_31_29 [3] */
3097             FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
3098             FN_SCL2_C, FN_REMOCON, 0, 0,
3099             /* IP3_28 [1] */
3100             FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
3101             /* IP3_27 [1] */
3102             FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
3103             /* IP3_26_24 [3] */
3104             FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
3105             FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0,
3106             /* IP3_23 [1] */
3107             FN_DU0_DOTCLKOUT0, FN_QCLK,
3108             /* IP3_22_21 [2] */
3109             FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B,
3110             /* IP3_20 [1] */
3111             FN_DU0_DB7, FN_LCDOUT23,
3112             /* IP3_19 [1] */
3113             FN_DU0_DB6, FN_LCDOUT22,
3114             /* IP3_18 [1] */
3115             FN_DU0_DB5, FN_LCDOUT21,
3116             /* IP3_17 [1] */
3117             FN_DU0_DB4, FN_LCDOUT20,
3118             /* IP3_16 [1] */
3119             FN_DU0_DB3, FN_LCDOUT19,
3120             /* IP3_15 [1] */
3121             FN_DU0_DB2, FN_LCDOUT18,
3122             /* IP3_14_12 [3] */
3123             FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1,
3124             FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0,
3125             /* IP3_11_9 [3] */
3126             FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1,
3127             FN_TCLK1, FN_AUDATA4, 0, 0,
3128             /* IP3_8 [1] */
3129             FN_DU0_DG7, FN_LCDOUT15,
3130             /* IP3_7 [1] */
3131             FN_DU0_DG6, FN_LCDOUT14,
3132             /* IP3_6 [1] */
3133             FN_DU0_DG5, FN_LCDOUT13,
3134             /* IP3_5 [1] */
3135             FN_DU0_DG4, FN_LCDOUT12,
3136             /* IP3_4 [1] */
3137             FN_DU0_DG3, FN_LCDOUT11,
3138             /* IP3_3 [1] */
3139             FN_DU0_DG2, FN_LCDOUT10,
3140             /* IP3_2_0 [3] */
3141             FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
3142             FN_AUDATA3, 0, 0, 0 }
3143         },
3144         { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3145                              3, 1, 1, 1, 1, 1, 1, 3, 3,
3146                              1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
3147             /* IP4_31_29 [3] */
3148             FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
3149             FN_TX5, FN_SCK0_D, 0, 0,
3150             /* IP4_28 [1] */
3151             FN_DU1_DG7, FN_VI2_R3,
3152             /* IP4_27 [1] */
3153             FN_DU1_DG6, FN_VI2_R2,
3154             /* IP4_26 [1] */
3155             FN_DU1_DG5, FN_VI2_R1,
3156             /* IP4_25 [1] */
3157             FN_DU1_DG4, FN_VI2_R0,
3158             /* IP4_24 [1] */
3159             FN_DU1_DG3, FN_VI2_G7,
3160             /* IP4_23 [1] */
3161             FN_DU1_DG2, FN_VI2_G6,
3162             /* IP4_22_20 [3] */
3163             FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
3164             FN_SCK5, FN_AUDATA7, FN_RX0_D, 0,
3165             /* IP4_19_17 [3] */
3166             FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2,
3167             FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0,
3168             /* IP4_16 [1] */
3169             FN_DU1_DR7, FN_VI2_G5,
3170             /* IP4_15 [1] */
3171             FN_DU1_DR6, FN_VI2_G4,
3172             /* IP4_14 [1] */
3173             FN_DU1_DR5, FN_VI2_G3,
3174             /* IP4_13 [1] */
3175             FN_DU1_DR4, FN_VI2_G2,
3176             /* IP4_12 [1] */
3177             FN_DU1_DR3, FN_VI2_G1,
3178             /* IP4_11 [1] */
3179             FN_DU1_DR2, FN_VI2_G0,
3180             /* IP4_10_8 [3] */
3181             FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD,
3182             FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0,
3183             /* IP4_7_5 [3] */
3184             FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK,
3185             FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0,
3186             /* IP4_4_2 [3] */
3187             FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
3188             FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
3189             /* IP4_1_0 [2] */
3190             FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C }
3191         },
3192         { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3193                              1, 2, 1, 4, 3, 4, 2, 2,
3194                              2, 2, 1, 1, 1, 1, 1, 1, 3) {
3195             /* IP5_31 [1] */
3196             0, 0,
3197             /* IP5_30_29 [2] */
3198             FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
3199             /* IP5_28 [1] */
3200             FN_AUDIO_CLKA, FN_CAN_TXCLK,
3201             /* IP5_27_24 [4] */
3202             FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP,
3203             FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT,
3204             FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0,
3205             0, 0, 0, 0,
3206             /* IP5_23_21 [3] */
3207             FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
3208             FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
3209             /* IP5_20_17 [4] */
3210             FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
3211             FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
3212             FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0,
3213             0, 0, 0, 0,
3214             /* IP5_16_15 [2] */
3215             FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0,
3216             /* IP5_14_13 [2] */
3217             FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0,
3218             /* IP5_12_11 [2] */
3219             FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0,
3220             /* IP5_10_9 [2] */
3221             FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D,
3222             /* IP5_8 [1] */
3223             FN_DU1_DB7, FN_SDA2_D,
3224             /* IP5_7 [1] */
3225             FN_DU1_DB6, FN_SCL2_D,
3226             /* IP5_6 [1] */
3227             FN_DU1_DB5, FN_VI2_R7,
3228             /* IP5_5 [1] */
3229             FN_DU1_DB4, FN_VI2_R6,
3230             /* IP5_4 [1] */
3231             FN_DU1_DB3, FN_VI2_R5,
3232             /* IP5_3 [1] */
3233             FN_DU1_DB2, FN_VI2_R4,
3234             /* IP5_2_0 [3] */
3235             FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
3236             FN_RX5, FN_RTS0_D_TANS_D, 0, 0 }
3237         },
3238         { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3239                              1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) {
3240             /* IP6_31 [1] */
3241             0, 0,
3242             /* IP6_30_29 [2] */
3243             FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
3244             /* IP_28_27 [2] */
3245             0, 0, 0, 0,
3246             /* IP6_26_25 [2] */
3247             FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
3248             /* IP6_24_23 [2] */
3249             FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX,
3250             /* IP6_22_20 [3] */
3251             FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3,
3252             FN_TCLK0_D, 0, 0, 0,
3253             /* IP6_19_18 [2] */
3254             FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0,
3255             /* IP6_17_15 [3] */
3256             FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
3257             FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0,
3258             /* IP6_14_12 [3] */
3259             FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX,
3260             FN_SSI_WS9_C, 0, 0, 0,
3261             /* IP6_11_9 [3] */
3262             FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX,
3263             FN_SSI_SCK9_C, 0, 0, 0,
3264             /* IP6_8 [1] */
3265             FN_SSI_SDATA2, FN_CAN_DEBUGOUT5,
3266             /* IP6_7_6 [2] */
3267             FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0,
3268             /* IP6_5_4 [2] */
3269             FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0,
3270             /* IP6_3_2 [2] */
3271             FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
3272             /* IP6_1_0 [2] */
3273             FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 }
3274         },
3275         { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3276                              1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) {
3277             /* IP7_31 [1] */
3278             0, 0,
3279             /* IP7_30_29 [2] */
3280             FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
3281             /* IP7_28_27 [2] */
3282             FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0,
3283             /* IP7_26_25 [2] */
3284             FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI,
3285             /* IP7_24_23 [2] */
3286             FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK,
3287             /* IP7_22_21 [2] */
3288             FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS,
3289             /* IP7_20_19 [2] */
3290             FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST,
3291             /* IP7_18_17 [2] */
3292             FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO,
3293             /* IP7_16_15 [2] */
3294             FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0,
3295             /* IP7_14_13 [2] */
3296             FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C,
3297             /* IP7_12_10 [3] */
3298             FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C,
3299             FN_HSPI_TX1_C, 0, 0, 0,
3300             /* IP7_9_7 [3] */
3301             FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B,
3302             FN_HSPI_CS1_C, 0, 0, 0,
3303             /* IP7_6_4 [3] */
3304             FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
3305             FN_HSPI_CLK1_C, 0, 0, 0,
3306             /* IP7_3_2 [2] */
3307             FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
3308             /* IP7_1_0 [2] */
3309             FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B }
3310         },
3311         { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3312                              1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) {
3313             /* IP8_31 [1] */
3314             0, 0,
3315             /* IP8_30_28 [3] */
3316             FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
3317             FN_PWMFSW0_C, 0, 0, 0,
3318             /* IP8_27_25 [3] */
3319             FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
3320             FN_MMC1_CMD, FN_HSCK1_B, 0, 0,
3321             /* IP8_24_23 [2] */
3322             FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0,
3323             /* IP8_22_21 [2] */
3324             FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC,
3325             /* IP8_20 [1] */
3326             FN_VI0_CLK, FN_MMC1_CLK,
3327             /* IP8_19 [1] */
3328             FN_FMIN, FN_RDS_DATA,
3329             /* IP8_18 [1] */
3330             FN_BPFCLK, FN_PCMWE,
3331             /* IP8_17_16 [2] */
3332             FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0,
3333             /* IP8_15_12 [4] */
3334             FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS,
3335             FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31,
3336             FN_CC5_STATE39, 0, 0, 0,
3337             0, 0, 0, 0,
3338             /* IP8_11_8 [4] */
3339             FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO,
3340             FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30,
3341             FN_CC5_STATE38, 0, 0, 0,
3342             0, 0, 0, 0,
3343             /* IP8_7_4 [4] */
3344             FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI,
3345             FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29,
3346             FN_CC5_STATE37, 0, 0, 0,
3347             0, 0, 0, 0,
3348             /* IP8_3_0 [4] */
3349             FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
3350             FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
3351             FN_CC5_STATE36, 0, 0, 0,
3352             0, 0, 0, 0 }
3353         },
3354         { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
3355                              2, 2, 2, 2, 2, 3, 3, 2, 2,
3356                              2, 2, 1, 1, 1, 1, 2, 2) {
3357             /* IP9_31_30 [2] */
3358             0, 0, 0, 0,
3359             /* IP9_29_28 [2] */
3360             FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
3361             /* IP9_27_26 [2] */
3362             FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8,
3363             /* IP9_25_24 [2] */
3364             FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7,
3365             /* IP9_23_22 [2] */
3366             FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6,
3367             /* IP9_21_19 [3] */
3368             FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5,
3369             FN_TS_SDAT0, 0, 0, 0,
3370             /* IP9_18_16 [3] */
3371             FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4,
3372             FN_TS_SPSYNC0, 0, 0, 0,
3373             /* IP9_15_14 [2] */
3374             FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3,
3375             /* IP9_13_12 [2] */
3376             FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2,
3377             /* IP9_11_10 [2] */
3378             FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0,
3379             /* IP9_9_8 [2] */
3380             FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0,
3381             /* IP9_7 [1] */
3382             FN_VI0_DATA5_VI0_B5, FN_MMC1_D3,
3383             /* IP9_6 [1] */
3384             FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
3385             /* IP9_5 [1] */
3386             FN_VI0_DATA3_VI0_B3, FN_MMC1_D1,
3387             /* IP9_4 [1] */
3388             FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
3389             /* IP9_3_2 [2] */
3390             FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
3391             /* IP9_1_0 [2] */
3392             FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 }
3393         },
3394         { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
3395                              3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
3396             /* IP10_31_29 [3] */
3397             FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
3398             FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
3399             /* IP10_28_26 [3] */
3400             FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
3401             FN_PWMFSW0_E, 0, 0, 0,
3402             /* IP10_25_24 [2] */
3403             FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0,
3404             /* IP10_23_21 [3] */
3405             FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B,
3406             FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0,
3407             /* IP10_20_18 [3] */
3408             FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B,
3409             FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0,
3410             /* IP10_17_15 [3] */
3411             FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
3412             FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0,
3413             /* IP10_14_12 [3] */
3414             FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B,
3415             FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0,
3416             /* IP10_11_9 [3] */
3417             FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3,
3418             FN_ARM_TRACEDATA_13, 0, 0, 0,
3419             /* IP10_8_6 [3] */
3420             FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
3421             FN_ARM_TRACEDATA_12, 0, 0, 0,
3422             /* IP10_5_3 [3] */
3423             FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11,
3424             FN_DACK0_C, FN_DRACK0_C, 0, 0,
3425             /* IP10_2_0 [3] */
3426             FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
3427             FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 }
3428         },
3429         { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
3430                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3431             /* IP11_31_30 [2] */
3432             0, 0, 0, 0,
3433             /* IP11_29_27 [3] */
3434             FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
3435             FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
3436             /* IP11_26_24 [3] */
3437             FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1,
3438             FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
3439             /* IP11_23_21 [3] */
3440             FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
3441             FN_HSPI_RX1_D, 0, 0, 0,
3442             /* IP11_20_18 [3] */
3443             FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
3444             FN_HSPI_TX1_D, 0, 0, 0,
3445             /* IP11_17_15 [3] */
3446             FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK,
3447             FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0,
3448             /* IP11_14_12 [3] */
3449             FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
3450             FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0,
3451             /* IP11_11_9 [3] */
3452             FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO,
3453             FN_ADICHS0_B, 0, 0, 0,
3454             /* IP11_8_6 [3] */
3455             FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI,
3456             FN_ADIDATA_B, 0, 0, 0,
3457             /* IP11_5_3 [3] */
3458             FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS,
3459             FN_ADICS_B_SAMP_B, 0, 0, 0,
3460             /* IP11_2_0 [3] */
3461             FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
3462             FN_ADICLK_B, 0, 0, 0 }
3463         },
3464         { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
3465                              4, 4, 4, 2, 3, 3, 3, 3, 3, 3) {
3466             /* IP12_31_28 [4] */
3467             0, 0, 0, 0, 0, 0, 0, 0,
3468             0, 0, 0, 0, 0, 0, 0, 0,
3469             /* IP12_27_24 [4] */
3470             0, 0, 0, 0, 0, 0, 0, 0,
3471             0, 0, 0, 0, 0, 0, 0, 0,
3472             /* IP12_23_20 [4] */
3473             0, 0, 0, 0, 0, 0, 0, 0,
3474             0, 0, 0, 0, 0, 0, 0, 0,
3475             /* IP12_19_18 [2] */
3476             0, 0, 0, 0,
3477             /* IP12_17_15 [3] */
3478             FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
3479             FN_SCK4_B, 0, 0, 0,
3480             /* IP12_14_12 [3] */
3481             FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
3482             FN_RX4_B, FN_SIM_CLK_B, 0, 0,
3483             /* IP12_11_9 [3] */
3484             FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE,
3485             FN_TX4_B, FN_SIM_D_B, 0, 0,
3486             /* IP12_8_6 [3] */
3487             FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
3488             FN_SIM_RST_B, FN_HRX0_B, 0, 0,
3489             /* IP12_5_3 [3] */
3490             FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1,
3491             FN_SCL1_C, FN_HTX0_B, 0, 0,
3492             /* IP12_2_0 [3] */
3493             FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
3494             FN_SCK2, FN_HSCK0_B, 0, 0 }
3495         },
3496         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
3497                              2, 2, 3, 3, 2, 2, 2, 2, 2,
3498                              1, 1, 1, 1, 1, 1, 1, 2, 1, 2) {
3499             /* SEL_SCIF5 [2] */
3500             FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
3501             /* SEL_SCIF4 [2] */
3502             FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
3503             /* SEL_SCIF3 [3] */
3504             FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
3505             FN_SEL_SCIF3_4, 0, 0, 0,
3506             /* SEL_SCIF2 [3] */
3507             FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
3508             FN_SEL_SCIF2_4, 0, 0, 0,
3509             /* SEL_SCIF1 [2] */
3510             FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
3511             /* SEL_SCIF0 [2] */
3512             FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
3513             /* SEL_SSI9 [2] */
3514             FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0,
3515             /* SEL_SSI8 [2] */
3516             FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0,
3517             /* SEL_SSI7 [2] */
3518             FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
3519             /* SEL_VI0 [1] */
3520             FN_SEL_VI0_0, FN_SEL_VI0_1,
3521             /* SEL_SD2 [1] */
3522             FN_SEL_SD2_0, FN_SEL_SD2_1,
3523             /* SEL_INT3 [1] */
3524             FN_SEL_INT3_0, FN_SEL_INT3_1,
3525             /* SEL_INT2 [1] */
3526             FN_SEL_INT2_0, FN_SEL_INT2_1,
3527             /* SEL_INT1 [1] */
3528             FN_SEL_INT1_0, FN_SEL_INT1_1,
3529             /* SEL_INT0 [1] */
3530             FN_SEL_INT0_0, FN_SEL_INT0_1,
3531             /* SEL_IE [1] */
3532             FN_SEL_IE_0, FN_SEL_IE_1,
3533             /* SEL_EXBUS2 [2] */
3534             FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0,
3535             /* SEL_EXBUS1 [1] */
3536             FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
3537             /* SEL_EXBUS0 [2] */
3538             FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 }
3539         },
3540         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
3541                              2, 2, 2, 2, 1, 1, 1, 3, 1,
3542                              2, 2, 2, 2, 1, 1, 2, 1, 2, 2) {
3543             /* SEL_TMU1 [2] */
3544             FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
3545             /* SEL_TMU0 [2] */
3546             FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
3547             /* SEL_SCIF [2] */
3548             FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
3549             /* SEL_CANCLK [2] */
3550             FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
3551             /* SEL_CAN0 [1] */
3552             FN_SEL_CAN0_0, FN_SEL_CAN0_1,
3553             /* SEL_HSCIF1 [1] */
3554             FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
3555             /* SEL_HSCIF0 [1] */
3556             FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
3557             /* SEL_PWMFSW [3] */
3558             FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
3559             FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
3560             /* SEL_ADI [1] */
3561             FN_SEL_ADI_0, FN_SEL_ADI_1,
3562             /* [2] */
3563             0, 0, 0, 0,
3564             /* [2] */
3565             0, 0, 0, 0,
3566             /* [2] */
3567             0, 0, 0, 0,
3568             /* SEL_GPS [2] */
3569             FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
3570             /* SEL_SIM [1] */
3571             FN_SEL_SIM_0, FN_SEL_SIM_1,
3572             /* SEL_HSPI2 [1] */
3573             FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
3574             /* SEL_HSPI1 [2] */
3575             FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
3576             /* SEL_I2C3 [1] */
3577             FN_SEL_I2C3_0, FN_SEL_I2C3_1,
3578             /* SEL_I2C2 [2] */
3579             FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
3580             /* SEL_I2C1 [2] */
3581             FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
3582         },
3583         { PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } },
3584         { PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } },
3585         { PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } },
3586         { PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } },
3587         { PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } },
3588         { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } },
3589         { PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) {
3590                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3591                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3592                 0, 0, 0, 0, 0, 0, 0, 0,
3593                 0, 0,
3594                 0, 0,
3595                 0, 0,
3596                 GP_6_8_IN, GP_6_8_OUT,
3597                 GP_6_7_IN, GP_6_7_OUT,
3598                 GP_6_6_IN, GP_6_6_OUT,
3599                 GP_6_5_IN, GP_6_5_OUT,
3600                 GP_6_4_IN, GP_6_4_OUT,
3601                 GP_6_3_IN, GP_6_3_OUT,
3602                 GP_6_2_IN, GP_6_2_OUT,
3603                 GP_6_1_IN, GP_6_1_OUT,
3604                 GP_6_0_IN, GP_6_0_OUT, }
3605         },
3606         { },
3607 };
3608
3609 static const struct pinmux_data_reg pinmux_data_regs[] = {
3610         { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } },
3611         { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } },
3612         { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } },
3613         { PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } },
3614         { PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } },
3615         { PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } },
3616         { PINMUX_DATA_REG("INDT6", 0xffc46008, 32) {
3617                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3618                 0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA,
3619                 GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
3620                 GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
3621         },
3622         { },
3623 };
3624
3625 const struct sh_pfc_soc_info r8a7779_pinmux_info = {
3626         .name = "r8a7779_pfc",
3627
3628         .unlock_reg = 0xfffc0000, /* PMMR */
3629
3630         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
3631         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
3632         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3633
3634         .pins = pinmux_pins,
3635         .nr_pins = ARRAY_SIZE(pinmux_pins),
3636         .groups = pinmux_groups,
3637         .nr_groups = ARRAY_SIZE(pinmux_groups),
3638         .functions = pinmux_functions,
3639         .nr_functions = ARRAY_SIZE(pinmux_functions),
3640
3641         .func_gpios = pinmux_func_gpios,
3642         .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
3643
3644         .cfg_regs = pinmux_config_regs,
3645         .data_regs = pinmux_data_regs,
3646
3647         .gpio_data = pinmux_data,
3648         .gpio_data_size = ARRAY_SIZE(pinmux_data),
3649 };