drivers/pinctrl/sh-pfc/pfc-r8a7791.c

   1 /*
   2  * r8a7791 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2
   8  * as published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/platform_data/gpio-rcar.h>
  13
  14 #include "core.h"
  15 #include "sh_pfc.h"
  16
  17 #define CPU_ALL_PORT(fn, sfx)                                           \
  18         PORT_GP_32(0, fn, sfx),                                         \
  19         PORT_GP_32(1, fn, sfx),                                         \
  20         PORT_GP_32(2, fn, sfx),                                         \
  21         PORT_GP_32(3, fn, sfx),                                         \
  22         PORT_GP_32(4, fn, sfx),                                         \
  23         PORT_GP_32(5, fn, sfx),                                         \
  24         PORT_GP_32(6, fn, sfx),                                         \
  25         PORT_GP_32(7, fn, sfx)
  26
  27 enum {
  28         PINMUX_RESERVED = 0,
  29
  30         PINMUX_DATA_BEGIN,
  31         GP_ALL(DATA),
  32         PINMUX_DATA_END,
  33
  34         PINMUX_FUNCTION_BEGIN,
  35         GP_ALL(FN),
  36
  37         /* GPSR0 */
  38         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  39         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  40         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
  41         FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
  42         FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
  43         FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
  44
  45         /* GPSR1 */
  46         FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
  47         FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
  48         FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
  49         FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
  50         FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
  51         FN_IP3_21_20,
  52
  53         /* GPSR2 */
  54         FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
  55         FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
  56         FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  57         FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
  58         FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
  59         FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
  60         FN_IP6_5_3, FN_IP6_7_6,
  61
  62         /* GPSR3 */
  63         FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
  64         FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
  65         FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
  66         FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
  67         FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
  68         FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
  69         FN_IP9_18_17,
  70
  71         /* GPSR4 */
  72         FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
  73         FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
  74         FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
  75         FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
  76         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
  77         FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
  78         FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
  79         FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
  80
  81         /* GPSR5 */
  82         FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
  83         FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
  84         FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
  85         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
  86         FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
  87         FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
  88         FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
  89
  90         /* GPSR6 */
  91         FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
  92         FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
  93         FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
  94         FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
  95         FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
  96         FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
  97         FN_USB1_OVC, FN_DU0_DOTCLKIN,
  98
  99         /* GPSR7 */
 100         FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
 101         FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
 102         FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
 103         FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
 104         FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
 105         FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
 106
 107         /* IPSR0 */
 108         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
 109         FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
 110         FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
 111         FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
 112         FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
 113         FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
 114
 115         /* IPSR1 */
 116         FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0,
 117         FN_A9, FN_MSIOF1_SS2, FN_SDA0,
 118         FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
 119         FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
 120         FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
 121         FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
 122         FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
 123         FN_A15, FN_BPFCLK_C,
 124         FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
 125         FN_A17, FN_DACK2_B, FN_SDA0_C,
 126         FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
 127
 128         /* IPSR2 */
 129         FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
 130         FN_A20, FN_SPCLK,
 131         FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
 132         FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
 133         FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
 134         FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
 135         FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
 136         FN_CS0_N, FN_ATAG0_N_B, FN_SCL1,
 137         FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1,
 138         FN_EX_CS1_N, FN_MSIOF2_SCK,
 139         FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
 140         FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
 141
 142         /* IPSR3 */
 143         FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
 144         FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
 145         FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
 146         FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
 147         FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
 148         FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
 149         FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
 150         FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
 151         FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
 152         FN_DREQ0, FN_PWM3, FN_TPU_TO3,
 153         FN_DACK0, FN_DRACK0, FN_REMOCON,
 154         FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
 155         FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
 156         FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
 157         FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
 158
 159         /* IPSR4 */
 160         FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C,
 161         FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
 162         FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
 163         FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
 164         FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
 165         FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
 166         FN_GLO_Q1_D, FN_HCTS1_N_E,
 167         FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
 168         FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
 169         FN_SSI_SCK4, FN_GLO_SS_D,
 170         FN_SSI_WS4, FN_GLO_RFON_D,
 171         FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
 172         FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
 173         FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
 174
 175         /* IPSR5 */
 176         FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
 177         FN_MSIOF2_TXD_D, FN_VI1_R3_B,
 178         FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
 179         FN_MSIOF2_SS1_D, FN_VI1_R4_B,
 180         FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
 181         FN_MSIOF2_RXD_D, FN_VI1_R5_B,
 182         FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
 183         FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
 184         FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
 185         FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
 186         FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
 187         FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
 188         FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
 189         FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
 190         FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
 191
 192         /* IPSR6 */
 193         FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
 194         FN_SCIF_CLK, FN_BPFCLK_E,
 195         FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
 196         FN_SCIFA2_RXD, FN_FMIN_E,
 197         FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
 198         FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
 199         FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
 200         FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
 201         FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
 202         FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
 203         FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
 204         FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
 205         FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
 206         FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
 207
 208         /* IPSR7 */
 209         FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
 210         FN_SCIF_CLK_B, FN_GPS_MAG_D,
 211         FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
 212         FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
 213         FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
 214         FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
 215         FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
 216         FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
 217         FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
 218         FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
 219         FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
 220         FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
 221         FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
 222         FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
 223         FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
 224         FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
 225         FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
 226         FN_SCIFA1_SCK, FN_SSI_SCK78_B,
 227
 228         /* IPSR8 */
 229         FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
 230         FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
 231         FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
 232         FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
 233         FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
 234         FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
 235         FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
 236         FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
 237         FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
 238         FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
 239         FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
 240         FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
 241         FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
 242         FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
 243         FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
 244         FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
 245         FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
 246
 247         /* IPSR9 */
 248         FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
 249         FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
 250         FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
 251         FN_DU1_DOTCLKOUT0, FN_QCLK,
 252         FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
 253         FN_TX3_B, FN_SCL2_B, FN_PWM4,
 254         FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
 255         FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
 256         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
 257         FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
 258         FN_DU1_DISP, FN_QPOLA,
 259         FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
 260         FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
 261         FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
 262         FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
 263         FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
 264         FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
 265         FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
 266         FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
 267
 268         /* IPSR10 */
 269         FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
 270         FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
 271         FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
 272         FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
 273         FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
 274         FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
 275         FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
 276         FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
 277         FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
 278         FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
 279         FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
 280         FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
 281         FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
 282         FN_TS_SDATA0_C, FN_ATACS11_N,
 283         FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
 284         FN_TS_SCK0_C, FN_ATAG1_N,
 285         FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
 286         FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
 287         FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
 288
 289         /* IPSR11 */
 290         FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
 291         FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
 292         FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
 293         FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
 294         FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
 295         FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
 296         FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
 297         FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
 298         FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
 299         FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
 300         FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
 301         FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
 302         FN_VI1_DATA7, FN_AVB_MDC,
 303         FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
 304         FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
 305
 306         /* IPSR12 */
 307         FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
 308         FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
 309         FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
 310         FN_SCL2_D, FN_MSIOF1_RXD_E,
 311         FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
 312         FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
 313         FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
 314         FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
 315         FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
 316         FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
 317         FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
 318         FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
 319         FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
 320         FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
 321         FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
 322         FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
 323         FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
 324
 325         /* IPSR13 */
 326         FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
 327         FN_ADICLK_B, FN_MSIOF0_SS1_C,
 328         FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
 329         FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
 330         FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
 331         FN_ADICHS2_B, FN_MSIOF0_TXD_C,
 332         FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
 333         FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
 334         FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
 335         FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
 336         FN_SCIFA5_TXD_B, FN_TX3_C,
 337         FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
 338         FN_SCIFA5_RXD_B, FN_RX3_C,
 339         FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
 340         FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
 341         FN_SD1_DATA3, FN_IERX_B,
 342         FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
 343
 344         /* IPSR14 */
 345         FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
 346         FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
 347         FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
 348         FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
 349         FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
 350         FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
 351         FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
 352         FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
 353         FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
 354         FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
 355         FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
 356         FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
 357         FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
 358         FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
 359
 360         /* IPSR15 */
 361         FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
 362         FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
 363         FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
 364         FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
 365         FN_PWM5_B, FN_SCIFA3_TXD_C,
 366         FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
 367         FN_VI1_G6_B, FN_SCIFA3_RXD_C,
 368         FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
 369         FN_VI1_G7_B, FN_SCIFA3_SCK_C,
 370         FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
 371         FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
 372         FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
 373         FN_TCLK2, FN_VI1_DATA3_C,
 374         FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
 375         FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
 376
 377         /* IPSR16 */
 378         FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
 379         FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
 380         FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
 381         FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
 382         FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
 383
 384         /* MOD_SEL */
 385         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 386         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
 387         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
 388         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 389         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
 390         FN_SEL_SSI9_0, FN_SEL_SSI9_1,
 391         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 392         FN_SEL_QSP_0, FN_SEL_QSP_1,
 393         FN_SEL_SSI7_0, FN_SEL_SSI7_1,
 394         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
 395         FN_SEL_HSCIF1_4,
 396         FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
 397         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 398         FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
 399         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 400         FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
 401
 402         /* MOD_SEL2 */
 403         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 404         FN_SEL_SCIF0_4,
 405         FN_SEL_SCIF_0, FN_SEL_SCIF_1,
 406         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 407         FN_SEL_CAN0_4, FN_SEL_CAN0_5,
 408         FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
 409         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 410         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
 411         FN_SEL_ADG_0, FN_SEL_ADG_1,
 412         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
 413         FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
 414         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
 415         FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
 416         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
 417         FN_SEL_SIM_0, FN_SEL_SIM_1,
 418         FN_SEL_SSI8_0, FN_SEL_SSI8_1,
 419
 420         /* MOD_SEL3 */
 421         FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
 422         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
 423         FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
 424         FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
 425         FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
 426         FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
 427         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
 428         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 429         FN_SEL_MMC_0, FN_SEL_MMC_1,
 430         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
 431         FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
 432         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
 433         FN_SEL_IIC1_4,
 434         FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
 435
 436         /* MOD_SEL4 */
 437         FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
 438         FN_SEL_SOF1_4,
 439         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
 440         FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
 441         FN_SEL_RAD_0, FN_SEL_RAD_1,
 442         FN_SEL_RCN_0, FN_SEL_RCN_1,
 443         FN_SEL_RSP_0, FN_SEL_RSP_1,
 444         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
 445         FN_SEL_SCIF2_4,
 446         FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
 447         FN_SEL_SOF2_4,
 448         FN_SEL_SSI1_0, FN_SEL_SSI1_1,
 449         FN_SEL_SSI0_0, FN_SEL_SSI0_1,
 450         FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
 451         PINMUX_FUNCTION_END,
 452
 453         PINMUX_MARK_BEGIN,
 454
 455         EX_CS0_N_MARK, RD_N_MARK,
 456
 457         AUDIO_CLKA_MARK,
 458
 459         VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
 460         VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
 461         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
 462
 463         SD1_CLK_MARK,
 464
 465         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 466         DU0_DOTCLKIN_MARK,
 467
 468         /* IPSR0 */
 469         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
 470         D6_MARK, D7_MARK, D8_MARK,
 471         D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
 472         A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK,
 473         A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
 474         A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
 475         A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
 476
 477         /* IPSR1 */
 478         A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK,
 479         A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK,
 480         A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
 481         A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK,
 482         A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK,
 483         A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
 484         A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
 485         A15_MARK, BPFCLK_C_MARK,
 486         A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
 487         A17_MARK, DACK2_B_MARK, SDA0_C_MARK,
 488         A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
 489
 490         /* IPSR2 */
 491         A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
 492         SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
 493         A20_MARK, SPCLK_MARK,
 494         A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
 495         A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
 496         A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
 497         A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
 498         A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
 499         RX1_MARK, SCIFA1_RXD_MARK,
 500         CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK,
 501         CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK,
 502         EX_CS1_N_MARK, MSIOF2_SCK_MARK,
 503         EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
 504         EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
 505         ATAG0_N_MARK, EX_WAIT1_MARK,
 506
 507         /* IPSR3 */
 508         EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
 509         EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
 510         SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
 511         BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
 512         SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
 513         RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
 514         SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
 515         WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
 516         WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
 517         EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
 518         DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
 519         DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
 520         SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
 521         SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
 522         SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
 523         SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
 524         SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
 525         SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
 526
 527         /* IPSR4 */
 528         SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK,
 529         SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK,
 530         MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
 531         SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK,
 532         MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
 533         SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK,
 534         SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK,
 535         SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
 536         GLO_Q1_D_MARK, HCTS1_N_E_MARK,
 537         SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
 538         SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
 539         SSI_SCK4_MARK, GLO_SS_D_MARK,
 540         SSI_WS4_MARK, GLO_RFON_D_MARK,
 541         SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
 542         SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
 543         MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
 544
 545         /* IPSR5 */
 546         SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
 547         MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
 548         SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
 549         MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
 550         SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
 551         MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
 552         SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
 553         SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
 554         SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
 555         SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
 556         SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
 557         SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
 558         SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
 559         SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
 560         SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
 561
 562         /* IPSR6 */
 563         AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
 564         SCIF_CLK_MARK, BPFCLK_E_MARK,
 565         AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
 566         SCIFA2_RXD_MARK, FMIN_E_MARK,
 567         AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
 568         IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
 569         IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
 570         IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
 571         IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
 572         IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
 573         MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
 574         IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
 575         IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
 576         SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
 577         IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
 578         GPS_CLK_C_MARK, GPS_CLK_D_MARK,
 579         IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
 580         GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
 581
 582         /* IPSR7 */
 583         IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
 584         SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
 585         DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
 586         SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
 587         DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
 588         SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
 589         DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
 590         DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
 591         DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
 592         DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
 593         DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
 594         DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
 595         DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
 596         SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
 597         DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
 598         SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
 599         DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
 600         SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
 601
 602         /* IPSR8 */
 603         DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
 604         DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
 605         SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
 606         DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
 607         SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
 608         DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
 609         SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
 610         DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
 611         SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
 612         DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
 613         SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
 614         DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
 615         SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
 616         DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
 617         SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
 618         DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
 619         DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
 620         DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
 621
 622         /* IPSR9 */
 623         DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
 624         DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK,
 625         SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
 626         DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
 627         DU1_DOTCLKOUT0_MARK, QCLK_MARK,
 628         DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
 629         TX3_B_MARK, SCL2_B_MARK, PWM4_MARK,
 630         DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
 631         DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
 632         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 633         CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK,
 634         DU1_DISP_MARK, QPOLA_MARK,
 635         DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
 636         VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
 637         VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
 638         VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
 639         VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
 640         VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
 641         VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK,
 642         HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
 643
 644         /* IPSR10 */
 645         VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK,
 646         HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
 647         VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK,
 648         HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
 649         VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK,
 650         HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
 651         VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
 652         HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
 653         VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
 654         CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
 655         VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
 656         VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
 657         VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
 658         TS_SDATA0_C_MARK, ATACS11_N_MARK,
 659         VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
 660         TS_SCK0_C_MARK, ATAG1_N_MARK,
 661         VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
 662         VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
 663         VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK,
 664
 665         /* IPSR11 */
 666         VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
 667         VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
 668         VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
 669         SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
 670         VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
 671         TX4_B_MARK, SCIFA4_TXD_B_MARK,
 672         VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
 673         RX4_B_MARK, SCIFA4_RXD_B_MARK,
 674         VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
 675         VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
 676         VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
 677         VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
 678         VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
 679         VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
 680         VI1_DATA7_MARK, AVB_MDC_MARK,
 681         ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
 682         ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
 683
 684         /* IPSR12 */
 685         ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
 686         ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
 687         ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
 688         SCL2_D_MARK, MSIOF1_RXD_E_MARK,
 689         ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
 690         SDA2_D_MARK, MSIOF1_SCK_E_MARK,
 691         ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
 692         CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
 693         ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
 694         CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
 695         ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
 696         ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
 697         ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
 698         ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
 699         STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
 700         ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
 701         STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
 702         ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
 703
 704         /* IPSR13 */
 705         STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
 706         ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
 707         STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
 708         STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
 709         STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
 710         ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
 711         SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
 712         SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
 713         SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
 714         SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
 715         SCIFA5_TXD_B_MARK, TX3_C_MARK,
 716         SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
 717         SCIFA5_RXD_B_MARK, RX3_C_MARK,
 718         SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
 719         SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
 720         SD1_DATA3_MARK, IERX_B_MARK,
 721         SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
 722
 723         /* IPSR14 */
 724         SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
 725         SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
 726         SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
 727         SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
 728         SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
 729         SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
 730         MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
 731         VI1_CLK_C_MARK, VI1_G0_B_MARK,
 732         MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
 733         VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
 734         MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
 735         MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
 736         MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
 737         VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
 738         MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
 739         VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
 740
 741         /* IPSR15 */
 742         SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
 743         SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
 744         SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
 745         GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
 746         PWM5_B_MARK, SCIFA3_TXD_C_MARK,
 747         GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
 748         VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
 749         GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
 750         VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
 751         HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
 752         TCLK1_MARK, VI1_DATA1_C_MARK,
 753         HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
 754         HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
 755         TCLK2_MARK, VI1_DATA3_C_MARK,
 756         HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
 757         CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
 758         HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
 759         CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
 760
 761         /* IPSR16 */
 762         HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
 763         GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
 764         HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
 765         GLO_SS_C_MARK, VI1_DATA7_C_MARK,
 766         HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK,
 767         HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
 768         HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
 769         PINMUX_MARK_END,
 770 };
 771
 772 static const u16 pinmux_data[] = {
 773         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 774
 775         PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
 776         PINMUX_DATA(RD_N_MARK, FN_RD_N),
 777         PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
 778         PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
 779         PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
 780         PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1),
 781         PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2),
 782         PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4),
 783         PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5),
 784         PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6),
 785         PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7),
 786         PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
 787         PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
 788         PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
 789         PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
 790         PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN),
 791
 792         /* IPSR0 */
 793         PINMUX_IPSR_DATA(IP0_0, D0),
 794         PINMUX_IPSR_DATA(IP0_1, D1),
 795         PINMUX_IPSR_DATA(IP0_2, D2),
 796         PINMUX_IPSR_DATA(IP0_3, D3),
 797         PINMUX_IPSR_DATA(IP0_4, D4),
 798         PINMUX_IPSR_DATA(IP0_5, D5),
 799         PINMUX_IPSR_DATA(IP0_6, D6),
 800         PINMUX_IPSR_DATA(IP0_7, D7),
 801         PINMUX_IPSR_DATA(IP0_8, D8),
 802         PINMUX_IPSR_DATA(IP0_9, D9),
 803         PINMUX_IPSR_DATA(IP0_10, D10),
 804         PINMUX_IPSR_DATA(IP0_11, D11),
 805         PINMUX_IPSR_DATA(IP0_12, D12),
 806         PINMUX_IPSR_DATA(IP0_13, D13),
 807         PINMUX_IPSR_DATA(IP0_14, D14),
 808         PINMUX_IPSR_DATA(IP0_15, D15),
 809         PINMUX_IPSR_DATA(IP0_18_16, A0),
 810         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
 811         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
 812         PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SCL0_C, SEL_IIC0_2),
 813         PINMUX_IPSR_DATA(IP0_18_16, PWM2_B),
 814         PINMUX_IPSR_DATA(IP0_20_19, A1),
 815         PINMUX_IPSR_MODSEL_DATA(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
 816         PINMUX_IPSR_DATA(IP0_22_21, A2),
 817         PINMUX_IPSR_MODSEL_DATA(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
 818         PINMUX_IPSR_DATA(IP0_24_23, A3),
 819         PINMUX_IPSR_MODSEL_DATA(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
 820         PINMUX_IPSR_DATA(IP0_26_25, A4),
 821         PINMUX_IPSR_MODSEL_DATA(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
 822         PINMUX_IPSR_DATA(IP0_28_27, A5),
 823         PINMUX_IPSR_MODSEL_DATA(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
 824         PINMUX_IPSR_DATA(IP0_30_29, A6),
 825         PINMUX_IPSR_MODSEL_DATA(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
 826
 827         /* IPSR1 */
 828         PINMUX_IPSR_DATA(IP1_1_0, A7),
 829         PINMUX_IPSR_MODSEL_DATA(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
 830         PINMUX_IPSR_DATA(IP1_3_2, A8),
 831         PINMUX_IPSR_MODSEL_DATA(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
 832         PINMUX_IPSR_MODSEL_DATA(IP1_3_2, SCL0, SEL_IIC0_0),
 833         PINMUX_IPSR_DATA(IP1_5_4, A9),
 834         PINMUX_IPSR_MODSEL_DATA(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
 835         PINMUX_IPSR_MODSEL_DATA(IP1_5_4, SDA0, SEL_IIC0_0),
 836         PINMUX_IPSR_DATA(IP1_7_6, A10),
 837         PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
 838         PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
 839         PINMUX_IPSR_DATA(IP1_10_8, A11),
 840         PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
 841         PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCL3_D, SEL_IIC3_3),
 842         PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
 843         PINMUX_IPSR_DATA(IP1_13_11, A12),
 844         PINMUX_IPSR_MODSEL_DATA(IP1_13_11, FMCLK, SEL_FM_0),
 845         PINMUX_IPSR_MODSEL_DATA(IP1_13_11, SDA3_D, SEL_IIC3_3),
 846         PINMUX_IPSR_MODSEL_DATA(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
 847         PINMUX_IPSR_DATA(IP1_16_14, A13),
 848         PINMUX_IPSR_MODSEL_DATA(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
 849         PINMUX_IPSR_MODSEL_DATA(IP1_16_14, BPFCLK, SEL_FM_0),
 850         PINMUX_IPSR_MODSEL_DATA(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
 851         PINMUX_IPSR_DATA(IP1_19_17, A14),
 852         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
 853         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN, SEL_FM_0),
 854         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN_C, SEL_FM_2),
 855         PINMUX_IPSR_MODSEL_DATA(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
 856         PINMUX_IPSR_DATA(IP1_22_20, A15),
 857         PINMUX_IPSR_MODSEL_DATA(IP1_22_20, BPFCLK_C, SEL_FM_2),
 858         PINMUX_IPSR_DATA(IP1_25_23, A16),
 859         PINMUX_IPSR_MODSEL_DATA(IP1_25_23, DREQ2_B, SEL_LBS_1),
 860         PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FMCLK_C, SEL_FM_2),
 861         PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
 862         PINMUX_IPSR_DATA(IP1_28_26, A17),
 863         PINMUX_IPSR_MODSEL_DATA(IP1_28_26, DACK2_B, SEL_LBS_1),
 864         PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SDA0_C, SEL_IIC0_2),
 865         PINMUX_IPSR_DATA(IP1_31_29, A18),
 866         PINMUX_IPSR_MODSEL_DATA(IP1_31_29, DREQ1, SEL_LBS_0),
 867         PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
 868         PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
 869
 870         /* IPSR2 */
 871         PINMUX_IPSR_DATA(IP2_2_0, A19),
 872         PINMUX_IPSR_DATA(IP2_2_0, DACK1),
 873         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
 874         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
 875         PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_0),
 876         PINMUX_IPSR_DATA(IP2_2_0, A20),
 877         PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0),
 878         PINMUX_IPSR_DATA(IP2_6_5, A21),
 879         PINMUX_IPSR_MODSEL_DATA(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
 880         PINMUX_IPSR_MODSEL_DATA(IP2_6_5, MOSI_IO0, SEL_QSP_0),
 881         PINMUX_IPSR_DATA(IP2_9_7, A22),
 882         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, MISO_IO1, SEL_QSP_0),
 883         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, FMCLK_B, SEL_FM_1),
 884         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, TX0, SEL_SCIF0_0),
 885         PINMUX_IPSR_MODSEL_DATA(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
 886         PINMUX_IPSR_DATA(IP2_12_10, A23),
 887         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, IO2, SEL_QSP_0),
 888         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, BPFCLK_B, SEL_FM_1),
 889         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, RX0, SEL_SCIF0_0),
 890         PINMUX_IPSR_MODSEL_DATA(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
 891         PINMUX_IPSR_DATA(IP2_15_13, A24),
 892         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, DREQ2, SEL_LBS_0),
 893         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, IO3, SEL_QSP_0),
 894         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, TX1, SEL_SCIF1_0),
 895         PINMUX_IPSR_MODSEL_DATA(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
 896         PINMUX_IPSR_DATA(IP2_18_16, A25),
 897         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DACK2, SEL_LBS_0),
 898         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SSL, SEL_QSP_0),
 899         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ1_C, SEL_LBS_2),
 900         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, RX1, SEL_SCIF1_0),
 901         PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
 902         PINMUX_IPSR_DATA(IP2_20_19, CS0_N),
 903         PINMUX_IPSR_MODSEL_DATA(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
 904         PINMUX_IPSR_MODSEL_DATA(IP2_20_19, SCL1, SEL_IIC1_0),
 905         PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26),
 906         PINMUX_IPSR_MODSEL_DATA(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
 907         PINMUX_IPSR_MODSEL_DATA(IP2_22_21, SDA1, SEL_IIC1_0),
 908         PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N),
 909         PINMUX_IPSR_MODSEL_DATA(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
 910         PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N),
 911         PINMUX_IPSR_MODSEL_DATA(IP2_26_25, ATAWR0_N, SEL_LBS_0),
 912         PINMUX_IPSR_MODSEL_DATA(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
 913         PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N),
 914         PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATADIR0_N, SEL_LBS_0),
 915         PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
 916         PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATAG0_N, SEL_LBS_0),
 917         PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1),
 918
 919         /* IPSR3 */
 920         PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N),
 921         PINMUX_IPSR_MODSEL_DATA(IP3_2_0, ATARD0_N, SEL_LBS_0),
 922         PINMUX_IPSR_MODSEL_DATA(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
 923         PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2),
 924         PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N),
 925         PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N),
 926         PINMUX_IPSR_MODSEL_DATA(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
 927         PINMUX_IPSR_MODSEL_DATA(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
 928         PINMUX_IPSR_MODSEL_DATA(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
 929         PINMUX_IPSR_DATA(IP3_5_3, PWM1),
 930         PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1),
 931         PINMUX_IPSR_DATA(IP3_8_6, BS_N),
 932         PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N),
 933         PINMUX_IPSR_MODSEL_DATA(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
 934         PINMUX_IPSR_MODSEL_DATA(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
 935         PINMUX_IPSR_MODSEL_DATA(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
 936         PINMUX_IPSR_DATA(IP3_8_6, PWM2),
 937         PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2),
 938         PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N),
 939         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
 940         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, FMIN_B, SEL_FM_1),
 941         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
 942         PINMUX_IPSR_MODSEL_DATA(IP3_11_9, DREQ1_D, SEL_LBS_1),
 943         PINMUX_IPSR_DATA(IP3_13_12, WE0_N),
 944         PINMUX_IPSR_MODSEL_DATA(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
 945         PINMUX_IPSR_MODSEL_DATA(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
 946         PINMUX_IPSR_DATA(IP3_15_14, WE1_N),
 947         PINMUX_IPSR_MODSEL_DATA(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
 948         PINMUX_IPSR_MODSEL_DATA(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
 949         PINMUX_IPSR_MODSEL_DATA(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
 950         PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0),
 951         PINMUX_IPSR_MODSEL_DATA(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
 952         PINMUX_IPSR_MODSEL_DATA(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
 953         PINMUX_IPSR_DATA(IP3_19_18, DREQ0),
 954         PINMUX_IPSR_DATA(IP3_19_18, PWM3),
 955         PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3),
 956         PINMUX_IPSR_DATA(IP3_21_20, DACK0),
 957         PINMUX_IPSR_DATA(IP3_21_20, DRACK0),
 958         PINMUX_IPSR_MODSEL_DATA(IP3_21_20, REMOCON, SEL_RCN_0),
 959         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SPEEDIN, SEL_RSP_0),
 960         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
 961         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
 962         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
 963         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
 964         PINMUX_IPSR_MODSEL_DATA(IP3_24_22, DREQ2_C, SEL_LBS_2),
 965         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 966         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
 967         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
 968         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
 969         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
 970         PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
 971         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
 972         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
 973         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
 974         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
 975         PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
 976
 977         /* IPSR4 */
 978         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
 979         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL0_B, SEL_IIC0_1),
 980         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL7_B, SEL_IIC7_1),
 981         PINMUX_IPSR_MODSEL_DATA(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
 982         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
 983         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA0_B, SEL_IIC0_1),
 984         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA7_B, SEL_IIC7_1),
 985         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
 986         PINMUX_IPSR_MODSEL_DATA(IP4_4_2, GLO_I0_D, SEL_GPS_3),
 987         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SSI_WS1, SEL_SSI1_0),
 988         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL1_B, SEL_IIC1_1),
 989         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL8_B, SEL_IIC8_1),
 990         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
 991         PINMUX_IPSR_MODSEL_DATA(IP4_7_5, GLO_I1_D, SEL_GPS_3),
 992         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
 993         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA1_B, SEL_IIC1_1),
 994         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA8_B, SEL_IIC8_1),
 995         PINMUX_IPSR_MODSEL_DATA(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
 996         PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2),
 997         PINMUX_IPSR_MODSEL_DATA(IP4_12_10, SCL2, SEL_IIC2_0),
 998         PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
 999         PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1000         PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2),
1001         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, SDA2, SEL_IIC2_0),
1002         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1003         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, RX2_E, SEL_SCIF2_4),
1004         PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1005         PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2),
1006         PINMUX_IPSR_MODSEL_DATA(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1007         PINMUX_IPSR_MODSEL_DATA(IP4_18_16, TX2_E, SEL_SCIF2_4),
1008         PINMUX_IPSR_DATA(IP4_19, SSI_SCK34),
1009         PINMUX_IPSR_DATA(IP4_20, SSI_WS34),
1010         PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3),
1011         PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4),
1012         PINMUX_IPSR_MODSEL_DATA(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1013         PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4),
1014         PINMUX_IPSR_MODSEL_DATA(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1015         PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4),
1016         PINMUX_IPSR_MODSEL_DATA(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1017         PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5),
1018         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1019         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1020         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, GLO_I0, SEL_GPS_0),
1021         PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1022         PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B),
1023
1024         /* IPSR5 */
1025         PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5),
1026         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1027         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1028         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, GLO_I1, SEL_GPS_0),
1029         PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1030         PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B),
1031         PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5),
1032         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1033         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1034         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, GLO_Q0, SEL_GPS_0),
1035         PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1036         PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B),
1037         PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6),
1038         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1039         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1040         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, GLO_Q1, SEL_GPS_0),
1041         PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1042         PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B),
1043         PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6),
1044         PINMUX_IPSR_MODSEL_DATA(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1045         PINMUX_IPSR_MODSEL_DATA(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1046         PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B),
1047         PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6),
1048         PINMUX_IPSR_MODSEL_DATA(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1049         PINMUX_IPSR_MODSEL_DATA(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1050         PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B),
1051         PINMUX_IPSR_MODSEL_DATA(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1052         PINMUX_IPSR_MODSEL_DATA(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1053         PINMUX_IPSR_MODSEL_DATA(IP5_16_15, GLO_SS, SEL_GPS_0),
1054         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1055         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, TX0_D, SEL_SCIF0_3),
1056         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1057         PINMUX_IPSR_MODSEL_DATA(IP5_19_17, GLO_RFON, SEL_GPS_0),
1058         PINMUX_IPSR_MODSEL_DATA(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1059         PINMUX_IPSR_MODSEL_DATA(IP5_21_20, RX0_D, SEL_SCIF0_3),
1060         PINMUX_IPSR_MODSEL_DATA(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1061         PINMUX_IPSR_MODSEL_DATA(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1062         PINMUX_IPSR_MODSEL_DATA(IP5_23_22, TX1_D, SEL_SCIF1_3),
1063         PINMUX_IPSR_MODSEL_DATA(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1064         PINMUX_IPSR_MODSEL_DATA(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1065         PINMUX_IPSR_MODSEL_DATA(IP5_25_24, RX1_D, SEL_SCIF1_3),
1066         PINMUX_IPSR_MODSEL_DATA(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1067         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1068         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, TX3_D, SEL_SCIF3_3),
1069         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1070         PINMUX_IPSR_MODSEL_DATA(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1071         PINMUX_IPSR_MODSEL_DATA(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1072         PINMUX_IPSR_MODSEL_DATA(IP5_31_29, RX3_D, SEL_SCIF3_3),
1073         PINMUX_IPSR_MODSEL_DATA(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1074
1075         /* IPSR6 */
1076         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1077         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1078         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1079         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1080         PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4),
1081         PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
1082         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1083         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1084         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0),
1085         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1086         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4),
1087         PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
1088         PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1089         PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0),
1090         PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1091         PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
1092         PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1093         PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
1094         PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
1095         PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1096         PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
1097         PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
1098         PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1099         PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
1100         PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
1101         PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2),
1102         PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1103         PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
1104         PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
1105         PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1106         PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2),
1107         PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1108         PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
1109         PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
1110         PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1111         PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4),
1112         PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1113         PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
1114         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1115         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1116         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4),
1117         PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1118         PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
1119         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1120         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1121         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1122         PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1123         PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
1124         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1125         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1126         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1127         PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1128
1129         /* IPSR7 */
1130         PINMUX_IPSR_DATA(IP7_2_0, IRQ9),
1131         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1132         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1133         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1134         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1135         PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1136         PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0),
1137         PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0),
1138         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1139         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TX0_B, SEL_SCIF0_1),
1140         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1141         PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1142         PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1),
1143         PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1),
1144         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1145         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX0_B, SEL_SCIF0_1),
1146         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1147         PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1148         PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2),
1149         PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2),
1150         PINMUX_IPSR_MODSEL_DATA(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1151         PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3),
1152         PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3),
1153         PINMUX_IPSR_MODSEL_DATA(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1154         PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4),
1155         PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4),
1156         PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1157         PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5),
1158         PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5),
1159         PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1160         PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6),
1161         PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6),
1162         PINMUX_IPSR_MODSEL_DATA(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1163         PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7),
1164         PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7),
1165         PINMUX_IPSR_MODSEL_DATA(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1166         PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0),
1167         PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8),
1168         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1169         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX1_B, SEL_SCIF1_1),
1170         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1171         PINMUX_IPSR_MODSEL_DATA(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1172         PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1),
1173         PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9),
1174         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1175         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX1_B, SEL_SCIF1_1),
1176         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1177         PINMUX_IPSR_MODSEL_DATA(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1178         PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2),
1179         PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10),
1180         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1181         PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B),
1182         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1183         PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1184
1185         /* IPSR8 */
1186         PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3),
1187         PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11),
1188         PINMUX_IPSR_MODSEL_DATA(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1189         PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1190         PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4),
1191         PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12),
1192         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1193         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1194         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1195         PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1196         PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5),
1197         PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13),
1198         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1199         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1200         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1201         PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1202         PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6),
1203         PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14),
1204         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1205         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1206         PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1207         PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7),
1208         PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15),
1209         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1210         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1211         PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1212         PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0),
1213         PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16),
1214         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1215         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, TX2_B, SEL_SCIF2_1),
1216         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1217         PINMUX_IPSR_MODSEL_DATA(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1218         PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1),
1219         PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17),
1220         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1221         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, RX2_B, SEL_SCIF2_1),
1222         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1223         PINMUX_IPSR_MODSEL_DATA(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1224         PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2),
1225         PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18),
1226         PINMUX_IPSR_MODSEL_DATA(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1227         PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B),
1228         PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1229         PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1230         PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3),
1231         PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19),
1232         PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1233         PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4),
1234         PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20),
1235         PINMUX_IPSR_MODSEL_DATA(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1236         PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1237         PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5),
1238         PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21),
1239         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, TX3, SEL_SCIF3_0),
1240         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1241         PINMUX_IPSR_MODSEL_DATA(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1242
1243         /* IPSR9 */
1244         PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6),
1245         PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22),
1246         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCL3_C, SEL_IIC3_2),
1247         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RX3, SEL_SCIF3_0),
1248         PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1249         PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7),
1250         PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23),
1251         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SDA3_C, SEL_IIC3_2),
1252         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1253         PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1254         PINMUX_IPSR_MODSEL_DATA(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1255         PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS),
1256         PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0),
1257         PINMUX_IPSR_DATA(IP9_7, QCLK),
1258         PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1),
1259         PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE),
1260         PINMUX_IPSR_MODSEL_DATA(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1261         PINMUX_IPSR_MODSEL_DATA(IP9_10_8, TX3_B, SEL_SCIF3_1),
1262         PINMUX_IPSR_MODSEL_DATA(IP9_10_8, SCL2_B, SEL_IIC2_1),
1263         PINMUX_IPSR_DATA(IP9_10_8, PWM4),
1264         PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1265         PINMUX_IPSR_DATA(IP9_11, QSTH_QHS),
1266         PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1267         PINMUX_IPSR_DATA(IP9_12, QSTB_QHE),
1268         PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1269         PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE),
1270         PINMUX_IPSR_MODSEL_DATA(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1271         PINMUX_IPSR_MODSEL_DATA(IP9_15_13, RX3_B, SEL_SCIF3_1),
1272         PINMUX_IPSR_MODSEL_DATA(IP9_15_13, SDA2_B, SEL_IIC2_1),
1273         PINMUX_IPSR_DATA(IP9_16, DU1_DISP),
1274         PINMUX_IPSR_DATA(IP9_16, QPOLA),
1275         PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE),
1276         PINMUX_IPSR_DATA(IP9_18_17, QPOLB),
1277         PINMUX_IPSR_DATA(IP9_18_17, PWM4_B),
1278         PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB),
1279         PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TX4, SEL_SCIF4_0),
1280         PINMUX_IPSR_MODSEL_DATA(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1281         PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1282         PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD),
1283         PINMUX_IPSR_MODSEL_DATA(IP9_22_21, RX4, SEL_SCIF4_0),
1284         PINMUX_IPSR_MODSEL_DATA(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1285         PINMUX_IPSR_MODSEL_DATA(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1286         PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N),
1287         PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TX5, SEL_SCIF5_0),
1288         PINMUX_IPSR_MODSEL_DATA(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1289         PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1290         PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N),
1291         PINMUX_IPSR_MODSEL_DATA(IP9_26_25, RX5, SEL_SCIF5_0),
1292         PINMUX_IPSR_MODSEL_DATA(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1293         PINMUX_IPSR_MODSEL_DATA(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1294         PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3),
1295         PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1296         PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1297         PINMUX_IPSR_DATA(IP9_31_29, VI0_G0),
1298         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL8, SEL_IIC8_0),
1299         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1300         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL4, SEL_IIC4_0),
1301         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1302         PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1303         PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N),
1304
1305         /* IPSR10 */
1306         PINMUX_IPSR_DATA(IP10_2_0, VI0_G1),
1307         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA8, SEL_IIC8_0),
1308         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1309         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA4, SEL_IIC4_0),
1310         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1311         PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1312         PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N),
1313         PINMUX_IPSR_DATA(IP10_5_3, VI0_G2),
1314         PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N),
1315         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1316         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCL3_B, SEL_IIC3_1),
1317         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1318         PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1319         PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N),
1320         PINMUX_IPSR_DATA(IP10_8_6, VI0_G3),
1321         PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N),
1322         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1323         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SDA3_B, SEL_IIC3_1),
1324         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX2, SEL_HSCIF2_0),
1325         PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1326         PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N),
1327         PINMUX_IPSR_DATA(IP10_11_9, VI0_G4),
1328         PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB),
1329         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1330         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX2, SEL_HSCIF2_0),
1331         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1332         PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1333         PINMUX_IPSR_DATA(IP10_14_12, VI0_G5),
1334         PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD),
1335         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1336         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, FMCLK_D, SEL_FM_3),
1337         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1338         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1339         PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1340         PINMUX_IPSR_DATA(IP10_16_15, VI0_G6),
1341         PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK),
1342         PINMUX_IPSR_MODSEL_DATA(IP10_16_15, BPFCLK_D, SEL_FM_3),
1343         PINMUX_IPSR_DATA(IP10_18_17, VI0_G7),
1344         PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0),
1345         PINMUX_IPSR_MODSEL_DATA(IP10_18_17, FMIN_D, SEL_FM_3),
1346         PINMUX_IPSR_DATA(IP10_21_19, VI0_R0),
1347         PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1),
1348         PINMUX_IPSR_MODSEL_DATA(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1349         PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1350         PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N),
1351         PINMUX_IPSR_DATA(IP10_24_22, VI0_R1),
1352         PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2),
1353         PINMUX_IPSR_MODSEL_DATA(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1354         PINMUX_IPSR_MODSEL_DATA(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1355         PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N),
1356         PINMUX_IPSR_DATA(IP10_26_25, VI0_R2),
1357         PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3),
1358         PINMUX_IPSR_MODSEL_DATA(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1359         PINMUX_IPSR_MODSEL_DATA(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1360         PINMUX_IPSR_DATA(IP10_28_27, VI0_R3),
1361         PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4),
1362         PINMUX_IPSR_MODSEL_DATA(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1363         PINMUX_IPSR_MODSEL_DATA(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1364         PINMUX_IPSR_DATA(IP10_31_29, VI0_R4),
1365         PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5),
1366         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1367         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, TX0_C, SEL_SCIF0_2),
1368         PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL1_D, SEL_IIC1_3),
1369
1370         /* IPSR11 */
1371         PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
1372         PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
1373         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1374         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
1375         PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
1376         PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
1377         PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
1378         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1379         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
1380         PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
1381         PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
1382         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1383         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
1384         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1385         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
1386         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1387         PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1388         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1389         PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
1390         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1391         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
1392         PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1393         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1394         PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
1395         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1396         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
1397         PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1398         PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1399         PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
1400         PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1401         PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1402         PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
1403         PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1404         PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
1405         PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
1406         PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
1407         PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
1408         PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
1409         PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
1410         PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
1411         PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
1412         PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
1413         PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
1414         PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
1415         PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
1416         PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
1417         PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
1418         PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
1419         PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
1420         PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
1421         PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
1422         PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
1423         PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
1424         PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
1425         PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
1426         PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
1427         PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
1428
1429         /* IPSR12 */
1430         PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
1431         PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
1432         PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
1433         PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
1434         PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
1435         PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
1436         PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
1437         PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
1438         PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
1439         PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
1440         PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1441         PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
1442         PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1443         PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
1444         PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
1445         PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1446         PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
1447         PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1448         PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
1449         PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
1450         PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1451         PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1452         PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1453         PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
1454         PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
1455         PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1456         PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1457         PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1458         PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
1459         PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
1460         PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1461         PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1462         PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
1463         PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
1464         PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
1465         PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
1466         PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
1467         PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
1468         PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
1469         PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
1470         PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
1471         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1472         PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
1473         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1474         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1475         PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1476         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1477         PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
1478         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1479         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1480         PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1481
1482         /* IPSR13 */
1483         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1484         PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
1485         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1486         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1),
1487         PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1488         PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1489         PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
1490         PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1491         PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1492         PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1493         PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
1494         PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1495         PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1496         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1497         PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
1498         PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
1499         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1500         PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1501         PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
1502         PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1),
1503         PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
1504         PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1505         PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
1506         PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1),
1507         PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
1508         PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1),
1509         PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
1510         PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1),
1511         PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
1512         PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1),
1513         PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
1514         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1515         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1516         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1517         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1518         PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2),
1519         PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
1520         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1521         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1522         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1523         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1524         PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2),
1525         PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
1526         PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1),
1527         PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
1528         PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1529         PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
1530         PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1),
1531         PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
1532         PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1),
1533         PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
1534         PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1),
1535         PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
1536         PINMUX_IPSR_DATA(IP13_30_28, PWM0),
1537         PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
1538         PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2),
1539
1540         /* IPSR14 */
1541         PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
1542         PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
1543         PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2),
1544         PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
1545         PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
1546         PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
1547         PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
1548         PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
1549         PINMUX_IPSR_DATA(IP14_4, MMC_D0),
1550         PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
1551         PINMUX_IPSR_DATA(IP14_5, MMC_D1),
1552         PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
1553         PINMUX_IPSR_DATA(IP14_6, MMC_D2),
1554         PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
1555         PINMUX_IPSR_DATA(IP14_7, MMC_D3),
1556         PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
1557         PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
1558         PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2),
1559         PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1),
1560         PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1561         PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
1562         PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
1563         PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2),
1564         PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1),
1565         PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1566         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1567         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2),
1568         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0),
1569         PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1570         PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
1571         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1572         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2),
1573         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1574         PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1575         PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
1576         PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1577         PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0),
1578         PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1579         PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
1580         PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1581         PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0),
1582         PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1583         PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
1584         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1585         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0),
1586         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0),
1587         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4),
1588         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1589         PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2),
1590         PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
1591         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1592         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0),
1593         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0),
1594         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4),
1595         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1596         PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2),
1597         PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
1598
1599         /* IPSR15 */
1600         PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0),
1601         PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0),
1602         PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1603         PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
1604         PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0),
1605         PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1606         PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0),
1607         PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0),
1608         PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1609         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0),
1610         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1611         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1612         PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
1613         PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1614         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1615         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2),
1616         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1617         PINMUX_IPSR_DATA(IP15_11_9, PWM5),
1618         PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
1619         PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1620         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0),
1621         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2),
1622         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1623         PINMUX_IPSR_DATA(IP15_14_12, PWM6),
1624         PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
1625         PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1626         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1627         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1628         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1629         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0),
1630         PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1631         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1632         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1633         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1634         PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1635         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1636         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1637         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1638         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1639         PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
1640         PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1641         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0),
1642         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1643         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1644         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1645         PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1646         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0),
1647         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1648         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1649         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1650         PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1651
1652         /* IPSR16 */
1653         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0),
1654         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1655         PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
1656         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1657         PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1658         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0),
1659         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1660         PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
1661         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1662         PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1663         PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1664         PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1665         PINMUX_IPSR_DATA(IP16_7_6, MLB_CK),
1666         PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1667         PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1668         PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
1669         PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
1670         PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1671         PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1672         PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
1673         PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
1674         PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1675 };
1676
1677 static const struct sh_pfc_pin pinmux_pins[] = {
1678         PINMUX_GPIO_GP_ALL(),
1679 };
1680
1681 /* - DU --------------------------------------------------------------------- */
1682 static const unsigned int du_rgb666_pins[] = {
1683         /* R[7:2], G[7:2], B[7:2] */
1684         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
1685         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
1686         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1687         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1688         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1689         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1690 };
1691 static const unsigned int du_rgb666_mux[] = {
1692         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1693         DU1_DR3_MARK, DU1_DR2_MARK,
1694         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1695         DU1_DG3_MARK, DU1_DG2_MARK,
1696         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1697         DU1_DB3_MARK, DU1_DB2_MARK,
1698 };
1699 static const unsigned int du_rgb888_pins[] = {
1700         /* R[7:0], G[7:0], B[7:0] */
1701         RCAR_GP_PIN(3, 7),  RCAR_GP_PIN(3, 6),  RCAR_GP_PIN(3, 5),
1702         RCAR_GP_PIN(3, 4),  RCAR_GP_PIN(3, 3),  RCAR_GP_PIN(3, 2),
1703         RCAR_GP_PIN(3, 1),  RCAR_GP_PIN(3, 0),
1704         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1705         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1706         RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 8),
1707         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1708         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1709         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
1710 };
1711 static const unsigned int du_rgb888_mux[] = {
1712         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1713         DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1714         DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1715         DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1716         DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1717         DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1718 };
1719 static const unsigned int du_clk_out_0_pins[] = {
1720         /* CLKOUT */
1721         RCAR_GP_PIN(3, 25),
1722 };
1723 static const unsigned int du_clk_out_0_mux[] = {
1724         DU1_DOTCLKOUT0_MARK
1725 };
1726 static const unsigned int du_clk_out_1_pins[] = {
1727         /* CLKOUT */
1728         RCAR_GP_PIN(3, 26),
1729 };
1730 static const unsigned int du_clk_out_1_mux[] = {
1731         DU1_DOTCLKOUT1_MARK
1732 };
1733 static const unsigned int du_sync_pins[] = {
1734         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC, EXDISP/EXODDF/EXCDE */
1735         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1736 };
1737 static const unsigned int du_sync_mux[] = {
1738         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1739         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1740 };
1741 static const unsigned int du_cde_disp_pins[] = {
1742         /* CDE DISP */
1743         RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
1744 };
1745 static const unsigned int du_cde_disp_mux[] = {
1746         DU1_CDE_MARK, DU1_DISP_MARK
1747 };
1748 static const unsigned int du0_clk_in_pins[] = {
1749         /* CLKIN */
1750         RCAR_GP_PIN(6, 31),
1751 };
1752 static const unsigned int du0_clk_in_mux[] = {
1753         DU0_DOTCLKIN_MARK
1754 };
1755 static const unsigned int du1_clk_in_pins[] = {
1756         /* CLKIN */
1757         RCAR_GP_PIN(3, 24),
1758 };
1759 static const unsigned int du1_clk_in_mux[] = {
1760         DU1_DOTCLKIN_MARK
1761 };
1762 static const unsigned int du1_clk_in_b_pins[] = {
1763         /* CLKIN */
1764         RCAR_GP_PIN(7, 19),
1765 };
1766 static const unsigned int du1_clk_in_b_mux[] = {
1767         DU1_DOTCLKIN_B_MARK,
1768 };
1769 static const unsigned int du1_clk_in_c_pins[] = {
1770         /* CLKIN */
1771         RCAR_GP_PIN(7, 20),
1772 };
1773 static const unsigned int du1_clk_in_c_mux[] = {
1774         DU1_DOTCLKIN_C_MARK,
1775 };
1776 /* - ETH -------------------------------------------------------------------- */
1777 static const unsigned int eth_link_pins[] = {
1778         /* LINK */
1779         RCAR_GP_PIN(5, 18),
1780 };
1781 static const unsigned int eth_link_mux[] = {
1782         ETH_LINK_MARK,
1783 };
1784 static const unsigned int eth_magic_pins[] = {
1785         /* MAGIC */
1786         RCAR_GP_PIN(5, 22),
1787 };
1788 static const unsigned int eth_magic_mux[] = {
1789         ETH_MAGIC_MARK,
1790 };
1791 static const unsigned int eth_mdio_pins[] = {
1792         /* MDC, MDIO */
1793         RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
1794 };
1795 static const unsigned int eth_mdio_mux[] = {
1796         ETH_MDC_MARK, ETH_MDIO_MARK,
1797 };
1798 static const unsigned int eth_rmii_pins[] = {
1799         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1800         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
1801         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
1802         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
1803 };
1804 static const unsigned int eth_rmii_mux[] = {
1805         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1806         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1807 };
1808 /* - I2C0 ------------------------------------------------------------------- */
1809 static const unsigned int i2c0_pins[] = {
1810         /* SCL, SDA */
1811         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
1812 };
1813 static const unsigned int i2c0_mux[] = {
1814         SCL0_MARK, SDA0_MARK,
1815 };
1816 static const unsigned int i2c0_b_pins[] = {
1817         /* SCL, SDA */
1818         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1819 };
1820 static const unsigned int i2c0_b_mux[] = {
1821         SCL0_B_MARK, SDA0_B_MARK,
1822 };
1823 static const unsigned int i2c0_c_pins[] = {
1824         /* SCL, SDA */
1825         RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
1826 };
1827 static const unsigned int i2c0_c_mux[] = {
1828         SCL0_C_MARK, SDA0_C_MARK,
1829 };
1830 /* - I2C1 ------------------------------------------------------------------- */
1831 static const unsigned int i2c1_pins[] = {
1832         /* SCL, SDA */
1833         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
1834 };
1835 static const unsigned int i2c1_mux[] = {
1836         SCL1_MARK, SDA1_MARK,
1837 };
1838 static const unsigned int i2c1_b_pins[] = {
1839         /* SCL, SDA */
1840         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1841 };
1842 static const unsigned int i2c1_b_mux[] = {
1843         SCL1_B_MARK, SDA1_B_MARK,
1844 };
1845 static const unsigned int i2c1_c_pins[] = {
1846         /* SCL, SDA */
1847         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1848 };
1849 static const unsigned int i2c1_c_mux[] = {
1850         SCL1_C_MARK, SDA1_C_MARK,
1851 };
1852 static const unsigned int i2c1_d_pins[] = {
1853         /* SCL, SDA */
1854         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
1855 };
1856 static const unsigned int i2c1_d_mux[] = {
1857         SCL1_D_MARK, SDA1_D_MARK,
1858 };
1859 static const unsigned int i2c1_e_pins[] = {
1860         /* SCL, SDA */
1861         RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
1862 };
1863 static const unsigned int i2c1_e_mux[] = {
1864         SCL1_E_MARK, SDA1_E_MARK,
1865 };
1866 /* - I2C2 ------------------------------------------------------------------- */
1867 static const unsigned int i2c2_pins[] = {
1868         /* SCL, SDA */
1869         RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1870 };
1871 static const unsigned int i2c2_mux[] = {
1872         SCL2_MARK, SDA2_MARK,
1873 };
1874 static const unsigned int i2c2_b_pins[] = {
1875         /* SCL, SDA */
1876         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1877 };
1878 static const unsigned int i2c2_b_mux[] = {
1879         SCL2_B_MARK, SDA2_B_MARK,
1880 };
1881 static const unsigned int i2c2_c_pins[] = {
1882         /* SCL, SDA */
1883         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1884 };
1885 static const unsigned int i2c2_c_mux[] = {
1886         SCL2_C_MARK, SDA2_C_MARK,
1887 };
1888 static const unsigned int i2c2_d_pins[] = {
1889         /* SCL, SDA */
1890         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1891 };
1892 static const unsigned int i2c2_d_mux[] = {
1893         SCL2_D_MARK, SDA2_D_MARK,
1894 };
1895 /* - I2C3 ------------------------------------------------------------------- */
1896 static const unsigned int i2c3_pins[] = {
1897         /* SCL, SDA */
1898         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1899 };
1900 static const unsigned int i2c3_mux[] = {
1901         SCL3_MARK, SDA3_MARK,
1902 };
1903 static const unsigned int i2c3_b_pins[] = {
1904         /* SCL, SDA */
1905         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
1906 };
1907 static const unsigned int i2c3_b_mux[] = {
1908         SCL3_B_MARK, SDA3_B_MARK,
1909 };
1910 static const unsigned int i2c3_c_pins[] = {
1911         /* SCL, SDA */
1912         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
1913 };
1914 static const unsigned int i2c3_c_mux[] = {
1915         SCL3_C_MARK, SDA3_C_MARK,
1916 };
1917 static const unsigned int i2c3_d_pins[] = {
1918         /* SCL, SDA */
1919         RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
1920 };
1921 static const unsigned int i2c3_d_mux[] = {
1922         SCL3_D_MARK, SDA3_D_MARK,
1923 };
1924 /* - I2C4 ------------------------------------------------------------------- */
1925 static const unsigned int i2c4_pins[] = {
1926         /* SCL, SDA */
1927         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
1928 };
1929 static const unsigned int i2c4_mux[] = {
1930         SCL4_MARK, SDA4_MARK,
1931 };
1932 static const unsigned int i2c4_b_pins[] = {
1933         /* SCL, SDA */
1934         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
1935 };
1936 static const unsigned int i2c4_b_mux[] = {
1937         SCL4_B_MARK, SDA4_B_MARK,
1938 };
1939 static const unsigned int i2c4_c_pins[] = {
1940         /* SCL, SDA */
1941         RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1942 };
1943 static const unsigned int i2c4_c_mux[] = {
1944         SCL4_C_MARK, SDA4_C_MARK,
1945 };
1946 /* - I2C7 ------------------------------------------------------------------- */
1947 static const unsigned int i2c7_pins[] = {
1948         /* SCL, SDA */
1949         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1950 };
1951 static const unsigned int i2c7_mux[] = {
1952         SCL7_MARK, SDA7_MARK,
1953 };
1954 static const unsigned int i2c7_b_pins[] = {
1955         /* SCL, SDA */
1956         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1957 };
1958 static const unsigned int i2c7_b_mux[] = {
1959         SCL7_B_MARK, SDA7_B_MARK,
1960 };
1961 static const unsigned int i2c7_c_pins[] = {
1962         /* SCL, SDA */
1963         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
1964 };
1965 static const unsigned int i2c7_c_mux[] = {
1966         SCL7_C_MARK, SDA7_C_MARK,
1967 };
1968 /* - I2C8 ------------------------------------------------------------------- */
1969 static const unsigned int i2c8_pins[] = {
1970         /* SCL, SDA */
1971         RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
1972 };
1973 static const unsigned int i2c8_mux[] = {
1974         SCL8_MARK, SDA8_MARK,
1975 };
1976 static const unsigned int i2c8_b_pins[] = {
1977         /* SCL, SDA */
1978         RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1979 };
1980 static const unsigned int i2c8_b_mux[] = {
1981         SCL8_B_MARK, SDA8_B_MARK,
1982 };
1983 static const unsigned int i2c8_c_pins[] = {
1984         /* SCL, SDA */
1985         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
1986 };
1987 static const unsigned int i2c8_c_mux[] = {
1988         SCL8_C_MARK, SDA8_C_MARK,
1989 };
1990 /* - INTC ------------------------------------------------------------------- */
1991 static const unsigned int intc_irq0_pins[] = {
1992         /* IRQ */
1993         RCAR_GP_PIN(7, 10),
1994 };
1995 static const unsigned int intc_irq0_mux[] = {
1996         IRQ0_MARK,
1997 };
1998 static const unsigned int intc_irq1_pins[] = {
1999         /* IRQ */
2000         RCAR_GP_PIN(7, 11),
2001 };
2002 static const unsigned int intc_irq1_mux[] = {
2003         IRQ1_MARK,
2004 };
2005 static const unsigned int intc_irq2_pins[] = {
2006         /* IRQ */
2007         RCAR_GP_PIN(7, 12),
2008 };
2009 static const unsigned int intc_irq2_mux[] = {
2010         IRQ2_MARK,
2011 };
2012 static const unsigned int intc_irq3_pins[] = {
2013         /* IRQ */
2014         RCAR_GP_PIN(7, 13),
2015 };
2016 static const unsigned int intc_irq3_mux[] = {
2017         IRQ3_MARK,
2018 };
2019 /* - MMCIF ------------------------------------------------------------------ */
2020 static const unsigned int mmc_data1_pins[] = {
2021         /* D[0] */
2022         RCAR_GP_PIN(6, 18),
2023 };
2024 static const unsigned int mmc_data1_mux[] = {
2025         MMC_D0_MARK,
2026 };
2027 static const unsigned int mmc_data4_pins[] = {
2028         /* D[0:3] */
2029         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2030         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2031 };
2032 static const unsigned int mmc_data4_mux[] = {
2033         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2034 };
2035 static const unsigned int mmc_data8_pins[] = {
2036         /* D[0:7] */
2037         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2038         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2039         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2040         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2041 };
2042 static const unsigned int mmc_data8_mux[] = {
2043         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2044         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2045 };
2046 static const unsigned int mmc_ctrl_pins[] = {
2047         /* CLK, CMD */
2048         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2049 };
2050 static const unsigned int mmc_ctrl_mux[] = {
2051         MMC_CLK_MARK, MMC_CMD_MARK,
2052 };
2053 /* - MSIOF0 ----------------------------------------------------------------- */
2054 static const unsigned int msiof0_clk_pins[] = {
2055         /* SCK */
2056         RCAR_GP_PIN(6, 24),
2057 };
2058 static const unsigned int msiof0_clk_mux[] = {
2059         MSIOF0_SCK_MARK,
2060 };
2061 static const unsigned int msiof0_sync_pins[] = {
2062         /* SYNC */
2063         RCAR_GP_PIN(6, 25),
2064 };
2065 static const unsigned int msiof0_sync_mux[] = {
2066         MSIOF0_SYNC_MARK,
2067 };
2068 static const unsigned int msiof0_ss1_pins[] = {
2069         /* SS1 */
2070         RCAR_GP_PIN(6, 28),
2071 };
2072 static const unsigned int msiof0_ss1_mux[] = {
2073         MSIOF0_SS1_MARK,
2074 };
2075 static const unsigned int msiof0_ss2_pins[] = {
2076         /* SS2 */
2077         RCAR_GP_PIN(6, 29),
2078 };
2079 static const unsigned int msiof0_ss2_mux[] = {
2080         MSIOF0_SS2_MARK,
2081 };
2082 static const unsigned int msiof0_rx_pins[] = {
2083         /* RXD */
2084         RCAR_GP_PIN(6, 27),
2085 };
2086 static const unsigned int msiof0_rx_mux[] = {
2087         MSIOF0_RXD_MARK,
2088 };
2089 static const unsigned int msiof0_tx_pins[] = {
2090         /* TXD */
2091         RCAR_GP_PIN(6, 26),
2092 };
2093 static const unsigned int msiof0_tx_mux[] = {
2094         MSIOF0_TXD_MARK,
2095 };
2096
2097 static const unsigned int msiof0_clk_b_pins[] = {
2098         /* SCK */
2099         RCAR_GP_PIN(0, 16),
2100 };
2101 static const unsigned int msiof0_clk_b_mux[] = {
2102         MSIOF0_SCK_B_MARK,
2103 };
2104 static const unsigned int msiof0_sync_b_pins[] = {
2105         /* SYNC */
2106         RCAR_GP_PIN(0, 17),
2107 };
2108 static const unsigned int msiof0_sync_b_mux[] = {
2109         MSIOF0_SYNC_B_MARK,
2110 };
2111 static const unsigned int msiof0_ss1_b_pins[] = {
2112         /* SS1 */
2113         RCAR_GP_PIN(0, 18),
2114 };
2115 static const unsigned int msiof0_ss1_b_mux[] = {
2116         MSIOF0_SS1_B_MARK,
2117 };
2118 static const unsigned int msiof0_ss2_b_pins[] = {
2119         /* SS2 */
2120         RCAR_GP_PIN(0, 19),
2121 };
2122 static const unsigned int msiof0_ss2_b_mux[] = {
2123         MSIOF0_SS2_B_MARK,
2124 };
2125 static const unsigned int msiof0_rx_b_pins[] = {
2126         /* RXD */
2127         RCAR_GP_PIN(0, 21),
2128 };
2129 static const unsigned int msiof0_rx_b_mux[] = {
2130         MSIOF0_RXD_B_MARK,
2131 };
2132 static const unsigned int msiof0_tx_b_pins[] = {
2133         /* TXD */
2134         RCAR_GP_PIN(0, 20),
2135 };
2136 static const unsigned int msiof0_tx_b_mux[] = {
2137         MSIOF0_TXD_B_MARK,
2138 };
2139
2140 static const unsigned int msiof0_clk_c_pins[] = {
2141         /* SCK */
2142         RCAR_GP_PIN(5, 26),
2143 };
2144 static const unsigned int msiof0_clk_c_mux[] = {
2145         MSIOF0_SCK_C_MARK,
2146 };
2147 static const unsigned int msiof0_sync_c_pins[] = {
2148         /* SYNC */
2149         RCAR_GP_PIN(5, 25),
2150 };
2151 static const unsigned int msiof0_sync_c_mux[] = {
2152         MSIOF0_SYNC_C_MARK,
2153 };
2154 static const unsigned int msiof0_ss1_c_pins[] = {
2155         /* SS1 */
2156         RCAR_GP_PIN(5, 27),
2157 };
2158 static const unsigned int msiof0_ss1_c_mux[] = {
2159         MSIOF0_SS1_C_MARK,
2160 };
2161 static const unsigned int msiof0_ss2_c_pins[] = {
2162         /* SS2 */
2163         RCAR_GP_PIN(5, 28),
2164 };
2165 static const unsigned int msiof0_ss2_c_mux[] = {
2166         MSIOF0_SS2_C_MARK,
2167 };
2168 static const unsigned int msiof0_rx_c_pins[] = {
2169         /* RXD */
2170         RCAR_GP_PIN(5, 29),
2171 };
2172 static const unsigned int msiof0_rx_c_mux[] = {
2173         MSIOF0_RXD_C_MARK,
2174 };
2175 static const unsigned int msiof0_tx_c_pins[] = {
2176         /* TXD */
2177         RCAR_GP_PIN(5, 30),
2178 };
2179 static const unsigned int msiof0_tx_c_mux[] = {
2180         MSIOF0_TXD_C_MARK,
2181 };
2182 /* - MSIOF1 ----------------------------------------------------------------- */
2183 static const unsigned int msiof1_clk_pins[] = {
2184         /* SCK */
2185         RCAR_GP_PIN(0, 22),
2186 };
2187 static const unsigned int msiof1_clk_mux[] = {
2188         MSIOF1_SCK_MARK,
2189 };
2190 static const unsigned int msiof1_sync_pins[] = {
2191         /* SYNC */
2192         RCAR_GP_PIN(0, 23),
2193 };
2194 static const unsigned int msiof1_sync_mux[] = {
2195         MSIOF1_SYNC_MARK,
2196 };
2197 static const unsigned int msiof1_ss1_pins[] = {
2198         /* SS1 */
2199         RCAR_GP_PIN(0, 24),
2200 };
2201 static const unsigned int msiof1_ss1_mux[] = {
2202         MSIOF1_SS1_MARK,
2203 };
2204 static const unsigned int msiof1_ss2_pins[] = {
2205         /* SS2 */
2206         RCAR_GP_PIN(0, 25),
2207 };
2208 static const unsigned int msiof1_ss2_mux[] = {
2209         MSIOF1_SS2_MARK,
2210 };
2211 static const unsigned int msiof1_rx_pins[] = {
2212         /* RXD */
2213         RCAR_GP_PIN(0, 27),
2214 };
2215 static const unsigned int msiof1_rx_mux[] = {
2216         MSIOF1_RXD_MARK,
2217 };
2218 static const unsigned int msiof1_tx_pins[] = {
2219         /* TXD */
2220         RCAR_GP_PIN(0, 26),
2221 };
2222 static const unsigned int msiof1_tx_mux[] = {
2223         MSIOF1_TXD_MARK,
2224 };
2225
2226 static const unsigned int msiof1_clk_b_pins[] = {
2227         /* SCK */
2228         RCAR_GP_PIN(2, 29),
2229 };
2230 static const unsigned int msiof1_clk_b_mux[] = {
2231         MSIOF1_SCK_B_MARK,
2232 };
2233 static const unsigned int msiof1_sync_b_pins[] = {
2234         /* SYNC */
2235         RCAR_GP_PIN(2, 30),
2236 };
2237 static const unsigned int msiof1_sync_b_mux[] = {
2238         MSIOF1_SYNC_B_MARK,
2239 };
2240 static const unsigned int msiof1_ss1_b_pins[] = {
2241         /* SS1 */
2242         RCAR_GP_PIN(2, 31),
2243 };
2244 static const unsigned int msiof1_ss1_b_mux[] = {
2245         MSIOF1_SS1_B_MARK,
2246 };
2247 static const unsigned int msiof1_ss2_b_pins[] = {
2248         /* SS2 */
2249         RCAR_GP_PIN(7, 16),
2250 };
2251 static const unsigned int msiof1_ss2_b_mux[] = {
2252         MSIOF1_SS2_B_MARK,
2253 };
2254 static const unsigned int msiof1_rx_b_pins[] = {
2255         /* RXD */
2256         RCAR_GP_PIN(7, 18),
2257 };
2258 static const unsigned int msiof1_rx_b_mux[] = {
2259         MSIOF1_RXD_B_MARK,
2260 };
2261 static const unsigned int msiof1_tx_b_pins[] = {
2262         /* TXD */
2263         RCAR_GP_PIN(7, 17),
2264 };
2265 static const unsigned int msiof1_tx_b_mux[] = {
2266         MSIOF1_TXD_B_MARK,
2267 };
2268
2269 static const unsigned int msiof1_clk_c_pins[] = {
2270         /* SCK */
2271         RCAR_GP_PIN(2, 15),
2272 };
2273 static const unsigned int msiof1_clk_c_mux[] = {
2274         MSIOF1_SCK_C_MARK,
2275 };
2276 static const unsigned int msiof1_sync_c_pins[] = {
2277         /* SYNC */
2278         RCAR_GP_PIN(2, 16),
2279 };
2280 static const unsigned int msiof1_sync_c_mux[] = {
2281         MSIOF1_SYNC_C_MARK,
2282 };
2283 static const unsigned int msiof1_rx_c_pins[] = {
2284         /* RXD */
2285         RCAR_GP_PIN(2, 18),
2286 };
2287 static const unsigned int msiof1_rx_c_mux[] = {
2288         MSIOF1_RXD_C_MARK,
2289 };
2290 static const unsigned int msiof1_tx_c_pins[] = {
2291         /* TXD */
2292         RCAR_GP_PIN(2, 17),
2293 };
2294 static const unsigned int msiof1_tx_c_mux[] = {
2295         MSIOF1_TXD_C_MARK,
2296 };
2297
2298 static const unsigned int msiof1_clk_d_pins[] = {
2299         /* SCK */
2300         RCAR_GP_PIN(0, 28),
2301 };
2302 static const unsigned int msiof1_clk_d_mux[] = {
2303         MSIOF1_SCK_D_MARK,
2304 };
2305 static const unsigned int msiof1_sync_d_pins[] = {
2306         /* SYNC */
2307         RCAR_GP_PIN(0, 30),
2308 };
2309 static const unsigned int msiof1_sync_d_mux[] = {
2310         MSIOF1_SYNC_D_MARK,
2311 };
2312 static const unsigned int msiof1_ss1_d_pins[] = {
2313         /* SS1 */
2314         RCAR_GP_PIN(0, 29),
2315 };
2316 static const unsigned int msiof1_ss1_d_mux[] = {
2317         MSIOF1_SS1_D_MARK,
2318 };
2319 static const unsigned int msiof1_rx_d_pins[] = {
2320         /* RXD */
2321         RCAR_GP_PIN(0, 27),
2322 };
2323 static const unsigned int msiof1_rx_d_mux[] = {
2324         MSIOF1_RXD_D_MARK,
2325 };
2326 static const unsigned int msiof1_tx_d_pins[] = {
2327         /* TXD */
2328         RCAR_GP_PIN(0, 26),
2329 };
2330 static const unsigned int msiof1_tx_d_mux[] = {
2331         MSIOF1_TXD_D_MARK,
2332 };
2333
2334 static const unsigned int msiof1_clk_e_pins[] = {
2335         /* SCK */
2336         RCAR_GP_PIN(5, 18),
2337 };
2338 static const unsigned int msiof1_clk_e_mux[] = {
2339         MSIOF1_SCK_E_MARK,
2340 };
2341 static const unsigned int msiof1_sync_e_pins[] = {
2342         /* SYNC */
2343         RCAR_GP_PIN(5, 19),
2344 };
2345 static const unsigned int msiof1_sync_e_mux[] = {
2346         MSIOF1_SYNC_E_MARK,
2347 };
2348 static const unsigned int msiof1_rx_e_pins[] = {
2349         /* RXD */
2350         RCAR_GP_PIN(5, 17),
2351 };
2352 static const unsigned int msiof1_rx_e_mux[] = {
2353         MSIOF1_RXD_E_MARK,
2354 };
2355 static const unsigned int msiof1_tx_e_pins[] = {
2356         /* TXD */
2357         RCAR_GP_PIN(5, 20),
2358 };
2359 static const unsigned int msiof1_tx_e_mux[] = {
2360         MSIOF1_TXD_E_MARK,
2361 };
2362 /* - MSIOF2 ----------------------------------------------------------------- */
2363 static const unsigned int msiof2_clk_pins[] = {
2364         /* SCK */
2365         RCAR_GP_PIN(1, 13),
2366 };
2367 static const unsigned int msiof2_clk_mux[] = {
2368         MSIOF2_SCK_MARK,
2369 };
2370 static const unsigned int msiof2_sync_pins[] = {
2371         /* SYNC */
2372         RCAR_GP_PIN(1, 14),
2373 };
2374 static const unsigned int msiof2_sync_mux[] = {
2375         MSIOF2_SYNC_MARK,
2376 };
2377 static const unsigned int msiof2_ss1_pins[] = {
2378         /* SS1 */
2379         RCAR_GP_PIN(1, 17),
2380 };
2381 static const unsigned int msiof2_ss1_mux[] = {
2382         MSIOF2_SS1_MARK,
2383 };
2384 static const unsigned int msiof2_ss2_pins[] = {
2385         /* SS2 */
2386         RCAR_GP_PIN(1, 18),
2387 };
2388 static const unsigned int msiof2_ss2_mux[] = {
2389         MSIOF2_SS2_MARK,
2390 };
2391 static const unsigned int msiof2_rx_pins[] = {
2392         /* RXD */
2393         RCAR_GP_PIN(1, 16),
2394 };
2395 static const unsigned int msiof2_rx_mux[] = {
2396         MSIOF2_RXD_MARK,
2397 };
2398 static const unsigned int msiof2_tx_pins[] = {
2399         /* TXD */
2400         RCAR_GP_PIN(1, 15),
2401 };
2402 static const unsigned int msiof2_tx_mux[] = {
2403         MSIOF2_TXD_MARK,
2404 };
2405
2406 static const unsigned int msiof2_clk_b_pins[] = {
2407         /* SCK */
2408         RCAR_GP_PIN(3, 0),
2409 };
2410 static const unsigned int msiof2_clk_b_mux[] = {
2411         MSIOF2_SCK_B_MARK,
2412 };
2413 static const unsigned int msiof2_sync_b_pins[] = {
2414         /* SYNC */
2415         RCAR_GP_PIN(3, 1),
2416 };
2417 static const unsigned int msiof2_sync_b_mux[] = {
2418         MSIOF2_SYNC_B_MARK,
2419 };
2420 static const unsigned int msiof2_ss1_b_pins[] = {
2421         /* SS1 */
2422         RCAR_GP_PIN(3, 8),
2423 };
2424 static const unsigned int msiof2_ss1_b_mux[] = {
2425         MSIOF2_SS1_B_MARK,
2426 };
2427 static const unsigned int msiof2_ss2_b_pins[] = {
2428         /* SS2 */
2429         RCAR_GP_PIN(3, 9),
2430 };
2431 static const unsigned int msiof2_ss2_b_mux[] = {
2432         MSIOF2_SS2_B_MARK,
2433 };
2434 static const unsigned int msiof2_rx_b_pins[] = {
2435         /* RXD */
2436         RCAR_GP_PIN(3, 17),
2437 };
2438 static const unsigned int msiof2_rx_b_mux[] = {
2439         MSIOF2_RXD_B_MARK,
2440 };
2441 static const unsigned int msiof2_tx_b_pins[] = {
2442         /* TXD */
2443         RCAR_GP_PIN(3, 16),
2444 };
2445 static const unsigned int msiof2_tx_b_mux[] = {
2446         MSIOF2_TXD_B_MARK,
2447 };
2448
2449 static const unsigned int msiof2_clk_c_pins[] = {
2450         /* SCK */
2451         RCAR_GP_PIN(2, 2),
2452 };
2453 static const unsigned int msiof2_clk_c_mux[] = {
2454         MSIOF2_SCK_C_MARK,
2455 };
2456 static const unsigned int msiof2_sync_c_pins[] = {
2457         /* SYNC */
2458         RCAR_GP_PIN(2, 3),
2459 };
2460 static const unsigned int msiof2_sync_c_mux[] = {
2461         MSIOF2_SYNC_C_MARK,
2462 };
2463 static const unsigned int msiof2_rx_c_pins[] = {
2464         /* RXD */
2465         RCAR_GP_PIN(2, 5),
2466 };
2467 static const unsigned int msiof2_rx_c_mux[] = {
2468         MSIOF2_RXD_C_MARK,
2469 };
2470 static const unsigned int msiof2_tx_c_pins[] = {
2471         /* TXD */
2472         RCAR_GP_PIN(2, 4),
2473 };
2474 static const unsigned int msiof2_tx_c_mux[] = {
2475         MSIOF2_TXD_C_MARK,
2476 };
2477
2478 static const unsigned int msiof2_clk_d_pins[] = {
2479         /* SCK */
2480         RCAR_GP_PIN(2, 14),
2481 };
2482 static const unsigned int msiof2_clk_d_mux[] = {
2483         MSIOF2_SCK_D_MARK,
2484 };
2485 static const unsigned int msiof2_sync_d_pins[] = {
2486         /* SYNC */
2487         RCAR_GP_PIN(2, 15),
2488 };
2489 static const unsigned int msiof2_sync_d_mux[] = {
2490         MSIOF2_SYNC_D_MARK,
2491 };
2492 static const unsigned int msiof2_ss1_d_pins[] = {
2493         /* SS1 */
2494         RCAR_GP_PIN(2, 17),
2495 };
2496 static const unsigned int msiof2_ss1_d_mux[] = {
2497         MSIOF2_SS1_D_MARK,
2498 };
2499 static const unsigned int msiof2_ss2_d_pins[] = {
2500         /* SS2 */
2501         RCAR_GP_PIN(2, 19),
2502 };
2503 static const unsigned int msiof2_ss2_d_mux[] = {
2504         MSIOF2_SS2_D_MARK,
2505 };
2506 static const unsigned int msiof2_rx_d_pins[] = {
2507         /* RXD */
2508         RCAR_GP_PIN(2, 18),
2509 };
2510 static const unsigned int msiof2_rx_d_mux[] = {
2511         MSIOF2_RXD_D_MARK,
2512 };
2513 static const unsigned int msiof2_tx_d_pins[] = {
2514         /* TXD */
2515         RCAR_GP_PIN(2, 16),
2516 };
2517 static const unsigned int msiof2_tx_d_mux[] = {
2518         MSIOF2_TXD_D_MARK,
2519 };
2520
2521 static const unsigned int msiof2_clk_e_pins[] = {
2522         /* SCK */
2523         RCAR_GP_PIN(7, 15),
2524 };
2525 static const unsigned int msiof2_clk_e_mux[] = {
2526         MSIOF2_SCK_E_MARK,
2527 };
2528 static const unsigned int msiof2_sync_e_pins[] = {
2529         /* SYNC */
2530         RCAR_GP_PIN(7, 16),
2531 };
2532 static const unsigned int msiof2_sync_e_mux[] = {
2533         MSIOF2_SYNC_E_MARK,
2534 };
2535 static const unsigned int msiof2_rx_e_pins[] = {
2536         /* RXD */
2537         RCAR_GP_PIN(7, 14),
2538 };
2539 static const unsigned int msiof2_rx_e_mux[] = {
2540         MSIOF2_RXD_E_MARK,
2541 };
2542 static const unsigned int msiof2_tx_e_pins[] = {
2543         /* TXD */
2544         RCAR_GP_PIN(7, 13),
2545 };
2546 static const unsigned int msiof2_tx_e_mux[] = {
2547         MSIOF2_TXD_E_MARK,
2548 };
2549 /* - QSPI ------------------------------------------------------------------- */
2550 static const unsigned int qspi_ctrl_pins[] = {
2551         /* SPCLK, SSL */
2552         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2553 };
2554 static const unsigned int qspi_ctrl_mux[] = {
2555         SPCLK_MARK, SSL_MARK,
2556 };
2557 static const unsigned int qspi_data2_pins[] = {
2558         /* MOSI_IO0, MISO_IO1 */
2559         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2560 };
2561 static const unsigned int qspi_data2_mux[] = {
2562         MOSI_IO0_MARK, MISO_IO1_MARK,
2563 };
2564 static const unsigned int qspi_data4_pins[] = {
2565         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2566         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2567         RCAR_GP_PIN(1, 8),
2568 };
2569 static const unsigned int qspi_data4_mux[] = {
2570         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2571 };
2572
2573 static const unsigned int qspi_ctrl_b_pins[] = {
2574         /* SPCLK, SSL */
2575         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
2576 };
2577 static const unsigned int qspi_ctrl_b_mux[] = {
2578         SPCLK_B_MARK, SSL_B_MARK,
2579 };
2580 static const unsigned int qspi_data2_b_pins[] = {
2581         /* MOSI_IO0, MISO_IO1 */
2582         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
2583 };
2584 static const unsigned int qspi_data2_b_mux[] = {
2585         MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
2586 };
2587 static const unsigned int qspi_data4_b_pins[] = {
2588         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2589         RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
2590         RCAR_GP_PIN(6, 4),
2591 };
2592 static const unsigned int qspi_data4_b_mux[] = {
2593         SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
2594         IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
2595 };
2596 /* - SCIF0 ------------------------------------------------------------------ */
2597 static const unsigned int scif0_data_pins[] = {
2598         /* RX, TX */
2599         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2600 };
2601 static const unsigned int scif0_data_mux[] = {
2602         RX0_MARK, TX0_MARK,
2603 };
2604 static const unsigned int scif0_data_b_pins[] = {
2605         /* RX, TX */
2606         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2607 };
2608 static const unsigned int scif0_data_b_mux[] = {
2609         RX0_B_MARK, TX0_B_MARK,
2610 };
2611 static const unsigned int scif0_data_c_pins[] = {
2612         /* RX, TX */
2613         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
2614 };
2615 static const unsigned int scif0_data_c_mux[] = {
2616         RX0_C_MARK, TX0_C_MARK,
2617 };
2618 static const unsigned int scif0_data_d_pins[] = {
2619         /* RX, TX */
2620         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
2621 };
2622 static const unsigned int scif0_data_d_mux[] = {
2623         RX0_D_MARK, TX0_D_MARK,
2624 };
2625 static const unsigned int scif0_data_e_pins[] = {
2626         /* RX, TX */
2627         RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
2628 };
2629 static const unsigned int scif0_data_e_mux[] = {
2630         RX0_E_MARK, TX0_E_MARK,
2631 };
2632 /* - SCIF1 ------------------------------------------------------------------ */
2633 static const unsigned int scif1_data_pins[] = {
2634         /* RX, TX */
2635         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2636 };
2637 static const unsigned int scif1_data_mux[] = {
2638         RX1_MARK, TX1_MARK,
2639 };
2640 static const unsigned int scif1_data_b_pins[] = {
2641         /* RX, TX */
2642         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2643 };
2644 static const unsigned int scif1_data_b_mux[] = {
2645         RX1_B_MARK, TX1_B_MARK,
2646 };
2647 static const unsigned int scif1_clk_b_pins[] = {
2648         /* SCK */
2649         RCAR_GP_PIN(3, 10),
2650 };
2651 static const unsigned int scif1_clk_b_mux[] = {
2652         SCIF1_SCK_B_MARK,
2653 };
2654 static const unsigned int scif1_data_c_pins[] = {
2655         /* RX, TX */
2656         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
2657 };
2658 static const unsigned int scif1_data_c_mux[] = {
2659         RX1_C_MARK, TX1_C_MARK,
2660 };
2661 static const unsigned int scif1_data_d_pins[] = {
2662         /* RX, TX */
2663         RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
2664 };
2665 static const unsigned int scif1_data_d_mux[] = {
2666         RX1_D_MARK, TX1_D_MARK,
2667 };
2668 /* - SCIF2 ------------------------------------------------------------------ */
2669 static const unsigned int scif2_data_pins[] = {
2670         /* RX, TX */
2671         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2672 };
2673 static const unsigned int scif2_data_mux[] = {
2674         RX2_MARK, TX2_MARK,
2675 };
2676 static const unsigned int scif2_data_b_pins[] = {
2677         /* RX, TX */
2678         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2679 };
2680 static const unsigned int scif2_data_b_mux[] = {
2681         RX2_B_MARK, TX2_B_MARK,
2682 };
2683 static const unsigned int scif2_clk_b_pins[] = {
2684         /* SCK */
2685         RCAR_GP_PIN(3, 18),
2686 };
2687 static const unsigned int scif2_clk_b_mux[] = {
2688         SCIF2_SCK_B_MARK,
2689 };
2690 static const unsigned int scif2_data_c_pins[] = {
2691         /* RX, TX */
2692         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2693 };
2694 static const unsigned int scif2_data_c_mux[] = {
2695         RX2_C_MARK, TX2_C_MARK,
2696 };
2697 static const unsigned int scif2_data_e_pins[] = {
2698         /* RX, TX */
2699         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2700 };
2701 static const unsigned int scif2_data_e_mux[] = {
2702         RX2_E_MARK, TX2_E_MARK,
2703 };
2704 /* - SCIF3 ------------------------------------------------------------------ */
2705 static const unsigned int scif3_data_pins[] = {
2706         /* RX, TX */
2707         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2708 };
2709 static const unsigned int scif3_data_mux[] = {
2710         RX3_MARK, TX3_MARK,
2711 };
2712 static const unsigned int scif3_clk_pins[] = {
2713         /* SCK */
2714         RCAR_GP_PIN(3, 23),
2715 };
2716 static const unsigned int scif3_clk_mux[] = {
2717         SCIF3_SCK_MARK,
2718 };
2719 static const unsigned int scif3_data_b_pins[] = {
2720         /* RX, TX */
2721         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
2722 };
2723 static const unsigned int scif3_data_b_mux[] = {
2724         RX3_B_MARK, TX3_B_MARK,
2725 };
2726 static const unsigned int scif3_clk_b_pins[] = {
2727         /* SCK */
2728         RCAR_GP_PIN(4, 8),
2729 };
2730 static const unsigned int scif3_clk_b_mux[] = {
2731         SCIF3_SCK_B_MARK,
2732 };
2733 static const unsigned int scif3_data_c_pins[] = {
2734         /* RX, TX */
2735         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2736 };
2737 static const unsigned int scif3_data_c_mux[] = {
2738         RX3_C_MARK, TX3_C_MARK,
2739 };
2740 static const unsigned int scif3_data_d_pins[] = {
2741         /* RX, TX */
2742         RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
2743 };
2744 static const unsigned int scif3_data_d_mux[] = {
2745         RX3_D_MARK, TX3_D_MARK,
2746 };
2747 /* - SCIF4 ------------------------------------------------------------------ */
2748 static const unsigned int scif4_data_pins[] = {
2749         /* RX, TX */
2750         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2751 };
2752 static const unsigned int scif4_data_mux[] = {
2753         RX4_MARK, TX4_MARK,
2754 };
2755 static const unsigned int scif4_data_b_pins[] = {
2756         /* RX, TX */
2757         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2758 };
2759 static const unsigned int scif4_data_b_mux[] = {
2760         RX4_B_MARK, TX4_B_MARK,
2761 };
2762 static const unsigned int scif4_data_c_pins[] = {
2763         /* RX, TX */
2764         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2765 };
2766 static const unsigned int scif4_data_c_mux[] = {
2767         RX4_C_MARK, TX4_C_MARK,
2768 };
2769 /* - SCIF5 ------------------------------------------------------------------ */
2770 static const unsigned int scif5_data_pins[] = {
2771         /* RX, TX */
2772         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2773 };
2774 static const unsigned int scif5_data_mux[] = {
2775         RX5_MARK, TX5_MARK,
2776 };
2777 static const unsigned int scif5_data_b_pins[] = {
2778         /* RX, TX */
2779         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
2780 };
2781 static const unsigned int scif5_data_b_mux[] = {
2782         RX5_B_MARK, TX5_B_MARK,
2783 };
2784 /* - SCIFA0 ----------------------------------------------------------------- */
2785 static const unsigned int scifa0_data_pins[] = {
2786         /* RXD, TXD */
2787         RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2788 };
2789 static const unsigned int scifa0_data_mux[] = {
2790         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2791 };
2792 static const unsigned int scifa0_data_b_pins[] = {
2793         /* RXD, TXD */
2794         RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2795 };
2796 static const unsigned int scifa0_data_b_mux[] = {
2797         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2798 };
2799 /* - SCIFA1 ----------------------------------------------------------------- */
2800 static const unsigned int scifa1_data_pins[] = {
2801         /* RXD, TXD */
2802         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2803 };
2804 static const unsigned int scifa1_data_mux[] = {
2805         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2806 };
2807 static const unsigned int scifa1_clk_pins[] = {
2808         /* SCK */
2809         RCAR_GP_PIN(3, 10),
2810 };
2811 static const unsigned int scifa1_clk_mux[] = {
2812         SCIFA1_SCK_MARK,
2813 };
2814 static const unsigned int scifa1_data_b_pins[] = {
2815         /* RXD, TXD */
2816         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2817 };
2818 static const unsigned int scifa1_data_b_mux[] = {
2819         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2820 };
2821 static const unsigned int scifa1_clk_b_pins[] = {
2822         /* SCK */
2823         RCAR_GP_PIN(1, 0),
2824 };
2825 static const unsigned int scifa1_clk_b_mux[] = {
2826         SCIFA1_SCK_B_MARK,
2827 };
2828 static const unsigned int scifa1_data_c_pins[] = {
2829         /* RXD, TXD */
2830         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2831 };
2832 static const unsigned int scifa1_data_c_mux[] = {
2833         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2834 };
2835 /* - SCIFA2 ----------------------------------------------------------------- */
2836 static const unsigned int scifa2_data_pins[] = {
2837         /* RXD, TXD */
2838         RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2839 };
2840 static const unsigned int scifa2_data_mux[] = {
2841         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2842 };
2843 static const unsigned int scifa2_clk_pins[] = {
2844         /* SCK */
2845         RCAR_GP_PIN(3, 18),
2846 };
2847 static const unsigned int scifa2_clk_mux[] = {
2848         SCIFA2_SCK_MARK,
2849 };
2850 static const unsigned int scifa2_data_b_pins[] = {
2851         /* RXD, TXD */
2852         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2853 };
2854 static const unsigned int scifa2_data_b_mux[] = {
2855         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2856 };
2857 /* - SCIFA3 ----------------------------------------------------------------- */
2858 static const unsigned int scifa3_data_pins[] = {
2859         /* RXD, TXD */
2860         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2861 };
2862 static const unsigned int scifa3_data_mux[] = {
2863         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2864 };
2865 static const unsigned int scifa3_clk_pins[] = {
2866         /* SCK */
2867         RCAR_GP_PIN(3, 23),
2868 };
2869 static const unsigned int scifa3_clk_mux[] = {
2870         SCIFA3_SCK_MARK,
2871 };
2872 static const unsigned int scifa3_data_b_pins[] = {
2873         /* RXD, TXD */
2874         RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
2875 };
2876 static const unsigned int scifa3_data_b_mux[] = {
2877         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2878 };
2879 static const unsigned int scifa3_clk_b_pins[] = {
2880         /* SCK */
2881         RCAR_GP_PIN(4, 8),
2882 };
2883 static const unsigned int scifa3_clk_b_mux[] = {
2884         SCIFA3_SCK_B_MARK,
2885 };
2886 static const unsigned int scifa3_data_c_pins[] = {
2887         /* RXD, TXD */
2888         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
2889 };
2890 static const unsigned int scifa3_data_c_mux[] = {
2891         SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
2892 };
2893 static const unsigned int scifa3_clk_c_pins[] = {
2894         /* SCK */
2895         RCAR_GP_PIN(7, 22),
2896 };
2897 static const unsigned int scifa3_clk_c_mux[] = {
2898         SCIFA3_SCK_C_MARK,
2899 };
2900 /* - SCIFA4 ----------------------------------------------------------------- */
2901 static const unsigned int scifa4_data_pins[] = {
2902         /* RXD, TXD */
2903         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2904 };
2905 static const unsigned int scifa4_data_mux[] = {
2906         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2907 };
2908 static const unsigned int scifa4_data_b_pins[] = {
2909         /* RXD, TXD */
2910         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2911 };
2912 static const unsigned int scifa4_data_b_mux[] = {
2913         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2914 };
2915 static const unsigned int scifa4_data_c_pins[] = {
2916         /* RXD, TXD */
2917         RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2918 };
2919 static const unsigned int scifa4_data_c_mux[] = {
2920         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2921 };
2922 /* - SCIFA5 ----------------------------------------------------------------- */
2923 static const unsigned int scifa5_data_pins[] = {
2924         /* RXD, TXD */
2925         RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2926 };
2927 static const unsigned int scifa5_data_mux[] = {
2928         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2929 };
2930 static const unsigned int scifa5_data_b_pins[] = {
2931         /* RXD, TXD */
2932         RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2933 };
2934 static const unsigned int scifa5_data_b_mux[] = {
2935         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2936 };
2937 static const unsigned int scifa5_data_c_pins[] = {
2938         /* RXD, TXD */
2939         RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
2940 };
2941 static const unsigned int scifa5_data_c_mux[] = {
2942         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
2943 };
2944 /* - SCIFB0 ----------------------------------------------------------------- */
2945 static const unsigned int scifb0_data_pins[] = {
2946         /* RXD, TXD */
2947         RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2948 };
2949 static const unsigned int scifb0_data_mux[] = {
2950         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2951 };
2952 static const unsigned int scifb0_clk_pins[] = {
2953         /* SCK */
2954         RCAR_GP_PIN(7, 2),
2955 };
2956 static const unsigned int scifb0_clk_mux[] = {
2957         SCIFB0_SCK_MARK,
2958 };
2959 static const unsigned int scifb0_ctrl_pins[] = {
2960         /* RTS, CTS */
2961         RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2962 };
2963 static const unsigned int scifb0_ctrl_mux[] = {
2964         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2965 };
2966 static const unsigned int scifb0_data_b_pins[] = {
2967         /* RXD, TXD */
2968         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2969 };
2970 static const unsigned int scifb0_data_b_mux[] = {
2971         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2972 };
2973 static const unsigned int scifb0_clk_b_pins[] = {
2974         /* SCK */
2975         RCAR_GP_PIN(5, 31),
2976 };
2977 static const unsigned int scifb0_clk_b_mux[] = {
2978         SCIFB0_SCK_B_MARK,
2979 };
2980 static const unsigned int scifb0_ctrl_b_pins[] = {
2981         /* RTS, CTS */
2982         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
2983 };
2984 static const unsigned int scifb0_ctrl_b_mux[] = {
2985         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
2986 };
2987 static const unsigned int scifb0_data_c_pins[] = {
2988         /* RXD, TXD */
2989         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2990 };
2991 static const unsigned int scifb0_data_c_mux[] = {
2992         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
2993 };
2994 static const unsigned int scifb0_clk_c_pins[] = {
2995         /* SCK */
2996         RCAR_GP_PIN(2, 30),
2997 };
2998 static const unsigned int scifb0_clk_c_mux[] = {
2999         SCIFB0_SCK_C_MARK,
3000 };
3001 static const unsigned int scifb0_data_d_pins[] = {
3002         /* RXD, TXD */
3003         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3004 };
3005 static const unsigned int scifb0_data_d_mux[] = {
3006         SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3007 };
3008 static const unsigned int scifb0_clk_d_pins[] = {
3009         /* SCK */
3010         RCAR_GP_PIN(4, 17),
3011 };
3012 static const unsigned int scifb0_clk_d_mux[] = {
3013         SCIFB0_SCK_D_MARK,
3014 };
3015 /* - SCIFB1 ----------------------------------------------------------------- */
3016 static const unsigned int scifb1_data_pins[] = {
3017         /* RXD, TXD */
3018         RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3019 };
3020 static const unsigned int scifb1_data_mux[] = {
3021         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3022 };
3023 static const unsigned int scifb1_clk_pins[] = {
3024         /* SCK */
3025         RCAR_GP_PIN(7, 7),
3026 };
3027 static const unsigned int scifb1_clk_mux[] = {
3028         SCIFB1_SCK_MARK,
3029 };
3030 static const unsigned int scifb1_ctrl_pins[] = {
3031         /* RTS, CTS */
3032         RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3033 };
3034 static const unsigned int scifb1_ctrl_mux[] = {
3035         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3036 };
3037 static const unsigned int scifb1_data_b_pins[] = {
3038         /* RXD, TXD */
3039         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3040 };
3041 static const unsigned int scifb1_data_b_mux[] = {
3042         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3043 };
3044 static const unsigned int scifb1_clk_b_pins[] = {
3045         /* SCK */
3046         RCAR_GP_PIN(1, 3),
3047 };
3048 static const unsigned int scifb1_clk_b_mux[] = {
3049         SCIFB1_SCK_B_MARK,
3050 };
3051 static const unsigned int scifb1_data_c_pins[] = {
3052         /* RXD, TXD */
3053         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3054 };
3055 static const unsigned int scifb1_data_c_mux[] = {
3056         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3057 };
3058 static const unsigned int scifb1_clk_c_pins[] = {
3059         /* SCK */
3060         RCAR_GP_PIN(7, 11),
3061 };
3062 static const unsigned int scifb1_clk_c_mux[] = {
3063         SCIFB1_SCK_C_MARK,
3064 };
3065 static const unsigned int scifb1_data_d_pins[] = {
3066         /* RXD, TXD */
3067         RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3068 };
3069 static const unsigned int scifb1_data_d_mux[] = {
3070         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3071 };
3072 /* - SCIFB2 ----------------------------------------------------------------- */
3073 static const unsigned int scifb2_data_pins[] = {
3074         /* RXD, TXD */
3075         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3076 };
3077 static const unsigned int scifb2_data_mux[] = {
3078         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3079 };
3080 static const unsigned int scifb2_clk_pins[] = {
3081         /* SCK */
3082         RCAR_GP_PIN(4, 15),
3083 };
3084 static const unsigned int scifb2_clk_mux[] = {
3085         SCIFB2_SCK_MARK,
3086 };
3087 static const unsigned int scifb2_ctrl_pins[] = {
3088         /* RTS, CTS */
3089         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3090 };
3091 static const unsigned int scifb2_ctrl_mux[] = {
3092         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3093 };
3094 static const unsigned int scifb2_data_b_pins[] = {
3095         /* RXD, TXD */
3096         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3097 };
3098 static const unsigned int scifb2_data_b_mux[] = {
3099         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3100 };
3101 static const unsigned int scifb2_clk_b_pins[] = {
3102         /* SCK */
3103         RCAR_GP_PIN(5, 31),
3104 };
3105 static const unsigned int scifb2_clk_b_mux[] = {
3106         SCIFB2_SCK_B_MARK,
3107 };
3108 static const unsigned int scifb2_ctrl_b_pins[] = {
3109         /* RTS, CTS */
3110         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3111 };
3112 static const unsigned int scifb2_ctrl_b_mux[] = {
3113         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3114 };
3115 static const unsigned int scifb2_data_c_pins[] = {
3116         /* RXD, TXD */
3117         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3118 };
3119 static const unsigned int scifb2_data_c_mux[] = {
3120         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3121 };
3122 static const unsigned int scifb2_clk_c_pins[] = {
3123         /* SCK */
3124         RCAR_GP_PIN(5, 27),
3125 };
3126 static const unsigned int scifb2_clk_c_mux[] = {
3127         SCIFB2_SCK_C_MARK,
3128 };
3129 static const unsigned int scifb2_data_d_pins[] = {
3130         /* RXD, TXD */
3131         RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3132 };
3133 static const unsigned int scifb2_data_d_mux[] = {
3134         SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3135 };
3136 /* - SDHI0 ------------------------------------------------------------------ */
3137 static const unsigned int sdhi0_data1_pins[] = {
3138         /* D0 */
3139         RCAR_GP_PIN(6, 2),
3140 };
3141 static const unsigned int sdhi0_data1_mux[] = {
3142         SD0_DATA0_MARK,
3143 };
3144 static const unsigned int sdhi0_data4_pins[] = {
3145         /* D[0:3] */
3146         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3147         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3148 };
3149 static const unsigned int sdhi0_data4_mux[] = {
3150         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3151 };
3152 static const unsigned int sdhi0_ctrl_pins[] = {
3153         /* CLK, CMD */
3154         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3155 };
3156 static const unsigned int sdhi0_ctrl_mux[] = {
3157         SD0_CLK_MARK, SD0_CMD_MARK,
3158 };
3159 static const unsigned int sdhi0_cd_pins[] = {
3160         /* CD */
3161         RCAR_GP_PIN(6, 6),
3162 };
3163 static const unsigned int sdhi0_cd_mux[] = {
3164         SD0_CD_MARK,
3165 };
3166 static const unsigned int sdhi0_wp_pins[] = {
3167         /* WP */
3168         RCAR_GP_PIN(6, 7),
3169 };
3170 static const unsigned int sdhi0_wp_mux[] = {
3171         SD0_WP_MARK,
3172 };
3173 /* - SDHI1 ------------------------------------------------------------------ */
3174 static const unsigned int sdhi1_data1_pins[] = {
3175         /* D0 */
3176         RCAR_GP_PIN(6, 10),
3177 };
3178 static const unsigned int sdhi1_data1_mux[] = {
3179         SD1_DATA0_MARK,
3180 };
3181 static const unsigned int sdhi1_data4_pins[] = {
3182         /* D[0:3] */
3183         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3184         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3185 };
3186 static const unsigned int sdhi1_data4_mux[] = {
3187         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3188 };
3189 static const unsigned int sdhi1_ctrl_pins[] = {
3190         /* CLK, CMD */
3191         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3192 };
3193 static const unsigned int sdhi1_ctrl_mux[] = {
3194         SD1_CLK_MARK, SD1_CMD_MARK,
3195 };
3196 static const unsigned int sdhi1_cd_pins[] = {
3197         /* CD */
3198         RCAR_GP_PIN(6, 14),
3199 };
3200 static const unsigned int sdhi1_cd_mux[] = {
3201         SD1_CD_MARK,
3202 };
3203 static const unsigned int sdhi1_wp_pins[] = {
3204         /* WP */
3205         RCAR_GP_PIN(6, 15),
3206 };
3207 static const unsigned int sdhi1_wp_mux[] = {
3208         SD1_WP_MARK,
3209 };
3210 /* - SDHI2 ------------------------------------------------------------------ */
3211 static const unsigned int sdhi2_data1_pins[] = {
3212         /* D0 */
3213         RCAR_GP_PIN(6, 18),
3214 };
3215 static const unsigned int sdhi2_data1_mux[] = {
3216         SD2_DATA0_MARK,
3217 };
3218 static const unsigned int sdhi2_data4_pins[] = {
3219         /* D[0:3] */
3220         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3221         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3222 };
3223 static const unsigned int sdhi2_data4_mux[] = {
3224         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3225 };
3226 static const unsigned int sdhi2_ctrl_pins[] = {
3227         /* CLK, CMD */
3228         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3229 };
3230 static const unsigned int sdhi2_ctrl_mux[] = {
3231         SD2_CLK_MARK, SD2_CMD_MARK,
3232 };
3233 static const unsigned int sdhi2_cd_pins[] = {
3234         /* CD */
3235         RCAR_GP_PIN(6, 22),
3236 };
3237 static const unsigned int sdhi2_cd_mux[] = {
3238         SD2_CD_MARK,
3239 };
3240 static const unsigned int sdhi2_wp_pins[] = {
3241         /* WP */
3242         RCAR_GP_PIN(6, 23),
3243 };
3244 static const unsigned int sdhi2_wp_mux[] = {
3245         SD2_WP_MARK,
3246 };
3247 /* - USB0 ------------------------------------------------------------------- */
3248 static const unsigned int usb0_pins[] = {
3249         RCAR_GP_PIN(7, 23), /* PWEN */
3250         RCAR_GP_PIN(7, 24), /* OVC */
3251 };
3252 static const unsigned int usb0_mux[] = {
3253         USB0_PWEN_MARK,
3254         USB0_OVC_MARK,
3255 };
3256 /* - USB1 ------------------------------------------------------------------- */
3257 static const unsigned int usb1_pins[] = {
3258         RCAR_GP_PIN(7, 25), /* PWEN */
3259         RCAR_GP_PIN(6, 30), /* OVC */
3260 };
3261 static const unsigned int usb1_mux[] = {
3262         USB1_PWEN_MARK,
3263         USB1_OVC_MARK,
3264 };
3265
3266 union vin_data {
3267         unsigned int data24[24];
3268         unsigned int data20[20];
3269         unsigned int data16[16];
3270         unsigned int data12[12];
3271         unsigned int data10[10];
3272         unsigned int data8[8];
3273 };
3274
3275 #define VIN_DATA_PIN_GROUP(n, s)                                \
3276         {                                                       \
3277                 .name = #n#s,                                   \
3278                 .pins = n##_pins.data##s,                       \
3279                 .mux = n##_mux.data##s,                         \
3280                 .nr_pins = ARRAY_SIZE(n##_pins.data##s),        \
3281         }
3282
3283 /* - VIN0 ------------------------------------------------------------------- */
3284 static const union vin_data vin0_data_pins = {
3285         .data24 = {
3286                 /* B */
3287                 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
3288                 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3289                 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3290                 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3291                 /* G */
3292                 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3293                 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3294                 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3295                 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
3296                 /* R */
3297                 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
3298                 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
3299                 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
3300                 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3301         },
3302 };
3303 static const union vin_data vin0_data_mux = {
3304         .data24 = {
3305                 /* B */
3306                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3307                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3308                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3309                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3310                 /* G */
3311                 VI0_G0_MARK, VI0_G1_MARK,
3312                 VI0_G2_MARK, VI0_G3_MARK,
3313                 VI0_G4_MARK, VI0_G5_MARK,
3314                 VI0_G6_MARK, VI0_G7_MARK,
3315                 /* R */
3316                 VI0_R0_MARK, VI0_R1_MARK,
3317                 VI0_R2_MARK, VI0_R3_MARK,
3318                 VI0_R4_MARK, VI0_R5_MARK,
3319                 VI0_R6_MARK, VI0_R7_MARK,
3320         },
3321 };
3322 static const unsigned int vin0_data18_pins[] = {
3323         /* B */
3324         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3325         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3326         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3327         /* G */
3328         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3329         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3330         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
3331         /* R */
3332         RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
3333         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
3334         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3335 };
3336 static const unsigned int vin0_data18_mux[] = {
3337         /* B */
3338         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3339         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3340         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3341         /* G */
3342         VI0_G2_MARK, VI0_G3_MARK,
3343         VI0_G4_MARK, VI0_G5_MARK,
3344         VI0_G6_MARK, VI0_G7_MARK,
3345         /* R */
3346         VI0_R2_MARK, VI0_R3_MARK,
3347         VI0_R4_MARK, VI0_R5_MARK,
3348         VI0_R6_MARK, VI0_R7_MARK,
3349 };
3350 static const unsigned int vin0_sync_pins[] = {
3351         RCAR_GP_PIN(4, 3), /* HSYNC */
3352         RCAR_GP_PIN(4, 4), /* VSYNC */
3353 };
3354 static const unsigned int vin0_sync_mux[] = {
3355         VI0_HSYNC_N_MARK,
3356         VI0_VSYNC_N_MARK,
3357 };
3358 static const unsigned int vin0_field_pins[] = {
3359         RCAR_GP_PIN(4, 2),
3360 };
3361 static const unsigned int vin0_field_mux[] = {
3362         VI0_FIELD_MARK,
3363 };
3364 static const unsigned int vin0_clkenb_pins[] = {
3365         RCAR_GP_PIN(4, 1),
3366 };
3367 static const unsigned int vin0_clkenb_mux[] = {
3368         VI0_CLKENB_MARK,
3369 };
3370 static const unsigned int vin0_clk_pins[] = {
3371         RCAR_GP_PIN(4, 0),
3372 };
3373 static const unsigned int vin0_clk_mux[] = {
3374         VI0_CLK_MARK,
3375 };
3376 /* - VIN1 ----------------------------------------------------------------- */
3377 static const unsigned int vin1_data8_pins[] = {
3378         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3379         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
3380         RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
3381         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
3382 };
3383 static const unsigned int vin1_data8_mux[] = {
3384         VI1_DATA0_MARK, VI1_DATA1_MARK,
3385         VI1_DATA2_MARK, VI1_DATA3_MARK,
3386         VI1_DATA4_MARK, VI1_DATA5_MARK,
3387         VI1_DATA6_MARK, VI1_DATA7_MARK,
3388 };
3389 static const unsigned int vin1_sync_pins[] = {
3390         RCAR_GP_PIN(5, 0), /* HSYNC */
3391         RCAR_GP_PIN(5, 1), /* VSYNC */
3392 };
3393 static const unsigned int vin1_sync_mux[] = {
3394         VI1_HSYNC_N_MARK,
3395         VI1_VSYNC_N_MARK,
3396 };
3397 static const unsigned int vin1_field_pins[] = {
3398         RCAR_GP_PIN(5, 3),
3399 };
3400 static const unsigned int vin1_field_mux[] = {
3401         VI1_FIELD_MARK,
3402 };
3403 static const unsigned int vin1_clkenb_pins[] = {
3404         RCAR_GP_PIN(5, 2),
3405 };
3406 static const unsigned int vin1_clkenb_mux[] = {
3407         VI1_CLKENB_MARK,
3408 };
3409 static const unsigned int vin1_clk_pins[] = {
3410         RCAR_GP_PIN(5, 4),
3411 };
3412 static const unsigned int vin1_clk_mux[] = {
3413         VI1_CLK_MARK,
3414 };
3415 static const union vin_data vin1_b_data_pins = {
3416         .data24 = {
3417                 /* B */
3418                 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3419                 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3420                 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3421                 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3422                 /* G */
3423                 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3424                 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3425                 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3426                 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
3427                 /* R */
3428                 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3429                 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3430                 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
3431                 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
3432         },
3433 };
3434 static const union vin_data vin1_b_data_mux = {
3435         .data24 = {
3436                 /* B */
3437                 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
3438                 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
3439                 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
3440                 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
3441                 /* G */
3442                 VI1_G0_B_MARK, VI1_G1_B_MARK,
3443                 VI1_G2_B_MARK, VI1_G3_B_MARK,
3444                 VI1_G4_B_MARK, VI1_G5_B_MARK,
3445                 VI1_G6_B_MARK, VI1_G7_B_MARK,
3446                 /* R */
3447                 VI1_R0_B_MARK, VI1_R1_B_MARK,
3448                 VI1_R2_B_MARK, VI1_R3_B_MARK,
3449                 VI1_R4_B_MARK, VI1_R5_B_MARK,
3450                 VI1_R6_B_MARK, VI1_R7_B_MARK,
3451         },
3452 };
3453 static const unsigned int vin1_b_data18_pins[] = {
3454         /* B */
3455         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3456         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3457         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3458         /* G */
3459         RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3460         RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3461         RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
3462         /* R */
3463         RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3464         RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
3465         RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
3466 };
3467 static const unsigned int vin1_b_data18_mux[] = {
3468         /* B */
3469         VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
3470         VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
3471         VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
3472         VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
3473         /* G */
3474         VI1_G0_B_MARK, VI1_G1_B_MARK,
3475         VI1_G2_B_MARK, VI1_G3_B_MARK,
3476         VI1_G4_B_MARK, VI1_G5_B_MARK,
3477         VI1_G6_B_MARK, VI1_G7_B_MARK,
3478         /* R */
3479         VI1_R0_B_MARK, VI1_R1_B_MARK,
3480         VI1_R2_B_MARK, VI1_R3_B_MARK,
3481         VI1_R4_B_MARK, VI1_R5_B_MARK,
3482         VI1_R6_B_MARK, VI1_R7_B_MARK,
3483 };
3484 static const unsigned int vin1_b_sync_pins[] = {
3485         RCAR_GP_PIN(3, 17), /* HSYNC */
3486         RCAR_GP_PIN(3, 18), /* VSYNC */
3487 };
3488 static const unsigned int vin1_b_sync_mux[] = {
3489         VI1_HSYNC_N_B_MARK,
3490         VI1_VSYNC_N_B_MARK,
3491 };
3492 static const unsigned int vin1_b_field_pins[] = {
3493         RCAR_GP_PIN(3, 20),
3494 };
3495 static const unsigned int vin1_b_field_mux[] = {
3496         VI1_FIELD_B_MARK,
3497 };
3498 static const unsigned int vin1_b_clkenb_pins[] = {
3499         RCAR_GP_PIN(3, 19),
3500 };
3501 static const unsigned int vin1_b_clkenb_mux[] = {
3502         VI1_CLKENB_B_MARK,
3503 };
3504 static const unsigned int vin1_b_clk_pins[] = {
3505         RCAR_GP_PIN(3, 16),
3506 };
3507 static const unsigned int vin1_b_clk_mux[] = {
3508         VI1_CLK_B_MARK,
3509 };
3510 /* - VIN2 ----------------------------------------------------------------- */
3511 static const unsigned int vin2_data8_pins[] = {
3512         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3513         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3514         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3515         RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
3516 };
3517 static const unsigned int vin2_data8_mux[] = {
3518         VI2_DATA0_MARK, VI2_DATA1_MARK,
3519         VI2_DATA2_MARK, VI2_DATA3_MARK,
3520         VI2_DATA4_MARK, VI2_DATA5_MARK,
3521         VI2_DATA6_MARK, VI2_DATA7_MARK,
3522 };
3523 static const unsigned int vin2_sync_pins[] = {
3524         RCAR_GP_PIN(4, 15), /* HSYNC */
3525         RCAR_GP_PIN(4, 16), /* VSYNC */
3526 };
3527 static const unsigned int vin2_sync_mux[] = {
3528         VI2_HSYNC_N_MARK,
3529         VI2_VSYNC_N_MARK,
3530 };
3531 static const unsigned int vin2_field_pins[] = {
3532         RCAR_GP_PIN(4, 18),
3533 };
3534 static const unsigned int vin2_field_mux[] = {
3535         VI2_FIELD_MARK,
3536 };
3537 static const unsigned int vin2_clkenb_pins[] = {
3538         RCAR_GP_PIN(4, 17),
3539 };
3540 static const unsigned int vin2_clkenb_mux[] = {
3541         VI2_CLKENB_MARK,
3542 };
3543 static const unsigned int vin2_clk_pins[] = {
3544         RCAR_GP_PIN(4, 19),
3545 };
3546 static const unsigned int vin2_clk_mux[] = {
3547         VI2_CLK_MARK,
3548 };
3549
3550 static const struct sh_pfc_pin_group pinmux_groups[] = {
3551         SH_PFC_PIN_GROUP(du_rgb666),
3552         SH_PFC_PIN_GROUP(du_rgb888),
3553         SH_PFC_PIN_GROUP(du_clk_out_0),
3554         SH_PFC_PIN_GROUP(du_clk_out_1),
3555         SH_PFC_PIN_GROUP(du_sync),
3556         SH_PFC_PIN_GROUP(du_cde_disp),
3557         SH_PFC_PIN_GROUP(du0_clk_in),
3558         SH_PFC_PIN_GROUP(du1_clk_in),
3559         SH_PFC_PIN_GROUP(du1_clk_in_b),
3560         SH_PFC_PIN_GROUP(du1_clk_in_c),
3561         SH_PFC_PIN_GROUP(eth_link),
3562         SH_PFC_PIN_GROUP(eth_magic),
3563         SH_PFC_PIN_GROUP(eth_mdio),
3564         SH_PFC_PIN_GROUP(eth_rmii),
3565         SH_PFC_PIN_GROUP(i2c0),
3566         SH_PFC_PIN_GROUP(i2c0_b),
3567         SH_PFC_PIN_GROUP(i2c0_c),
3568         SH_PFC_PIN_GROUP(i2c1),
3569         SH_PFC_PIN_GROUP(i2c1_b),
3570         SH_PFC_PIN_GROUP(i2c1_c),
3571         SH_PFC_PIN_GROUP(i2c1_d),
3572         SH_PFC_PIN_GROUP(i2c1_e),
3573         SH_PFC_PIN_GROUP(i2c2),
3574         SH_PFC_PIN_GROUP(i2c2_b),
3575         SH_PFC_PIN_GROUP(i2c2_c),
3576         SH_PFC_PIN_GROUP(i2c2_d),
3577         SH_PFC_PIN_GROUP(i2c3),
3578         SH_PFC_PIN_GROUP(i2c3_b),
3579         SH_PFC_PIN_GROUP(i2c3_c),
3580         SH_PFC_PIN_GROUP(i2c3_d),
3581         SH_PFC_PIN_GROUP(i2c4),
3582         SH_PFC_PIN_GROUP(i2c4_b),
3583         SH_PFC_PIN_GROUP(i2c4_c),
3584         SH_PFC_PIN_GROUP(i2c7),
3585         SH_PFC_PIN_GROUP(i2c7_b),
3586         SH_PFC_PIN_GROUP(i2c7_c),
3587         SH_PFC_PIN_GROUP(i2c8),
3588         SH_PFC_PIN_GROUP(i2c8_b),
3589         SH_PFC_PIN_GROUP(i2c8_c),
3590         SH_PFC_PIN_GROUP(intc_irq0),
3591         SH_PFC_PIN_GROUP(intc_irq1),
3592         SH_PFC_PIN_GROUP(intc_irq2),
3593         SH_PFC_PIN_GROUP(intc_irq3),
3594         SH_PFC_PIN_GROUP(mmc_data1),
3595         SH_PFC_PIN_GROUP(mmc_data4),
3596         SH_PFC_PIN_GROUP(mmc_data8),
3597         SH_PFC_PIN_GROUP(mmc_ctrl),
3598         SH_PFC_PIN_GROUP(msiof0_clk),
3599         SH_PFC_PIN_GROUP(msiof0_sync),
3600         SH_PFC_PIN_GROUP(msiof0_ss1),
3601         SH_PFC_PIN_GROUP(msiof0_ss2),
3602         SH_PFC_PIN_GROUP(msiof0_rx),
3603         SH_PFC_PIN_GROUP(msiof0_tx),
3604         SH_PFC_PIN_GROUP(msiof0_clk_b),
3605         SH_PFC_PIN_GROUP(msiof0_sync_b),
3606         SH_PFC_PIN_GROUP(msiof0_ss1_b),
3607         SH_PFC_PIN_GROUP(msiof0_ss2_b),
3608         SH_PFC_PIN_GROUP(msiof0_rx_b),
3609         SH_PFC_PIN_GROUP(msiof0_tx_b),
3610         SH_PFC_PIN_GROUP(msiof0_clk_c),
3611         SH_PFC_PIN_GROUP(msiof0_sync_c),
3612         SH_PFC_PIN_GROUP(msiof0_ss1_c),
3613         SH_PFC_PIN_GROUP(msiof0_ss2_c),
3614         SH_PFC_PIN_GROUP(msiof0_rx_c),
3615         SH_PFC_PIN_GROUP(msiof0_tx_c),
3616         SH_PFC_PIN_GROUP(msiof1_clk),
3617         SH_PFC_PIN_GROUP(msiof1_sync),
3618         SH_PFC_PIN_GROUP(msiof1_ss1),
3619         SH_PFC_PIN_GROUP(msiof1_ss2),
3620         SH_PFC_PIN_GROUP(msiof1_rx),
3621         SH_PFC_PIN_GROUP(msiof1_tx),
3622         SH_PFC_PIN_GROUP(msiof1_clk_b),
3623         SH_PFC_PIN_GROUP(msiof1_sync_b),
3624         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3625         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3626         SH_PFC_PIN_GROUP(msiof1_rx_b),
3627         SH_PFC_PIN_GROUP(msiof1_tx_b),
3628         SH_PFC_PIN_GROUP(msiof1_clk_c),
3629         SH_PFC_PIN_GROUP(msiof1_sync_c),
3630         SH_PFC_PIN_GROUP(msiof1_rx_c),
3631         SH_PFC_PIN_GROUP(msiof1_tx_c),
3632         SH_PFC_PIN_GROUP(msiof1_clk_d),
3633         SH_PFC_PIN_GROUP(msiof1_sync_d),
3634         SH_PFC_PIN_GROUP(msiof1_ss1_d),
3635         SH_PFC_PIN_GROUP(msiof1_rx_d),
3636         SH_PFC_PIN_GROUP(msiof1_tx_d),
3637         SH_PFC_PIN_GROUP(msiof1_clk_e),
3638         SH_PFC_PIN_GROUP(msiof1_sync_e),
3639         SH_PFC_PIN_GROUP(msiof1_rx_e),
3640         SH_PFC_PIN_GROUP(msiof1_tx_e),
3641         SH_PFC_PIN_GROUP(msiof2_clk),
3642         SH_PFC_PIN_GROUP(msiof2_sync),
3643         SH_PFC_PIN_GROUP(msiof2_ss1),
3644         SH_PFC_PIN_GROUP(msiof2_ss2),
3645         SH_PFC_PIN_GROUP(msiof2_rx),
3646         SH_PFC_PIN_GROUP(msiof2_tx),
3647         SH_PFC_PIN_GROUP(msiof2_clk_b),
3648         SH_PFC_PIN_GROUP(msiof2_sync_b),
3649         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3650         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3651         SH_PFC_PIN_GROUP(msiof2_rx_b),
3652         SH_PFC_PIN_GROUP(msiof2_tx_b),
3653         SH_PFC_PIN_GROUP(msiof2_clk_c),
3654         SH_PFC_PIN_GROUP(msiof2_sync_c),
3655         SH_PFC_PIN_GROUP(msiof2_rx_c),
3656         SH_PFC_PIN_GROUP(msiof2_tx_c),
3657         SH_PFC_PIN_GROUP(msiof2_clk_d),
3658         SH_PFC_PIN_GROUP(msiof2_sync_d),
3659         SH_PFC_PIN_GROUP(msiof2_ss1_d),
3660         SH_PFC_PIN_GROUP(msiof2_ss2_d),
3661         SH_PFC_PIN_GROUP(msiof2_rx_d),
3662         SH_PFC_PIN_GROUP(msiof2_tx_d),
3663         SH_PFC_PIN_GROUP(msiof2_clk_e),
3664         SH_PFC_PIN_GROUP(msiof2_sync_e),
3665         SH_PFC_PIN_GROUP(msiof2_rx_e),
3666         SH_PFC_PIN_GROUP(msiof2_tx_e),
3667         SH_PFC_PIN_GROUP(qspi_ctrl),
3668         SH_PFC_PIN_GROUP(qspi_data2),
3669         SH_PFC_PIN_GROUP(qspi_data4),
3670         SH_PFC_PIN_GROUP(qspi_ctrl_b),
3671         SH_PFC_PIN_GROUP(qspi_data2_b),
3672         SH_PFC_PIN_GROUP(qspi_data4_b),
3673         SH_PFC_PIN_GROUP(scif0_data),
3674         SH_PFC_PIN_GROUP(scif0_data_b),
3675         SH_PFC_PIN_GROUP(scif0_data_c),
3676         SH_PFC_PIN_GROUP(scif0_data_d),
3677         SH_PFC_PIN_GROUP(scif0_data_e),
3678         SH_PFC_PIN_GROUP(scif1_data),
3679         SH_PFC_PIN_GROUP(scif1_data_b),
3680         SH_PFC_PIN_GROUP(scif1_clk_b),
3681         SH_PFC_PIN_GROUP(scif1_data_c),
3682         SH_PFC_PIN_GROUP(scif1_data_d),
3683         SH_PFC_PIN_GROUP(scif2_data),
3684         SH_PFC_PIN_GROUP(scif2_data_b),
3685         SH_PFC_PIN_GROUP(scif2_clk_b),
3686         SH_PFC_PIN_GROUP(scif2_data_c),
3687         SH_PFC_PIN_GROUP(scif2_data_e),
3688         SH_PFC_PIN_GROUP(scif3_data),
3689         SH_PFC_PIN_GROUP(scif3_clk),
3690         SH_PFC_PIN_GROUP(scif3_data_b),
3691         SH_PFC_PIN_GROUP(scif3_clk_b),
3692         SH_PFC_PIN_GROUP(scif3_data_c),
3693         SH_PFC_PIN_GROUP(scif3_data_d),
3694         SH_PFC_PIN_GROUP(scif4_data),
3695         SH_PFC_PIN_GROUP(scif4_data_b),
3696         SH_PFC_PIN_GROUP(scif4_data_c),
3697         SH_PFC_PIN_GROUP(scif5_data),
3698         SH_PFC_PIN_GROUP(scif5_data_b),
3699         SH_PFC_PIN_GROUP(scifa0_data),
3700         SH_PFC_PIN_GROUP(scifa0_data_b),
3701         SH_PFC_PIN_GROUP(scifa1_data),
3702         SH_PFC_PIN_GROUP(scifa1_clk),
3703         SH_PFC_PIN_GROUP(scifa1_data_b),
3704         SH_PFC_PIN_GROUP(scifa1_clk_b),
3705         SH_PFC_PIN_GROUP(scifa1_data_c),
3706         SH_PFC_PIN_GROUP(scifa2_data),
3707         SH_PFC_PIN_GROUP(scifa2_clk),
3708         SH_PFC_PIN_GROUP(scifa2_data_b),
3709         SH_PFC_PIN_GROUP(scifa3_data),
3710         SH_PFC_PIN_GROUP(scifa3_clk),
3711         SH_PFC_PIN_GROUP(scifa3_data_b),
3712         SH_PFC_PIN_GROUP(scifa3_clk_b),
3713         SH_PFC_PIN_GROUP(scifa3_data_c),
3714         SH_PFC_PIN_GROUP(scifa3_clk_c),
3715         SH_PFC_PIN_GROUP(scifa4_data),
3716         SH_PFC_PIN_GROUP(scifa4_data_b),
3717         SH_PFC_PIN_GROUP(scifa4_data_c),
3718         SH_PFC_PIN_GROUP(scifa5_data),
3719         SH_PFC_PIN_GROUP(scifa5_data_b),
3720         SH_PFC_PIN_GROUP(scifa5_data_c),
3721         SH_PFC_PIN_GROUP(scifb0_data),
3722         SH_PFC_PIN_GROUP(scifb0_clk),
3723         SH_PFC_PIN_GROUP(scifb0_ctrl),
3724         SH_PFC_PIN_GROUP(scifb0_data_b),
3725         SH_PFC_PIN_GROUP(scifb0_clk_b),
3726         SH_PFC_PIN_GROUP(scifb0_ctrl_b),
3727         SH_PFC_PIN_GROUP(scifb0_data_c),
3728         SH_PFC_PIN_GROUP(scifb0_clk_c),
3729         SH_PFC_PIN_GROUP(scifb0_data_d),
3730         SH_PFC_PIN_GROUP(scifb0_clk_d),
3731         SH_PFC_PIN_GROUP(scifb1_data),
3732         SH_PFC_PIN_GROUP(scifb1_clk),
3733         SH_PFC_PIN_GROUP(scifb1_ctrl),
3734         SH_PFC_PIN_GROUP(scifb1_data_b),
3735         SH_PFC_PIN_GROUP(scifb1_clk_b),
3736         SH_PFC_PIN_GROUP(scifb1_data_c),
3737         SH_PFC_PIN_GROUP(scifb1_clk_c),
3738         SH_PFC_PIN_GROUP(scifb1_data_d),
3739         SH_PFC_PIN_GROUP(scifb2_data),
3740         SH_PFC_PIN_GROUP(scifb2_clk),
3741         SH_PFC_PIN_GROUP(scifb2_ctrl),
3742         SH_PFC_PIN_GROUP(scifb2_data_b),
3743         SH_PFC_PIN_GROUP(scifb2_clk_b),
3744         SH_PFC_PIN_GROUP(scifb2_ctrl_b),
3745         SH_PFC_PIN_GROUP(scifb2_data_c),
3746         SH_PFC_PIN_GROUP(scifb2_clk_c),
3747         SH_PFC_PIN_GROUP(scifb2_data_d),
3748         SH_PFC_PIN_GROUP(sdhi0_data1),
3749         SH_PFC_PIN_GROUP(sdhi0_data4),
3750         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3751         SH_PFC_PIN_GROUP(sdhi0_cd),
3752         SH_PFC_PIN_GROUP(sdhi0_wp),
3753         SH_PFC_PIN_GROUP(sdhi1_data1),
3754         SH_PFC_PIN_GROUP(sdhi1_data4),
3755         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3756         SH_PFC_PIN_GROUP(sdhi1_cd),
3757         SH_PFC_PIN_GROUP(sdhi1_wp),
3758         SH_PFC_PIN_GROUP(sdhi2_data1),
3759         SH_PFC_PIN_GROUP(sdhi2_data4),
3760         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3761         SH_PFC_PIN_GROUP(sdhi2_cd),
3762         SH_PFC_PIN_GROUP(sdhi2_wp),
3763         SH_PFC_PIN_GROUP(usb0),
3764         SH_PFC_PIN_GROUP(usb1),
3765         VIN_DATA_PIN_GROUP(vin0_data, 24),
3766         VIN_DATA_PIN_GROUP(vin0_data, 20),
3767         SH_PFC_PIN_GROUP(vin0_data18),
3768         VIN_DATA_PIN_GROUP(vin0_data, 16),
3769         VIN_DATA_PIN_GROUP(vin0_data, 12),
3770         VIN_DATA_PIN_GROUP(vin0_data, 10),
3771         VIN_DATA_PIN_GROUP(vin0_data, 8),
3772         SH_PFC_PIN_GROUP(vin0_sync),
3773         SH_PFC_PIN_GROUP(vin0_field),
3774         SH_PFC_PIN_GROUP(vin0_clkenb),
3775         SH_PFC_PIN_GROUP(vin0_clk),
3776         SH_PFC_PIN_GROUP(vin1_data8),
3777         SH_PFC_PIN_GROUP(vin1_sync),
3778         SH_PFC_PIN_GROUP(vin1_field),
3779         SH_PFC_PIN_GROUP(vin1_clkenb),
3780         SH_PFC_PIN_GROUP(vin1_clk),
3781         VIN_DATA_PIN_GROUP(vin1_b_data, 24),
3782         VIN_DATA_PIN_GROUP(vin1_b_data, 20),
3783         SH_PFC_PIN_GROUP(vin1_b_data18),
3784         VIN_DATA_PIN_GROUP(vin1_b_data, 16),
3785         VIN_DATA_PIN_GROUP(vin1_b_data, 12),
3786         VIN_DATA_PIN_GROUP(vin1_b_data, 10),
3787         VIN_DATA_PIN_GROUP(vin1_b_data, 8),
3788         SH_PFC_PIN_GROUP(vin1_b_sync),
3789         SH_PFC_PIN_GROUP(vin1_b_field),
3790         SH_PFC_PIN_GROUP(vin1_b_clkenb),
3791         SH_PFC_PIN_GROUP(vin1_b_clk),
3792         SH_PFC_PIN_GROUP(vin2_data8),
3793         SH_PFC_PIN_GROUP(vin2_sync),
3794         SH_PFC_PIN_GROUP(vin2_field),
3795         SH_PFC_PIN_GROUP(vin2_clkenb),
3796         SH_PFC_PIN_GROUP(vin2_clk),
3797 };
3798
3799 static const char * const du_groups[] = {
3800         "du_rgb666",
3801         "du_rgb888",
3802         "du_clk_out_0",
3803         "du_clk_out_1",
3804         "du_sync",
3805         "du_cde_disp",
3806 };
3807
3808 static const char * const du0_groups[] = {
3809         "du0_clk_in",
3810 };
3811
3812 static const char * const du1_groups[] = {
3813         "du1_clk_in",
3814         "du1_clk_in_b",
3815         "du1_clk_in_c",
3816 };
3817
3818 static const char * const eth_groups[] = {
3819         "eth_link",
3820         "eth_magic",
3821         "eth_mdio",
3822         "eth_rmii",
3823 };
3824
3825 static const char * const i2c0_groups[] = {
3826         "i2c0",
3827         "i2c0_b",
3828         "i2c0_c",
3829 };
3830
3831 static const char * const i2c1_groups[] = {
3832         "i2c1",
3833         "i2c1_b",
3834         "i2c1_c",
3835         "i2c1_d",
3836         "i2c1_e",
3837 };
3838
3839 static const char * const i2c2_groups[] = {
3840         "i2c2",
3841         "i2c2_b",
3842         "i2c2_c",
3843         "i2c2_d",
3844 };
3845
3846 static const char * const i2c3_groups[] = {
3847         "i2c3",
3848         "i2c3_b",
3849         "i2c3_c",
3850         "i2c3_d",
3851 };
3852
3853 static const char * const i2c4_groups[] = {
3854         "i2c4",
3855         "i2c4_b",
3856         "i2c4_c",
3857 };
3858
3859 static const char * const i2c7_groups[] = {
3860         "i2c7",
3861         "i2c7_b",
3862         "i2c7_c",
3863 };
3864
3865 static const char * const i2c8_groups[] = {
3866         "i2c8",
3867         "i2c8_b",
3868         "i2c8_c",
3869 };
3870
3871 static const char * const intc_groups[] = {
3872         "intc_irq0",
3873         "intc_irq1",
3874         "intc_irq2",
3875         "intc_irq3",
3876 };
3877
3878 static const char * const mmc_groups[] = {
3879         "mmc_data1",
3880         "mmc_data4",
3881         "mmc_data8",
3882         "mmc_ctrl",
3883 };
3884
3885 static const char * const msiof0_groups[] = {
3886         "msiof0_clk",
3887         "msiof0_sync",
3888         "msiof0_ss1",
3889         "msiof0_ss2",
3890         "msiof0_rx",
3891         "msiof0_tx",
3892         "msiof0_clk_b",
3893         "msiof0_sync_b",
3894         "msiof0_ss1_b",
3895         "msiof0_ss2_b",
3896         "msiof0_rx_b",
3897         "msiof0_tx_b",
3898         "msiof0_clk_c",
3899         "msiof0_sync_c",
3900         "msiof0_ss1_c",
3901         "msiof0_ss2_c",
3902         "msiof0_rx_c",
3903         "msiof0_tx_c",
3904 };
3905
3906 static const char * const msiof1_groups[] = {
3907         "msiof1_clk",
3908         "msiof1_sync",
3909         "msiof1_ss1",
3910         "msiof1_ss2",
3911         "msiof1_rx",
3912         "msiof1_tx",
3913         "msiof1_clk_b",
3914         "msiof1_sync_b",
3915         "msiof1_ss1_b",
3916         "msiof1_ss2_b",
3917         "msiof1_rx_b",
3918         "msiof1_tx_b",
3919         "msiof1_clk_c",
3920         "msiof1_sync_c",
3921         "msiof1_rx_c",
3922         "msiof1_tx_c",
3923         "msiof1_clk_d",
3924         "msiof1_sync_d",
3925         "msiof1_ss1_d",
3926         "msiof1_rx_d",
3927         "msiof1_tx_d",
3928         "msiof1_clk_e",
3929         "msiof1_sync_e",
3930         "msiof1_rx_e",
3931         "msiof1_tx_e",
3932 };
3933
3934 static const char * const msiof2_groups[] = {
3935         "msiof2_clk",
3936         "msiof2_sync",
3937         "msiof2_ss1",
3938         "msiof2_ss2",
3939         "msiof2_rx",
3940         "msiof2_tx",
3941         "msiof2_clk_b",
3942         "msiof2_sync_b",
3943         "msiof2_ss1_b",
3944         "msiof2_ss2_b",
3945         "msiof2_rx_b",
3946         "msiof2_tx_b",
3947         "msiof2_clk_c",
3948         "msiof2_sync_c",
3949         "msiof2_rx_c",
3950         "msiof2_tx_c",
3951         "msiof2_clk_d",
3952         "msiof2_sync_d",
3953         "msiof2_ss1_d",
3954         "msiof2_ss2_d",
3955         "msiof2_rx_d",
3956         "msiof2_tx_d",
3957         "msiof2_clk_e",
3958         "msiof2_sync_e",
3959         "msiof2_rx_e",
3960         "msiof2_tx_e",
3961 };
3962
3963 static const char * const qspi_groups[] = {
3964         "qspi_ctrl",
3965         "qspi_data2",
3966         "qspi_data4",
3967         "qspi_ctrl_b",
3968         "qspi_data2_b",
3969         "qspi_data4_b",
3970 };
3971
3972 static const char * const scif0_groups[] = {
3973         "scif0_data",
3974         "scif0_data_b",
3975         "scif0_data_c",
3976         "scif0_data_d",
3977         "scif0_data_e",
3978 };
3979
3980 static const char * const scif1_groups[] = {
3981         "scif1_data",
3982         "scif1_data_b",
3983         "scif1_clk_b",
3984         "scif1_data_c",
3985         "scif1_data_d",
3986 };
3987
3988 static const char * const scif2_groups[] = {
3989         "scif2_data",
3990         "scif2_data_b",
3991         "scif2_clk_b",
3992         "scif2_data_c",
3993         "scif2_data_e",
3994 };
3995 static const char * const scif3_groups[] = {
3996         "scif3_data",
3997         "scif3_clk",
3998         "scif3_data_b",
3999         "scif3_clk_b",
4000         "scif3_data_c",
4001         "scif3_data_d",
4002 };
4003 static const char * const scif4_groups[] = {
4004         "scif4_data",
4005         "scif4_data_b",
4006         "scif4_data_c",
4007 };
4008 static const char * const scif5_groups[] = {
4009         "scif5_data",
4010         "scif5_data_b",
4011 };
4012 static const char * const scifa0_groups[] = {
4013         "scifa0_data",
4014         "scifa0_data_b",
4015 };
4016 static const char * const scifa1_groups[] = {
4017         "scifa1_data",
4018         "scifa1_clk",
4019         "scifa1_data_b",
4020         "scifa1_clk_b",
4021         "scifa1_data_c",
4022 };
4023 static const char * const scifa2_groups[] = {
4024         "scifa2_data",
4025         "scifa2_clk",
4026         "scifa2_data_b",
4027 };
4028 static const char * const scifa3_groups[] = {
4029         "scifa3_data",
4030         "scifa3_clk",
4031         "scifa3_data_b",
4032         "scifa3_clk_b",
4033         "scifa3_data_c",
4034         "scifa3_clk_c",
4035 };
4036 static const char * const scifa4_groups[] = {
4037         "scifa4_data",
4038         "scifa4_data_b",
4039         "scifa4_data_c",
4040 };
4041 static const char * const scifa5_groups[] = {
4042         "scifa5_data",
4043         "scifa5_data_b",
4044         "scifa5_data_c",
4045 };
4046 static const char * const scifb0_groups[] = {
4047         "scifb0_data",
4048         "scifb0_clk",
4049         "scifb0_ctrl",
4050         "scifb0_data_b",
4051         "scifb0_clk_b",
4052         "scifb0_ctrl_b",
4053         "scifb0_data_c",
4054         "scifb0_clk_c",
4055         "scifb0_data_d",
4056         "scifb0_clk_d",
4057 };
4058 static const char * const scifb1_groups[] = {
4059         "scifb1_data",
4060         "scifb1_clk",
4061         "scifb1_ctrl",
4062         "scifb1_data_b",
4063         "scifb1_clk_b",
4064         "scifb1_data_c",
4065         "scifb1_clk_c",
4066         "scifb1_data_d",
4067 };
4068 static const char * const scifb2_groups[] = {
4069         "scifb2_data",
4070         "scifb2_clk",
4071         "scifb2_ctrl",
4072         "scifb2_data_b",
4073         "scifb2_clk_b",
4074         "scifb2_ctrl_b",
4075         "scifb0_data_c",
4076         "scifb2_clk_c",
4077         "scifb2_data_d",
4078 };
4079
4080 static const char * const sdhi0_groups[] = {
4081         "sdhi0_data1",
4082         "sdhi0_data4",
4083         "sdhi0_ctrl",
4084         "sdhi0_cd",
4085         "sdhi0_wp",
4086 };
4087
4088 static const char * const sdhi1_groups[] = {
4089         "sdhi1_data1",
4090         "sdhi1_data4",
4091         "sdhi1_ctrl",
4092         "sdhi1_cd",
4093         "sdhi1_wp",
4094 };
4095
4096 static const char * const sdhi2_groups[] = {
4097         "sdhi2_data1",
4098         "sdhi2_data4",
4099         "sdhi2_ctrl",
4100         "sdhi2_cd",
4101         "sdhi2_wp",
4102 };
4103
4104 static const char * const usb0_groups[] = {
4105         "usb0",
4106 };
4107 static const char * const usb1_groups[] = {
4108         "usb1",
4109 };
4110
4111 static const char * const vin0_groups[] = {
4112         "vin0_data24",
4113         "vin0_data20",
4114         "vin0_data18",
4115         "vin0_data16",
4116         "vin0_data12",
4117         "vin0_data10",
4118         "vin0_data8",
4119         "vin0_sync",
4120         "vin0_field",
4121         "vin0_clkenb",
4122         "vin0_clk",
4123 };
4124
4125 static const char * const vin1_groups[] = {
4126         "vin1_data8",
4127         "vin1_sync",
4128         "vin1_field",
4129         "vin1_clkenb",
4130         "vin1_clk",
4131         "vin1_b_data24",
4132         "vin1_b_data20",
4133         "vin1_b_data18",
4134         "vin1_b_data16",
4135         "vin1_b_data12",
4136         "vin1_b_data10",
4137         "vin1_b_data8",
4138         "vin1_b_sync",
4139         "vin1_b_field",
4140         "vin1_b_clkenb",
4141         "vin1_b_clk",
4142 };
4143
4144 static const char * const vin2_groups[] = {
4145         "vin2_data8",
4146         "vin2_sync",
4147         "vin2_field",
4148         "vin2_clkenb",
4149         "vin2_clk",
4150 };
4151
4152 static const struct sh_pfc_function pinmux_functions[] = {
4153         SH_PFC_FUNCTION(du),
4154         SH_PFC_FUNCTION(du0),
4155         SH_PFC_FUNCTION(du1),
4156         SH_PFC_FUNCTION(eth),
4157         SH_PFC_FUNCTION(i2c0),
4158         SH_PFC_FUNCTION(i2c1),
4159         SH_PFC_FUNCTION(i2c2),
4160         SH_PFC_FUNCTION(i2c3),
4161         SH_PFC_FUNCTION(i2c4),
4162         SH_PFC_FUNCTION(i2c7),
4163         SH_PFC_FUNCTION(i2c8),
4164         SH_PFC_FUNCTION(intc),
4165         SH_PFC_FUNCTION(mmc),
4166         SH_PFC_FUNCTION(msiof0),
4167         SH_PFC_FUNCTION(msiof1),
4168         SH_PFC_FUNCTION(msiof2),
4169         SH_PFC_FUNCTION(qspi),
4170         SH_PFC_FUNCTION(scif0),
4171         SH_PFC_FUNCTION(scif1),
4172         SH_PFC_FUNCTION(scif2),
4173         SH_PFC_FUNCTION(scif3),
4174         SH_PFC_FUNCTION(scif4),
4175         SH_PFC_FUNCTION(scif5),
4176         SH_PFC_FUNCTION(scifa0),
4177         SH_PFC_FUNCTION(scifa1),
4178         SH_PFC_FUNCTION(scifa2),
4179         SH_PFC_FUNCTION(scifa3),
4180         SH_PFC_FUNCTION(scifa4),
4181         SH_PFC_FUNCTION(scifa5),
4182         SH_PFC_FUNCTION(scifb0),
4183         SH_PFC_FUNCTION(scifb1),
4184         SH_PFC_FUNCTION(scifb2),
4185         SH_PFC_FUNCTION(sdhi0),
4186         SH_PFC_FUNCTION(sdhi1),
4187         SH_PFC_FUNCTION(sdhi2),
4188         SH_PFC_FUNCTION(usb0),
4189         SH_PFC_FUNCTION(usb1),
4190         SH_PFC_FUNCTION(vin0),
4191         SH_PFC_FUNCTION(vin1),
4192         SH_PFC_FUNCTION(vin2),
4193 };
4194
4195 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4196         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4197                 GP_0_31_FN, FN_IP1_22_20,
4198                 GP_0_30_FN, FN_IP1_19_17,
4199                 GP_0_29_FN, FN_IP1_16_14,
4200                 GP_0_28_FN, FN_IP1_13_11,
4201                 GP_0_27_FN, FN_IP1_10_8,
4202                 GP_0_26_FN, FN_IP1_7_6,
4203                 GP_0_25_FN, FN_IP1_5_4,
4204                 GP_0_24_FN, FN_IP1_3_2,
4205                 GP_0_23_FN, FN_IP1_1_0,
4206                 GP_0_22_FN, FN_IP0_30_29,
4207                 GP_0_21_FN, FN_IP0_28_27,
4208                 GP_0_20_FN, FN_IP0_26_25,
4209                 GP_0_19_FN, FN_IP0_24_23,
4210                 GP_0_18_FN, FN_IP0_22_21,
4211                 GP_0_17_FN, FN_IP0_20_19,
4212                 GP_0_16_FN, FN_IP0_18_16,
4213                 GP_0_15_FN, FN_IP0_15,
4214                 GP_0_14_FN, FN_IP0_14,
4215                 GP_0_13_FN, FN_IP0_13,
4216                 GP_0_12_FN, FN_IP0_12,
4217                 GP_0_11_FN, FN_IP0_11,
4218                 GP_0_10_FN, FN_IP0_10,
4219                 GP_0_9_FN, FN_IP0_9,
4220                 GP_0_8_FN, FN_IP0_8,
4221                 GP_0_7_FN, FN_IP0_7,
4222                 GP_0_6_FN, FN_IP0_6,
4223                 GP_0_5_FN, FN_IP0_5,
4224                 GP_0_4_FN, FN_IP0_4,
4225                 GP_0_3_FN, FN_IP0_3,
4226                 GP_0_2_FN, FN_IP0_2,
4227                 GP_0_1_FN, FN_IP0_1,
4228                 GP_0_0_FN, FN_IP0_0, }
4229         },
4230         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4231                 0, 0,
4232                 0, 0,
4233                 0, 0,
4234                 0, 0,
4235                 0, 0,
4236                 0, 0,
4237                 GP_1_25_FN, FN_IP3_21_20,
4238                 GP_1_24_FN, FN_IP3_19_18,
4239                 GP_1_23_FN, FN_IP3_17_16,
4240                 GP_1_22_FN, FN_IP3_15_14,
4241                 GP_1_21_FN, FN_IP3_13_12,
4242                 GP_1_20_FN, FN_IP3_11_9,
4243                 GP_1_19_FN, FN_RD_N,
4244                 GP_1_18_FN, FN_IP3_8_6,
4245                 GP_1_17_FN, FN_IP3_5_3,
4246                 GP_1_16_FN, FN_IP3_2_0,
4247                 GP_1_15_FN, FN_IP2_29_27,
4248                 GP_1_14_FN, FN_IP2_26_25,
4249                 GP_1_13_FN, FN_IP2_24_23,
4250                 GP_1_12_FN, FN_EX_CS0_N,
4251                 GP_1_11_FN, FN_IP2_22_21,
4252                 GP_1_10_FN, FN_IP2_20_19,
4253                 GP_1_9_FN, FN_IP2_18_16,
4254                 GP_1_8_FN, FN_IP2_15_13,
4255                 GP_1_7_FN, FN_IP2_12_10,
4256                 GP_1_6_FN, FN_IP2_9_7,
4257                 GP_1_5_FN, FN_IP2_6_5,
4258                 GP_1_4_FN, FN_IP2_4_3,
4259                 GP_1_3_FN, FN_IP2_2_0,
4260                 GP_1_2_FN, FN_IP1_31_29,
4261                 GP_1_1_FN, FN_IP1_28_26,
4262                 GP_1_0_FN, FN_IP1_25_23, }
4263         },
4264         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4265                 GP_2_31_FN, FN_IP6_7_6,
4266                 GP_2_30_FN, FN_IP6_5_3,
4267                 GP_2_29_FN, FN_IP6_2_0,
4268                 GP_2_28_FN, FN_AUDIO_CLKA,
4269                 GP_2_27_FN, FN_IP5_31_29,
4270                 GP_2_26_FN, FN_IP5_28_26,
4271                 GP_2_25_FN, FN_IP5_25_24,
4272                 GP_2_24_FN, FN_IP5_23_22,
4273                 GP_2_23_FN, FN_IP5_21_20,
4274                 GP_2_22_FN, FN_IP5_19_17,
4275                 GP_2_21_FN, FN_IP5_16_15,
4276                 GP_2_20_FN, FN_IP5_14_12,
4277                 GP_2_19_FN, FN_IP5_11_9,
4278                 GP_2_18_FN, FN_IP5_8_6,
4279                 GP_2_17_FN, FN_IP5_5_3,
4280                 GP_2_16_FN, FN_IP5_2_0,
4281                 GP_2_15_FN, FN_IP4_30_28,
4282                 GP_2_14_FN, FN_IP4_27_26,
4283                 GP_2_13_FN, FN_IP4_25_24,
4284                 GP_2_12_FN, FN_IP4_23_22,
4285                 GP_2_11_FN, FN_IP4_21,
4286                 GP_2_10_FN, FN_IP4_20,
4287                 GP_2_9_FN, FN_IP4_19,
4288                 GP_2_8_FN, FN_IP4_18_16,
4289                 GP_2_7_FN, FN_IP4_15_13,
4290                 GP_2_6_FN, FN_IP4_12_10,
4291                 GP_2_5_FN, FN_IP4_9_8,
4292                 GP_2_4_FN, FN_IP4_7_5,
4293                 GP_2_3_FN, FN_IP4_4_2,
4294                 GP_2_2_FN, FN_IP4_1_0,
4295                 GP_2_1_FN, FN_IP3_30_28,
4296                 GP_2_0_FN, FN_IP3_27_25 }
4297         },
4298         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4299                 GP_3_31_FN, FN_IP9_18_17,
4300                 GP_3_30_FN, FN_IP9_16,
4301                 GP_3_29_FN, FN_IP9_15_13,
4302                 GP_3_28_FN, FN_IP9_12,
4303                 GP_3_27_FN, FN_IP9_11,
4304                 GP_3_26_FN, FN_IP9_10_8,
4305                 GP_3_25_FN, FN_IP9_7,
4306                 GP_3_24_FN, FN_IP9_6,
4307                 GP_3_23_FN, FN_IP9_5_3,
4308                 GP_3_22_FN, FN_IP9_2_0,
4309                 GP_3_21_FN, FN_IP8_30_28,
4310                 GP_3_20_FN, FN_IP8_27_26,
4311                 GP_3_19_FN, FN_IP8_25_24,
4312                 GP_3_18_FN, FN_IP8_23_21,
4313                 GP_3_17_FN, FN_IP8_20_18,
4314                 GP_3_16_FN, FN_IP8_17_15,
4315                 GP_3_15_FN, FN_IP8_14_12,
4316                 GP_3_14_FN, FN_IP8_11_9,
4317                 GP_3_13_FN, FN_IP8_8_6,
4318                 GP_3_12_FN, FN_IP8_5_3,
4319                 GP_3_11_FN, FN_IP8_2_0,
4320                 GP_3_10_FN, FN_IP7_29_27,
4321                 GP_3_9_FN, FN_IP7_26_24,
4322                 GP_3_8_FN, FN_IP7_23_21,
4323                 GP_3_7_FN, FN_IP7_20_19,
4324                 GP_3_6_FN, FN_IP7_18_17,
4325                 GP_3_5_FN, FN_IP7_16_15,
4326                 GP_3_4_FN, FN_IP7_14_13,
4327                 GP_3_3_FN, FN_IP7_12_11,
4328                 GP_3_2_FN, FN_IP7_10_9,
4329                 GP_3_1_FN, FN_IP7_8_6,
4330                 GP_3_0_FN, FN_IP7_5_3 }
4331         },
4332         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4333                 GP_4_31_FN, FN_IP15_5_4,
4334                 GP_4_30_FN, FN_IP15_3_2,
4335                 GP_4_29_FN, FN_IP15_1_0,
4336                 GP_4_28_FN, FN_IP11_8_6,
4337                 GP_4_27_FN, FN_IP11_5_3,
4338                 GP_4_26_FN, FN_IP11_2_0,
4339                 GP_4_25_FN, FN_IP10_31_29,
4340                 GP_4_24_FN, FN_IP10_28_27,
4341                 GP_4_23_FN, FN_IP10_26_25,
4342                 GP_4_22_FN, FN_IP10_24_22,
4343                 GP_4_21_FN, FN_IP10_21_19,
4344                 GP_4_20_FN, FN_IP10_18_17,
4345                 GP_4_19_FN, FN_IP10_16_15,
4346                 GP_4_18_FN, FN_IP10_14_12,
4347                 GP_4_17_FN, FN_IP10_11_9,
4348                 GP_4_16_FN, FN_IP10_8_6,
4349                 GP_4_15_FN, FN_IP10_5_3,
4350                 GP_4_14_FN, FN_IP10_2_0,
4351                 GP_4_13_FN, FN_IP9_31_29,
4352                 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
4353                 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
4354                 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
4355                 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
4356                 GP_4_8_FN, FN_IP9_28_27,
4357                 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
4358                 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
4359                 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
4360                 GP_4_4_FN, FN_IP9_26_25,
4361                 GP_4_3_FN, FN_IP9_24_23,
4362                 GP_4_2_FN, FN_IP9_22_21,
4363                 GP_4_1_FN, FN_IP9_20_19,
4364                 GP_4_0_FN, FN_VI0_CLK }
4365         },
4366         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4367                 GP_5_31_FN, FN_IP3_24_22,
4368                 GP_5_30_FN, FN_IP13_9_7,
4369                 GP_5_29_FN, FN_IP13_6_5,
4370                 GP_5_28_FN, FN_IP13_4_3,
4371                 GP_5_27_FN, FN_IP13_2_0,
4372                 GP_5_26_FN, FN_IP12_29_27,
4373                 GP_5_25_FN, FN_IP12_26_24,
4374                 GP_5_24_FN, FN_IP12_23_22,
4375                 GP_5_23_FN, FN_IP12_21_20,
4376                 GP_5_22_FN, FN_IP12_19_18,
4377                 GP_5_21_FN, FN_IP12_17_16,
4378                 GP_5_20_FN, FN_IP12_15_13,
4379                 GP_5_19_FN, FN_IP12_12_10,
4380                 GP_5_18_FN, FN_IP12_9_7,
4381                 GP_5_17_FN, FN_IP12_6_4,
4382                 GP_5_16_FN, FN_IP12_3_2,
4383                 GP_5_15_FN, FN_IP12_1_0,
4384                 GP_5_14_FN, FN_IP11_31_30,
4385                 GP_5_13_FN, FN_IP11_29_28,
4386                 GP_5_12_FN, FN_IP11_27,
4387                 GP_5_11_FN, FN_IP11_26,
4388                 GP_5_10_FN, FN_IP11_25,
4389                 GP_5_9_FN, FN_IP11_24,
4390                 GP_5_8_FN, FN_IP11_23,
4391                 GP_5_7_FN, FN_IP11_22,
4392                 GP_5_6_FN, FN_IP11_21,
4393                 GP_5_5_FN, FN_IP11_20,
4394                 GP_5_4_FN, FN_IP11_19,
4395                 GP_5_3_FN, FN_IP11_18_17,
4396                 GP_5_2_FN, FN_IP11_16_15,
4397                 GP_5_1_FN, FN_IP11_14_12,
4398                 GP_5_0_FN, FN_IP11_11_9 }
4399         },
4400         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
4401                 GP_6_31_FN, FN_DU0_DOTCLKIN,
4402                 GP_6_30_FN, FN_USB1_OVC,
4403                 GP_6_29_FN, FN_IP14_31_29,
4404                 GP_6_28_FN, FN_IP14_28_26,
4405                 GP_6_27_FN, FN_IP14_25_23,
4406                 GP_6_26_FN, FN_IP14_22_20,
4407                 GP_6_25_FN, FN_IP14_19_17,
4408                 GP_6_24_FN, FN_IP14_16_14,
4409                 GP_6_23_FN, FN_IP14_13_11,
4410                 GP_6_22_FN, FN_IP14_10_8,
4411                 GP_6_21_FN, FN_IP14_7,
4412                 GP_6_20_FN, FN_IP14_6,
4413                 GP_6_19_FN, FN_IP14_5,
4414                 GP_6_18_FN, FN_IP14_4,
4415                 GP_6_17_FN, FN_IP14_3,
4416                 GP_6_16_FN, FN_IP14_2,
4417                 GP_6_15_FN, FN_IP14_1_0,
4418                 GP_6_14_FN, FN_IP13_30_28,
4419                 GP_6_13_FN, FN_IP13_27,
4420                 GP_6_12_FN, FN_IP13_26,
4421                 GP_6_11_FN, FN_IP13_25,
4422                 GP_6_10_FN, FN_IP13_24_23,
4423                 GP_6_9_FN, FN_IP13_22,
4424                 0, 0,
4425                 GP_6_7_FN, FN_IP13_21_19,
4426                 GP_6_6_FN, FN_IP13_18_16,
4427                 GP_6_5_FN, FN_IP13_15,
4428                 GP_6_4_FN, FN_IP13_14,
4429                 GP_6_3_FN, FN_IP13_13,
4430                 GP_6_2_FN, FN_IP13_12,
4431                 GP_6_1_FN, FN_IP13_11,
4432                 GP_6_0_FN, FN_IP13_10 }
4433         },
4434         { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
4435                 0, 0,
4436                 0, 0,
4437                 0, 0,
4438                 0, 0,
4439                 0, 0,
4440                 0, 0,
4441                 GP_7_25_FN, FN_USB1_PWEN,
4442                 GP_7_24_FN, FN_USB0_OVC,
4443                 GP_7_23_FN, FN_USB0_PWEN,
4444                 GP_7_22_FN, FN_IP15_14_12,
4445                 GP_7_21_FN, FN_IP15_11_9,
4446                 GP_7_20_FN, FN_IP15_8_6,
4447                 GP_7_19_FN, FN_IP7_2_0,
4448                 GP_7_18_FN, FN_IP6_29_27,
4449                 GP_7_17_FN, FN_IP6_26_24,
4450                 GP_7_16_FN, FN_IP6_23_21,
4451                 GP_7_15_FN, FN_IP6_20_19,
4452                 GP_7_14_FN, FN_IP6_18_16,
4453                 GP_7_13_FN, FN_IP6_15_14,
4454                 GP_7_12_FN, FN_IP6_13_12,
4455                 GP_7_11_FN, FN_IP6_11_10,
4456                 GP_7_10_FN, FN_IP6_9_8,
4457                 GP_7_9_FN, FN_IP16_11_10,
4458                 GP_7_8_FN, FN_IP16_9_8,
4459                 GP_7_7_FN, FN_IP16_7_6,
4460                 GP_7_6_FN, FN_IP16_5_3,
4461                 GP_7_5_FN, FN_IP16_2_0,
4462                 GP_7_4_FN, FN_IP15_29_27,
4463                 GP_7_3_FN, FN_IP15_26_24,
4464                 GP_7_2_FN, FN_IP15_23_21,
4465                 GP_7_1_FN, FN_IP15_20_18,
4466                 GP_7_0_FN, FN_IP15_17_15 }
4467         },
4468         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4469                              1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
4470                              1, 1, 1, 1, 1, 1, 1, 1) {
4471                 /* IP0_31 [1] */
4472                 0, 0,
4473                 /* IP0_30_29 [2] */
4474                 FN_A6, FN_MSIOF1_SCK,
4475                 0, 0,
4476                 /* IP0_28_27 [2] */
4477                 FN_A5, FN_MSIOF0_RXD_B,
4478                 0, 0,
4479                 /* IP0_26_25 [2] */
4480                 FN_A4, FN_MSIOF0_TXD_B,
4481                 0, 0,
4482                 /* IP0_24_23 [2] */
4483                 FN_A3, FN_MSIOF0_SS2_B,
4484                 0, 0,
4485                 /* IP0_22_21 [2] */
4486                 FN_A2, FN_MSIOF0_SS1_B,
4487                 0, 0,
4488                 /* IP0_20_19 [2] */
4489                 FN_A1, FN_MSIOF0_SYNC_B,
4490                 0, 0,
4491                 /* IP0_18_16 [3] */
4492                 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
4493                 0, 0, 0,
4494                 /* IP0_15 [1] */
4495                 FN_D15, 0,
4496                 /* IP0_14 [1] */
4497                 FN_D14, 0,
4498                 /* IP0_13 [1] */
4499                 FN_D13, 0,
4500                 /* IP0_12 [1] */
4501                 FN_D12, 0,
4502                 /* IP0_11 [1] */
4503                 FN_D11, 0,
4504                 /* IP0_10 [1] */
4505                 FN_D10, 0,
4506                 /* IP0_9 [1] */
4507                 FN_D9, 0,
4508                 /* IP0_8 [1] */
4509                 FN_D8, 0,
4510                 /* IP0_7 [1] */
4511                 FN_D7, 0,
4512                 /* IP0_6 [1] */
4513                 FN_D6, 0,
4514                 /* IP0_5 [1] */
4515                 FN_D5, 0,
4516                 /* IP0_4 [1] */
4517                 FN_D4, 0,
4518                 /* IP0_3 [1] */
4519                 FN_D3, 0,
4520                 /* IP0_2 [1] */
4521                 FN_D2, 0,
4522                 /* IP0_1 [1] */
4523                 FN_D1, 0,
4524                 /* IP0_0 [1] */
4525                 FN_D0, 0, }
4526         },
4527         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4528                              3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
4529                 /* IP1_31_29 [3] */
4530                 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
4531                 0, 0, 0,
4532                 /* IP1_28_26 [3] */
4533                 FN_A17, FN_DACK2_B, 0, FN_SDA0_C,
4534                 0, 0, 0, 0,
4535                 /* IP1_25_23 [3] */
4536                 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
4537                 0, 0, 0,
4538                 /* IP1_22_20 [3] */
4539                 FN_A15, FN_BPFCLK_C,
4540                 0, 0, 0, 0, 0, 0,
4541                 /* IP1_19_17 [3] */
4542                 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
4543                 0, 0, 0,
4544                 /* IP1_16_14 [3] */
4545                 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
4546                 0, 0, 0, 0,
4547                 /* IP1_13_11 [3] */
4548                 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
4549                 0, 0, 0, 0,
4550                 /* IP1_10_8 [3] */
4551                 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
4552                 0, 0, 0, 0,
4553                 /* IP1_7_6 [2] */
4554                 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
4555                 /* IP1_5_4 [2] */
4556                 FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0,
4557                 /* IP1_3_2 [2] */
4558                 FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0,
4559                 /* IP1_1_0 [2] */
4560                 FN_A7, FN_MSIOF1_SYNC,
4561                 0, 0, }
4562         },
4563         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4564                              2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
4565                 /* IP2_31_20 [2] */
4566                 0, 0, 0, 0,
4567                 /* IP2_29_27 [3] */
4568                 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
4569                 FN_ATAG0_N, 0, FN_EX_WAIT1,
4570                 0, 0,
4571                 /* IP2_26_25 [2] */
4572                 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
4573                 /* IP2_24_23 [2] */
4574                 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
4575                 /* IP2_22_21 [2] */
4576                 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0,
4577                 /* IP2_20_19 [2] */
4578                 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0,
4579                 /* IP2_18_16 [3] */
4580                 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
4581                 0, 0,
4582                 /* IP2_15_13 [3] */
4583                 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
4584                 0, 0, 0,
4585                 /* IP2_12_0 [3] */
4586                 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
4587                 0, 0, 0,
4588                 /* IP2_9_7 [3] */
4589                 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
4590                 0, 0, 0,
4591                 /* IP2_6_5 [2] */
4592                 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
4593                 /* IP2_4_3 [2] */
4594                 FN_A20, FN_SPCLK, 0, 0,
4595                 /* IP2_2_0 [3] */
4596                 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
4597                 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
4598         },
4599         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4600                              1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
4601                 /* IP3_31 [1] */
4602                 0, 0,
4603                 /* IP3_30_28 [3] */
4604                 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
4605                 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
4606                 0, 0, 0,
4607                 /* IP3_27_25 [3] */
4608                 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
4609                 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
4610                 0, 0, 0,
4611                 /* IP3_24_22 [3] */
4612                 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
4613                 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
4614                 /* IP3_21_20 [2] */
4615                 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
4616                 /* IP3_19_18 [2] */
4617                 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
4618                 /* IP3_17_16 [2] */
4619                 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
4620                 /* IP3_15_14 [2] */
4621                 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
4622                 /* IP3_13_12 [2] */
4623                 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
4624                 /* IP3_11_9 [3] */
4625                 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
4626                 0, 0, 0,
4627                 /* IP3_8_6 [3] */
4628                 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
4629                 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
4630                 /* IP3_5_3 [3] */
4631                 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
4632                 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
4633                 /* IP3_2_0 [3] */
4634                 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
4635                 0, 0, 0, }
4636         },
4637         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
4638                              1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
4639                 /* IP4_31 [1] */
4640                 0, 0,
4641                 /* IP4_30_28 [3] */
4642                 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
4643                 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
4644                 0, 0,
4645                 /* IP4_27_26 [2] */
4646                 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
4647                 /* IP4_25_24 [2] */
4648                 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
4649                 /* IP4_23_22 [2] */
4650                 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
4651                 /* IP4_21 [1] */
4652                 FN_SSI_SDATA3, 0,
4653                 /* IP4_20 [1] */
4654                 FN_SSI_WS34, 0,
4655                 /* IP4_19 [1] */
4656                 FN_SSI_SCK34, 0,
4657                 /* IP4_18_16 [3] */
4658                 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
4659                 0, 0, 0, 0,
4660                 /* IP4_15_13 [3] */
4661                 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
4662                 FN_GLO_Q1_D, FN_HCTS1_N_E,
4663                 0, 0,
4664                 /* IP4_12_10 [3] */
4665                 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
4666                 0, 0, 0,
4667                 /* IP4_9_8 [2] */
4668                 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
4669                 /* IP4_7_5 [3] */
4670                 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
4671                 0, 0, 0,
4672                 /* IP4_4_2 [3] */
4673                 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B,
4674                 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
4675                 0, 0, 0,
4676                 /* IP4_1_0 [2] */
4677                 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, }
4678         },
4679         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
4680                              3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
4681                 /* IP5_31_29 [3] */
4682                 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
4683                 0, 0, 0, 0, 0,
4684                 /* IP5_28_26 [3] */
4685                 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
4686                 0, 0, 0, 0,
4687                 /* IP5_25_24 [2] */
4688                 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
4689                 /* IP5_23_22 [2] */
4690                 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
4691                 /* IP5_21_20 [2] */
4692                 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
4693                 /* IP5_19_17 [3] */
4694                 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
4695                 0, 0, 0, 0,
4696                 /* IP5_16_15 [2] */
4697                 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
4698                 /* IP5_14_12 [3] */
4699                 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
4700                 0, 0, 0, 0,
4701                 /* IP5_11_9 [3] */
4702                 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
4703                 0, 0, 0, 0,
4704                 /* IP5_8_6 [3] */
4705                 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
4706                 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
4707                 0, 0,
4708                 /* IP5_5_3 [3] */
4709                 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
4710                 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
4711                 0, 0,
4712                 /* IP5_2_0 [3] */
4713                 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
4714                 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
4715                 0, 0, }
4716         },
4717         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4718                              2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
4719                 /* IP6_31_30 [2] */
4720                 0, 0, 0, 0,
4721                 /* IP6_29_27 [3] */
4722                 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
4723                 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
4724                 0, 0, 0,
4725                 /* IP6_26_24 [3] */
4726                 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
4727                 FN_GPS_CLK_C, FN_GPS_CLK_D,
4728                 0, 0, 0,
4729                 /* IP6_23_21 [3] */
4730                 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
4731                 FN_SDA1_E, FN_MSIOF2_SYNC_E,
4732                 0, 0, 0,
4733                 /* IP6_20_19 [2] */
4734                 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
4735                 /* IP6_18_16 [3] */
4736                 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
4737                 0, 0, 0,
4738                 /* IP6_15_14 [2] */
4739                 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
4740                 /* IP6_13_12 [2] */
4741                 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
4742                 /* IP6_11_10 [2] */
4743                 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
4744                 /* IP6_9_8 [2] */
4745                 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
4746                 /* IP6_7_6 [2] */
4747                 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
4748                 /* IP6_5_3 [3] */
4749                 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
4750                 FN_SCIFA2_RXD, FN_FMIN_E,
4751                 0, 0,
4752                 /* IP6_2_0 [3] */
4753                 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
4754                 FN_SCIF_CLK, 0, FN_BPFCLK_E,
4755                 0, 0, }
4756         },
4757         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4758                              2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
4759                 /* IP7_31_30 [2] */
4760                 0, 0, 0, 0,
4761                 /* IP7_29_27 [3] */
4762                 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
4763                 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
4764                 0, 0,
4765                 /* IP7_26_24 [3] */
4766                 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
4767                 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
4768                 0, 0,
4769                 /* IP7_23_21 [3] */
4770                 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
4771                 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
4772                 0, 0,
4773                 /* IP7_20_19 [2] */
4774                 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
4775                 /* IP7_18_17 [2] */
4776                 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
4777                 /* IP7_16_15 [2] */
4778                 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
4779                 /* IP7_14_13 [2] */
4780                 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
4781                 /* IP7_12_11 [2] */
4782                 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
4783                 /* IP7_10_9 [2] */
4784                 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
4785                 /* IP7_8_6 [3] */
4786                 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
4787                 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
4788                 0, 0,
4789                 /* IP7_5_3 [3] */
4790                 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
4791                 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
4792                 0, 0,
4793                 /* IP7_2_0 [3] */
4794                 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
4795                 FN_SCIF_CLK_B, FN_GPS_MAG_D,
4796                 0, 0, }
4797         },
4798         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4799                              1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
4800                 /* IP8_31 [1] */
4801                 0, 0,
4802                 /* IP8_30_28 [3] */
4803                 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
4804                 0, 0, 0,
4805                 /* IP8_27_26 [2] */
4806                 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
4807                 /* IP8_25_24 [2] */
4808                 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
4809                 /* IP8_23_21 [3] */
4810                 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
4811                 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
4812                 0, 0,
4813                 /* IP8_20_18 [3] */
4814                 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
4815                 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
4816                 0, 0,
4817                 /* IP8_17_15 [3] */
4818                 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
4819                 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
4820                 0, 0,
4821                 /* IP8_14_12 [3] */
4822                 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
4823                 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
4824                 0, 0, 0,
4825                 /* IP8_11_9 [3] */
4826                 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
4827                 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
4828                 0, 0, 0,
4829                 /* IP8_8_6 [3] */
4830                 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
4831                 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
4832                 0, 0,
4833                 /* IP8_5_3 [3] */
4834                 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
4835                 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
4836                 0, 0,
4837                 /* IP8_2_0 [3] */
4838                 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
4839                 0, 0, 0, }
4840         },
4841         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4842                              3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
4843                 /* IP9_31_29 [3] */
4844                 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
4845                 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
4846                 /* IP9_28_27 [2] */
4847                 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
4848                 /* IP9_26_25 [2] */
4849                 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
4850                 /* IP9_24_23 [2] */
4851                 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
4852                 /* IP9_22_21 [2] */
4853                 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
4854                 /* IP9_20_19 [2] */
4855                 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
4856                 /* IP9_18_17 [2] */
4857                 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
4858                 /* IP9_16 [1] */
4859                 FN_DU1_DISP, FN_QPOLA,
4860                 /* IP9_15_13 [3] */
4861                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
4862                 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
4863                 0, 0, 0,
4864                 /* IP9_12 [1] */
4865                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
4866                 /* IP9_11 [1] */
4867                 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
4868                 /* IP9_10_8 [3] */
4869                 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
4870                 FN_TX3_B, FN_SCL2_B, FN_PWM4,
4871                 0, 0,
4872                 /* IP9_7 [1] */
4873                 FN_DU1_DOTCLKOUT0, FN_QCLK,
4874                 /* IP9_6 [1] */
4875                 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
4876                 /* IP9_5_3 [3] */
4877                 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C,
4878                 FN_SCIF3_SCK, FN_SCIFA3_SCK,
4879                 0, 0, 0,
4880                 /* IP9_2_0 [3] */
4881                 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
4882                 0, 0, 0, }
4883         },
4884         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
4885                              3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
4886                 /* IP10_31_29 [3] */
4887                 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
4888                 0, 0, 0,
4889                 /* IP10_28_27 [2] */
4890                 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
4891                 /* IP10_26_25 [2] */
4892                 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
4893                 /* IP10_24_22 [3] */
4894                 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
4895                 0, 0, 0,
4896                 /* IP10_21_29 [3] */
4897                 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
4898                 FN_TS_SDATA0_C, FN_ATACS11_N,
4899                 0, 0, 0,
4900                 /* IP10_18_17 [2] */
4901                 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
4902                 /* IP10_16_15 [2] */
4903                 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
4904                 /* IP10_14_12 [3] */
4905                 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
4906                 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
4907                 /* IP10_11_9 [3] */
4908                 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
4909                 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
4910                 0, 0,
4911                 /* IP10_8_6 [3] */
4912                 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
4913                 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
4914                 /* IP10_5_3 [3] */
4915                 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
4916                 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
4917                 /* IP10_2_0 [3] */
4918                 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
4919                 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
4920         },
4921         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
4922                              2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
4923                              3, 3, 3, 3, 3) {
4924                 /* IP11_31_30 [2] */
4925                 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
4926                 /* IP11_29_28 [2] */
4927                 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
4928                 /* IP11_27 [1] */
4929                 FN_VI1_DATA7, FN_AVB_MDC,
4930                 /* IP11_26 [1] */
4931                 FN_VI1_DATA6, FN_AVB_MAGIC,
4932                 /* IP11_25 [1] */
4933                 FN_VI1_DATA5, FN_AVB_RX_DV,
4934                 /* IP11_24 [1] */
4935                 FN_VI1_DATA4, FN_AVB_MDIO,
4936                 /* IP11_23 [1] */
4937                 FN_VI1_DATA3, FN_AVB_RX_ER,
4938                 /* IP11_22 [1] */
4939                 FN_VI1_DATA2, FN_AVB_RXD7,
4940                 /* IP11_21 [1] */
4941                 FN_VI1_DATA1, FN_AVB_RXD6,
4942                 /* IP11_20 [1] */
4943                 FN_VI1_DATA0, FN_AVB_RXD5,
4944                 /* IP11_19 [1] */
4945                 FN_VI1_CLK, FN_AVB_RXD4,
4946                 /* IP11_18_17 [2] */
4947                 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
4948                 /* IP11_16_15 [2] */
4949                 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
4950                 /* IP11_14_12 [3] */
4951                 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
4952                 FN_RX4_B, FN_SCIFA4_RXD_B,
4953                 0, 0, 0,
4954                 /* IP11_11_9 [3] */
4955                 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
4956                 FN_TX4_B, FN_SCIFA4_TXD_B,
4957                 0, 0, 0,
4958                 /* IP11_8_6 [3] */
4959                 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
4960                 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
4961                 /* IP11_5_3 [3] */
4962                 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
4963                 0, 0, 0,
4964                 /* IP11_2_0 [3] */
4965                 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
4966                 0, 0, 0, }
4967         },
4968         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
4969                              2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
4970                 /* IP12_31_30 [2] */
4971                 0, 0, 0, 0,
4972                 /* IP12_29_27 [3] */
4973                 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
4974                 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
4975                 0, 0, 0,
4976                 /* IP12_26_24 [3] */
4977                 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
4978                 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
4979                 0, 0, 0,
4980                 /* IP12_23_22 [2] */
4981                 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
4982                 /* IP12_21_20 [2] */
4983                 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
4984                 /* IP12_19_18 [2] */
4985                 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
4986                 /* IP12_17_16 [2] */
4987                 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
4988                 /* IP12_15_13 [3] */
4989                 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
4990                 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
4991                 0, 0, 0,
4992                 /* IP12_12_10 [3] */
4993                 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
4994                 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
4995                 0, 0, 0,
4996                 /* IP12_9_7 [3] */
4997                 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
4998                 FN_SDA2_D, FN_MSIOF1_SCK_E,
4999                 0, 0, 0,
5000                 /* IP12_6_4 [3] */
5001                 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
5002                 FN_SCL2_D, FN_MSIOF1_RXD_E,
5003                 0, 0, 0,
5004                 /* IP12_3_2 [2] */
5005                 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
5006                 /* IP12_1_0 [2] */
5007                 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
5008         },
5009         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5010                              1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
5011                              3, 2, 2, 3) {
5012                 /* IP13_31 [1] */
5013                 0, 0,
5014                 /* IP13_30_28 [3] */
5015                 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
5016                 0, 0, 0, 0,
5017                 /* IP13_27 [1] */
5018                 FN_SD1_DATA3, FN_IERX_B,
5019                 /* IP13_26 [1] */
5020                 FN_SD1_DATA2, FN_IECLK_B,
5021                 /* IP13_25 [1] */
5022                 FN_SD1_DATA1, FN_IETX_B,
5023                 /* IP13_24_23 [2] */
5024                 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
5025                 /* IP13_22 [1] */
5026                 FN_SD1_CMD, FN_REMOCON_B,
5027                 /* IP13_21_19 [3] */
5028                 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
5029                 FN_SCIFA5_RXD_B, FN_RX3_C,
5030                 0, 0,
5031                 /* IP13_18_16 [3] */
5032                 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
5033                 FN_SCIFA5_TXD_B, FN_TX3_C,
5034                 0, 0,
5035                 /* IP13_15 [1] */
5036                 FN_SD0_DATA3, FN_SSL_B,
5037                 /* IP13_14 [1] */
5038                 FN_SD0_DATA2, FN_IO3_B,
5039                 /* IP13_13 [1] */
5040                 FN_SD0_DATA1, FN_IO2_B,
5041                 /* IP13_12 [1] */
5042                 FN_SD0_DATA0, FN_MISO_IO1_B,
5043                 /* IP13_11 [1] */
5044                 FN_SD0_CMD, FN_MOSI_IO0_B,
5045                 /* IP13_10 [1] */
5046                 FN_SD0_CLK, FN_SPCLK_B,
5047                 /* IP13_9_7 [3] */
5048                 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
5049                 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
5050                 0, 0, 0,
5051                 /* IP13_6_5 [2] */
5052                 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
5053                 /* IP13_4_3 [2] */
5054                 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
5055                 /* IP13_2_0 [3] */
5056                 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
5057                 FN_ADICLK_B, FN_MSIOF0_SS1_C,
5058                 0, 0, 0, }
5059         },
5060         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5061                              3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
5062                 /* IP14_31_29 [3] */
5063                 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
5064                 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
5065                 /* IP14_28_26 [3] */
5066                 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
5067                 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
5068                 /* IP14_25_23 [3] */
5069                 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
5070                 0, 0, 0,
5071                 /* IP14_22_20 [3] */
5072                 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
5073                 0, 0, 0,
5074                 /* IP14_19_17 [3] */
5075                 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
5076                 FN_VI1_CLKENB_C, FN_VI1_G1_B,
5077                 0, 0,
5078                 /* IP14_16_14 [3] */
5079                 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
5080                 FN_VI1_CLK_C, FN_VI1_G0_B,
5081                 0, 0,
5082                 /* IP14_13_11 [3] */
5083                 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
5084                 0, 0, 0,
5085                 /* IP14_10_8 [3] */
5086                 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
5087                 0, 0, 0,
5088                 /* IP14_7 [1] */
5089                 FN_SD2_DATA3, FN_MMC_D3,
5090                 /* IP14_6 [1] */
5091                 FN_SD2_DATA2, FN_MMC_D2,
5092                 /* IP14_5 [1] */
5093                 FN_SD2_DATA1, FN_MMC_D1,
5094                 /* IP14_4 [1] */
5095                 FN_SD2_DATA0, FN_MMC_D0,
5096                 /* IP14_3 [1] */
5097                 FN_SD2_CMD, FN_MMC_CMD,
5098                 /* IP14_2 [1] */
5099                 FN_SD2_CLK, FN_MMC_CLK,
5100                 /* IP14_1_0 [2] */
5101                 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
5102         },
5103         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5104                              2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
5105                 /* IP15_31_30 [2] */
5106                 0, 0, 0, 0,
5107                 /* IP15_29_27 [3] */
5108                 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
5109                 FN_CAN0_TX_B, FN_VI1_DATA5_C,
5110                 0, 0,
5111                 /* IP15_26_24 [3] */
5112                 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
5113                 FN_CAN0_RX_B, FN_VI1_DATA4_C,
5114                 0, 0,
5115                 /* IP15_23_21 [3] */
5116                 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
5117                 FN_TCLK2, FN_VI1_DATA3_C, 0,
5118                 /* IP15_20_18 [3] */
5119                 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
5120                 0, 0, 0,
5121                 /* IP15_17_15 [3] */
5122                 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
5123                 FN_TCLK1, FN_VI1_DATA1_C,
5124                 0, 0,
5125                 /* IP15_14_12 [3] */
5126                 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
5127                 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
5128                 0, 0,
5129                 /* IP15_11_9 [3] */
5130                 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
5131                 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
5132                 0, 0,
5133                 /* IP15_8_6 [3] */
5134                 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
5135                 FN_PWM5_B, FN_SCIFA3_TXD_C,
5136                 0, 0, 0,
5137                 /* IP15_5_4 [2] */
5138                 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
5139                 /* IP15_3_2 [2] */
5140                 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
5141                 /* IP15_1_0 [2] */
5142                 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
5143         },
5144         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5145                              4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
5146                 /* IP16_31_28 [4] */
5147                 0, 0, 0, 0, 0, 0, 0, 0,
5148                 0, 0, 0, 0, 0, 0, 0, 0,
5149                 /* IP16_27_24 [4] */
5150                 0, 0, 0, 0, 0, 0, 0, 0,
5151                 0, 0, 0, 0, 0, 0, 0, 0,
5152                 /* IP16_23_20 [4] */
5153                 0, 0, 0, 0, 0, 0, 0, 0,
5154                 0, 0, 0, 0, 0, 0, 0, 0,
5155                 /* IP16_19_16 [4] */
5156                 0, 0, 0, 0, 0, 0, 0, 0,
5157                 0, 0, 0, 0, 0, 0, 0, 0,
5158                 /* IP16_15_12 [4] */
5159                 0, 0, 0, 0, 0, 0, 0, 0,
5160                 0, 0, 0, 0, 0, 0, 0, 0,
5161                 /* IP16_11_10 [2] */
5162                 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
5163                 /* IP16_9_8 [2] */
5164                 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
5165                 /* IP16_7_6 [2] */
5166                 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
5167                 /* IP16_5_3 [3] */
5168                 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
5169                 FN_GLO_SS_C, FN_VI1_DATA7_C,
5170                 0, 0, 0,
5171                 /* IP16_2_0 [3] */
5172                 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
5173                 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
5174                 0, 0, 0, }
5175         },
5176         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5177                              1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
5178                              3, 2, 2, 2, 1, 2, 2, 2) {
5179                 /* RESEVED [1] */
5180                 0, 0,
5181                 /* SEL_SCIF1 [2] */
5182                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5183                 /* SEL_SCIFB [2] */
5184                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
5185                 /* SEL_SCIFB2 [2] */
5186                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
5187                 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
5188                 /* SEL_SCIFB1 [3] */
5189                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
5190                 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
5191                 0, 0, 0, 0,
5192                 /* SEL_SCIFA1 [2] */
5193                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
5194                 /* SEL_SSI9 [1] */
5195                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
5196                 /* SEL_SCFA [1] */
5197                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5198                 /* SEL_QSP [1] */
5199                 FN_SEL_QSP_0, FN_SEL_QSP_1,
5200                 /* SEL_SSI7 [1] */
5201                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
5202                 /* SEL_HSCIF1 [3] */
5203                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
5204                 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
5205                 0, 0, 0,
5206                 /* RESEVED [2] */
5207                 0, 0, 0, 0,
5208                 /* SEL_VI1 [2] */
5209                 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
5210                 /* RESEVED [2] */
5211                 0, 0, 0, 0,
5212                 /* SEL_TMU [1] */
5213                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5214                 /* SEL_LBS [2] */
5215                 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
5216                 /* SEL_TSIF0 [2] */
5217                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5218                 /* SEL_SOF0 [2] */
5219                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
5220         },
5221         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5222                              3, 1, 1, 3, 2, 1, 1, 2, 2,
5223                              1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
5224                 /* SEL_SCIF0 [3] */
5225                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
5226                 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
5227                 0, 0, 0,
5228                 /* RESEVED [1] */
5229                 0, 0,
5230                 /* SEL_SCIF [1] */
5231                 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
5232                 /* SEL_CAN0 [3] */
5233                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5234                 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
5235                 0, 0,
5236                 /* SEL_CAN1 [2] */
5237                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
5238                 /* RESEVED [1] */
5239                 0, 0,
5240                 /* SEL_SCIFA2 [1] */
5241                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
5242                 /* SEL_SCIF4 [2] */
5243                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
5244                 /* RESEVED [2] */
5245                 0, 0, 0, 0,
5246                 /* SEL_ADG [1] */
5247                 FN_SEL_ADG_0, FN_SEL_ADG_1,
5248                 /* SEL_FM [3] */
5249                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
5250                 FN_SEL_FM_3, FN_SEL_FM_4,
5251                 0, 0, 0,
5252                 /* SEL_SCIFA5 [2] */
5253                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
5254                 /* RESEVED [1] */
5255                 0, 0,
5256                 /* SEL_GPS [2] */
5257                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
5258                 /* SEL_SCIFA4 [2] */
5259                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
5260                 /* SEL_SCIFA3 [2] */
5261                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
5262                 /* SEL_SIM [1] */
5263                 FN_SEL_SIM_0, FN_SEL_SIM_1,
5264                 /* RESEVED [1] */
5265                 0, 0,
5266                 /* SEL_SSI8 [1] */
5267                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
5268         },
5269         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5270                              2, 2, 2, 2, 2, 2, 2, 2,
5271                              1, 1, 2, 2, 3, 2, 2, 2, 1) {
5272                 /* SEL_HSCIF2 [2] */
5273                 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
5274                 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
5275                 /* SEL_CANCLK [2] */
5276                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5277                 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
5278                 /* SEL_IIC8 [2] */
5279                 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
5280                 /* SEL_IIC7 [2] */
5281                 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
5282                 /* SEL_IIC4 [2] */
5283                 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
5284                 /* SEL_IIC3 [2] */
5285                 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
5286                 /* SEL_SCIF3 [2] */
5287                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
5288                 /* SEL_IEB [2] */
5289                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
5290                 /* SEL_MMC [1] */
5291                 FN_SEL_MMC_0, FN_SEL_MMC_1,
5292                 /* SEL_SCIF5 [1] */
5293                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
5294                 /* RESEVED [2] */
5295                 0, 0, 0, 0,
5296                 /* SEL_IIC2 [2] */
5297                 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5298                 /* SEL_IIC1 [3] */
5299                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
5300                 FN_SEL_IIC1_4,
5301                 0, 0, 0,
5302                 /* SEL_IIC0 [2] */
5303                 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
5304                 /* RESEVED [2] */
5305                 0, 0, 0, 0,
5306                 /* RESEVED [2] */
5307                 0, 0, 0, 0,
5308                 /* RESEVED [1] */
5309                 0, 0, }
5310         },
5311         { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
5312                              3, 2, 2, 1, 1, 1, 1, 3, 2,
5313                              2, 3, 1, 1, 1, 2, 2, 2, 2) {
5314                 /* SEL_SOF1 [3] */
5315                 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
5316                 FN_SEL_SOF1_4,
5317                 0, 0, 0,
5318                 /* SEL_HSCIF0 [2] */
5319                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
5320                 /* SEL_DIS [2] */
5321                 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
5322                 /* RESEVED [1] */
5323                 0, 0,
5324                 /* SEL_RAD [1] */
5325                 FN_SEL_RAD_0, FN_SEL_RAD_1,
5326                 /* SEL_RCN [1] */
5327                 FN_SEL_RCN_0, FN_SEL_RCN_1,
5328                 /* SEL_RSP [1] */
5329                 FN_SEL_RSP_0, FN_SEL_RSP_1,
5330                 /* SEL_SCIF2 [3] */
5331                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
5332                 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
5333                 0, 0, 0,
5334                 /* RESEVED [2] */
5335                 0, 0, 0, 0,
5336                 /* RESEVED [2] */
5337                 0, 0, 0, 0,
5338                 /* SEL_SOF2 [3] */
5339                 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
5340                 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
5341                 0, 0, 0,
5342                 /* RESEVED [1] */
5343                 0, 0,
5344                 /* SEL_SSI1 [1] */
5345                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
5346                 /* SEL_SSI0 [1] */
5347                 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
5348                 /* SEL_SSP [2] */
5349                 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
5350                 /* RESEVED [2] */
5351                 0, 0, 0, 0,
5352                 /* RESEVED [2] */
5353                 0, 0, 0, 0,
5354                 /* RESEVED [2] */
5355                 0, 0, 0, 0, }
5356         },
5357         { },
5358 };
5359
5360 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
5361         .name = "r8a77910_pfc",
5362         .unlock_reg = 0xe6060000, /* PMMR */
5363
5364         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5365
5366         .pins = pinmux_pins,
5367         .nr_pins = ARRAY_SIZE(pinmux_pins),
5368         .groups = pinmux_groups,
5369         .nr_groups = ARRAY_SIZE(pinmux_groups),
5370         .functions = pinmux_functions,
5371         .nr_functions = ARRAY_SIZE(pinmux_functions),
5372
5373         .cfg_regs = pinmux_config_regs,
5374
5375         .gpio_data = pinmux_data,
5376         .gpio_data_size = ARRAY_SIZE(pinmux_data),
5377 };