2 * SuperH Pin Function Controller pinmux support.
4 * Copyright (C) 2012 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
11 #define DRV_NAME "sh-pfc"
12 #define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinconf-generic.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
28 #include "../pinconf.h"
30 struct sh_pfc_pin_config {
34 struct sh_pfc_pinctrl {
35 struct pinctrl_dev *pctl;
36 struct pinctrl_desc pctl_desc;
40 struct pinctrl_pin_desc *pins;
41 struct sh_pfc_pin_config *configs;
44 static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
46 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
48 return pmx->pfc->info->nr_groups;
51 static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
54 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
56 return pmx->pfc->info->groups[selector].name;
59 static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
60 const unsigned **pins, unsigned *num_pins)
62 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
64 *pins = pmx->pfc->info->groups[selector].pins;
65 *num_pins = pmx->pfc->info->groups[selector].nr_pins;
70 static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
73 seq_printf(s, "%s", DRV_NAME);
76 static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
77 .get_groups_count = sh_pfc_get_groups_count,
78 .get_group_name = sh_pfc_get_group_name,
79 .get_group_pins = sh_pfc_get_group_pins,
80 .pin_dbg_show = sh_pfc_pin_dbg_show,
83 static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
85 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
87 return pmx->pfc->info->nr_functions;
90 static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
93 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
95 return pmx->pfc->info->functions[selector].name;
98 static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
100 const char * const **groups,
101 unsigned * const num_groups)
103 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
105 *groups = pmx->pfc->info->functions[selector].groups;
106 *num_groups = pmx->pfc->info->functions[selector].nr_groups;
111 static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
114 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
115 struct sh_pfc *pfc = pmx->pfc;
116 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
121 spin_lock_irqsave(&pfc->lock, flags);
123 for (i = 0; i < grp->nr_pins; ++i) {
124 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
125 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
127 if (cfg->type != PINMUX_TYPE_NONE) {
133 for (i = 0; i < grp->nr_pins; ++i) {
134 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
140 spin_unlock_irqrestore(&pfc->lock, flags);
144 static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
147 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
148 struct sh_pfc *pfc = pmx->pfc;
149 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
153 spin_lock_irqsave(&pfc->lock, flags);
155 for (i = 0; i < grp->nr_pins; ++i) {
156 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
157 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
159 cfg->type = PINMUX_TYPE_NONE;
162 spin_unlock_irqrestore(&pfc->lock, flags);
165 static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
166 struct pinctrl_gpio_range *range,
169 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
170 struct sh_pfc *pfc = pmx->pfc;
171 int idx = sh_pfc_get_pin_index(pfc, offset);
172 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
176 spin_lock_irqsave(&pfc->lock, flags);
178 if (cfg->type != PINMUX_TYPE_NONE) {
179 pr_err("Pin %u is busy, can't configure it as GPIO.\n", offset);
184 cfg->type = PINMUX_TYPE_GPIO;
189 spin_unlock_irqrestore(&pfc->lock, flags);
194 static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
195 struct pinctrl_gpio_range *range,
198 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
199 struct sh_pfc *pfc = pmx->pfc;
200 int idx = sh_pfc_get_pin_index(pfc, offset);
201 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
204 spin_lock_irqsave(&pfc->lock, flags);
205 cfg->type = PINMUX_TYPE_NONE;
206 spin_unlock_irqrestore(&pfc->lock, flags);
209 static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
210 struct pinctrl_gpio_range *range,
211 unsigned offset, bool input)
213 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
214 struct sh_pfc *pfc = pmx->pfc;
215 int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
216 int idx = sh_pfc_get_pin_index(pfc, offset);
217 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
218 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
222 spin_lock_irqsave(&pfc->lock, flags);
224 ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
228 cfg->type = new_type;
231 spin_unlock_irqrestore(&pfc->lock, flags);
235 static const struct pinmux_ops sh_pfc_pinmux_ops = {
236 .get_functions_count = sh_pfc_get_functions_count,
237 .get_function_name = sh_pfc_get_function_name,
238 .get_function_groups = sh_pfc_get_function_groups,
239 .enable = sh_pfc_func_enable,
240 .disable = sh_pfc_func_disable,
241 .gpio_request_enable = sh_pfc_gpio_request_enable,
242 .gpio_disable_free = sh_pfc_gpio_disable_free,
243 .gpio_set_direction = sh_pfc_gpio_set_direction,
246 /* Check whether the requested parameter is supported for a pin. */
247 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
248 enum pin_config_param param)
250 int idx = sh_pfc_get_pin_index(pfc, _pin);
251 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
254 case PIN_CONFIG_BIAS_DISABLE:
257 case PIN_CONFIG_BIAS_PULL_UP:
258 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
260 case PIN_CONFIG_BIAS_PULL_DOWN:
261 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
268 static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
269 unsigned long *config)
271 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
272 struct sh_pfc *pfc = pmx->pfc;
273 enum pin_config_param param = pinconf_to_config_param(*config);
277 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
281 case PIN_CONFIG_BIAS_DISABLE:
282 case PIN_CONFIG_BIAS_PULL_UP:
283 case PIN_CONFIG_BIAS_PULL_DOWN:
284 if (!pfc->info->ops || !pfc->info->ops->get_bias)
287 spin_lock_irqsave(&pfc->lock, flags);
288 bias = pfc->info->ops->get_bias(pfc, _pin);
289 spin_unlock_irqrestore(&pfc->lock, flags);
304 static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
305 unsigned long config)
307 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
308 struct sh_pfc *pfc = pmx->pfc;
309 enum pin_config_param param = pinconf_to_config_param(config);
312 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
316 case PIN_CONFIG_BIAS_PULL_UP:
317 case PIN_CONFIG_BIAS_PULL_DOWN:
318 case PIN_CONFIG_BIAS_DISABLE:
319 if (!pfc->info->ops || !pfc->info->ops->set_bias)
322 spin_lock_irqsave(&pfc->lock, flags);
323 pfc->info->ops->set_bias(pfc, _pin, param);
324 spin_unlock_irqrestore(&pfc->lock, flags);
335 static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
336 unsigned long config)
338 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
339 const unsigned int *pins;
340 unsigned int num_pins;
343 pins = pmx->pfc->info->groups[group].pins;
344 num_pins = pmx->pfc->info->groups[group].nr_pins;
346 for (i = 0; i < num_pins; ++i)
347 sh_pfc_pinconf_set(pctldev, pins[i], config);
352 static const struct pinconf_ops sh_pfc_pinconf_ops = {
354 .pin_config_get = sh_pfc_pinconf_get,
355 .pin_config_set = sh_pfc_pinconf_set,
356 .pin_config_group_set = sh_pfc_pinconf_group_set,
357 .pin_config_config_dbg_show = pinconf_generic_dump_config,
360 /* PFC ranges -> pinctrl pin descs */
361 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
363 const struct pinmux_range *ranges;
364 struct pinmux_range def_range;
365 unsigned int nr_ranges;
366 unsigned int nr_pins;
369 if (pfc->info->ranges == NULL) {
371 def_range.end = pfc->info->nr_pins - 1;
375 ranges = pfc->info->ranges;
376 nr_ranges = pfc->info->nr_ranges;
379 pmx->pins = devm_kzalloc(pfc->dev,
380 sizeof(*pmx->pins) * pfc->info->nr_pins,
382 if (unlikely(!pmx->pins))
385 pmx->configs = devm_kzalloc(pfc->dev,
386 sizeof(*pmx->configs) * pfc->info->nr_pins,
388 if (unlikely(!pmx->configs))
391 for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
392 const struct pinmux_range *range = &ranges[i];
395 for (number = range->begin; number <= range->end;
396 number++, nr_pins++) {
397 struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
398 struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
399 const struct sh_pfc_pin *info =
400 &pfc->info->pins[nr_pins];
402 pin->number = number;
403 pin->name = info->name;
404 cfg->type = PINMUX_TYPE_NONE;
408 pfc->nr_pins = ranges[nr_ranges-1].end + 1;
413 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
415 struct sh_pfc_pinctrl *pmx;
418 pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
425 nr_ranges = sh_pfc_map_pins(pfc, pmx);
426 if (unlikely(nr_ranges < 0))
429 pmx->pctl_desc.name = DRV_NAME;
430 pmx->pctl_desc.owner = THIS_MODULE;
431 pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
432 pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
433 pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
434 pmx->pctl_desc.pins = pmx->pins;
435 pmx->pctl_desc.npins = pfc->info->nr_pins;
437 pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
438 if (pmx->pctl == NULL)
444 int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
446 struct sh_pfc_pinctrl *pmx = pfc->pinctrl;
448 pinctrl_unregister(pmx->pctl);