drivers/platform/goldfish/goldfish_pipe.c

   1 /*
   2  * Copyright (C) 2011 Google, Inc.
   3  * Copyright (C) 2012 Intel, Inc.
   4  * Copyright (C) 2013 Intel, Inc.
   5  * Copyright (C) 2014 Linaro Limited
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 /* This source file contains the implementation of a special device driver
  19  * that intends to provide a *very* fast communication channel between the
  20  * guest system and the QEMU emulator.
  21  *
  22  * Usage from the guest is simply the following (error handling simplified):
  23  *
  24  *    int  fd = open("/dev/qemu_pipe",O_RDWR);
  25  *    .... write() or read() through the pipe.
  26  *
  27  * This driver doesn't deal with the exact protocol used during the session.
  28  * It is intended to be as simple as something like:
  29  *
  30  *    // do this _just_ after opening the fd to connect to a specific
  31  *    // emulator service.
  32  *    const char*  msg = "<pipename>";
  33  *    if (write(fd, msg, strlen(msg)+1) < 0) {
  34  *       ... could not connect to <pipename> service
  35  *       close(fd);
  36  *    }
  37  *
  38  *    // after this, simply read() and write() to communicate with the
  39  *    // service. Exact protocol details left as an exercise to the reader.
  40  *
  41  * This driver is very fast because it doesn't copy any data through
  42  * intermediate buffers, since the emulator is capable of translating
  43  * guest user addresses into host ones.
  44  *
  45  * Note that we must however ensure that each user page involved in the
  46  * exchange is properly mapped during a transfer.
  47  */
  48
  49 #include <linux/module.h>
  50 #include <linux/interrupt.h>
  51 #include <linux/kernel.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/miscdevice.h>
  54 #include <linux/platform_device.h>
  55 #include <linux/poll.h>
  56 #include <linux/sched.h>
  57 #include <linux/bitops.h>
  58 #include <linux/slab.h>
  59 #include <linux/io.h>
  60 #include <linux/goldfish.h>
  61 #include <linux/mm.h>
  62 #include <linux/acpi.h>
  63
  64 /*
  65  * IMPORTANT: The following constants must match the ones used and defined
  66  * in external/qemu/hw/goldfish_pipe.c in the Android source tree.
  67  */
  68
  69 /* pipe device registers */
  70 #define PIPE_REG_COMMAND                0x00  /* write: value = command */
  71 #define PIPE_REG_STATUS                 0x04  /* read */
  72 #define PIPE_REG_CHANNEL                0x08  /* read/write: channel id */
  73 #define PIPE_REG_CHANNEL_HIGH           0x30  /* read/write: channel id */
  74 #define PIPE_REG_SIZE                   0x0c  /* read/write: buffer size */
  75 #define PIPE_REG_ADDRESS                0x10  /* write: physical address */
  76 #define PIPE_REG_ADDRESS_HIGH           0x34  /* write: physical address */
  77 #define PIPE_REG_WAKES                  0x14  /* read: wake flags */
  78 #define PIPE_REG_PARAMS_ADDR_LOW        0x18  /* read/write: batch data address */
  79 #define PIPE_REG_PARAMS_ADDR_HIGH       0x1c  /* read/write: batch data address */
  80 #define PIPE_REG_ACCESS_PARAMS          0x20  /* write: batch access */
  81 #define PIPE_REG_VERSION                0x24  /* read: device version */
  82
  83 /* list of commands for PIPE_REG_COMMAND */
  84 #define CMD_OPEN                        1  /* open new channel */
  85 #define CMD_CLOSE                       2  /* close channel (from guest) */
  86 #define CMD_POLL                        3  /* poll read/write status */
  87
  88 /* List of bitflags returned in status of CMD_POLL command */
  89 #define PIPE_POLL_IN                    (1 << 0)
  90 #define PIPE_POLL_OUT                   (1 << 1)
  91 #define PIPE_POLL_HUP                   (1 << 2)
  92
  93 /* The following commands are related to write operations */
  94 #define CMD_WRITE_BUFFER        4  /* send a user buffer to the emulator */
  95 #define CMD_WAKE_ON_WRITE       5  /* tell the emulator to wake us when writing
  96                                      is possible */
  97 #define CMD_READ_BUFFER        6  /* receive a user buffer from the emulator */
  98 #define CMD_WAKE_ON_READ       7  /* tell the emulator to wake us when reading
  99                                    * is possible */
 100
 101 /* Possible status values used to signal errors - see goldfish_pipe_error_convert */
 102 #define PIPE_ERROR_INVAL       -1
 103 #define PIPE_ERROR_AGAIN       -2
 104 #define PIPE_ERROR_NOMEM       -3
 105 #define PIPE_ERROR_IO          -4
 106
 107 /* Bit-flags used to signal events from the emulator */
 108 #define PIPE_WAKE_CLOSED       (1 << 0)  /* emulator closed pipe */
 109 #define PIPE_WAKE_READ         (1 << 1)  /* pipe can now be read from */
 110 #define PIPE_WAKE_WRITE        (1 << 2)  /* pipe can now be written to */
 111
 112 struct access_params {
 113         unsigned long channel;
 114         u32 size;
 115         unsigned long address;
 116         u32 cmd;
 117         u32 result;
 118         /* reserved for future extension */
 119         u32 flags;
 120 };
 121
 122 /* The global driver data. Holds a reference to the i/o page used to
 123  * communicate with the emulator, and a wake queue for blocked tasks
 124  * waiting to be awoken.
 125  */
 126 struct goldfish_pipe_dev {
 127         spinlock_t lock;
 128         unsigned char __iomem *base;
 129         struct access_params *aps;
 130         int irq;
 131         u32 version;
 132 };
 133
 134 static struct goldfish_pipe_dev   pipe_dev[1];
 135
 136 /* This data type models a given pipe instance */
 137 struct goldfish_pipe {
 138         struct goldfish_pipe_dev *dev;
 139         struct mutex lock;
 140         unsigned long flags;
 141         wait_queue_head_t wake_queue;
 142 };
 143
 144
 145 /* Bit flags for the 'flags' field */
 146 enum {
 147         BIT_CLOSED_ON_HOST = 0,  /* pipe closed by host */
 148         BIT_WAKE_ON_WRITE  = 1,  /* want to be woken on writes */
 149         BIT_WAKE_ON_READ   = 2,  /* want to be woken on reads */
 150 };
 151
 152
 153 static u32 goldfish_cmd_status(struct goldfish_pipe *pipe, u32 cmd)
 154 {
 155         unsigned long flags;
 156         u32 status;
 157         struct goldfish_pipe_dev *dev = pipe->dev;
 158
 159         spin_lock_irqsave(&dev->lock, flags);
 160         gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL,
 161                      dev->base + PIPE_REG_CHANNEL_HIGH);
 162         writel(cmd, dev->base + PIPE_REG_COMMAND);
 163         status = readl(dev->base + PIPE_REG_STATUS);
 164         spin_unlock_irqrestore(&dev->lock, flags);
 165         return status;
 166 }
 167
 168 static void goldfish_cmd(struct goldfish_pipe *pipe, u32 cmd)
 169 {
 170         unsigned long flags;
 171         struct goldfish_pipe_dev *dev = pipe->dev;
 172
 173         spin_lock_irqsave(&dev->lock, flags);
 174         gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL,
 175                      dev->base + PIPE_REG_CHANNEL_HIGH);
 176         writel(cmd, dev->base + PIPE_REG_COMMAND);
 177         spin_unlock_irqrestore(&dev->lock, flags);
 178 }
 179
 180 /* This function converts an error code returned by the emulator through
 181  * the PIPE_REG_STATUS i/o register into a valid negative errno value.
 182  */
 183 static int goldfish_pipe_error_convert(int status)
 184 {
 185         switch (status) {
 186         case PIPE_ERROR_AGAIN:
 187                 return -EAGAIN;
 188         case PIPE_ERROR_NOMEM:
 189                 return -ENOMEM;
 190         case PIPE_ERROR_IO:
 191                 return -EIO;
 192         default:
 193                 return -EINVAL;
 194         }
 195 }
 196
 197 /*
 198  * Notice: QEMU will return 0 for un-known register access, indicating
 199  * param_acess is supported or not
 200  */
 201 static int valid_batchbuffer_addr(struct goldfish_pipe_dev *dev,
 202                                   struct access_params *aps)
 203 {
 204         u32 aph, apl;
 205         u64 paddr;
 206         aph = readl(dev->base + PIPE_REG_PARAMS_ADDR_HIGH);
 207         apl = readl(dev->base + PIPE_REG_PARAMS_ADDR_LOW);
 208
 209         paddr = ((u64)aph << 32) | apl;
 210         if (paddr != (__pa(aps)))
 211                 return 0;
 212         return 1;
 213 }
 214
 215 /* 0 on success */
 216 static int setup_access_params_addr(struct platform_device *pdev,
 217                                         struct goldfish_pipe_dev *dev)
 218 {
 219         u64 paddr;
 220         struct access_params *aps;
 221
 222         aps = devm_kzalloc(&pdev->dev, sizeof(struct access_params), GFP_KERNEL);
 223         if (!aps)
 224                 return -1;
 225
 226         /* FIXME */
 227         paddr = __pa(aps);
 228         writel((u32)(paddr >> 32), dev->base + PIPE_REG_PARAMS_ADDR_HIGH);
 229         writel((u32)paddr, dev->base + PIPE_REG_PARAMS_ADDR_LOW);
 230
 231         if (valid_batchbuffer_addr(dev, aps)) {
 232                 dev->aps = aps;
 233                 return 0;
 234         } else
 235                 return -1;
 236 }
 237
 238 /* A value that will not be set by qemu emulator */
 239 #define INITIAL_BATCH_RESULT (0xdeadbeaf)
 240 static int access_with_param(struct goldfish_pipe_dev *dev, const int cmd,
 241                                 unsigned long address, unsigned long avail,
 242                                 struct goldfish_pipe *pipe, int *status)
 243 {
 244         struct access_params *aps = dev->aps;
 245
 246         if (aps == NULL)
 247                 return -1;
 248
 249         aps->result = INITIAL_BATCH_RESULT;
 250         aps->channel = (unsigned long)pipe;
 251         aps->size = avail;
 252         aps->address = address;
 253         aps->cmd = cmd;
 254         writel(cmd, dev->base + PIPE_REG_ACCESS_PARAMS);
 255         /*
 256          * If the aps->result has not changed, that means
 257          * that the batch command failed
 258          */
 259         if (aps->result == INITIAL_BATCH_RESULT)
 260                 return -1;
 261         *status = aps->result;
 262         return 0;
 263 }
 264
 265 static ssize_t goldfish_pipe_read_write(struct file *filp, char __user *buffer,
 266                                     size_t bufflen, int is_write)
 267 {
 268         unsigned long irq_flags;
 269         struct goldfish_pipe *pipe = filp->private_data;
 270         struct goldfish_pipe_dev *dev = pipe->dev;
 271         unsigned long address, address_end;
 272         int count = 0, ret = -EINVAL;
 273
 274         /* If the emulator already closed the pipe, no need to go further */
 275         if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags))
 276                 return -EIO;
 277
 278         /* Null reads or writes succeeds */
 279         if (unlikely(bufflen == 0))
 280                 return 0;
 281
 282         /* Check the buffer range for access */
 283         if (!access_ok(is_write ? VERIFY_WRITE : VERIFY_READ,
 284                         buffer, bufflen))
 285                 return -EFAULT;
 286
 287         /* Serialize access to the pipe */
 288         if (mutex_lock_interruptible(&pipe->lock))
 289                 return -ERESTARTSYS;
 290
 291         address = (unsigned long)(void *)buffer;
 292         address_end = address + bufflen;
 293
 294         while (address < address_end) {
 295                 unsigned long  page_end = (address & PAGE_MASK) + PAGE_SIZE;
 296                 unsigned long  next     = page_end < address_end ? page_end
 297                                                                  : address_end;
 298                 unsigned long  avail    = next - address;
 299                 int status, wakeBit;
 300
 301                 struct page *page;
 302
 303                 /* Either vaddr or paddr depending on the device version */
 304                 unsigned long xaddr;
 305
 306                 /*
 307                  * We grab the pages on a page-by-page basis in case user
 308                  * space gives us a potentially huge buffer but the read only
 309                  * returns a small amount, then there's no need to pin that
 310                  * much memory to the process.
 311                  */
 312                 down_read(&current->mm->mmap_sem);
 313                 ret = get_user_pages(current, current->mm, address, 1,
 314                                      !is_write, 0, &page, NULL);
 315                 up_read(&current->mm->mmap_sem);
 316                 if (ret < 0)
 317                         return ret;
 318
 319                 if (dev->version) {
 320                         /* Device version 1 or newer (qemu-android) expects the
 321                          * physical address. */
 322                         xaddr = page_to_phys(page) | (address & ~PAGE_MASK);
 323                 } else {
 324                         /* Device version 0 (classic emulator) expects the
 325                          * virtual address. */
 326                         xaddr = address;
 327                 }
 328
 329                 /* Now, try to transfer the bytes in the current page */
 330                 spin_lock_irqsave(&dev->lock, irq_flags);
 331                 if (access_with_param(dev,
 332                                       is_write ? CMD_WRITE_BUFFER : CMD_READ_BUFFER,
 333                                       xaddr, avail, pipe, &status)) {
 334                         gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL,
 335                                      dev->base + PIPE_REG_CHANNEL_HIGH);
 336                         writel(avail, dev->base + PIPE_REG_SIZE);
 337                         gf_write_ptr((void *)xaddr,
 338                                      dev->base + PIPE_REG_ADDRESS,
 339                                      dev->base + PIPE_REG_ADDRESS_HIGH);
 340                         writel(is_write ? CMD_WRITE_BUFFER : CMD_READ_BUFFER,
 341                                dev->base + PIPE_REG_COMMAND);
 342                         status = readl(dev->base + PIPE_REG_STATUS);
 343                 }
 344                 spin_unlock_irqrestore(&dev->lock, irq_flags);
 345
 346                 if (status > 0 && !is_write)
 347                         set_page_dirty(page);
 348                 put_page(page);
 349
 350                 if (status > 0) { /* Correct transfer */
 351                         count += status;
 352                         address += status;
 353                         continue;
 354                 } else if (status == 0) { /* EOF */
 355                         ret = 0;
 356                         break;
 357                 } else if (status < 0 && count > 0) {
 358                         /*
 359                          * An error occured and we already transfered
 360                          * something on one of the previous pages.
 361                          * Just return what we already copied and log this
 362                          * err.
 363                          *
 364                          * Note: This seems like an incorrect approach but
 365                          * cannot change it until we check if any user space
 366                          * ABI relies on this behavior.
 367                          */
 368                         if (status != PIPE_ERROR_AGAIN)
 369                                 pr_info_ratelimited("goldfish_pipe: backend returned error %d on %s\n",
 370                                             status, is_write ? "write" : "read");
 371                         ret = 0;
 372                         break;
 373                 }
 374
 375                 /*
 376                  * If the error is not PIPE_ERROR_AGAIN, or if we are not in
 377                  * non-blocking mode, just return the error code.
 378                  */
 379                 if (status != PIPE_ERROR_AGAIN ||
 380                         (filp->f_flags & O_NONBLOCK) != 0) {
 381                         ret = goldfish_pipe_error_convert(status);
 382                         break;
 383                 }
 384
 385                 /*
 386                  * The backend blocked the read/write, wait until the backend
 387                  * tells us it's ready to process more data.
 388                  */
 389                 wakeBit = is_write ? BIT_WAKE_ON_WRITE : BIT_WAKE_ON_READ;
 390                 set_bit(wakeBit, &pipe->flags);
 391
 392                 /* Tell the emulator we're going to wait for a wake event */
 393                 goldfish_cmd(pipe,
 394                              is_write ? CMD_WAKE_ON_WRITE : CMD_WAKE_ON_READ);
 395
 396                 /* Unlock the pipe, then wait for the wake signal */
 397                 mutex_unlock(&pipe->lock);
 398
 399                 while (test_bit(wakeBit, &pipe->flags)) {
 400                         if (wait_event_interruptible(
 401                                         pipe->wake_queue,
 402                                         !test_bit(wakeBit, &pipe->flags))) {
 403                                 ret = -ERESTARTSYS;
 404                                 break;
 405                         }
 406
 407                         if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags)) {
 408                                 ret = -EIO;
 409                                 break;
 410                         }
 411                 }
 412
 413                 /* Try to re-acquire the lock */
 414                 if (mutex_lock_interruptible(&pipe->lock)) {
 415                         ret = -ERESTARTSYS;
 416                         break;
 417                 }
 418         }
 419         mutex_unlock(&pipe->lock);
 420
 421         if (ret < 0)
 422                 return ret;
 423         else
 424                 return count;
 425 }
 426
 427 static ssize_t goldfish_pipe_read(struct file *filp, char __user *buffer,
 428                               size_t bufflen, loff_t *ppos)
 429 {
 430         return goldfish_pipe_read_write(filp, buffer, bufflen, 0);
 431 }
 432
 433 static ssize_t goldfish_pipe_write(struct file *filp,
 434                                 const char __user *buffer, size_t bufflen,
 435                                 loff_t *ppos)
 436 {
 437         return goldfish_pipe_read_write(filp, (char __user *)buffer,
 438                                                                 bufflen, 1);
 439 }
 440
 441
 442 static unsigned int goldfish_pipe_poll(struct file *filp, poll_table *wait)
 443 {
 444         struct goldfish_pipe *pipe = filp->private_data;
 445         unsigned int mask = 0;
 446         int status;
 447
 448         mutex_lock(&pipe->lock);
 449
 450         poll_wait(filp, &pipe->wake_queue, wait);
 451
 452         status = goldfish_cmd_status(pipe, CMD_POLL);
 453
 454         mutex_unlock(&pipe->lock);
 455
 456         if (status & PIPE_POLL_IN)
 457                 mask |= POLLIN | POLLRDNORM;
 458
 459         if (status & PIPE_POLL_OUT)
 460                 mask |= POLLOUT | POLLWRNORM;
 461
 462         if (status & PIPE_POLL_HUP)
 463                 mask |= POLLHUP;
 464
 465         if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags))
 466                 mask |= POLLERR;
 467
 468         return mask;
 469 }
 470
 471 static irqreturn_t goldfish_pipe_interrupt(int irq, void *dev_id)
 472 {
 473         struct goldfish_pipe_dev *dev = dev_id;
 474         unsigned long irq_flags;
 475         int count = 0;
 476
 477         /*
 478          * We're going to read from the emulator a list of (channel,flags)
 479          * pairs corresponding to the wake events that occured on each
 480          * blocked pipe (i.e. channel).
 481          */
 482         spin_lock_irqsave(&dev->lock, irq_flags);
 483         for (;;) {
 484                 /* First read the channel, 0 means the end of the list */
 485                 struct goldfish_pipe *pipe;
 486                 unsigned long wakes;
 487                 unsigned long channel = 0;
 488
 489 #ifdef CONFIG_64BIT
 490                 channel = (u64)readl(dev->base + PIPE_REG_CHANNEL_HIGH) << 32;
 491
 492                 if (channel == 0)
 493                         break;
 494 #endif
 495                 channel |= readl(dev->base + PIPE_REG_CHANNEL);
 496
 497                 if (channel == 0)
 498                         break;
 499
 500                 /* Convert channel to struct pipe pointer + read wake flags */
 501                 wakes = readl(dev->base + PIPE_REG_WAKES);
 502                 pipe  = (struct goldfish_pipe *)(ptrdiff_t)channel;
 503
 504                 /* Did the emulator just closed a pipe? */
 505                 if (wakes & PIPE_WAKE_CLOSED) {
 506                         set_bit(BIT_CLOSED_ON_HOST, &pipe->flags);
 507                         wakes |= PIPE_WAKE_READ | PIPE_WAKE_WRITE;
 508                 }
 509                 if (wakes & PIPE_WAKE_READ)
 510                         clear_bit(BIT_WAKE_ON_READ, &pipe->flags);
 511                 if (wakes & PIPE_WAKE_WRITE)
 512                         clear_bit(BIT_WAKE_ON_WRITE, &pipe->flags);
 513
 514                 wake_up_interruptible(&pipe->wake_queue);
 515                 count++;
 516         }
 517         spin_unlock_irqrestore(&dev->lock, irq_flags);
 518
 519         return (count == 0) ? IRQ_NONE : IRQ_HANDLED;
 520 }
 521
 522 /**
 523  *      goldfish_pipe_open      -       open a channel to the AVD
 524  *      @inode: inode of device
 525  *      @file: file struct of opener
 526  *
 527  *      Create a new pipe link between the emulator and the use application.
 528  *      Each new request produces a new pipe.
 529  *
 530  *      Note: we use the pipe ID as a mux. All goldfish emulations are 32bit
 531  *      right now so this is fine. A move to 64bit will need this addressing
 532  */
 533 static int goldfish_pipe_open(struct inode *inode, struct file *file)
 534 {
 535         struct goldfish_pipe *pipe;
 536         struct goldfish_pipe_dev *dev = pipe_dev;
 537         int32_t status;
 538
 539         /* Allocate new pipe kernel object */
 540         pipe = kzalloc(sizeof(*pipe), GFP_KERNEL);
 541         if (pipe == NULL)
 542                 return -ENOMEM;
 543
 544         pipe->dev = dev;
 545         mutex_init(&pipe->lock);
 546         init_waitqueue_head(&pipe->wake_queue);
 547
 548         /*
 549          * Now, tell the emulator we're opening a new pipe. We use the
 550          * pipe object's address as the channel identifier for simplicity.
 551          */
 552
 553         status = goldfish_cmd_status(pipe, CMD_OPEN);
 554         if (status < 0) {
 555                 kfree(pipe);
 556                 return status;
 557         }
 558
 559         /* All is done, save the pipe into the file's private data field */
 560         file->private_data = pipe;
 561         return 0;
 562 }
 563
 564 static int goldfish_pipe_release(struct inode *inode, struct file *filp)
 565 {
 566         struct goldfish_pipe *pipe = filp->private_data;
 567
 568         /* The guest is closing the channel, so tell the emulator right now */
 569         goldfish_cmd(pipe, CMD_CLOSE);
 570         kfree(pipe);
 571         filp->private_data = NULL;
 572         return 0;
 573 }
 574
 575 static const struct file_operations goldfish_pipe_fops = {
 576         .owner = THIS_MODULE,
 577         .read = goldfish_pipe_read,
 578         .write = goldfish_pipe_write,
 579         .poll = goldfish_pipe_poll,
 580         .open = goldfish_pipe_open,
 581         .release = goldfish_pipe_release,
 582 };
 583
 584 static struct miscdevice goldfish_pipe_device = {
 585         .minor = MISC_DYNAMIC_MINOR,
 586         .name = "goldfish_pipe",
 587         .fops = &goldfish_pipe_fops,
 588 };
 589
 590 static int goldfish_pipe_probe(struct platform_device *pdev)
 591 {
 592         int err;
 593         struct resource *r;
 594         struct goldfish_pipe_dev *dev = pipe_dev;
 595
 596         /* not thread safe, but this should not happen */
 597         WARN_ON(dev->base != NULL);
 598
 599         spin_lock_init(&dev->lock);
 600
 601         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 602         if (r == NULL || resource_size(r) < PAGE_SIZE) {
 603                 dev_err(&pdev->dev, "can't allocate i/o page\n");
 604                 return -EINVAL;
 605         }
 606         dev->base = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
 607         if (dev->base == NULL) {
 608                 dev_err(&pdev->dev, "ioremap failed\n");
 609                 return -EINVAL;
 610         }
 611
 612         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 613         if (r == NULL) {
 614                 err = -EINVAL;
 615                 goto error;
 616         }
 617         dev->irq = r->start;
 618
 619         err = devm_request_irq(&pdev->dev, dev->irq, goldfish_pipe_interrupt,
 620                                 IRQF_SHARED, "goldfish_pipe", dev);
 621         if (err) {
 622                 dev_err(&pdev->dev, "unable to allocate IRQ\n");
 623                 goto error;
 624         }
 625
 626         err = misc_register(&goldfish_pipe_device);
 627         if (err) {
 628                 dev_err(&pdev->dev, "unable to register device\n");
 629                 goto error;
 630         }
 631         setup_access_params_addr(pdev, dev);
 632
 633         /* Although the pipe device in the classic Android emulator does not
 634          * recognize the 'version' register, it won't treat this as an error
 635          * either and will simply return 0, which is fine. */
 636         dev->version = readl(dev->base + PIPE_REG_VERSION);
 637         return 0;
 638
 639 error:
 640         dev->base = NULL;
 641         return err;
 642 }
 643
 644 static int goldfish_pipe_remove(struct platform_device *pdev)
 645 {
 646         struct goldfish_pipe_dev *dev = pipe_dev;
 647         misc_deregister(&goldfish_pipe_device);
 648         dev->base = NULL;
 649         return 0;
 650 }
 651
 652 static const struct acpi_device_id goldfish_pipe_acpi_match[] = {
 653         { "GFSH0003", 0 },
 654         { },
 655 };
 656 MODULE_DEVICE_TABLE(acpi, goldfish_pipe_acpi_match);
 657
 658 static const struct of_device_id goldfish_pipe_of_match[] = {
 659         { .compatible = "generic,android-pipe", },
 660         {},
 661 };
 662 MODULE_DEVICE_TABLE(of, goldfish_pipe_of_match);
 663
 664 static struct platform_driver goldfish_pipe = {
 665         .probe = goldfish_pipe_probe,
 666         .remove = goldfish_pipe_remove,
 667         .driver = {
 668                 .name = "goldfish_pipe",
 669                 .of_match_table = goldfish_pipe_of_match,
 670                 .acpi_match_table = ACPI_PTR(goldfish_pipe_acpi_match),
 671         }
 672 };
 673
 674 module_platform_driver(goldfish_pipe);
 675 MODULE_AUTHOR("David Turner <digit@google.com>");
 676 MODULE_LICENSE("GPL");