2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
4 * (C) Copyright 2008-2010 Intel Corporation
5 * Author: Sreedhara DS (sreedhara.ds@intel.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
12 * SCU runing in ARC processor communicates with other entity running in IA
13 * core through IPC mechanism which in turn messaging between IA core ad SCU.
14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
17 * along with other APIs.
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/sysdev.h>
24 #include <linux/pci.h>
25 #include <linux/interrupt.h>
27 #include <asm/intel_scu_ipc.h>
29 /* IPC defines the following message types */
30 #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
31 #define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
32 #define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
33 #define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
34 #define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
36 /* Command id associated with message IPCMSG_PCNTRL */
37 #define IPC_CMD_PCNTRL_W 0 /* Register write */
38 #define IPC_CMD_PCNTRL_R 1 /* Register read */
39 #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
42 * IPC register summary
44 * IPC register blocks are memory mapped at fixed address of 0xFF11C000
45 * To read or write information to the SCU, driver writes to IPC-1 memory
46 * mapped registers (base address 0xFF11C000). The following is the IPC
49 * 1. IA core cDMI interface claims this transaction and converts it to a
50 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
52 * 2. South Complex cDMI block receives this message and writes it to
53 * the IPC-1 register block, causing an interrupt to the SCU
55 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
56 * message handler is called within firmware.
59 #define IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */
60 #define IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */
61 #define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
62 #define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
63 #define IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */
64 #define IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */
66 static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id);
67 static void ipc_remove(struct pci_dev *pdev);
69 struct intel_scu_ipc_dev {
71 void __iomem *ipc_base;
72 void __iomem *i2c_base;
75 static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
77 static int platform; /* Platform type */
80 * IPC Read Buffer (Read Only):
81 * 16 byte buffer for receiving data from SCU, if IPC command
82 * processing results in response data
84 #define IPC_READ_BUFFER 0x90
86 #define IPC_I2C_CNTRL_ADDR 0
87 #define I2C_DATA_ADDR 0x04
89 static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
92 * Command Register (Write Only):
93 * A write to this register results in an interrupt to the SCU core processor
95 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
97 static inline void ipc_command(u32 cmd) /* Send ipc command */
99 writel(cmd, ipcdev.ipc_base);
103 * IPC Write Buffer (Write Only):
104 * 16-byte buffer for sending data associated with IPC command to
105 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
107 static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */
109 writel(data, ipcdev.ipc_base + 0x80 + offset);
113 * Status Register (Read Only):
114 * Driver will read this register to get the ready/busy status of the IPC
115 * block and error status of the IPC command that was just processed by SCU
117 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
120 static inline u8 ipc_read_status(void)
122 return __raw_readl(ipcdev.ipc_base + 0x04);
125 static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */
127 return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
130 static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */
132 return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
135 static inline int busy_loop(void) /* Wait till scu status is busy */
140 status = ipc_read_status();
142 udelay(1); /* scu processing time is in few u secods */
143 status = ipc_read_status();
145 /* break if scu doesn't reset busy bit after huge retry */
146 if (loop_count > 100000) {
147 dev_err(&ipcdev.pdev->dev, "IPC timed out");
151 return (status >> 1) & 1;
154 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
155 static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
160 u8 cbuf[IPC_WWBUF_SIZE] = { };
161 u32 *wbuf = (u32 *)&cbuf;
163 mutex_lock(&ipclock);
165 if (ipcdev.pdev == NULL) {
166 mutex_unlock(&ipclock);
170 if (platform != MRST_CPU_CHIP_PENWELL) {
171 /* Entry is 4 bytes for read/write, 5 bytes for read modify */
172 for (nc = 0; nc < count; nc++, offset += 3) {
173 cbuf[offset] = addr[nc];
174 cbuf[offset + 1] = addr[nc] >> 8;
175 if (id != IPC_CMD_PCNTRL_R)
176 cbuf[offset + 2] = data[nc];
177 if (id == IPC_CMD_PCNTRL_M) {
178 cbuf[offset + 3] = data[nc + 1];
182 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
183 ipc_data_writel(wbuf[nc], offset); /* Write wbuff */
185 if (id != IPC_CMD_PCNTRL_M)
186 ipc_command((count*4) << 16 | id << 12 | 0 << 8 | op);
188 ipc_command((count*5) << 16 | id << 12 | 0 << 8 | op);
191 for (nc = 0; nc < count; nc++, offset += 2) {
192 cbuf[offset] = addr[nc];
193 cbuf[offset + 1] = addr[nc] >> 8;
196 if (id == IPC_CMD_PCNTRL_R) {
197 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
198 ipc_data_writel(wbuf[nc], offset);
199 ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op);
200 } else if (id == IPC_CMD_PCNTRL_W) {
201 for (nc = 0; nc < count; nc++, offset += 1)
202 cbuf[offset] = data[nc];
203 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
204 ipc_data_writel(wbuf[nc], offset);
205 ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op);
206 } else if (id == IPC_CMD_PCNTRL_M) {
207 cbuf[offset] = data[0];
208 cbuf[offset + 1] = data[1];
209 ipc_data_writel(wbuf[0], 0); /* Write wbuff */
210 ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
215 if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
216 /* Workaround: values are read as 0 without memcpy_fromio */
217 memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
218 if (platform != MRST_CPU_CHIP_PENWELL) {
219 for (nc = 0, offset = 2; nc < count; nc++, offset += 3)
220 data[nc] = ipc_data_readb(offset);
222 for (nc = 0; nc < count; nc++)
223 data[nc] = ipc_data_readb(nc);
226 mutex_unlock(&ipclock);
231 * intel_scu_ipc_ioread8 - read a word via the SCU
232 * @addr: register on SCU
233 * @data: return pointer for read byte
235 * Read a single register. Returns 0 on success or an error code. All
236 * locking between SCU accesses is handled for the caller.
238 * This function may sleep.
240 int intel_scu_ipc_ioread8(u16 addr, u8 *data)
242 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
244 EXPORT_SYMBOL(intel_scu_ipc_ioread8);
247 * intel_scu_ipc_ioread16 - read a word via the SCU
248 * @addr: register on SCU
249 * @data: return pointer for read word
251 * Read a register pair. Returns 0 on success or an error code. All
252 * locking between SCU accesses is handled for the caller.
254 * This function may sleep.
256 int intel_scu_ipc_ioread16(u16 addr, u16 *data)
258 u16 x[2] = {addr, addr + 1 };
259 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
261 EXPORT_SYMBOL(intel_scu_ipc_ioread16);
264 * intel_scu_ipc_ioread32 - read a dword via the SCU
265 * @addr: register on SCU
266 * @data: return pointer for read dword
268 * Read four registers. Returns 0 on success or an error code. All
269 * locking between SCU accesses is handled for the caller.
271 * This function may sleep.
273 int intel_scu_ipc_ioread32(u16 addr, u32 *data)
275 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
276 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
278 EXPORT_SYMBOL(intel_scu_ipc_ioread32);
281 * intel_scu_ipc_iowrite8 - write a byte via the SCU
282 * @addr: register on SCU
283 * @data: byte to write
285 * Write a single register. Returns 0 on success or an error code. All
286 * locking between SCU accesses is handled for the caller.
288 * This function may sleep.
290 int intel_scu_ipc_iowrite8(u16 addr, u8 data)
292 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
294 EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
297 * intel_scu_ipc_iowrite16 - write a word via the SCU
298 * @addr: register on SCU
299 * @data: word to write
301 * Write two registers. Returns 0 on success or an error code. All
302 * locking between SCU accesses is handled for the caller.
304 * This function may sleep.
306 int intel_scu_ipc_iowrite16(u16 addr, u16 data)
308 u16 x[2] = {addr, addr + 1 };
309 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
311 EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
314 * intel_scu_ipc_iowrite32 - write a dword via the SCU
315 * @addr: register on SCU
316 * @data: dword to write
318 * Write four registers. Returns 0 on success or an error code. All
319 * locking between SCU accesses is handled for the caller.
321 * This function may sleep.
323 int intel_scu_ipc_iowrite32(u16 addr, u32 data)
325 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
326 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
328 EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
331 * intel_scu_ipc_readvv - read a set of registers
332 * @addr: register list
333 * @data: bytes to return
334 * @len: length of array
336 * Read registers. Returns 0 on success or an error code. All
337 * locking between SCU accesses is handled for the caller.
339 * The largest array length permitted by the hardware is 5 items.
341 * This function may sleep.
343 int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
345 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
347 EXPORT_SYMBOL(intel_scu_ipc_readv);
350 * intel_scu_ipc_writev - write a set of registers
351 * @addr: register list
352 * @data: bytes to write
353 * @len: length of array
355 * Write registers. Returns 0 on success or an error code. All
356 * locking between SCU accesses is handled for the caller.
358 * The largest array length permitted by the hardware is 5 items.
360 * This function may sleep.
363 int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
365 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
367 EXPORT_SYMBOL(intel_scu_ipc_writev);
371 * intel_scu_ipc_update_register - r/m/w a register
372 * @addr: register address
373 * @bits: bits to update
374 * @mask: mask of bits to update
376 * Read-modify-write power control unit register. The first data argument
377 * must be register value and second is mask value
378 * mask is a bitmap that indicates which bits to update.
379 * 0 = masked. Don't modify this bit, 1 = modify this bit.
380 * returns 0 on success or an error code.
382 * This function may sleep. Locking between SCU accesses is handled
385 int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
387 u8 data[2] = { bits, mask };
388 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
390 EXPORT_SYMBOL(intel_scu_ipc_update_register);
393 * intel_scu_ipc_simple_command - send a simple command
397 * Issue a simple command to the SCU. Do not use this interface if
398 * you must then access data as any data values may be overwritten
399 * by another SCU access by the time this function returns.
401 * This function may sleep. Locking for SCU accesses is handled for
404 int intel_scu_ipc_simple_command(int cmd, int sub)
408 mutex_lock(&ipclock);
409 if (ipcdev.pdev == NULL) {
410 mutex_unlock(&ipclock);
413 ipc_command(sub << 12 | cmd);
415 mutex_unlock(&ipclock);
418 EXPORT_SYMBOL(intel_scu_ipc_simple_command);
421 * intel_scu_ipc_command - command with data
425 * @inlen: input length in dwords
427 * @outlein: output length in dwords
429 * Issue a command to the SCU which involves data transfers. Do the
430 * data copies under the lock but leave it for the caller to interpret
433 int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
434 u32 *out, int outlen)
439 mutex_lock(&ipclock);
440 if (ipcdev.pdev == NULL) {
441 mutex_unlock(&ipclock);
445 for (i = 0; i < inlen; i++)
446 ipc_data_writel(*in++, 4 * i);
448 ipc_command((sub << 12) | cmd | (inlen << 18));
451 for (i = 0; i < outlen; i++)
452 *out++ = ipc_data_readl(4 * i);
454 mutex_unlock(&ipclock);
457 EXPORT_SYMBOL(intel_scu_ipc_command);
460 #define IPC_I2C_WRITE 1 /* I2C Write command */
461 #define IPC_I2C_READ 2 /* I2C Read command */
464 * intel_scu_ipc_i2c_cntrl - I2C read/write operations
465 * @addr: I2C address + command bits
466 * @data: data to read/write
468 * Perform an an I2C read/write operation via the SCU. All locking is
469 * handled for the caller. This function may sleep.
471 * Returns an error code or 0 on success.
473 * This has to be in the IPC driver for the locking.
475 int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
479 mutex_lock(&ipclock);
480 if (ipcdev.pdev == NULL) {
481 mutex_unlock(&ipclock);
484 cmd = (addr >> 24) & 0xFF;
485 if (cmd == IPC_I2C_READ) {
486 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
487 /* Write not getting updated without delay */
489 *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR);
490 } else if (cmd == IPC_I2C_WRITE) {
491 writel(addr, ipcdev.i2c_base + I2C_DATA_ADDR);
493 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
495 dev_err(&ipcdev.pdev->dev,
496 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
498 mutex_unlock(&ipclock);
501 mutex_unlock(&ipclock);
504 EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
506 #define IPC_FW_LOAD_ADDR 0xFFFC0000 /* Storage location for FW image */
507 #define IPC_FW_UPDATE_MBOX_ADDR 0xFFFFDFF4 /* Mailbox between ipc and scu */
508 #define IPC_MAX_FW_SIZE 262144 /* 256K storage size for loading the FW image */
509 #define IPC_FW_MIP_HEADER_SIZE 2048 /* Firmware MIP header size */
510 /* IPC inform SCU to get ready for update process */
511 #define IPC_CMD_FW_UPDATE_READY 0x10FE
512 /* IPC inform SCU to go for update process */
513 #define IPC_CMD_FW_UPDATE_GO 0x20FE
514 /* Status code for fw update */
515 #define IPC_FW_UPDATE_SUCCESS 0x444f4e45 /* Status code 'DONE' */
516 #define IPC_FW_UPDATE_BADN 0x4241444E /* Status code 'BADN' */
517 #define IPC_FW_TXHIGH 0x54784849 /* Status code 'IPC_FW_TXHIGH' */
518 #define IPC_FW_TXLOW 0x54784c4f /* Status code 'IPC_FW_TXLOW' */
520 struct fw_update_mailbox {
528 * intel_scu_ipc_fw_update - Firmware update utility
529 * @buffer: firmware buffer
530 * @length: size of firmware buffer
532 * This function provides an interface to load the firmware into
533 * the SCU. Returns 0 on success or -1 on failure
535 int intel_scu_ipc_fw_update(u8 *buffer, u32 length)
537 void __iomem *fw_update_base;
538 struct fw_update_mailbox __iomem *mailbox = NULL;
542 mutex_lock(&ipclock);
543 fw_update_base = ioremap_nocache(IPC_FW_LOAD_ADDR, (128*1024));
544 if (fw_update_base == NULL) {
545 mutex_unlock(&ipclock);
548 mailbox = ioremap_nocache(IPC_FW_UPDATE_MBOX_ADDR,
549 sizeof(struct fw_update_mailbox));
550 if (mailbox == NULL) {
551 iounmap(fw_update_base);
552 mutex_unlock(&ipclock);
556 ipc_command(IPC_CMD_FW_UPDATE_READY);
558 /* Intitialize mailbox */
559 writel(0, &mailbox->status);
560 writel(0, &mailbox->scu_flag);
561 writel(0, &mailbox->driver_flag);
563 /* Driver copies the 2KB MIP header to SRAM at 0xFFFC0000*/
564 memcpy_toio(fw_update_base, buffer, 0x800);
566 /* Driver sends "FW Update" IPC command (CMD_ID 0xFE; MSG_ID 0x02).
567 * Upon receiving this command, SCU will write the 2K MIP header
568 * from 0xFFFC0000 into NAND.
569 * SCU will write a status code into the Mailbox, and then set scu_flag.
572 ipc_command(IPC_CMD_FW_UPDATE_GO);
574 /*Driver stalls until scu_flag is set */
575 while (readl(&mailbox->scu_flag) != 1) {
580 /* Driver checks Mailbox status.
581 * If the status is 'BADN', then abort (bad NAND).
582 * If the status is 'IPC_FW_TXLOW', then continue.
584 while (readl(&mailbox->status) != IPC_FW_TXLOW) {
594 if (readl(&mailbox->status) != IPC_FW_TXLOW)
596 buffer = buffer + 0x800;
597 memcpy_toio(fw_update_base, buffer, 0x20000);
598 writel(1, &mailbox->driver_flag);
599 while (readl(&mailbox->scu_flag) == 1) {
604 /* check for 'BADN' */
605 if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN)
608 while (readl(&mailbox->status) != IPC_FW_TXHIGH) {
614 if (readl(&mailbox->status) != IPC_FW_TXHIGH)
617 buffer = buffer + 0x20000;
618 memcpy_toio(fw_update_base, buffer, 0x20000);
619 writel(0, &mailbox->driver_flag);
621 while (mailbox->scu_flag == 0) {
626 /* check for 'BADN' */
627 if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN)
630 if (readl(&mailbox->status) == IPC_FW_TXLOW) {
636 status = readl(&mailbox->status);
638 iounmap(fw_update_base);
640 mutex_unlock(&ipclock);
642 if (status == IPC_FW_UPDATE_SUCCESS)
646 EXPORT_SYMBOL(intel_scu_ipc_fw_update);
649 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
650 * When ioc bit is set to 1, caller api must wait for interrupt handler called
651 * which in turn unlocks the caller api. Currently this is not used
653 * This is edge triggered so we need take no action to clear anything
655 static irqreturn_t ioc(int irq, void *dev_id)
661 * ipc_probe - probe an Intel SCU IPC
662 * @dev: the PCI device matching
663 * @id: entry in the match table
665 * Enable and install an intel SCU IPC. This appears in the PCI space
666 * but uses some hard coded addresses as well.
668 static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
671 resource_size_t pci_resource;
673 if (ipcdev.pdev) /* We support only one SCU */
676 ipcdev.pdev = pci_dev_get(dev);
678 err = pci_enable_device(dev);
682 err = pci_request_regions(dev, "intel_scu_ipc");
686 pci_resource = pci_resource_start(dev, 0);
690 if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev))
693 ipcdev.ipc_base = ioremap_nocache(IPC_BASE_ADDR, IPC_MAX_ADDR);
694 if (!ipcdev.ipc_base)
697 ipcdev.i2c_base = ioremap_nocache(IPC_I2C_BASE, IPC_I2C_MAX_ADDR);
698 if (!ipcdev.i2c_base) {
699 iounmap(ipcdev.ipc_base);
706 * ipc_remove - remove a bound IPC device
709 * In practice the SCU is not removable but this function is also
710 * called for each device on a module unload or cleanup which is the
711 * path that will get used.
713 * Free up the mappings and release the PCI resources
715 static void ipc_remove(struct pci_dev *pdev)
717 free_irq(pdev->irq, &ipcdev);
718 pci_release_regions(pdev);
719 pci_dev_put(ipcdev.pdev);
720 iounmap(ipcdev.ipc_base);
721 iounmap(ipcdev.i2c_base);
725 static const struct pci_device_id pci_ids[] = {
726 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080e)},
727 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)},
730 MODULE_DEVICE_TABLE(pci, pci_ids);
732 static struct pci_driver ipc_driver = {
733 .name = "intel_scu_ipc",
736 .remove = ipc_remove,
740 static int __init intel_scu_ipc_init(void)
742 platform = mrst_identify_cpu();
745 return pci_register_driver(&ipc_driver);
748 static void __exit intel_scu_ipc_exit(void)
750 pci_unregister_driver(&ipc_driver);
753 MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>");
754 MODULE_DESCRIPTION("Intel SCU IPC driver");
755 MODULE_LICENSE("GPL");
757 module_init(intel_scu_ipc_init);
758 module_exit(intel_scu_ipc_exit);