2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
4 * (C) Copyright 2008-2010 Intel Corporation
5 * Author: Sreedhara DS (sreedhara.ds@intel.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
12 * SCU runing in ARC processor communicates with other entity running in IA
13 * core through IPC mechanism which in turn messaging between IA core ad SCU.
14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
17 * along with other APIs.
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/sysdev.h>
24 #include <linux/pci.h>
25 #include <linux/interrupt.h>
26 #include <asm/setup.h>
27 #include <asm/intel_scu_ipc.h>
29 /* IPC defines the following message types */
30 #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
31 #define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
32 #define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
33 #define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
34 #define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
36 /* Command id associated with message IPCMSG_PCNTRL */
37 #define IPC_CMD_PCNTRL_W 0 /* Register write */
38 #define IPC_CMD_PCNTRL_R 1 /* Register read */
39 #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
41 /* Miscelaneous Command ids */
42 #define IPC_CMD_INDIRECT_RD 2 /* 32bit indirect read */
43 #define IPC_CMD_INDIRECT_WR 5 /* 32bit indirect write */
46 * IPC register summary
48 * IPC register blocks are memory mapped at fixed address of 0xFF11C000
49 * To read or write information to the SCU, driver writes to IPC-1 memory
50 * mapped registers (base address 0xFF11C000). The following is the IPC
53 * 1. IA core cDMI interface claims this transaction and converts it to a
54 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
56 * 2. South Complex cDMI block receives this message and writes it to
57 * the IPC-1 register block, causing an interrupt to the SCU
59 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
60 * message handler is called within firmware.
63 #define IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */
64 #define IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */
65 #define IPC_WWBUF_SIZE 16 /* IPC Write buffer Size */
66 #define IPC_RWBUF_SIZE 16 /* IPC Read buffer Size */
67 #define IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */
68 #define IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */
70 static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id);
71 static void ipc_remove(struct pci_dev *pdev);
73 struct intel_scu_ipc_dev {
75 void __iomem *ipc_base;
76 void __iomem *i2c_base;
79 static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
81 static int platform = 1;
82 module_param(platform, int, 0);
83 MODULE_PARM_DESC(platform, "1 for moorestown platform");
89 * IPC Read Buffer (Read Only):
90 * 16 byte buffer for receiving data from SCU, if IPC command
91 * processing results in response data
93 #define IPC_READ_BUFFER 0x90
95 #define IPC_I2C_CNTRL_ADDR 0
96 #define I2C_DATA_ADDR 0x04
98 static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
101 * Command Register (Write Only):
102 * A write to this register results in an interrupt to the SCU core processor
104 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
106 static inline void ipc_command(u32 cmd) /* Send ipc command */
108 writel(cmd, ipcdev.ipc_base);
112 * IPC Write Buffer (Write Only):
113 * 16-byte buffer for sending data associated with IPC command to
114 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
116 static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */
118 writel(data, ipcdev.ipc_base + 0x80 + offset);
122 * IPC destination Pointer (Write Only):
123 * Use content as pointer for destination write
125 static inline void ipc_write_dptr(u32 data) /* Write dptr data */
127 writel(data, ipcdev.ipc_base + 0x0C);
131 * IPC Source Pointer (Write Only):
132 * Use content as pointer for read location
134 static inline void ipc_write_sptr(u32 data) /* Write dptr data */
136 writel(data, ipcdev.ipc_base + 0x08);
140 * Status Register (Read Only):
141 * Driver will read this register to get the ready/busy status of the IPC
142 * block and error status of the IPC command that was just processed by SCU
144 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
147 static inline u8 ipc_read_status(void)
149 return __raw_readl(ipcdev.ipc_base + 0x04);
152 static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */
154 return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
157 static inline u8 ipc_data_readl(u32 offset) /* Read ipc u32 data */
159 return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
162 static inline int busy_loop(void) /* Wait till scu status is busy */
167 status = ipc_read_status();
169 udelay(1); /* scu processing time is in few u secods */
170 status = ipc_read_status();
172 /* break if scu doesn't reset busy bit after huge retry */
173 if (loop_count > 100000) {
174 dev_err(&ipcdev.pdev->dev, "IPC timed out");
178 return (status >> 1) & 1;
181 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
182 static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
187 u8 cbuf[IPC_WWBUF_SIZE] = { '\0' };
188 u32 *wbuf = (u32 *)&cbuf;
190 mutex_lock(&ipclock);
191 if (ipcdev.pdev == NULL) {
192 mutex_unlock(&ipclock);
197 /* Entry is 4 bytes for read/write, 5 bytes for read modify */
198 for (nc = 0; nc < count; nc++) {
199 cbuf[offset] = addr[nc];
200 cbuf[offset + 1] = addr[nc] >> 8;
201 if (id != IPC_CMD_PCNTRL_R)
202 cbuf[offset + 2] = data[nc];
203 if (id == IPC_CMD_PCNTRL_M) {
204 cbuf[offset + 3] = data[nc + 1];
209 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
210 ipc_data_writel(wbuf[nc], offset); /* Write wbuff */
213 for (nc = 0, offset = 0; nc < count; nc++, offset += 2)
214 ipc_data_writel(addr[nc], offset); /* Write addresses */
215 if (id != IPC_CMD_PCNTRL_R) {
216 for (nc = 0; nc < count; nc++, offset++)
217 ipc_data_writel(data[nc], offset); /* Write data */
218 if (id == IPC_CMD_PCNTRL_M)
219 ipc_data_writel(data[nc + 1], offset); /* Mask value*/
223 if (id != IPC_CMD_PCNTRL_M)
224 ipc_command((count * 3) << 16 | id << 12 | 0 << 8 | op);
226 ipc_command((count * 4) << 16 | id << 12 | 0 << 8 | op);
230 if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
231 /* Workaround: values are read as 0 without memcpy_fromio */
232 memcpy_fromio(cbuf, ipcdev.ipc_base + IPC_READ_BUFFER, 16);
234 for (nc = 0, offset = 2; nc < count; nc++, offset += 3)
235 data[nc] = ipc_data_readb(offset);
237 for (nc = 0; nc < count; nc++)
238 data[nc] = ipc_data_readb(nc);
241 mutex_unlock(&ipclock);
246 * intel_scu_ipc_ioread8 - read a word via the SCU
247 * @addr: register on SCU
248 * @data: return pointer for read byte
250 * Read a single register. Returns 0 on success or an error code. All
251 * locking between SCU accesses is handled for the caller.
253 * This function may sleep.
255 int intel_scu_ipc_ioread8(u16 addr, u8 *data)
257 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
259 EXPORT_SYMBOL(intel_scu_ipc_ioread8);
262 * intel_scu_ipc_ioread16 - read a word via the SCU
263 * @addr: register on SCU
264 * @data: return pointer for read word
266 * Read a register pair. Returns 0 on success or an error code. All
267 * locking between SCU accesses is handled for the caller.
269 * This function may sleep.
271 int intel_scu_ipc_ioread16(u16 addr, u16 *data)
273 u16 x[2] = {addr, addr + 1 };
274 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
276 EXPORT_SYMBOL(intel_scu_ipc_ioread16);
279 * intel_scu_ipc_ioread32 - read a dword via the SCU
280 * @addr: register on SCU
281 * @data: return pointer for read dword
283 * Read four registers. Returns 0 on success or an error code. All
284 * locking between SCU accesses is handled for the caller.
286 * This function may sleep.
288 int intel_scu_ipc_ioread32(u16 addr, u32 *data)
290 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
291 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
293 EXPORT_SYMBOL(intel_scu_ipc_ioread32);
296 * intel_scu_ipc_iowrite8 - write a byte via the SCU
297 * @addr: register on SCU
298 * @data: byte to write
300 * Write a single register. Returns 0 on success or an error code. All
301 * locking between SCU accesses is handled for the caller.
303 * This function may sleep.
305 int intel_scu_ipc_iowrite8(u16 addr, u8 data)
307 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
309 EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
312 * intel_scu_ipc_iowrite16 - write a word via the SCU
313 * @addr: register on SCU
314 * @data: word to write
316 * Write two registers. Returns 0 on success or an error code. All
317 * locking between SCU accesses is handled for the caller.
319 * This function may sleep.
321 int intel_scu_ipc_iowrite16(u16 addr, u16 data)
323 u16 x[2] = {addr, addr + 1 };
324 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
326 EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
329 * intel_scu_ipc_iowrite32 - write a dword via the SCU
330 * @addr: register on SCU
331 * @data: dword to write
333 * Write four registers. Returns 0 on success or an error code. All
334 * locking between SCU accesses is handled for the caller.
336 * This function may sleep.
338 int intel_scu_ipc_iowrite32(u16 addr, u32 data)
340 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
341 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
343 EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
346 * intel_scu_ipc_readvv - read a set of registers
347 * @addr: register list
348 * @data: bytes to return
349 * @len: length of array
351 * Read registers. Returns 0 on success or an error code. All
352 * locking between SCU accesses is handled for the caller.
354 * The largest array length permitted by the hardware is 5 items.
356 * This function may sleep.
358 int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
360 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
362 EXPORT_SYMBOL(intel_scu_ipc_readv);
365 * intel_scu_ipc_writev - write a set of registers
366 * @addr: register list
367 * @data: bytes to write
368 * @len: length of array
370 * Write registers. Returns 0 on success or an error code. All
371 * locking between SCU accesses is handled for the caller.
373 * The largest array length permitted by the hardware is 5 items.
375 * This function may sleep.
378 int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
380 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
382 EXPORT_SYMBOL(intel_scu_ipc_writev);
386 * intel_scu_ipc_update_register - r/m/w a register
387 * @addr: register address
388 * @bits: bits to update
389 * @mask: mask of bits to update
391 * Read-modify-write power control unit register. The first data argument
392 * must be register value and second is mask value
393 * mask is a bitmap that indicates which bits to update.
394 * 0 = masked. Don't modify this bit, 1 = modify this bit.
395 * returns 0 on success or an error code.
397 * This function may sleep. Locking between SCU accesses is handled
400 int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
402 u8 data[2] = { bits, mask };
403 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
405 EXPORT_SYMBOL(intel_scu_ipc_update_register);
408 * intel_scu_ipc_register_read - 32bit indirect read
409 * @addr: register address
410 * @value: 32bit value return
412 * Performs IA 32 bit indirect read, returns 0 on success, or an
415 * Can be used when SCCB(System Controller Configuration Block) register
416 * HRIM(Honor Restricted IPC Messages) is set (bit 23)
418 * This function may sleep. Locking for SCU accesses is handled for
421 int intel_scu_ipc_register_read(u32 addr, u32 *value)
425 mutex_lock(&ipclock);
426 if (ipcdev.pdev == NULL) {
427 mutex_unlock(&ipclock);
430 ipc_write_sptr(addr);
431 ipc_command(4 << 16 | IPC_CMD_INDIRECT_RD);
433 *value = ipc_data_readl(0);
434 mutex_unlock(&ipclock);
437 EXPORT_SYMBOL(intel_scu_ipc_register_read);
440 * intel_scu_ipc_register_write - 32bit indirect write
441 * @addr: register address
442 * @value: 32bit value to write
444 * Performs IA 32 bit indirect write, returns 0 on success, or an
447 * Can be used when SCCB(System Controller Configuration Block) register
448 * HRIM(Honor Restricted IPC Messages) is set (bit 23)
450 * This function may sleep. Locking for SCU accesses is handled for
453 int intel_scu_ipc_register_write(u32 addr, u32 value)
457 mutex_lock(&ipclock);
458 if (ipcdev.pdev == NULL) {
459 mutex_unlock(&ipclock);
462 ipc_write_dptr(addr);
463 ipc_data_writel(value, 0);
464 ipc_command(4 << 16 | IPC_CMD_INDIRECT_WR);
466 mutex_unlock(&ipclock);
469 EXPORT_SYMBOL(intel_scu_ipc_register_write);
472 * intel_scu_ipc_simple_command - send a simple command
476 * Issue a simple command to the SCU. Do not use this interface if
477 * you must then access data as any data values may be overwritten
478 * by another SCU access by the time this function returns.
480 * This function may sleep. Locking for SCU accesses is handled for
483 int intel_scu_ipc_simple_command(int cmd, int sub)
487 mutex_lock(&ipclock);
488 if (ipcdev.pdev == NULL) {
489 mutex_unlock(&ipclock);
492 ipc_command(sub << 12 | cmd);
494 mutex_unlock(&ipclock);
497 EXPORT_SYMBOL(intel_scu_ipc_simple_command);
500 * intel_scu_ipc_command - command with data
504 * @inlen: input length in dwords
506 * @outlein: output length in dwords
508 * Issue a command to the SCU which involves data transfers. Do the
509 * data copies under the lock but leave it for the caller to interpret
512 int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
513 u32 *out, int outlen)
518 mutex_lock(&ipclock);
519 if (ipcdev.pdev == NULL) {
520 mutex_unlock(&ipclock);
524 for (i = 0; i < inlen; i++)
525 ipc_data_writel(*in++, 4 * i);
527 ipc_command((sub << 12) | cmd | (inlen << 18));
530 for (i = 0; i < outlen; i++)
531 *out++ = ipc_data_readl(4 * i);
533 mutex_unlock(&ipclock);
536 EXPORT_SYMBOL(intel_scu_ipc_command);
539 #define IPC_I2C_WRITE 1 /* I2C Write command */
540 #define IPC_I2C_READ 2 /* I2C Read command */
543 * intel_scu_ipc_i2c_cntrl - I2C read/write operations
544 * @addr: I2C address + command bits
545 * @data: data to read/write
547 * Perform an an I2C read/write operation via the SCU. All locking is
548 * handled for the caller. This function may sleep.
550 * Returns an error code or 0 on success.
552 * This has to be in the IPC driver for the locking.
554 int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
558 mutex_lock(&ipclock);
559 if (ipcdev.pdev == NULL) {
560 mutex_unlock(&ipclock);
563 cmd = (addr >> 24) & 0xFF;
564 if (cmd == IPC_I2C_READ) {
565 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
566 /* Write not getting updated without delay */
568 *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR);
569 } else if (cmd == IPC_I2C_WRITE) {
570 writel(addr, ipcdev.i2c_base + I2C_DATA_ADDR);
572 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
574 dev_err(&ipcdev.pdev->dev,
575 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
577 mutex_unlock(&ipclock);
580 mutex_unlock(&ipclock);
583 EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
585 #define IPC_FW_LOAD_ADDR 0xFFFC0000 /* Storage location for FW image */
586 #define IPC_FW_UPDATE_MBOX_ADDR 0xFFFFDFF4 /* Mailbox between ipc and scu */
587 #define IPC_MAX_FW_SIZE 262144 /* 256K storage size for loading the FW image */
588 #define IPC_FW_MIP_HEADER_SIZE 2048 /* Firmware MIP header size */
589 /* IPC inform SCU to get ready for update process */
590 #define IPC_CMD_FW_UPDATE_READY 0x10FE
591 /* IPC inform SCU to go for update process */
592 #define IPC_CMD_FW_UPDATE_GO 0x20FE
593 /* Status code for fw update */
594 #define IPC_FW_UPDATE_SUCCESS 0x444f4e45 /* Status code 'DONE' */
595 #define IPC_FW_UPDATE_BADN 0x4241444E /* Status code 'BADN' */
596 #define IPC_FW_TXHIGH 0x54784849 /* Status code 'IPC_FW_TXHIGH' */
597 #define IPC_FW_TXLOW 0x54784c4f /* Status code 'IPC_FW_TXLOW' */
599 struct fw_update_mailbox {
607 * intel_scu_ipc_fw_update - Firmware update utility
608 * @buffer: firmware buffer
609 * @length: size of firmware buffer
611 * This function provides an interface to load the firmware into
612 * the SCU. Returns 0 on success or -1 on failure
614 int intel_scu_ipc_fw_update(u8 *buffer, u32 length)
616 void __iomem *fw_update_base;
617 struct fw_update_mailbox __iomem *mailbox = NULL;
621 mutex_lock(&ipclock);
622 fw_update_base = ioremap_nocache(IPC_FW_LOAD_ADDR, (128*1024));
623 if (fw_update_base == NULL) {
624 mutex_unlock(&ipclock);
627 mailbox = ioremap_nocache(IPC_FW_UPDATE_MBOX_ADDR,
628 sizeof(struct fw_update_mailbox));
629 if (mailbox == NULL) {
630 iounmap(fw_update_base);
631 mutex_unlock(&ipclock);
635 ipc_command(IPC_CMD_FW_UPDATE_READY);
637 /* Intitialize mailbox */
638 writel(0, &mailbox->status);
639 writel(0, &mailbox->scu_flag);
640 writel(0, &mailbox->driver_flag);
642 /* Driver copies the 2KB MIP header to SRAM at 0xFFFC0000*/
643 memcpy_toio(fw_update_base, buffer, 0x800);
645 /* Driver sends "FW Update" IPC command (CMD_ID 0xFE; MSG_ID 0x02).
646 * Upon receiving this command, SCU will write the 2K MIP header
647 * from 0xFFFC0000 into NAND.
648 * SCU will write a status code into the Mailbox, and then set scu_flag.
651 ipc_command(IPC_CMD_FW_UPDATE_GO);
653 /*Driver stalls until scu_flag is set */
654 while (readl(&mailbox->scu_flag) != 1) {
659 /* Driver checks Mailbox status.
660 * If the status is 'BADN', then abort (bad NAND).
661 * If the status is 'IPC_FW_TXLOW', then continue.
663 while (readl(&mailbox->status) != IPC_FW_TXLOW) {
673 if (readl(&mailbox->status) != IPC_FW_TXLOW)
675 buffer = buffer + 0x800;
676 memcpy_toio(fw_update_base, buffer, 0x20000);
677 writel(1, &mailbox->driver_flag);
678 while (readl(&mailbox->scu_flag) == 1) {
683 /* check for 'BADN' */
684 if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN)
687 while (readl(&mailbox->status) != IPC_FW_TXHIGH) {
693 if (readl(&mailbox->status) != IPC_FW_TXHIGH)
696 buffer = buffer + 0x20000;
697 memcpy_toio(fw_update_base, buffer, 0x20000);
698 writel(0, &mailbox->driver_flag);
700 while (mailbox->scu_flag == 0) {
705 /* check for 'BADN' */
706 if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN)
709 if (readl(&mailbox->status) == IPC_FW_TXLOW) {
715 status = readl(&mailbox->status);
717 iounmap(fw_update_base);
719 mutex_unlock(&ipclock);
721 if (status == IPC_FW_UPDATE_SUCCESS)
725 EXPORT_SYMBOL(intel_scu_ipc_fw_update);
728 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
729 * When ioc bit is set to 1, caller api must wait for interrupt handler called
730 * which in turn unlocks the caller api. Currently this is not used
732 * This is edge triggered so we need take no action to clear anything
734 static irqreturn_t ioc(int irq, void *dev_id)
740 * ipc_probe - probe an Intel SCU IPC
741 * @dev: the PCI device matching
742 * @id: entry in the match table
744 * Enable and install an intel SCU IPC. This appears in the PCI space
745 * but uses some hard coded addresses as well.
747 static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
750 resource_size_t pci_resource;
752 if (ipcdev.pdev) /* We support only one SCU */
755 ipcdev.pdev = pci_dev_get(dev);
757 err = pci_enable_device(dev);
761 err = pci_request_regions(dev, "intel_scu_ipc");
765 pci_resource = pci_resource_start(dev, 0);
769 if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev))
772 ipcdev.ipc_base = ioremap_nocache(IPC_BASE_ADDR, IPC_MAX_ADDR);
773 if (!ipcdev.ipc_base)
776 ipcdev.i2c_base = ioremap_nocache(IPC_I2C_BASE, IPC_I2C_MAX_ADDR);
777 if (!ipcdev.i2c_base) {
778 iounmap(ipcdev.ipc_base);
785 * ipc_remove - remove a bound IPC device
788 * In practice the SCU is not removable but this function is also
789 * called for each device on a module unload or cleanup which is the
790 * path that will get used.
792 * Free up the mappings and release the PCI resources
794 static void ipc_remove(struct pci_dev *pdev)
796 free_irq(pdev->irq, &ipcdev);
797 pci_release_regions(pdev);
798 pci_dev_put(ipcdev.pdev);
799 iounmap(ipcdev.ipc_base);
800 iounmap(ipcdev.i2c_base);
804 static const struct pci_device_id pci_ids[] = {
805 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080e)},
808 MODULE_DEVICE_TABLE(pci, pci_ids);
810 static struct pci_driver ipc_driver = {
811 .name = "intel_scu_ipc",
814 .remove = ipc_remove,
818 static int __init intel_scu_ipc_init(void)
820 return pci_register_driver(&ipc_driver);
823 static void __exit intel_scu_ipc_exit(void)
825 pci_unregister_driver(&ipc_driver);
828 MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>");
829 MODULE_DESCRIPTION("Intel SCU IPC driver");
830 MODULE_LICENSE("GPL");
832 module_init(intel_scu_ipc_init);
833 module_exit(intel_scu_ipc_exit);