2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
4 * (C) Copyright 2008-2010 Intel Corporation
5 * Author: Sreedhara DS (sreedhara.ds@intel.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
12 * SCU runing in ARC processor communicates with other entity running in IA
13 * core through IPC mechanism which in turn messaging between IA core ad SCU.
14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
17 * along with other APIs.
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/sysdev.h>
24 #include <linux/pci.h>
25 #include <linux/interrupt.h>
27 #include <asm/intel_scu_ipc.h>
29 /* IPC defines the following message types */
30 #define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
31 #define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
32 #define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
33 #define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
34 #define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
36 /* Command id associated with message IPCMSG_PCNTRL */
37 #define IPC_CMD_PCNTRL_W 0 /* Register write */
38 #define IPC_CMD_PCNTRL_R 1 /* Register read */
39 #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
42 * IPC register summary
44 * IPC register blocks are memory mapped at fixed address of 0xFF11C000
45 * To read or write information to the SCU, driver writes to IPC-1 memory
46 * mapped registers (base address 0xFF11C000). The following is the IPC
49 * 1. IA core cDMI interface claims this transaction and converts it to a
50 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
52 * 2. South Complex cDMI block receives this message and writes it to
53 * the IPC-1 register block, causing an interrupt to the SCU
55 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
56 * message handler is called within firmware.
59 #define IPC_BASE_ADDR 0xFF11C000 /* IPC1 base register address */
60 #define IPC_MAX_ADDR 0x100 /* Maximum IPC regisers */
61 #define IPC_WWBUF_SIZE 16 /* IPC Write buffer Size */
62 #define IPC_RWBUF_SIZE 16 /* IPC Read buffer Size */
63 #define IPC_I2C_BASE 0xFF12B000 /* I2C control register base address */
64 #define IPC_I2C_MAX_ADDR 0x10 /* Maximum I2C regisers */
66 static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id);
67 static void ipc_remove(struct pci_dev *pdev);
69 struct intel_scu_ipc_dev {
71 void __iomem *ipc_base;
72 void __iomem *i2c_base;
75 static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
77 #define PLATFORM_LANGWELL 1
78 #define PLATFORM_PENWELL 2
79 static int platform; /* Platform type */
82 * IPC Read Buffer (Read Only):
83 * 16 byte buffer for receiving data from SCU, if IPC command
84 * processing results in response data
86 #define IPC_READ_BUFFER 0x90
88 #define IPC_I2C_CNTRL_ADDR 0
89 #define I2C_DATA_ADDR 0x04
91 static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
94 * Command Register (Write Only):
95 * A write to this register results in an interrupt to the SCU core processor
97 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
99 static inline void ipc_command(u32 cmd) /* Send ipc command */
101 writel(cmd, ipcdev.ipc_base);
105 * IPC Write Buffer (Write Only):
106 * 16-byte buffer for sending data associated with IPC command to
107 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
109 static inline void ipc_data_writel(u32 data, u32 offset) /* Write ipc data */
111 writel(data, ipcdev.ipc_base + 0x80 + offset);
115 * Status Register (Read Only):
116 * Driver will read this register to get the ready/busy status of the IPC
117 * block and error status of the IPC command that was just processed by SCU
119 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
122 static inline u8 ipc_read_status(void)
124 return __raw_readl(ipcdev.ipc_base + 0x04);
127 static inline u8 ipc_data_readb(u32 offset) /* Read ipc byte data */
129 return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
132 static inline u32 ipc_data_readl(u32 offset) /* Read ipc u32 data */
134 return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
137 static inline int busy_loop(void) /* Wait till scu status is busy */
142 status = ipc_read_status();
144 udelay(1); /* scu processing time is in few u secods */
145 status = ipc_read_status();
147 /* break if scu doesn't reset busy bit after huge retry */
148 if (loop_count > 100000) {
149 dev_err(&ipcdev.pdev->dev, "IPC timed out");
153 return (status >> 1) & 1;
156 /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
157 static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
162 u8 cbuf[IPC_WWBUF_SIZE] = { };
163 u32 *wbuf = (u32 *)&cbuf;
165 mutex_lock(&ipclock);
167 if (ipcdev.pdev == NULL) {
168 mutex_unlock(&ipclock);
172 if (platform == PLATFORM_LANGWELL) {
173 /* Entry is 4 bytes for read/write, 5 bytes for read modify */
174 for (nc = 0; nc < count; nc++, offset += 3) {
175 cbuf[offset] = addr[nc];
176 cbuf[offset + 1] = addr[nc] >> 8;
177 if (id != IPC_CMD_PCNTRL_R)
178 cbuf[offset + 2] = data[nc];
179 if (id == IPC_CMD_PCNTRL_M) {
180 cbuf[offset + 3] = data[nc + 1];
184 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
185 ipc_data_writel(wbuf[nc], offset); /* Write wbuff */
187 if (id != IPC_CMD_PCNTRL_M)
188 ipc_command((count*4) << 16 | id << 12 | 0 << 8 | op);
190 ipc_command((count*5) << 16 | id << 12 | 0 << 8 | op);
193 for (nc = 0; nc < count; nc++, offset += 2) {
194 cbuf[offset] = addr[nc];
195 cbuf[offset + 1] = addr[nc] >> 8;
198 if (id == IPC_CMD_PCNTRL_R) {
199 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
200 ipc_data_writel(wbuf[nc], offset);
201 ipc_command((count*2) << 16 | id << 12 | 0 << 8 | op);
202 } else if (id == IPC_CMD_PCNTRL_W) {
203 for (nc = 0; nc < count; nc++, offset += 1)
204 cbuf[offset] = data[nc];
205 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
206 ipc_data_writel(wbuf[nc], offset);
207 ipc_command((count*3) << 16 | id << 12 | 0 << 8 | op);
208 } else if (id == IPC_CMD_PCNTRL_M) {
209 cbuf[offset] = data[0];
210 cbuf[offset + 1] = data[1];
211 ipc_data_writel(wbuf[0], 0); /* Write wbuff */
212 ipc_command(4 << 16 | id << 12 | 0 << 8 | op);
217 if (id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
218 /* Workaround: values are read as 0 without memcpy_fromio */
219 memcpy_fromio(cbuf, ipcdev.ipc_base + 0x90, 16);
220 if (platform == PLATFORM_LANGWELL) {
221 for (nc = 0, offset = 2; nc < count; nc++, offset += 3)
222 data[nc] = ipc_data_readb(offset);
224 for (nc = 0; nc < count; nc++)
225 data[nc] = ipc_data_readb(nc);
228 mutex_unlock(&ipclock);
233 * intel_scu_ipc_ioread8 - read a word via the SCU
234 * @addr: register on SCU
235 * @data: return pointer for read byte
237 * Read a single register. Returns 0 on success or an error code. All
238 * locking between SCU accesses is handled for the caller.
240 * This function may sleep.
242 int intel_scu_ipc_ioread8(u16 addr, u8 *data)
244 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
246 EXPORT_SYMBOL(intel_scu_ipc_ioread8);
249 * intel_scu_ipc_ioread16 - read a word via the SCU
250 * @addr: register on SCU
251 * @data: return pointer for read word
253 * Read a register pair. Returns 0 on success or an error code. All
254 * locking between SCU accesses is handled for the caller.
256 * This function may sleep.
258 int intel_scu_ipc_ioread16(u16 addr, u16 *data)
260 u16 x[2] = {addr, addr + 1 };
261 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
263 EXPORT_SYMBOL(intel_scu_ipc_ioread16);
266 * intel_scu_ipc_ioread32 - read a dword via the SCU
267 * @addr: register on SCU
268 * @data: return pointer for read dword
270 * Read four registers. Returns 0 on success or an error code. All
271 * locking between SCU accesses is handled for the caller.
273 * This function may sleep.
275 int intel_scu_ipc_ioread32(u16 addr, u32 *data)
277 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
278 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
280 EXPORT_SYMBOL(intel_scu_ipc_ioread32);
283 * intel_scu_ipc_iowrite8 - write a byte via the SCU
284 * @addr: register on SCU
285 * @data: byte to write
287 * Write a single register. Returns 0 on success or an error code. All
288 * locking between SCU accesses is handled for the caller.
290 * This function may sleep.
292 int intel_scu_ipc_iowrite8(u16 addr, u8 data)
294 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
296 EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
299 * intel_scu_ipc_iowrite16 - write a word via the SCU
300 * @addr: register on SCU
301 * @data: word to write
303 * Write two registers. Returns 0 on success or an error code. All
304 * locking between SCU accesses is handled for the caller.
306 * This function may sleep.
308 int intel_scu_ipc_iowrite16(u16 addr, u16 data)
310 u16 x[2] = {addr, addr + 1 };
311 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
313 EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
316 * intel_scu_ipc_iowrite32 - write a dword via the SCU
317 * @addr: register on SCU
318 * @data: dword to write
320 * Write four registers. Returns 0 on success or an error code. All
321 * locking between SCU accesses is handled for the caller.
323 * This function may sleep.
325 int intel_scu_ipc_iowrite32(u16 addr, u32 data)
327 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
328 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
330 EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
333 * intel_scu_ipc_readvv - read a set of registers
334 * @addr: register list
335 * @data: bytes to return
336 * @len: length of array
338 * Read registers. Returns 0 on success or an error code. All
339 * locking between SCU accesses is handled for the caller.
341 * The largest array length permitted by the hardware is 5 items.
343 * This function may sleep.
345 int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
347 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
349 EXPORT_SYMBOL(intel_scu_ipc_readv);
352 * intel_scu_ipc_writev - write a set of registers
353 * @addr: register list
354 * @data: bytes to write
355 * @len: length of array
357 * Write registers. Returns 0 on success or an error code. All
358 * locking between SCU accesses is handled for the caller.
360 * The largest array length permitted by the hardware is 5 items.
362 * This function may sleep.
365 int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
367 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
369 EXPORT_SYMBOL(intel_scu_ipc_writev);
373 * intel_scu_ipc_update_register - r/m/w a register
374 * @addr: register address
375 * @bits: bits to update
376 * @mask: mask of bits to update
378 * Read-modify-write power control unit register. The first data argument
379 * must be register value and second is mask value
380 * mask is a bitmap that indicates which bits to update.
381 * 0 = masked. Don't modify this bit, 1 = modify this bit.
382 * returns 0 on success or an error code.
384 * This function may sleep. Locking between SCU accesses is handled
387 int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
389 u8 data[2] = { bits, mask };
390 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
392 EXPORT_SYMBOL(intel_scu_ipc_update_register);
395 * intel_scu_ipc_simple_command - send a simple command
399 * Issue a simple command to the SCU. Do not use this interface if
400 * you must then access data as any data values may be overwritten
401 * by another SCU access by the time this function returns.
403 * This function may sleep. Locking for SCU accesses is handled for
406 int intel_scu_ipc_simple_command(int cmd, int sub)
410 mutex_lock(&ipclock);
411 if (ipcdev.pdev == NULL) {
412 mutex_unlock(&ipclock);
415 ipc_command(sub << 12 | cmd);
417 mutex_unlock(&ipclock);
420 EXPORT_SYMBOL(intel_scu_ipc_simple_command);
423 * intel_scu_ipc_command - command with data
427 * @inlen: input length in dwords
429 * @outlein: output length in dwords
431 * Issue a command to the SCU which involves data transfers. Do the
432 * data copies under the lock but leave it for the caller to interpret
435 int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
436 u32 *out, int outlen)
441 mutex_lock(&ipclock);
442 if (ipcdev.pdev == NULL) {
443 mutex_unlock(&ipclock);
447 for (i = 0; i < inlen; i++)
448 ipc_data_writel(*in++, 4 * i);
450 ipc_command((sub << 12) | cmd | (inlen << 18));
453 for (i = 0; i < outlen; i++)
454 *out++ = ipc_data_readl(4 * i);
456 mutex_unlock(&ipclock);
459 EXPORT_SYMBOL(intel_scu_ipc_command);
462 #define IPC_I2C_WRITE 1 /* I2C Write command */
463 #define IPC_I2C_READ 2 /* I2C Read command */
466 * intel_scu_ipc_i2c_cntrl - I2C read/write operations
467 * @addr: I2C address + command bits
468 * @data: data to read/write
470 * Perform an an I2C read/write operation via the SCU. All locking is
471 * handled for the caller. This function may sleep.
473 * Returns an error code or 0 on success.
475 * This has to be in the IPC driver for the locking.
477 int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
481 mutex_lock(&ipclock);
482 if (ipcdev.pdev == NULL) {
483 mutex_unlock(&ipclock);
486 cmd = (addr >> 24) & 0xFF;
487 if (cmd == IPC_I2C_READ) {
488 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
489 /* Write not getting updated without delay */
491 *data = readl(ipcdev.i2c_base + I2C_DATA_ADDR);
492 } else if (cmd == IPC_I2C_WRITE) {
493 writel(addr, ipcdev.i2c_base + I2C_DATA_ADDR);
495 writel(addr, ipcdev.i2c_base + IPC_I2C_CNTRL_ADDR);
497 dev_err(&ipcdev.pdev->dev,
498 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
500 mutex_unlock(&ipclock);
503 mutex_unlock(&ipclock);
506 EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
508 #define IPC_FW_LOAD_ADDR 0xFFFC0000 /* Storage location for FW image */
509 #define IPC_FW_UPDATE_MBOX_ADDR 0xFFFFDFF4 /* Mailbox between ipc and scu */
510 #define IPC_MAX_FW_SIZE 262144 /* 256K storage size for loading the FW image */
511 #define IPC_FW_MIP_HEADER_SIZE 2048 /* Firmware MIP header size */
512 /* IPC inform SCU to get ready for update process */
513 #define IPC_CMD_FW_UPDATE_READY 0x10FE
514 /* IPC inform SCU to go for update process */
515 #define IPC_CMD_FW_UPDATE_GO 0x20FE
516 /* Status code for fw update */
517 #define IPC_FW_UPDATE_SUCCESS 0x444f4e45 /* Status code 'DONE' */
518 #define IPC_FW_UPDATE_BADN 0x4241444E /* Status code 'BADN' */
519 #define IPC_FW_TXHIGH 0x54784849 /* Status code 'IPC_FW_TXHIGH' */
520 #define IPC_FW_TXLOW 0x54784c4f /* Status code 'IPC_FW_TXLOW' */
522 struct fw_update_mailbox {
530 * intel_scu_ipc_fw_update - Firmware update utility
531 * @buffer: firmware buffer
532 * @length: size of firmware buffer
534 * This function provides an interface to load the firmware into
535 * the SCU. Returns 0 on success or -1 on failure
537 int intel_scu_ipc_fw_update(u8 *buffer, u32 length)
539 void __iomem *fw_update_base;
540 struct fw_update_mailbox __iomem *mailbox = NULL;
544 mutex_lock(&ipclock);
545 fw_update_base = ioremap_nocache(IPC_FW_LOAD_ADDR, (128*1024));
546 if (fw_update_base == NULL) {
547 mutex_unlock(&ipclock);
550 mailbox = ioremap_nocache(IPC_FW_UPDATE_MBOX_ADDR,
551 sizeof(struct fw_update_mailbox));
552 if (mailbox == NULL) {
553 iounmap(fw_update_base);
554 mutex_unlock(&ipclock);
558 ipc_command(IPC_CMD_FW_UPDATE_READY);
560 /* Intitialize mailbox */
561 writel(0, &mailbox->status);
562 writel(0, &mailbox->scu_flag);
563 writel(0, &mailbox->driver_flag);
565 /* Driver copies the 2KB MIP header to SRAM at 0xFFFC0000*/
566 memcpy_toio(fw_update_base, buffer, 0x800);
568 /* Driver sends "FW Update" IPC command (CMD_ID 0xFE; MSG_ID 0x02).
569 * Upon receiving this command, SCU will write the 2K MIP header
570 * from 0xFFFC0000 into NAND.
571 * SCU will write a status code into the Mailbox, and then set scu_flag.
574 ipc_command(IPC_CMD_FW_UPDATE_GO);
576 /*Driver stalls until scu_flag is set */
577 while (readl(&mailbox->scu_flag) != 1) {
582 /* Driver checks Mailbox status.
583 * If the status is 'BADN', then abort (bad NAND).
584 * If the status is 'IPC_FW_TXLOW', then continue.
586 while (readl(&mailbox->status) != IPC_FW_TXLOW) {
596 if (readl(&mailbox->status) != IPC_FW_TXLOW)
598 buffer = buffer + 0x800;
599 memcpy_toio(fw_update_base, buffer, 0x20000);
600 writel(1, &mailbox->driver_flag);
601 while (readl(&mailbox->scu_flag) == 1) {
606 /* check for 'BADN' */
607 if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN)
610 while (readl(&mailbox->status) != IPC_FW_TXHIGH) {
616 if (readl(&mailbox->status) != IPC_FW_TXHIGH)
619 buffer = buffer + 0x20000;
620 memcpy_toio(fw_update_base, buffer, 0x20000);
621 writel(0, &mailbox->driver_flag);
623 while (mailbox->scu_flag == 0) {
628 /* check for 'BADN' */
629 if (readl(&mailbox->status) == IPC_FW_UPDATE_BADN)
632 if (readl(&mailbox->status) == IPC_FW_TXLOW) {
638 status = readl(&mailbox->status);
640 iounmap(fw_update_base);
642 mutex_unlock(&ipclock);
644 if (status == IPC_FW_UPDATE_SUCCESS)
648 EXPORT_SYMBOL(intel_scu_ipc_fw_update);
651 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
652 * When ioc bit is set to 1, caller api must wait for interrupt handler called
653 * which in turn unlocks the caller api. Currently this is not used
655 * This is edge triggered so we need take no action to clear anything
657 static irqreturn_t ioc(int irq, void *dev_id)
663 * ipc_probe - probe an Intel SCU IPC
664 * @dev: the PCI device matching
665 * @id: entry in the match table
667 * Enable and install an intel SCU IPC. This appears in the PCI space
668 * but uses some hard coded addresses as well.
670 static int ipc_probe(struct pci_dev *dev, const struct pci_device_id *id)
673 resource_size_t pci_resource;
675 if (ipcdev.pdev) /* We support only one SCU */
678 ipcdev.pdev = pci_dev_get(dev);
680 err = pci_enable_device(dev);
684 err = pci_request_regions(dev, "intel_scu_ipc");
688 pci_resource = pci_resource_start(dev, 0);
692 if (request_irq(dev->irq, ioc, 0, "intel_scu_ipc", &ipcdev))
695 ipcdev.ipc_base = ioremap_nocache(IPC_BASE_ADDR, IPC_MAX_ADDR);
696 if (!ipcdev.ipc_base)
699 ipcdev.i2c_base = ioremap_nocache(IPC_I2C_BASE, IPC_I2C_MAX_ADDR);
700 if (!ipcdev.i2c_base) {
701 iounmap(ipcdev.ipc_base);
708 * ipc_remove - remove a bound IPC device
711 * In practice the SCU is not removable but this function is also
712 * called for each device on a module unload or cleanup which is the
713 * path that will get used.
715 * Free up the mappings and release the PCI resources
717 static void ipc_remove(struct pci_dev *pdev)
719 free_irq(pdev->irq, &ipcdev);
720 pci_release_regions(pdev);
721 pci_dev_put(ipcdev.pdev);
722 iounmap(ipcdev.ipc_base);
723 iounmap(ipcdev.i2c_base);
727 static const struct pci_device_id pci_ids[] = {
728 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080e)},
729 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x082a)},
732 MODULE_DEVICE_TABLE(pci, pci_ids);
734 static struct pci_driver ipc_driver = {
735 .name = "intel_scu_ipc",
738 .remove = ipc_remove,
742 static int __init intel_scu_ipc_init(void)
744 if (boot_cpu_data.x86 == 6 &&
745 boot_cpu_data.x86_model == 0x27 &&
746 boot_cpu_data.x86_mask == 1)
747 platform = PLATFORM_PENWELL;
748 else if (boot_cpu_data.x86 == 6 &&
749 boot_cpu_data.x86_model == 0x26)
750 platform = PLATFORM_LANGWELL;
752 return pci_register_driver(&ipc_driver);
755 static void __exit intel_scu_ipc_exit(void)
757 pci_unregister_driver(&ipc_driver);
760 MODULE_AUTHOR("Sreedhara DS <sreedhara.ds@intel.com>");
761 MODULE_DESCRIPTION("Intel SCU IPC driver");
762 MODULE_LICENSE("GPL");
764 module_init(intel_scu_ipc_init);
765 module_exit(intel_scu_ipc_exit);