5 #include <linux/ioport.h>
6 #include <linux/kernel.h>
7 #include <linux/math64.h>
8 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/pwm.h>
12 #include <linux/slab.h>
13 #include <linux/types.h>
14 #include <linux/spinlock.h>
15 #include <linux/of_device.h>
16 #include <linux/of_address.h>
17 #include <linux/rockchip/grf.h>
18 #include <linux/rockchip/iomap.h>
21 static int pwm_dbg_level = 0;
22 module_param_named(dbg_level, pwm_dbg_level, int, 0644);
23 #define DBG( args...) \
25 if (pwm_dbg_level) { \
34 #define PWM_REG_CNTR 0x00
35 #define PWM_REG_HRC 0x04
36 #define PWM_REG_LRC 0x08
37 #define PWM_REG_CTRL 0x0c /* PWM Control Register */
39 #define PWM_REG_PERIOD PWM_REG_HRC /* Period Register */
40 #define PWM_REG_DUTY PWM_REG_LRC /* Duty Cycle Register */
42 #define VOP_REG_CNTR 0x0C
43 #define VOP_REG_CTRL 0x00 /* VOP-PWM Control Register */
45 //#define PWM_REG_CTRL 0x0c /* Control Register */
47 #define PWM_DIV_MASK (0xf << 9)
48 #define PWM_CAPTURE (1 << 8)
49 #define PWM_RESET (1 << 7)
50 #define PWM_INTCLR (1 << 6)
51 #define PWM_INTEN (1 << 5)
52 #define PWM_SINGLE (1 << 4)
54 #define PWM_ENABLE (1 << 3)
55 #define PWM_TIMER_EN (1 << 0)
57 #define RK_PWM_DISABLE (0 << 0)
58 #define RK_PWM_ENABLE (1 << 0)
60 #define PWM_SHOT (0 << 1)
61 #define PWM_CONTINUMOUS (1 << 1)
62 #define RK_PWM_CAPTURE (1 << 2)
64 #define PWM_DUTY_POSTIVE (1 << 3)
65 #define PWM_DUTY_NEGATIVE (0 << 3)
67 #define PWM_INACTIVE_POSTIVE (1 << 4)
68 #define PWM_INACTIVE_NEGATIVE (0 << 4)
70 #define PWM_OUTPUT_LEFT (0 << 5)
71 #define PWM_OUTPUT_ENTER (1 << 5)
73 #define PWM_LP_ENABLE (1<<8)
74 #define PWM_LP_DISABLE (0<<8)
76 #define DW_PWM_PRESCALE 9
77 #define RK_PWM_PRESCALE 16
79 #define PWMCR_MIN_PRESCALE 0x00
81 #define PWMCR_MIN_PRESCALE 0x00
82 #define PWMCR_MAX_PRESCALE 0x07
84 #define PWMDCR_MIN_DUTY 0x0001
85 #define PWMDCR_MAX_DUTY 0xFFFF
87 #define PWMPCR_MIN_PERIOD 0x0001
88 #define PWMPCR_MAX_PERIOD 0xFFFF
90 static spinlock_t pwm_lock[4] = {
91 __SPIN_LOCK_UNLOCKED(pwm_lock0),
92 __SPIN_LOCK_UNLOCKED(pwm_lock1),
93 __SPIN_LOCK_UNLOCKED(pwm_lock2),
94 __SPIN_LOCK_UNLOCKED(pwm_lock3),
98 /********************************************
99 * struct rk_pwm_chip - struct representing pwm chip
101 * @base: base address of pwm chip
102 * @clk: pointer to clk structure of pwm chip
103 * @chip: linux pwm chip representation
104 *********************************************/
108 struct pwm_chip chip;
115 int (*config)(struct pwm_chip *chip,
116 struct pwm_device *pwm, int duty_ns, int period_ns);
117 void (*set_enable)(struct pwm_chip *chip, struct pwm_device *pwm,bool enable);
118 void (*pwm_suspend)(struct pwm_chip *chip, struct pwm_device *pwm);
119 void (*pwm_resume)(struct pwm_chip *chip, struct pwm_device *pwm);
123 static inline struct rk_pwm_chip *to_rk_pwm_chip(struct pwm_chip *chip)
125 return container_of(chip, struct rk_pwm_chip, chip);
128 static inline u32 rk_pwm_readl(struct rk_pwm_chip *chip, unsigned int num,
129 unsigned long offset)
131 return readl_relaxed(chip->base + (num << 4) + offset);
134 static inline void rk_pwm_writel(struct rk_pwm_chip *chip,
135 unsigned int num, unsigned long offset,
138 writel_relaxed(val, chip->base + (num << 4) + offset);
141 /* config for rockchip,pwm*/
142 static int rk_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm,
143 int duty_ns, int period_ns)
145 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
146 u64 val, div, clk_rate;
147 unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
154 lock =(&pc->lock);// &pwm_lock[pwm->hwpwm];
156 on = PWM_ENABLE | PWM_TIMER_EN;
158 * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
159 * according to formulas described below:
161 * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
162 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
164 * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
165 * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
168 clk_rate = clk_get_rate(pc->clk);
175 val = clk_rate * period_ns;
176 pv = div64_u64(val, div);
177 val = clk_rate * duty_ns;
178 dc = div64_u64(val, div);
180 /* if duty_ns and period_ns are not achievable then return */
181 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
185 * if pv and dc have crossed their upper limit, then increase
186 * prescale and recalculate pv and dc.
188 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
189 if (++prescale > PWMCR_MAX_PRESCALE)
196 /* NOTE: the clock to PWM has to be enabled first before writing to the registers. */
198 spin_lock_irqsave(lock, flags);
200 conf |= (prescale << DW_PWM_PRESCALE);
202 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
204 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_HRC,dc);//0x1900);// dc);
205 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_LRC, pv);//0x5dc0);//pv);
206 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,0);
208 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,on|conf);
210 spin_unlock_irqrestore(lock, flags);
213 static void rk_pwm_set_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm, bool enable)
215 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
218 val = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
224 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL, val);
227 static void rk_pwm_suspend_v1(struct pwm_chip *chip, struct pwm_device *pwm)
229 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
230 pc->pwm_ctrl = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
231 pc->pwm_duty= rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_HRC);//0x1900);// dc);
232 pc->pwm_period = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_LRC );//0x5dc0);//pv);
233 pc->pwm_count= rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CNTR);
235 static void rk_pwm_resume_v1(struct pwm_chip *chip, struct pwm_device *pwm)
237 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
240 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
242 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_HRC,pc->pwm_duty);//0x1900);// dc);
243 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_LRC, pc->pwm_period);//0x5dc0);//pv);
244 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,pc->pwm_count);
246 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,pc->pwm_ctrl);
248 /* config for rockchip,pwm*/
249 static int rk_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
250 int duty_ns, int period_ns)
252 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
253 u64 val, div, clk_rate;
254 unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
261 lock = (&pc->lock);//&pwm_lock[pwm->hwpwm];
263 conf = PWM_OUTPUT_LEFT|PWM_LP_DISABLE|
264 PWM_CONTINUMOUS|PWM_DUTY_POSTIVE|PWM_INACTIVE_NEGATIVE;
266 * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
267 * according to formulas described below:
269 * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
270 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
272 * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
273 * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
276 clk_rate = clk_get_rate(pc->clk);
283 val = clk_rate * period_ns;
284 pv = div64_u64(val, div);
285 val = clk_rate * duty_ns;
286 dc = div64_u64(val, div);
288 /* if duty_ns and period_ns are not achievable then return */
289 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
293 * if pv and dc have crossed their upper limit, then increase
294 * prescale and recalculate pv and dc.
296 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
297 if (++prescale > PWMCR_MAX_PRESCALE)
305 * NOTE: the clock to PWM has to be enabled first before writing to the
308 spin_lock_irqsave(lock, flags);
310 conf |= (prescale << RK_PWM_PRESCALE);
312 //rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
314 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY,dc);//0x1900);// dc);
315 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD,pv);//0x5dc0);//pv);
316 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,0);
318 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,on|conf);
319 spin_unlock_irqrestore(lock, flags);
324 static void rk_pwm_set_enable_v2(struct pwm_chip *chip, struct pwm_device *pwm,bool enable)
326 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
329 val = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
331 val |= RK_PWM_ENABLE;
333 val &= ~RK_PWM_ENABLE;
334 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL, val);
335 DBG("%s %d \n", __FUNCTION__, rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL));
340 static void rk_pwm_suspend_v2(struct pwm_chip *chip, struct pwm_device *pwm)
342 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
343 pc->pwm_ctrl = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
344 pc->pwm_duty = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_DUTY);//0x1900);// dc);
345 pc->pwm_period = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_PERIOD );//0x5dc0);//pv);
346 pc->pwm_count = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CNTR);
348 static void rk_pwm_resume_v2(struct pwm_chip *chip, struct pwm_device *pwm)
350 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
352 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY, pc->pwm_duty);//0x1900);// dc);
353 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD, pc->pwm_period);//0x5dc0);//pv);
354 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,pc->pwm_count);
356 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,pc->pwm_ctrl);
359 /* config for rockchip,pwm*/
360 static int rk_pwm_config_v3(struct pwm_chip *chip, struct pwm_device *pwm,
361 int duty_ns, int period_ns)
363 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
364 u64 val, div, clk_rate;
365 unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
372 lock = (&pc->lock);//&pwm_lock[pwm->hwpwm];
374 conf = PWM_OUTPUT_LEFT|PWM_LP_DISABLE|
375 PWM_CONTINUMOUS|PWM_DUTY_POSTIVE|PWM_INACTIVE_NEGATIVE;
377 * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
378 * according to formulas described below:
380 * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
381 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
383 * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
384 * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
387 clk_rate = clk_get_rate(pc->clk);
394 val = clk_rate * period_ns;
395 pv = div64_u64(val, div);
396 val = clk_rate * duty_ns;
397 dc = div64_u64(val, div);
399 /* if duty_ns and period_ns are not achievable then return */
400 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
404 * if pv and dc have crossed their upper limit, then increase
405 * prescale and recalculate pv and dc.
407 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
408 if (++prescale > PWMCR_MAX_PRESCALE)
416 * NOTE: the clock to PWM has to be enabled first before writing to the
420 ret = clk_enable(pc->clk);
424 spin_lock_irqsave(lock, flags);
426 conf |= (prescale << RK_PWM_PRESCALE);
429 // rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL,off);
432 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY,dc); // 2 0x1900);// dc);
433 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD,pv); // 4 0x5dc0);//pv);
434 rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CNTR,0);
436 rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL,on|conf);
438 spin_unlock_irqrestore(lock, flags);
442 static void rk_pwm_set_enable_v3(struct pwm_chip *chip, struct pwm_device *pwm,bool enable)
444 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
447 val = rk_pwm_readl(pc, pwm->hwpwm, VOP_REG_CTRL);
449 val |= RK_PWM_ENABLE;
451 val &= ~RK_PWM_ENABLE;
452 rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL, val);
455 static void rk_pwm_suspend_v3(struct pwm_chip *chip, struct pwm_device *pwm)
457 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
458 pc->pwm_ctrl = rk_pwm_readl(pc, pwm->hwpwm, VOP_REG_CTRL);
459 pc->pwm_duty = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_DUTY);//0x1900);// dc);
460 pc->pwm_period = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_PERIOD );//0x5dc0);//pv);
461 pc->pwm_count = rk_pwm_readl(pc, pwm->hwpwm, VOP_REG_CNTR);
463 static void rk_pwm_resume_v3(struct pwm_chip *chip, struct pwm_device *pwm)
465 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
467 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY, pc->pwm_duty);//0x1900);// dc);
468 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD, pc->pwm_period);//0x5dc0);//pv);
469 rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CNTR,pc->pwm_count);
471 rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL,pc->pwm_ctrl);
475 static int rk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
476 int duty_ns, int period_ns)
478 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
481 ret = clk_prepare_enable(pc->clk);
485 ret = pc->config(chip, pwm, duty_ns, period_ns);
487 clk_disable_unprepare(pc->clk);
491 static int rk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
493 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
496 ret = clk_prepare_enable(pc->clk);
500 pc->set_enable(chip, pwm,true);
504 static void rk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
506 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
508 pc->set_enable(chip, pwm,false);
510 clk_disable_unprepare(pc->clk);
514 static const struct pwm_ops rk_pwm_ops = {
515 .config = rk_pwm_config,
516 .enable = rk_pwm_enable,
517 .disable = rk_pwm_disable,
518 .owner = THIS_MODULE,
522 int (*config)(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns);
523 void (*set_enable)(struct pwm_chip *chip, struct pwm_device *pwm,bool enable);
524 void (*pwm_suspend)(struct pwm_chip *chip, struct pwm_device *pwm);
525 void (*pwm_resume)(struct pwm_chip *chip, struct pwm_device *pwm);
530 static struct rk_pwm_data rk_pwm_data_v1={
531 .config = rk_pwm_config_v1,
532 .set_enable = rk_pwm_set_enable_v1,
533 .pwm_suspend = rk_pwm_suspend_v1,
534 .pwm_resume = rk_pwm_resume_v1,
538 static struct rk_pwm_data rk_pwm_data_v2={
539 .config = rk_pwm_config_v2,
540 .set_enable = rk_pwm_set_enable_v2,
541 .pwm_suspend = rk_pwm_suspend_v2,
542 .pwm_resume = rk_pwm_resume_v2,
546 static struct rk_pwm_data rk_pwm_data_v3={
547 .config = rk_pwm_config_v3,
548 .set_enable = rk_pwm_set_enable_v3,
549 .pwm_suspend = rk_pwm_suspend_v3,
550 .pwm_resume = rk_pwm_resume_v3,
554 static const struct of_device_id rk_pwm_of_match[] = {
555 { .compatible = "rockchip,pwm", .data = &rk_pwm_data_v1,},
556 { .compatible = "rockchip,rk-pwm", .data = &rk_pwm_data_v2,},
557 { .compatible = "rockchip,vop-pwm", .data = &rk_pwm_data_v3,},
561 MODULE_DEVICE_TABLE(of, rk_pwm_of_match);
562 static int rk_pwm_probe(struct platform_device *pdev)
564 const struct of_device_id *of_id =
565 of_match_device(rk_pwm_of_match, &pdev->dev);
566 struct device_node *np = pdev->dev.of_node;
567 const struct rk_pwm_data *data;
568 struct rk_pwm_chip *pc;
572 dev_err(&pdev->dev, "failed to match device\n");
575 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
577 dev_err(&pdev->dev, "failed to allocate memory\n");
581 pc->base = of_iomap(np, 0);
582 if (IS_ERR(pc->base)){
583 printk("PWM base ERR \n");
584 return PTR_ERR(pc->base);
586 pc->clk = devm_clk_get(&pdev->dev,"pclk_pwm");
588 return PTR_ERR(pc->clk);
590 platform_set_drvdata(pdev, pc);
592 pc->config = data->config;
593 pc->set_enable = data->set_enable;
594 pc->pwm_suspend = data->pwm_suspend;
595 pc->pwm_resume = data->pwm_resume;
596 pc->chip.dev = &pdev->dev;
597 pc->chip.ops = &rk_pwm_ops;
599 pc->chip.npwm = NUM_PWM;
600 pc->lock = __SPIN_LOCK_UNLOCKED(PWM##spinlock_num);
603 /* Following enables PWM chip, channels would still be enabled individually through their control register */
604 DBG("npwm = %d, of_pwm_ncells =%d \n", pc->chip.npwm,pc->chip.of_pwm_n_cells);
605 ret = pwmchip_add(&pc->chip);
607 printk("failed to add pwm\n");
611 DBG("%s end \n",__FUNCTION__);
615 //(struct platform_device *, pm_message_t state);
616 static int rk_pwm_suspend(struct platform_device *pdev, pm_message_t state)
618 struct pwm_device *pwm;
619 struct rk_pwm_chip *pc;
620 struct pwm_chip *chip;
622 pc = platform_get_drvdata(pdev);
626 pc->pwm_suspend(chip,pwm);
628 return 0;//pwmchip_remove(&pc->chip);
630 static int rk_pwm_resume(struct platform_device *pdev)
632 struct pwm_device *pwm;
633 struct rk_pwm_chip *pc;
634 struct pwm_chip *chip;
636 pc = platform_get_drvdata(pdev);
640 pc->pwm_resume(chip,pwm);
641 return 0;//pwmchip_remove(&pc->chip);
644 static int rk_pwm_remove(struct platform_device *pdev)
646 return 0;//pwmchip_remove(&pc->chip);
649 static struct platform_driver rk_pwm_driver = {
652 .of_match_table = rk_pwm_of_match,
654 .probe = rk_pwm_probe,
655 .remove = rk_pwm_remove,
658 module_platform_driver(rk_pwm_driver);
660 MODULE_LICENSE("GPL");
661 MODULE_AUTHOR("<xsf@rock-chips.com>");
662 MODULE_ALIAS("platform:rk-pwm");