2 * PWM driver for Rockchip SoCs
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 * Copyright (C) 2014 ROCKCHIP, Inc.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
12 #include <linux/clk.h>
14 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/pwm.h>
19 #include <linux/time.h>
20 #include <linux/rk_fb.h>
22 #define PWM_CTRL_TIMER_EN (1 << 0)
23 #define PWM_CTRL_OUTPUT_EN (1 << 3)
25 #define PWM_ENABLE (1 << 0)
26 #define PWM_CONTINUOUS (1 << 1)
27 #define PWM_DUTY_POSITIVE (1 << 3)
28 #define PWM_DUTY_NEGATIVE (0 << 3)
29 #define PWM_INACTIVE_NEGATIVE (0 << 4)
30 #define PWM_INACTIVE_POSITIVE (1 << 4)
31 #define PWM_OUTPUT_LEFT (0 << 5)
32 #define PWM_LP_DISABLE (0 << 8)
34 struct rockchip_pwm_chip {
38 const struct rockchip_pwm_data *data;
42 struct rockchip_pwm_regs {
49 struct rockchip_pwm_data {
50 struct rockchip_pwm_regs regs;
51 unsigned int prescaler;
52 const struct pwm_ops *ops;
54 void (*set_enable)(struct pwm_chip *chip,
55 struct pwm_device *pwm, bool enable);
58 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
60 return container_of(c, struct rockchip_pwm_chip, chip);
63 static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip,
64 struct pwm_device *pwm, bool enable)
66 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
67 u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN;
70 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
77 writel_relaxed(val, pc->base + pc->data->regs.ctrl);
80 static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip,
81 struct pwm_device *pwm, bool enable)
83 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
84 u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
88 if (pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED)
89 enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
91 enable_conf |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
93 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
94 val &= ~(GENMASK(5, 0) | BIT(8));
101 writel_relaxed(val, pc->base + pc->data->regs.ctrl);
104 static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
105 int duty_ns, int period_ns)
107 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
108 unsigned long period, duty;
112 clk_rate = clk_get_rate(pc->clk);
115 * Since period and duty cycle registers have a width of 32
116 * bits, every possible input period can be obtained using the
117 * default prescaler value for all practical clock rate values.
119 div = clk_rate * period_ns;
120 do_div(div, pc->data->prescaler * NSEC_PER_SEC);
123 div = clk_rate * duty_ns;
124 do_div(div, pc->data->prescaler * NSEC_PER_SEC);
127 ret = clk_enable(pc->pclk);
131 writel(period, pc->base + pc->data->regs.period);
132 writel(duty, pc->base + pc->data->regs.duty);
133 writel(0, pc->base + pc->data->regs.cntr);
135 clk_disable(pc->pclk);
137 #ifdef CONFIG_FB_ROCKCHIP
138 if (!pc->data->regs.ctrl) {
139 ret = rk_fb_set_vop_pwm();
141 dev_err(pc->chip.dev, "rk_fb_set_vop_pwm failed: %d\n", ret);
148 static int rockchip_pwm_set_polarity(struct pwm_chip *chip,
149 struct pwm_device *pwm,
150 enum pwm_polarity polarity)
153 * No action needed here because pwm->polarity will be set by the core
154 * and the core will only change polarity when the PWM is not enabled.
155 * We'll handle things in set_enable().
161 static int rockchip_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
163 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
166 ret = clk_enable(pc->clk);
169 ret = clk_enable(pc->pclk);
173 pc->data->set_enable(chip, pwm, true);
178 static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
180 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
182 pc->data->set_enable(chip, pwm, false);
184 clk_disable(pc->pclk);
185 clk_disable(pc->clk);
188 static const struct pwm_ops rockchip_pwm_ops_v1 = {
189 .config = rockchip_pwm_config,
190 .enable = rockchip_pwm_enable,
191 .disable = rockchip_pwm_disable,
192 .owner = THIS_MODULE,
195 static const struct pwm_ops rockchip_pwm_ops_v2 = {
196 .config = rockchip_pwm_config,
197 .set_polarity = rockchip_pwm_set_polarity,
198 .enable = rockchip_pwm_enable,
199 .disable = rockchip_pwm_disable,
200 .owner = THIS_MODULE,
203 static const struct rockchip_pwm_data pwm_data_v1 = {
211 .ops = &rockchip_pwm_ops_v1,
212 .set_enable = rockchip_pwm_set_enable_v1,
215 static const struct rockchip_pwm_data pwm_data_v2 = {
223 .ops = &rockchip_pwm_ops_v2,
224 .set_enable = rockchip_pwm_set_enable_v2,
227 static const struct rockchip_pwm_data pwm_data_vop = {
235 .ops = &rockchip_pwm_ops_v2,
236 .set_enable = rockchip_pwm_set_enable_v2,
239 static const struct of_device_id rockchip_pwm_dt_ids[] = {
240 { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
241 { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
242 { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
243 { .compatible = "rockchip,rk3399-pwm", .data = &pwm_data_v2},
246 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
248 static int rockchip_pwm_probe(struct platform_device *pdev)
250 const struct of_device_id *id;
251 struct rockchip_pwm_chip *pc;
255 id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
259 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
263 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
264 pc->base = devm_ioremap(&pdev->dev, r->start,
266 if (IS_ERR(pc->base))
267 return PTR_ERR(pc->base);
269 pc->clk = devm_clk_get(&pdev->dev, "pwm");
270 count = of_property_count_strings(pdev->dev.of_node, "clock-names");
272 pc->pclk = devm_clk_get(&pdev->dev, "pclk");
276 if (IS_ERR(pc->clk)) {
277 ret = PTR_ERR(pc->clk);
278 if (ret != -EPROBE_DEFER)
279 dev_err(&pdev->dev, "Can't get pwm clk: %d\n", ret);
283 if (IS_ERR(pc->pclk)) {
284 ret = PTR_ERR(pc->pclk);
285 if (ret != -EPROBE_DEFER)
286 dev_err(&pdev->dev, "Can't get pclk: %d\n", ret);
290 ret = clk_prepare(pc->clk);
292 dev_err(&pdev->dev, "Can't prepare pwm clk: %d\n", ret);
296 ret = clk_prepare(pc->pclk);
298 dev_err(&pdev->dev, "Can't prepare pclk: %d\n", ret);
302 platform_set_drvdata(pdev, pc);
305 pc->chip.dev = &pdev->dev;
306 pc->chip.ops = pc->data->ops;
310 if (pc->data->ops->set_polarity) {
311 pc->chip.of_xlate = of_pwm_xlate_with_flags;
312 pc->chip.of_pwm_n_cells = 3;
315 ret = pwmchip_add(&pc->chip);
317 clk_unprepare(pc->clk);
318 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
325 clk_unprepare(pc->pclk);
327 clk_unprepare(pc->clk);
332 static int rockchip_pwm_remove(struct platform_device *pdev)
334 struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
336 clk_unprepare(pc->pclk);
337 clk_unprepare(pc->clk);
339 return pwmchip_remove(&pc->chip);
342 static struct platform_driver rockchip_pwm_driver = {
344 .name = "rockchip-pwm",
345 .of_match_table = rockchip_pwm_dt_ids,
347 .probe = rockchip_pwm_probe,
348 .remove = rockchip_pwm_remove,
350 module_platform_driver(rockchip_pwm_driver);
352 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
353 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
354 MODULE_LICENSE("GPL v2");