drivers/pwm/pwm-rockchip.c

   1
   2 #include <linux/clk.h>
   3 #include <linux/err.h>
   4 #include <linux/io.h>
   5 #include <linux/ioport.h>
   6 #include <linux/kernel.h>
   7 #include <linux/math64.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/pwm.h>
  12 #include <linux/slab.h>
  13 #include <linux/types.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/rockchip/grf.h>
  18 #include <linux/rockchip/iomap.h>
  19
  20
  21 static int pwm_dbg_level = 0;
  22 module_param_named(dbg_level, pwm_dbg_level, int, 0644);
  23 #define DBG( args...) \
  24         do { \
  25                 if (pwm_dbg_level) { \
  26                         pr_info(args); \
  27                 } \
  28         } while (0)
  29
  30 #define PWM_CLK                                 1
  31 #define NUM_PWM                           1
  32
  33 /* PWM registers  */
  34 #define PWM_REG_CNTR                            0x00
  35 #define PWM_REG_HRC                             0x04
  36 #define PWM_REG_LRC                             0x08
  37 #define PWM_REG_CTRL                                    0x0c  /* PWM Control Register */
  38
  39 #define PWM_REG_PERIOD                          PWM_REG_HRC  /* Period Register */
  40 #define PWM_REG_DUTY                            PWM_REG_LRC  /* Duty Cycle Register */
  41
  42 #define VOP_REG_CNTR                            0x0C
  43 #define VOP_REG_CTRL                                    0x00  /* VOP-PWM Control Register */
  44
  45 //#define PWM_REG_CTRL                   0x0c /* Control Register */
  46
  47 #define PWM_DIV_MASK                            (0xf << 9)
  48 #define PWM_CAPTURE                                     (1 << 8)
  49 #define PWM_RESET                               (1 << 7)
  50 #define PWM_INTCLR                                      (1 << 6)
  51 #define PWM_INTEN                                       (1 << 5)
  52 #define PWM_SINGLE                                      (1 << 4)
  53
  54 #define PWM_ENABLE                                      (1 << 3)
  55 #define PWM_TIMER_EN                                    (1 << 0)
  56
  57 #define RK_PWM_DISABLE                     (0 << 0)
  58 #define RK_PWM_ENABLE                       (1 << 0)
  59
  60 #define PWM_SHOT                                 (0 << 1)
  61 #define PWM_CONTINUMOUS                 (1 << 1)
  62 #define RK_PWM_CAPTURE                    (1 << 2)
  63
  64 #define PWM_DUTY_POSTIVE                (1 << 3)
  65 #define PWM_DUTY_NEGATIVE              (0 << 3)
  66
  67 #define PWM_INACTIVE_POSTIVE         (1 << 4)
  68 #define PWM_INACTIVE_NEGATIVE       (0 << 4)
  69
  70 #define PWM_OUTPUT_LEFT                 (0 << 5)
  71 #define PWM_OUTPUT_ENTER               (1 << 5)
  72
  73 #define PWM_LP_ENABLE                     (1<<8)
  74 #define PWM_LP_DISABLE                    (0<<8)
  75
  76 #define DW_PWM_PRESCALE         9
  77 #define RK_PWM_PRESCALE         16
  78
  79 #define PWMCR_MIN_PRESCALE      0x00
  80
  81 #define PWMCR_MIN_PRESCALE      0x00
  82 #define PWMCR_MAX_PRESCALE      0x07
  83
  84 #define PWMDCR_MIN_DUTY         0x0000
  85 #define PWMDCR_MAX_DUTY         0xFFFF
  86
  87 #define PWMPCR_MIN_PERIOD               0x0001
  88 #define PWMPCR_MAX_PERIOD               0xFFFF
  89
  90 /********************************************
  91  * struct rk_pwm_chip - struct representing pwm chip
  92
  93  * @base: base address of pwm chip
  94  * @clk: pointer to clk structure of pwm chip
  95  * @chip: linux pwm chip representation
  96  *********************************************/
  97  struct rk_pwm_chip {
  98         void __iomem *base;
  99         struct clk *clk;
 100         struct pwm_chip chip;
 101         unsigned int pwm_id;
 102         spinlock_t              lock;
 103         int                             pwm_ctrl;
 104         int                             pwm_duty;
 105         int                             pwm_period;
 106         int                             pwm_count;
 107         int (*config)(struct pwm_chip *chip,
 108                 struct pwm_device *pwm, int duty_ns, int period_ns);
 109         void (*set_enable)(struct pwm_chip *chip, struct pwm_device *pwm,bool enable);
 110         void (*pwm_suspend)(struct pwm_chip *chip, struct pwm_device *pwm);
 111         void (*pwm_resume)(struct pwm_chip *chip, struct pwm_device *pwm);
 112
 113 };
 114
 115 static inline struct rk_pwm_chip *to_rk_pwm_chip(struct pwm_chip *chip)
 116 {
 117         return container_of(chip, struct rk_pwm_chip, chip);
 118 }
 119
 120 static inline u32 rk_pwm_readl(struct rk_pwm_chip *chip, unsigned int num,
 121                                   unsigned long offset)
 122 {
 123         return readl_relaxed(chip->base + (num << 4) + offset);
 124 }
 125
 126 static inline void rk_pwm_writel(struct rk_pwm_chip *chip,
 127                                     unsigned int num, unsigned long offset,
 128                                     unsigned long val)
 129 {
 130         writel_relaxed(val, chip->base + (num << 4) + offset);
 131 }
 132
 133 /* config for rockchip,pwm*/
 134 static int  rk_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm,
 135                             int duty_ns, int period_ns)
 136 {
 137         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 138         u64 val, div, clk_rate;
 139         unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
 140         u32 off, on;
 141         int conf=0;
 142        unsigned long flags;
 143        spinlock_t *lock;
 144
 145        lock =(&pc->lock);// &pwm_lock[pwm->hwpwm];
 146         off =  PWM_RESET;
 147         on =  PWM_ENABLE | PWM_TIMER_EN;
 148         /*
 149          * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
 150          * according to formulas described below:
 151          *
 152          * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
 153          * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
 154          *
 155          * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
 156          * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
 157          */
 158 #if PWM_CLK
 159         clk_rate = clk_get_rate(pc->clk);
 160 #else
 161         clk_rate = 24000000;
 162 #endif
 163         while (1) {
 164                 div = 1000000000;
 165                 div *= 1 + prescale;
 166                 val = clk_rate * period_ns;
 167                 pv = div64_u64(val, div);
 168                 val = clk_rate * duty_ns;
 169                 dc = div64_u64(val, div);
 170
 171                 /* if duty_ns and period_ns are not achievable then return */
 172                 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
 173                         return -EINVAL;
 174
 175                 /*
 176                  * if pv and dc have crossed their upper limit, then increase
 177                  * prescale and recalculate pv and dc.
 178                  */
 179                 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
 180                         if (++prescale > PWMCR_MAX_PRESCALE)
 181                                 return -EINVAL;
 182                         continue;
 183                 }
 184                 break;
 185         }
 186
 187         /* NOTE: the clock to PWM has to be enabled first before writing to the registers. */
 188
 189         spin_lock_irqsave(lock, flags);
 190
 191         conf |= (prescale << DW_PWM_PRESCALE);
 192         barrier();
 193         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
 194         dsb();
 195         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_HRC,dc);//0x1900);// dc);
 196         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_LRC, pv);//0x5dc0);//pv);
 197         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,0);
 198         dsb();
 199         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,on|conf);
 200
 201        spin_unlock_irqrestore(lock, flags);
 202         return 0;
 203 }
 204 static void rk_pwm_set_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm, bool enable)
 205 {
 206         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 207         u32 val;
 208
 209         val = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
 210         if (enable)
 211                 val |= PWM_ENABLE;
 212         else
 213                 val &= ~PWM_ENABLE;
 214
 215         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL, val);
 216
 217 }
 218 static void rk_pwm_suspend_v1(struct pwm_chip *chip, struct pwm_device *pwm)
 219 {
 220         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 221         pc->pwm_ctrl = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
 222         pc->pwm_duty=  rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_HRC);//0x1900);// dc);
 223         pc->pwm_period = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_LRC );//0x5dc0);//pv);
 224         pc->pwm_count=  rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CNTR);
 225 }
 226 static void rk_pwm_resume_v1(struct pwm_chip *chip, struct pwm_device *pwm)
 227 {
 228         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 229         int     off =  PWM_RESET;
 230
 231         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
 232         dsb();
 233         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_HRC,pc->pwm_duty);//0x1900);// dc);
 234         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_LRC, pc->pwm_period);//0x5dc0);//pv);
 235         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,pc->pwm_count);
 236         dsb();
 237         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,pc->pwm_ctrl);
 238 }
 239 /* config for rockchip,pwm*/
 240 static int  rk_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
 241                             int duty_ns, int period_ns)
 242 {
 243         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 244         u64 val, div, clk_rate;
 245         unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
 246         u32  on;
 247         int conf=0;
 248        unsigned long flags;
 249        spinlock_t *lock;
 250
 251        lock = (&pc->lock);//&pwm_lock[pwm->hwpwm];
 252         on   =  RK_PWM_ENABLE ;
 253         conf = PWM_OUTPUT_LEFT|PWM_LP_DISABLE|
 254                             PWM_CONTINUMOUS|PWM_DUTY_POSTIVE|PWM_INACTIVE_NEGATIVE;
 255         /*
 256          * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
 257          * according to formulas described below:
 258          *
 259          * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
 260          * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
 261          *
 262          * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
 263          * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
 264          */
 265 #if PWM_CLK
 266         clk_rate = clk_get_rate(pc->clk);
 267 #else
 268         clk_rate = 24000000;
 269 #endif
 270         while (1) {
 271                 div = 1000000000;
 272                 div *= 1 + prescale;
 273                 val = clk_rate * period_ns;
 274                 pv = div64_u64(val, div);
 275                 val = clk_rate * duty_ns;
 276                 dc = div64_u64(val, div);
 277
 278                 /* if duty_ns and period_ns are not achievable then return */
 279                 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
 280                         return -EINVAL;
 281
 282                 /*
 283                  * if pv and dc have crossed their upper limit, then increase
 284                  * prescale and recalculate pv and dc.
 285                  */
 286                 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
 287                         if (++prescale > PWMCR_MAX_PRESCALE)
 288                                 return -EINVAL;
 289                         continue;
 290                 }
 291                 break;
 292         }
 293
 294         /*
 295          * NOTE: the clock to PWM has to be enabled first before writing to the
 296          * registers.
 297          */
 298         spin_lock_irqsave(lock, flags);
 299
 300         conf |= (prescale << RK_PWM_PRESCALE);
 301         barrier();
 302         //rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
 303         //dsb();
 304         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY,dc);//0x1900);// dc);
 305         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD,pv);//0x5dc0);//pv);
 306         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,0);
 307         dsb();
 308         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,on|conf);
 309        spin_unlock_irqrestore(lock, flags);
 310
 311         return 0;
 312 }
 313
 314 static void rk_pwm_set_enable_v2(struct pwm_chip *chip, struct pwm_device *pwm,bool enable)
 315 {
 316         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 317         u32 val;
 318
 319         val = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
 320         if (enable)
 321                 val |= RK_PWM_ENABLE;
 322         else
 323                 val &= ~RK_PWM_ENABLE;
 324         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL, val);
 325         DBG("%s %d \n", __FUNCTION__, rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL));
 326
 327
 328 }
 329
 330 static void rk_pwm_suspend_v2(struct pwm_chip *chip, struct pwm_device *pwm)
 331 {
 332         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 333         pc->pwm_ctrl      = rk_pwm_readl(pc, pwm->hwpwm,        PWM_REG_CTRL);
 334         pc->pwm_duty    =  rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_DUTY);//0x1900);// dc);
 335         pc->pwm_period = rk_pwm_readl(pc, pwm->hwpwm,  PWM_REG_PERIOD );//0x5dc0);//pv);
 336         pc->pwm_count  =  rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CNTR);
 337 }
 338 static void rk_pwm_resume_v2(struct pwm_chip *chip, struct pwm_device *pwm)
 339 {
 340         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 341
 342         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY,    pc->pwm_duty);//0x1900);// dc);
 343         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD, pc->pwm_period);//0x5dc0);//pv);
 344         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,pc->pwm_count);
 345         dsb();
 346         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,pc->pwm_ctrl);
 347 }
 348
 349 /* config for rockchip,pwm*/
 350 static int  rk_pwm_config_v3(struct pwm_chip *chip, struct pwm_device *pwm,
 351                             int duty_ns, int period_ns)
 352 {
 353         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 354         u64 val, div, clk_rate;
 355         unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
 356         u32 on;
 357         int conf=0;
 358        unsigned long flags;
 359        spinlock_t *lock;
 360
 361        lock = (&pc->lock);//&pwm_lock[pwm->hwpwm];
 362         on   =  RK_PWM_ENABLE ;
 363         conf = PWM_OUTPUT_LEFT|PWM_LP_DISABLE|
 364                             PWM_CONTINUMOUS|PWM_DUTY_POSTIVE|PWM_INACTIVE_NEGATIVE;
 365         /*
 366          * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
 367          * according to formulas described below:
 368          *
 369          * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
 370          * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
 371          *
 372          * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
 373          * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
 374          */
 375 #if PWM_CLK
 376         clk_rate = clk_get_rate(pc->clk);
 377 #else
 378         clk_rate = 24000000;
 379 #endif
 380         while (1) {
 381                 div = 1000000000;
 382                 div *= 1 + prescale;
 383                 val = clk_rate * period_ns;
 384                 pv = div64_u64(val, div);
 385                 val = clk_rate * duty_ns;
 386                 dc = div64_u64(val, div);
 387
 388                 /* if duty_ns and period_ns are not achievable then return */
 389                 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
 390                         return -EINVAL;
 391
 392                 /*
 393                  * if pv and dc have crossed their upper limit, then increase
 394                  * prescale and recalculate pv and dc.
 395                  */
 396                 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
 397                         if (++prescale > PWMCR_MAX_PRESCALE)
 398                                 return -EINVAL;
 399                         continue;
 400                 }
 401                 break;
 402         }
 403
 404         /*
 405          * NOTE: the clock to PWM has to be enabled first before writing to the
 406          * registers.
 407          */
 408 #if 0
 409         ret = clk_enable(pc->clk);
 410         if (ret)
 411                 return ret;
 412 #endif
 413         spin_lock_irqsave(lock, flags);
 414
 415         conf |= (prescale << RK_PWM_PRESCALE);
 416
 417         barrier();
 418 //      rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL,off);
 419
 420 //      dsb();
 421         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY,dc);   //   2    0x1900);// dc);
 422         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD,pv);   // 4 0x5dc0);//pv);
 423         rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CNTR,0);
 424         dsb();
 425         rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL,on|conf);
 426
 427        spin_unlock_irqrestore(lock, flags);
 428
 429         return 0;
 430 }
 431 static void rk_pwm_set_enable_v3(struct pwm_chip *chip, struct pwm_device *pwm,bool enable)
 432 {
 433         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 434         u32 val;
 435
 436         val = rk_pwm_readl(pc, pwm->hwpwm, VOP_REG_CTRL);
 437         if (enable)
 438                 val |= RK_PWM_ENABLE;
 439         else
 440                 val &= ~RK_PWM_ENABLE;
 441         rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL, val);
 442
 443 }
 444 static void rk_pwm_suspend_v3(struct pwm_chip *chip, struct pwm_device *pwm)
 445 {
 446         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 447         pc->pwm_ctrl      = rk_pwm_readl(pc, pwm->hwpwm,        VOP_REG_CTRL);
 448         pc->pwm_duty    =  rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_DUTY);//0x1900);// dc);
 449         pc->pwm_period = rk_pwm_readl(pc, pwm->hwpwm,  PWM_REG_PERIOD );//0x5dc0);//pv);
 450         pc->pwm_count  =  rk_pwm_readl(pc, pwm->hwpwm, VOP_REG_CNTR);
 451 }
 452 static void rk_pwm_resume_v3(struct pwm_chip *chip, struct pwm_device *pwm)
 453 {
 454         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 455
 456         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY,    pc->pwm_duty);//0x1900);// dc);
 457         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD, pc->pwm_period);//0x5dc0);//pv);
 458         rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CNTR,pc->pwm_count);
 459         dsb();
 460         rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL,pc->pwm_ctrl);
 461 }
 462
 463
 464 static int  rk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 465                             int duty_ns, int period_ns)
 466 {
 467         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 468         int ret;
 469
 470         ret = clk_enable(pc->clk);
 471         if (ret)
 472                 return ret;
 473
 474         ret = pc->config(chip, pwm, duty_ns, period_ns);
 475
 476         clk_disable(pc->clk);
 477
 478         return 0;
 479 }
 480 static int rk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 481 {
 482         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 483         int ret = 0;
 484
 485         ret = clk_enable(pc->clk);
 486         if (ret)
 487                 return ret;
 488
 489         pc->set_enable(chip, pwm,true);
 490         return 0;
 491 }
 492
 493 static void rk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 494 {
 495         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 496
 497         pc->set_enable(chip, pwm,false);
 498
 499         clk_disable(pc->clk);
 500
 501 }
 502
 503 static const struct pwm_ops rk_pwm_ops = {
 504         .config = rk_pwm_config,
 505         .enable = rk_pwm_enable,
 506         .disable = rk_pwm_disable,
 507         .owner = THIS_MODULE,
 508 };
 509
 510 struct rk_pwm_data{
 511         int   (*config)(struct pwm_chip *chip,  struct pwm_device *pwm, int duty_ns, int period_ns);
 512         void (*set_enable)(struct pwm_chip *chip, struct pwm_device *pwm,bool enable);
 513         void (*pwm_suspend)(struct pwm_chip *chip, struct pwm_device *pwm);
 514         void (*pwm_resume)(struct pwm_chip *chip, struct pwm_device *pwm);
 515
 516
 517 };
 518
 519 static struct rk_pwm_data rk_pwm_data_v1={
 520         .config = rk_pwm_config_v1,
 521         .set_enable = rk_pwm_set_enable_v1,
 522         .pwm_suspend = rk_pwm_suspend_v1,
 523         .pwm_resume = rk_pwm_resume_v1,
 524
 525 };
 526
 527 static struct rk_pwm_data rk_pwm_data_v2={
 528         .config = rk_pwm_config_v2,
 529         .set_enable = rk_pwm_set_enable_v2,
 530         .pwm_suspend = rk_pwm_suspend_v2,
 531         .pwm_resume = rk_pwm_resume_v2,
 532
 533 };
 534
 535 static struct rk_pwm_data rk_pwm_data_v3={
 536         .config = rk_pwm_config_v3,
 537         .set_enable = rk_pwm_set_enable_v3,
 538         .pwm_suspend = rk_pwm_suspend_v3,
 539         .pwm_resume = rk_pwm_resume_v3,
 540
 541 };
 542
 543 static const struct of_device_id rk_pwm_of_match[] = {
 544         { .compatible = "rockchip,pwm",          .data = &rk_pwm_data_v1,},
 545         { .compatible =  "rockchip,rk-pwm",    .data = &rk_pwm_data_v2,},
 546         { .compatible =  "rockchip,vop-pwm",  .data = &rk_pwm_data_v3,},
 547         { }
 548 };
 549
 550 MODULE_DEVICE_TABLE(of, rk_pwm_of_match);
 551 static int rk_pwm_probe(struct platform_device *pdev)
 552 {
 553         const struct of_device_id *of_id =
 554                 of_match_device(rk_pwm_of_match, &pdev->dev);
 555         struct device_node *np = pdev->dev.of_node;
 556         const struct rk_pwm_data *data;
 557         struct rk_pwm_chip *pc;
 558         int ret;
 559
 560         if (!of_id){
 561                 dev_err(&pdev->dev, "failed to match device\n");
 562                 return -ENODEV;
 563         }
 564         pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 565         if (!pc) {
 566                 dev_err(&pdev->dev, "failed to allocate memory\n");
 567                 return -ENOMEM;
 568         }
 569
 570         pc->base = of_iomap(np, 0);
 571         if (IS_ERR(pc->base)){
 572                 printk("PWM base ERR \n");
 573                 return PTR_ERR(pc->base);
 574         }
 575         pc->clk = devm_clk_get(&pdev->dev,"pclk_pwm");
 576         if (IS_ERR(pc->clk))
 577                 return PTR_ERR(pc->clk);
 578
 579         platform_set_drvdata(pdev, pc);
 580         data = of_id->data;
 581         pc->config = data->config;
 582         pc->set_enable = data->set_enable;
 583         pc->pwm_suspend = data->pwm_suspend;
 584         pc->pwm_resume = data->pwm_resume;
 585         pc->chip.dev = &pdev->dev;
 586         pc->chip.ops = &rk_pwm_ops;
 587         pc->chip.base = -1;
 588         pc->chip.npwm = NUM_PWM;
 589         spin_lock_init(&pc->lock);
 590         clk_prepare(pc->clk);
 591
 592         /* Following enables PWM chip, channels would still be enabled individually through their control register */
 593         DBG("npwm = %d, of_pwm_ncells =%d \n", pc->chip.npwm,pc->chip.of_pwm_n_cells);
 594         ret = pwmchip_add(&pc->chip);
 595         if (ret < 0){
 596                 printk("failed to add pwm\n");
 597                 return ret;
 598         }
 599
 600         DBG("%s end \n",__FUNCTION__);
 601         return ret;
 602 }
 603 #if 0
 604 //(struct platform_device *, pm_message_t state);
 605 static int rk_pwm_suspend(struct platform_device *pdev, pm_message_t state)
 606 {
 607         struct pwm_device *pwm;
 608         struct rk_pwm_chip *pc;
 609         struct pwm_chip *chip;
 610
 611         pc = platform_get_drvdata(pdev);
 612         chip = &(pc->chip);
 613         pwm = chip->pwms;
 614
 615         pc->pwm_suspend(chip,pwm);
 616
 617         return 0;//pwmchip_remove(&pc->chip);
 618 }
 619 static int rk_pwm_resume(struct platform_device *pdev)
 620 {
 621         struct pwm_device *pwm;
 622         struct rk_pwm_chip *pc;
 623         struct pwm_chip *chip;
 624
 625         pc = platform_get_drvdata(pdev);
 626         chip = &(pc->chip);
 627         pwm = chip->pwms;
 628
 629         pc->pwm_resume(chip,pwm);
 630         return 0;//pwmchip_remove(&pc->chip);
 631 }
 632 #endif
 633 static int rk_pwm_remove(struct platform_device *pdev)
 634 {
 635         return 0;//pwmchip_remove(&pc->chip);
 636 }
 637
 638 static struct platform_driver rk_pwm_driver = {
 639         .driver = {
 640                 .name = "rk-pwm",
 641                 .of_match_table = rk_pwm_of_match,
 642         },
 643         .probe = rk_pwm_probe,
 644         .remove = rk_pwm_remove,
 645 };
 646
 647 module_platform_driver(rk_pwm_driver);
 648
 649 MODULE_LICENSE("GPL");
 650 MODULE_AUTHOR("<xsf@rock-chips.com>");
 651 MODULE_ALIAS("platform:rk-pwm");
 652
 653