drivers/pwm/pwm-rockchip.c

   1
   2 #include <linux/clk.h>
   3 #include <linux/err.h>
   4 #include <linux/io.h>
   5 #include <linux/ioport.h>
   6 #include <linux/kernel.h>
   7 #include <linux/math64.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/pwm.h>
  12 #include <linux/slab.h>
  13 #include <linux/types.h>
  14 #include <linux/spinlock.h>
  15
  16 #define NUM_PWM         1
  17
  18 /* PWM registers  */
  19 #if 0
  20 #define PWM_REG_CNTR                  0x00  /* Counter Register */
  21 #define PWM_REG_PERIOD                  0x04  /* Period Register */
  22 #define PWM_REG_DUTY                    0x08  /* Duty Cycle Register */
  23 #define PWM_REG_CTRL                   0x0c /* Control Register */
  24
  25 /*bits definitions*/
  26
  27 #define PWM_ENABLE                      (1 << 0)
  28 #define PWM_DISABLE                     (0 << 0)
  29
  30 #define PWM_SHOT                        (0x00 << 1)
  31 #define PWM_CONTINUMOUS         (0x01 << 1)
  32 #define PWM_CAPTURE             (0x01 << 1)
  33
  34 #define PWM_DUTY_POSTIVE        (0x01 << 3)
  35 #define PWM_DUTY_NEGATIVE       (0x00 << 3)
  36
  37 #define PWM_INACTIVE_POSTIVE            (0x01 << 4)
  38 #define PWM_INACTIVE_NEGATIVE           (0x00 << 4)
  39
  40 #define PWM_OUTPUT_LEFT                 (0x00 << 5)
  41 #define PWM_OUTPUT_ENTER                        (0x01 << 5)
  42
  43
  44 #define PWM_LP_ENABLE           (1<<8)
  45 #define PWM_LP_DISABLE          (0<<8)
  46
  47 #define PWM_CLK_SCALE           (1 << 9)
  48 #define PWM_CLK_NON_SCALE       (0 << 9)
  49
  50
  51
  52 #define PWMCR_MIN_PRESCALE      0x00
  53
  54 #define PWMCR_MIN_PRESCALE      0x00
  55 #define PWMCR_MAX_PRESCALE      0x07
  56
  57 #define PWMDCR_MIN_DUTY         0x0001
  58 #define PWMDCR_MAX_DUTY         0xFFFF
  59
  60 #define PWMPCR_MIN_PERIOD               0x0001
  61 #define PWMPCR_MAX_PERIOD               0xFFFF
  62
  63
  64 enum pwm_div {
  65         PWM_DIV1                 = (0x0 << 12),
  66         PWM_DIV2                 = (0x1 << 12),
  67         PWM_DIV4                 = (0x2 << 12),
  68         PWM_DIV8                 = (0x3 << 12),
  69         PWM_DIV16               = (0x4 << 12),
  70         PWM_DIV32               = (0x5 << 12),
  71         PWM_DIV64               = (0x6 << 12),
  72         PWM_DIV128              = (0x7 << 12),
  73 };
  74 #endif
  75 static int pwm_dbg_level = 0;
  76 module_param_named(dbg_level, pwm_dbg_level, int, 0644);
  77 #define DBG( args...) \
  78         do { \
  79                 if (pwm_dbg_level) { \
  80                         pr_info(args); \
  81                 } \
  82         } while (0)
  83
  84 #define PWM_REG_CNTR    0x00
  85 #define PWM_REG_HRC     0x04
  86 #define PWM_REG_LRC     0x08
  87 #define PWM_REG_CTRL    0x0c
  88
  89
  90 #define PWM_REG_PERIOD                  PWM_REG_HRC  /* Period Register */
  91 #define PWM_REG_DUTY                    PWM_REG_LRC  /* Duty Cycle Register */
  92 //#define PWM_REG_CTRL                   0x0c /* Control Register */
  93
  94
  95
  96 #define PWM_DIV_MASK    (0xf << 9)
  97 #define PWM_CAPTURE     (1 << 8)
  98 #define PWM_RESET       (1 << 7)
  99 #define PWM_INTCLR      (1 << 6)
 100 #define PWM_INTEN       (1 << 5)
 101 #define PWM_SINGLE      (1 << 4)
 102
 103 #define PWM_ENABLE      (1 << 3)
 104 #define PWM_TIMER_EN    (1 << 0)
 105 #define PWM_TimeEN      PWM_TIMER_EN
 106 #define PWMCR_MIN_PRESCALE      0x00
 107
 108 #define PWMCR_MIN_PRESCALE      0x00
 109 #define PWMCR_MAX_PRESCALE      0x07
 110
 111 #define PWMDCR_MIN_DUTY         0x0001
 112 #define PWMDCR_MAX_DUTY         0xFFFF
 113
 114 #define PWMPCR_MIN_PERIOD               0x0001
 115 #define PWMPCR_MAX_PERIOD               0xFFFF
 116
 117 /**
 118  * struct rk_pwm_chip - struct representing pwm chip
 119  *
 120  * @base: base address of pwm chip
 121  * @clk: pointer to clk structure of pwm chip
 122  * @chip: linux pwm chip representation
 123  */
 124
 125 static spinlock_t pwm_lock[4] = {
 126         __SPIN_LOCK_UNLOCKED(pwm_lock0),
 127         __SPIN_LOCK_UNLOCKED(pwm_lock1),
 128         __SPIN_LOCK_UNLOCKED(pwm_lock2),
 129         __SPIN_LOCK_UNLOCKED(pwm_lock3),
 130 };
 131
 132 struct rk_pwm_chip {
 133         void __iomem *base;
 134         struct clk *clk;
 135         struct pwm_chip chip;
 136 };
 137
 138 #define PWM_CLK 1
 139 #if 0
 140 static void __iomem *rk30_grf_base = NULL;
 141 static void __iomem *rk30_cru_base = NULL;
 142 static void __iomem *rk30_pwm_base = NULL;
 143 //#define SZ_16K                         0x4000
 144 //#define SZ_8K                         0x2000
 145 #define RK30_GRF_PHYS           0x20008000
 146 #define RK30_GRF_SIZE            SZ_8K
 147 #define RK30_CRU_PHYS           0x20000000
 148 #define RK30_CRU_SIZE            SZ_16K
 149 #define RK30_PWM_PHYS           0x20050000
 150 #define RK30_PWM_SIZE            SZ_16K
 151
 152 static void dump_register_of_pwm(void)
 153 {
 154         int off;
 155 //rk30_grf_base =  ioremap(RK30_GRF_PHYS, RK30_GRF_SIZE);
 156 // rk30_cru_base = ioremap(RK30_CRU_PHYS, RK30_CRU_SIZE);
 157  //rk30_pwm_base = ioremap(RK30_PWM_PHYS, RK30_PWM_SIZE);
 158
 159 // DBG("GRF IOMUX GPIO3_D6 = 0x%08x\n",readl_relaxed(rk30_grf_base+ 0x9C) );
 160  //DBG("CRU                            = 0x%08x\n",readl_relaxed(rk30_cru_base+ 0xeC) );
 161 //writel_relaxed(0x10001000, rk30_grf_base+ 0x9C);
 162  //DBG("GRF IOMUX GPIO3_D6 = 0x%08x\n",readl_relaxed(rk30_grf_base+ 0x9C) );
 163  //DBG("CRU                            = 0x%08x\n",readl_relaxed(rk30_cru_base+ 0xeC) );
 164
 165 #if 0
 166         barrier();
 167         writel_relaxed(off, rk30_pwm_base+3*0x10+ PWM_REG_CTRL);
 168
 169         dsb();
 170         writel_relaxed(0x1900, rk30_pwm_base+3*0x10+ PWM_REG_HRC);//rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_HRC,0x1900);// dc);
 171         writel_relaxed(0x5dc0, rk30_pwm_base+3*0x10+ PWM_REG_LRC);//rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_LRC, 0x5dc0);//pv);
 172         writel_relaxed(0, rk30_pwm_base+3*0x10+ PWM_REG_CNTR);//rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,0);
 173         dsb();
 174         writel_relaxed(0x09, rk30_pwm_base+3*0x10+ PWM_REG_CTRL);// rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,on);
 175         dsb();
 176 #endif
 177 }
 178 static void dump_pwm_register(struct rk_pwm_chip *chip)
 179 {
 180 DBG("dump pwm regitster start\n");
 181 #if 1
 182 DBG("PWM0\n");
 183 DBG("PWM_REG_CTRL =0x%08x\n",rk_pwm_readl(chip, 0, PWM_REG_CTRL));
 184 DBG("PWM_REG_HRC = 0x%08x\n",rk_pwm_readl(chip,0, PWM_REG_HRC));
 185 DBG("PWM_REG_LRC = 0x%08x\n",rk_pwm_readl(chip,0, PWM_REG_LRC));
 186 DBG("PWM_REG_CNTR = 0x%08x\n",rk_pwm_readl(chip,0, PWM_REG_CNTR));
 187
 188 DBG("PWM1\n");
 189 DBG("PWM_REG_CTRL =0x%08x\n",rk_pwm_readl(chip, 1, PWM_REG_CTRL));
 190 DBG("PWM_REG_HRC = 0x%08x\n",rk_pwm_readl(chip,1, PWM_REG_HRC));
 191 DBG("PWM_REG_LRC = 0x%08x\n",rk_pwm_readl(chip,1, PWM_REG_LRC));
 192 DBG("PWM_REG_CNTR = 0x%08x\n",rk_pwm_readl(chip,1, PWM_REG_CNTR));
 193
 194 DBG("PWM2\n");
 195 DBG("PWM_REG_CTRL =0x%08x\n",rk_pwm_readl(chip, 2, PWM_REG_CTRL));
 196 DBG("PWM_REG_HRC = 0x%08x\n",rk_pwm_readl(chip,2, PWM_REG_HRC));
 197 DBG("PWM_REG_LRC = 0x%08x\n",rk_pwm_readl(chip,2, PWM_REG_LRC));
 198 DBG("PWM_REG_CNTR = 0x%08x\n",rk_pwm_readl(chip,2, PWM_REG_CNTR));
 199
 200 DBG("PWM3\n");
 201 DBG("PWM_REG_CTRL =0x%08x\n",rk_pwm_readl(chip,3, PWM_REG_CTRL));
 202 DBG("PWM_REG_HRC = 0x%08x\n",rk_pwm_readl(chip,3, PWM_REG_HRC));
 203 DBG("PWM_REG_LRC = 0x%08x\n",rk_pwm_readl(chip,3, PWM_REG_LRC));
 204 DBG("PWM_REG_CNTR = 0x%08x\n",rk_pwm_readl(chip,3, PWM_REG_CNTR));
 205 #endif
 206 printk("dump pwm regitster end\n");
 207
 208 }
 209
 210 #endif
 211 static inline struct rk_pwm_chip *to_rk_pwm_chip(struct pwm_chip *chip)
 212 {
 213         return container_of(chip, struct rk_pwm_chip, chip);
 214 }
 215
 216 static inline u32 rk_pwm_readl(struct rk_pwm_chip *chip, unsigned int num,
 217                                   unsigned long offset)
 218 {
 219         return readl_relaxed(chip->base + (num << 4) + offset);
 220 }
 221
 222 static inline void rk_pwm_writel(struct rk_pwm_chip *chip,
 223                                     unsigned int num, unsigned long offset,
 224                                     unsigned long val)
 225 {
 226         writel_relaxed(val, chip->base + (num << 4) + offset);
 227 }
 228
 229
 230 #if 1
 231 static int  rk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 232                             int duty_ns, int period_ns)
 233 {
 234         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 235         u64 val, div, clk_rate;
 236         unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
 237         int ret;
 238         u32 off, on;
 239         int conf=0;
 240        unsigned long flags;
 241        spinlock_t *lock;
 242
 243        lock = &pwm_lock[pwm->hwpwm];
 244
 245         off =  PWM_RESET;
 246         on =  PWM_ENABLE | PWM_TIMER_EN;
 247
 248         //dump_pwm_register(pc);
 249
 250         /*
 251          * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
 252          * according to formulas described below:
 253          *
 254          * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
 255          * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
 256          *
 257          * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
 258          * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
 259          */
 260 #if PWM_CLK
 261         clk_rate = clk_get_rate(pc->clk);
 262 #else
 263         clk_rate = 24000000;
 264 #endif
 265         while (1) {
 266                 div = 1000000000;
 267                 div *= 1 + prescale;
 268                 val = clk_rate * period_ns;
 269                 pv = div64_u64(val, div);
 270                 val = clk_rate * duty_ns;
 271                 dc = div64_u64(val, div);
 272
 273                 /* if duty_ns and period_ns are not achievable then return */
 274                 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
 275                         return -EINVAL;
 276
 277                 /*
 278                  * if pv and dc have crossed their upper limit, then increase
 279                  * prescale and recalculate pv and dc.
 280                  */
 281                 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
 282                         if (++prescale > PWMCR_MAX_PRESCALE)
 283                                 return -EINVAL;
 284                         continue;
 285                 }
 286                 break;
 287         }
 288
 289         /*
 290          * NOTE: the clock to PWM has to be enabled first before writing to the
 291          * registers.
 292          */
 293          conf |= (prescale << 9);
 294 #if PWM_CLK
 295         ret = clk_enable(pc->clk);
 296         if (ret)
 297                 return ret;
 298 #endif
 299         spin_lock_irqsave(lock, flags);
 300
 301         barrier();
 302         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
 303
 304         dsb();
 305         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_HRC,dc);//0x1900);// dc);
 306         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_LRC, pv);//0x5dc0);//pv);
 307         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,0);
 308         dsb();
 309          rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,on|conf);
 310         dsb();
 311         spin_unlock_irqrestore(lock, flags);
 312
 313 #if PWM_CLK
 314         clk_disable(pc->clk);
 315 #endif
 316
 317         return 0;
 318 }
 319 #endif
 320
 321 static int rk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 322 {
 323         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 324         int rc = 0;
 325         u32 val;
 326 #if PWM_CLK
 327         rc = clk_enable(pc->clk);
 328         if (rc)
 329                 return rc;
 330 #endif
 331         val = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
 332         val |= PWM_ENABLE;
 333         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL, val);
 334
 335         return 0;
 336 }
 337
 338 static void rk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 339 {
 340         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 341         u32 val;
 342
 343         val = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
 344         val &= ~PWM_ENABLE;
 345         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL, val);
 346 #if PWM_CLK
 347         clk_disable(pc->clk);
 348 #endif
 349 }
 350
 351
 352 static const struct pwm_ops rk_pwm_ops = {
 353         .config = rk_pwm_config,
 354         .enable = rk_pwm_enable,
 355         .disable = rk_pwm_disable,
 356         .owner = THIS_MODULE,
 357 };
 358
 359
 360
 361 static int rk_pwm_probe(struct platform_device *pdev)
 362 {
 363         struct device_node *np = pdev->dev.of_node;
 364         struct rk_pwm_chip *pc;
 365         struct resource *r;
 366         int ret;
 367         DBG("%s start \n",__FUNCTION__);
 368         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 369         if (!r) {
 370                 dev_err(&pdev->dev, "no memory resources defined\n");
 371                 return -ENODEV;
 372         }
 373         pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 374         if (!pc) {
 375                 dev_err(&pdev->dev, "failed to allocate memory\n");
 376                 return -ENOMEM;
 377         }
 378         pc->base = devm_ioremap_resource(&pdev->dev, r);
 379         if (IS_ERR(pc->base))
 380                 return PTR_ERR(pc->base);
 381
 382 #if PWM_CLK
 383         //pc->clk = devm_clk_get(&pdev->dev, NULL);
 384         pc->clk = clk_get(NULL,"g_p_pwm23");
 385
 386
 387         if (IS_ERR(pc->clk))
 388                 return PTR_ERR(pc->clk);
 389 #endif
 390
 391         platform_set_drvdata(pdev, pc);
 392
 393         pc->chip.dev = &pdev->dev;
 394         pc->chip.ops = &rk_pwm_ops;
 395         pc->chip.base = -1;
 396         pc->chip.npwm = NUM_PWM;
 397
 398 #if PWM_CLK
 399         ret = clk_prepare(pc->clk);
 400         if (ret)
 401                 return ret;
 402 #endif
 403
 404 #if PWM_CLK
 405         if (of_device_is_compatible(np, "rockchip,pwm")) {
 406                 ret = clk_enable(pc->clk);
 407                 if (ret) {
 408                         clk_unprepare(pc->clk);
 409                         return ret;
 410                 }
 411                 /*
 412                  * Following enables PWM chip, channels would still be
 413                  * enabled individually through their control register
 414                  */
 415 #if PWM_CLK
 416 //              clk_disable(pc->clk);
 417 #endif
 418         }
 419 #endif
 420         DBG("npwm = %d, of_pwm_ncells =%d \n", pc->chip.npwm,pc->chip.of_pwm_n_cells);
 421         ret = pwmchip_add(&pc->chip);
 422         if (ret < 0) {
 423                 clk_unprepare(pc->clk);
 424                 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 425         }
 426         DBG("%s end \n",__FUNCTION__);
 427
 428         return ret;
 429 }
 430
 431 static int rk_pwm_remove(struct platform_device *pdev)
 432 {
 433         return 0;//pwmchip_remove(&pc->chip);
 434 }
 435
 436
 437 static const struct of_device_id rk_pwm_of_match[] = {
 438         { .compatible = "rockchip,pwm" },
 439         { }
 440 };
 441
 442 MODULE_DEVICE_TABLE(of, rk_pwm_of_match);
 443
 444 static struct platform_driver rk_pwm_driver = {
 445         .driver = {
 446                 .name = "rk-pwm",
 447                 .of_match_table = rk_pwm_of_match,
 448         },
 449         .probe = rk_pwm_probe,
 450         .remove = rk_pwm_remove,
 451 };
 452
 453 module_platform_driver(rk_pwm_driver);
 454
 455 MODULE_LICENSE("GPL");
 456 MODULE_AUTHOR("<xsf@rock-chips.com>");
 457 MODULE_ALIAS("platform:rk-pwm");
 458
 459