drivers/pwm/pwm-rockchip.c

   1
   2 #include <linux/clk.h>
   3 #include <linux/err.h>
   4 #include <linux/io.h>
   5 #include <linux/ioport.h>
   6 #include <linux/kernel.h>
   7 #include <linux/math64.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/pwm.h>
  12 #include <linux/slab.h>
  13 #include <linux/types.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/rockchip/grf.h>
  18 #include <linux/rockchip/iomap.h>
  19
  20
  21 static int pwm_dbg_level = 0;
  22 module_param_named(dbg_level, pwm_dbg_level, int, 0644);
  23 #define DBG( args...) \
  24         do { \
  25                 if (pwm_dbg_level) { \
  26                         pr_info(args); \
  27                 } \
  28         } while (0)
  29
  30 #define PWM_CLK                                 1
  31 #define NUM_PWM                           1
  32
  33 /* PWM registers  */
  34 #define PWM_REG_CNTR                            0x00
  35 #define PWM_REG_HRC                             0x04
  36 #define PWM_REG_LRC                             0x08
  37 #define PWM_REG_CTRL                                    0x0c  /* PWM Control Register */
  38
  39 #define PWM_REG_PERIOD                          PWM_REG_HRC  /* Period Register */
  40 #define PWM_REG_DUTY                            PWM_REG_LRC  /* Duty Cycle Register */
  41
  42 #define VOP_REG_CNTR                            0x0C
  43 #define VOP_REG_CTRL                                    0x00  /* VOP-PWM Control Register */
  44
  45 //#define PWM_REG_CTRL                   0x0c /* Control Register */
  46
  47 #define PWM_DIV_MASK                            (0xf << 9)
  48 #define PWM_CAPTURE                                     (1 << 8)
  49 #define PWM_RESET                               (1 << 7)
  50 #define PWM_INTCLR                                      (1 << 6)
  51 #define PWM_INTEN                                       (1 << 5)
  52 #define PWM_SINGLE                                      (1 << 4)
  53
  54 #define PWM_ENABLE                                      (1 << 3)
  55 #define PWM_TIMER_EN                                    (1 << 0)
  56
  57 #define RK_PWM_DISABLE                     (0 << 0)
  58 #define RK_PWM_ENABLE                       (1 << 0)
  59
  60 #define PWM_SHOT                                 (0 << 1)
  61 #define PWM_CONTINUMOUS                 (1 << 1)
  62 #define RK_PWM_CAPTURE                    (1 << 2)
  63
  64 #define PWM_DUTY_POSTIVE                (1 << 3)
  65 #define PWM_DUTY_NEGATIVE              (0 << 3)
  66
  67 #define PWM_INACTIVE_POSTIVE         (1 << 4)
  68 #define PWM_INACTIVE_NEGATIVE       (0 << 4)
  69
  70 #define PWM_OUTPUT_LEFT                 (0 << 5)
  71 #define PWM_OUTPUT_ENTER               (1 << 5)
  72
  73 #define PWM_LP_ENABLE                     (1<<8)
  74 #define PWM_LP_DISABLE                    (0<<8)
  75
  76 #define DW_PWM_PRESCALE         9
  77 #define RK_PWM_PRESCALE         16
  78
  79 #define PWMCR_MIN_PRESCALE      0x00
  80
  81 #define PWMCR_MIN_PRESCALE      0x00
  82 #define PWMCR_MAX_PRESCALE      0x07
  83
  84 #define PWMDCR_MIN_DUTY         0x0001
  85 #define PWMDCR_MAX_DUTY         0xFFFF
  86
  87 #define PWMPCR_MIN_PERIOD               0x0001
  88 #define PWMPCR_MAX_PERIOD               0xFFFF
  89 #if 0
  90 static spinlock_t pwm_lock[4] = {
  91         __SPIN_LOCK_UNLOCKED(pwm_lock0),
  92         __SPIN_LOCK_UNLOCKED(pwm_lock1),
  93         __SPIN_LOCK_UNLOCKED(pwm_lock2),
  94         __SPIN_LOCK_UNLOCKED(pwm_lock3),
  95 };
  96 #endif
  97 int spinlock_num = 0;
  98 /********************************************
  99  * struct rk_pwm_chip - struct representing pwm chip
 100
 101  * @base: base address of pwm chip
 102  * @clk: pointer to clk structure of pwm chip
 103  * @chip: linux pwm chip representation
 104  *********************************************/
 105  struct rk_pwm_chip {
 106         void __iomem *base;
 107         struct clk *clk;
 108         struct pwm_chip chip;
 109         unsigned int pwm_id;
 110         spinlock_t              lock;
 111         int                             pwm_ctrl;
 112         int                             pwm_duty;
 113         int                             pwm_period;
 114         int                             pwm_count;
 115         int (*config)(struct pwm_chip *chip,
 116                 struct pwm_device *pwm, int duty_ns, int period_ns);
 117         void (*set_enable)(struct pwm_chip *chip, struct pwm_device *pwm,bool enable);
 118         void (*pwm_suspend)(struct pwm_chip *chip, struct pwm_device *pwm);
 119         void (*pwm_resume)(struct pwm_chip *chip, struct pwm_device *pwm);
 120
 121 };
 122
 123 static inline struct rk_pwm_chip *to_rk_pwm_chip(struct pwm_chip *chip)
 124 {
 125         return container_of(chip, struct rk_pwm_chip, chip);
 126 }
 127
 128 static inline u32 rk_pwm_readl(struct rk_pwm_chip *chip, unsigned int num,
 129                                   unsigned long offset)
 130 {
 131         return readl_relaxed(chip->base + (num << 4) + offset);
 132 }
 133
 134 static inline void rk_pwm_writel(struct rk_pwm_chip *chip,
 135                                     unsigned int num, unsigned long offset,
 136                                     unsigned long val)
 137 {
 138         writel_relaxed(val, chip->base + (num << 4) + offset);
 139 }
 140
 141 /* config for rockchip,pwm*/
 142 static int  rk_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm,
 143                             int duty_ns, int period_ns)
 144 {
 145         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 146         u64 val, div, clk_rate;
 147         unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
 148         int ret;
 149         u32 off, on;
 150         int conf=0;
 151        unsigned long flags;
 152        spinlock_t *lock;
 153
 154        lock =(&pc->lock);// &pwm_lock[pwm->hwpwm];
 155         off =  PWM_RESET;
 156         on =  PWM_ENABLE | PWM_TIMER_EN;
 157         /*
 158          * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
 159          * according to formulas described below:
 160          *
 161          * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
 162          * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
 163          *
 164          * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
 165          * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
 166          */
 167 #if PWM_CLK
 168         clk_rate = clk_get_rate(pc->clk);
 169 #else
 170         clk_rate = 24000000;
 171 #endif
 172         while (1) {
 173                 div = 1000000000;
 174                 div *= 1 + prescale;
 175                 val = clk_rate * period_ns;
 176                 pv = div64_u64(val, div);
 177                 val = clk_rate * duty_ns;
 178                 dc = div64_u64(val, div);
 179
 180                 /* if duty_ns and period_ns are not achievable then return */
 181                 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
 182                         return -EINVAL;
 183
 184                 /*
 185                  * if pv and dc have crossed their upper limit, then increase
 186                  * prescale and recalculate pv and dc.
 187                  */
 188                 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
 189                         if (++prescale > PWMCR_MAX_PRESCALE)
 190                                 return -EINVAL;
 191                         continue;
 192                 }
 193                 break;
 194         }
 195
 196         /* NOTE: the clock to PWM has to be enabled first before writing to the registers. */
 197
 198 #if PWM_CLK
 199         ret = clk_enable(pc->clk);
 200         if (ret)
 201                 return ret;
 202 #endif
 203         spin_lock_irqsave(lock, flags);
 204
 205         conf |= (prescale << DW_PWM_PRESCALE);
 206         barrier();
 207         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
 208         dsb();
 209         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_HRC,dc);//0x1900);// dc);
 210         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_LRC, pv);//0x5dc0);//pv);
 211         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,0);
 212         dsb();
 213         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,on|conf);
 214
 215        spin_unlock_irqrestore(lock, flags);
 216         return 0;
 217 }
 218 static void rk_pwm_set_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm, bool enable)
 219 {
 220         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 221         u32 val;
 222
 223         val = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
 224         if (enable)
 225                 val |= PWM_ENABLE;
 226         else
 227                 val &= ~PWM_ENABLE;
 228
 229         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL, val);
 230
 231 }
 232 static void rk_pwm_suspend_v1(struct pwm_chip *chip, struct pwm_device *pwm)
 233 {
 234         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 235         pc->pwm_ctrl = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
 236         pc->pwm_duty=  rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_HRC);//0x1900);// dc);
 237         pc->pwm_period = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_LRC );//0x5dc0);//pv);
 238         pc->pwm_count=  rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CNTR);
 239 }
 240 static void rk_pwm_resume_v1(struct pwm_chip *chip, struct pwm_device *pwm)
 241 {
 242         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 243         int     off =  PWM_RESET;
 244
 245         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
 246         dsb();
 247         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_HRC,pc->pwm_duty);//0x1900);// dc);
 248         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_LRC, pc->pwm_period);//0x5dc0);//pv);
 249         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,pc->pwm_count);
 250         dsb();
 251         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,pc->pwm_ctrl);
 252 }
 253 /* config for rockchip,pwm*/
 254 static int  rk_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
 255                             int duty_ns, int period_ns)
 256 {
 257         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 258         u64 val, div, clk_rate;
 259         unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
 260         int ret;
 261         u32  on;
 262         int conf=0;
 263        unsigned long flags;
 264        spinlock_t *lock;
 265
 266        lock = (&pc->lock);//&pwm_lock[pwm->hwpwm];
 267         on   =  RK_PWM_ENABLE ;
 268         conf = PWM_OUTPUT_LEFT|PWM_LP_DISABLE|
 269                             PWM_CONTINUMOUS|PWM_DUTY_POSTIVE|PWM_INACTIVE_NEGATIVE;
 270         /*
 271          * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
 272          * according to formulas described below:
 273          *
 274          * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
 275          * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
 276          *
 277          * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
 278          * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
 279          */
 280 #if PWM_CLK
 281         clk_rate = clk_get_rate(pc->clk);
 282 #else
 283         clk_rate = 24000000;
 284 #endif
 285         while (1) {
 286                 div = 1000000000;
 287                 div *= 1 + prescale;
 288                 val = clk_rate * period_ns;
 289                 pv = div64_u64(val, div);
 290                 val = clk_rate * duty_ns;
 291                 dc = div64_u64(val, div);
 292
 293                 /* if duty_ns and period_ns are not achievable then return */
 294                 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
 295                         return -EINVAL;
 296
 297                 /*
 298                  * if pv and dc have crossed their upper limit, then increase
 299                  * prescale and recalculate pv and dc.
 300                  */
 301                 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
 302                         if (++prescale > PWMCR_MAX_PRESCALE)
 303                                 return -EINVAL;
 304                         continue;
 305                 }
 306                 break;
 307         }
 308
 309         /*
 310          * NOTE: the clock to PWM has to be enabled first before writing to the
 311          * registers.
 312          */
 313
 314         ret = clk_enable(pc->clk);
 315         if (ret)
 316                 return ret;
 317         spin_lock_irqsave(lock, flags);
 318
 319         conf |= (prescale << RK_PWM_PRESCALE);
 320         barrier();
 321         //rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
 322         //dsb();
 323         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY,dc);//0x1900);// dc);
 324         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD,pv);//0x5dc0);//pv);
 325         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,0);
 326         dsb();
 327         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,on|conf);
 328        spin_unlock_irqrestore(lock, flags);
 329
 330         return 0;
 331 }
 332
 333 static void rk_pwm_set_enable_v2(struct pwm_chip *chip, struct pwm_device *pwm,bool enable)
 334 {
 335         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 336         u32 val;
 337
 338         val = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
 339         if (enable)
 340                 val |= RK_PWM_ENABLE;
 341         else
 342                 val &= ~RK_PWM_ENABLE;
 343         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL, val);
 344         DBG("%s %d \n", __FUNCTION__, rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL));
 345
 346
 347 }
 348
 349 static void rk_pwm_suspend_v2(struct pwm_chip *chip, struct pwm_device *pwm)
 350 {
 351         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 352         pc->pwm_ctrl      = rk_pwm_readl(pc, pwm->hwpwm,        PWM_REG_CTRL);
 353         pc->pwm_duty    =  rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_DUTY);//0x1900);// dc);
 354         pc->pwm_period = rk_pwm_readl(pc, pwm->hwpwm,  PWM_REG_PERIOD );//0x5dc0);//pv);
 355         pc->pwm_count  =  rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CNTR);
 356 }
 357 static void rk_pwm_resume_v2(struct pwm_chip *chip, struct pwm_device *pwm)
 358 {
 359         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 360
 361         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY,    pc->pwm_duty);//0x1900);// dc);
 362         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD, pc->pwm_period);//0x5dc0);//pv);
 363         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,pc->pwm_count);
 364         dsb();
 365         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,pc->pwm_ctrl);
 366 }
 367 //#define grf_readl(offset)     readl_relaxed(RK_GRF_VIRT + offset)
 368 //#define grf_writel(v, offset) do { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(); } while (0)
 369 /* config for rockchip,pwm*/
 370 static int  rk_pwm_config_v3(struct pwm_chip *chip, struct pwm_device *pwm,
 371                             int duty_ns, int period_ns)
 372 {
 373         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 374         u64 val, div, clk_rate;
 375         unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
 376         int  ret;
 377         u32 on;
 378         int conf=0;
 379        unsigned long flags;
 380        spinlock_t *lock;
 381
 382        lock = (&pc->lock);//&pwm_lock[pwm->hwpwm];
 383         on   =  RK_PWM_ENABLE ;
 384         conf = PWM_OUTPUT_LEFT|PWM_LP_DISABLE|
 385                             PWM_CONTINUMOUS|PWM_DUTY_POSTIVE|PWM_INACTIVE_NEGATIVE;
 386         /*
 387          * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
 388          * according to formulas described below:
 389          *
 390          * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
 391          * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
 392          *
 393          * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
 394          * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
 395          */
 396 #if PWM_CLK
 397         clk_rate = clk_get_rate(pc->clk);
 398 #else
 399         clk_rate = 24000000;
 400 #endif
 401         while (1) {
 402                 div = 1000000000;
 403                 div *= 1 + prescale;
 404                 val = clk_rate * period_ns;
 405                 pv = div64_u64(val, div);
 406                 val = clk_rate * duty_ns;
 407                 dc = div64_u64(val, div);
 408
 409                 /* if duty_ns and period_ns are not achievable then return */
 410                 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
 411                         return -EINVAL;
 412
 413                 /*
 414                  * if pv and dc have crossed their upper limit, then increase
 415                  * prescale and recalculate pv and dc.
 416                  */
 417                 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
 418                         if (++prescale > PWMCR_MAX_PRESCALE)
 419                                 return -EINVAL;
 420                         continue;
 421                 }
 422                 break;
 423         }
 424
 425         /*
 426          * NOTE: the clock to PWM has to be enabled first before writing to the
 427          * registers.
 428          */
 429
 430         ret = clk_enable(pc->clk);
 431         if (ret)
 432                 return ret;
 433         spin_lock_irqsave(lock, flags);
 434
 435         conf |= (prescale << RK_PWM_PRESCALE);
 436
 437         barrier();
 438 //      rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL,off);
 439
 440 //      dsb();
 441         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY,dc);   //   2    0x1900);// dc);
 442         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD,pv);   // 4 0x5dc0);//pv);
 443         rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CNTR,0);
 444         dsb();
 445         rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL,on|conf);
 446 #if 0
 447         //grf_writel(0x00030002,0x6c);
 448         DBG("VOP  iomux 0x%x\n", grf_readl(0x6c));
 449         DBG("VOP_REG_CTRL0x%x\n", rk_pwm_readl(pc, pwm->hwpwm, VOP_REG_CTRL));
 450         DBG("PWM_REG_DUTY0x%x\n", rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_DUTY));
 451         DBG("PWM_REG_PERIOD 0x%x\n", rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_PERIOD));
 452         DBG("VOP_REG_CNTR 0x%x\n", rk_pwm_readl(pc, pwm->hwpwm, VOP_REG_CNTR));
 453 #endif
 454         spin_unlock_irqrestore(lock, flags);
 455
 456         return 0;
 457 }
 458 static void rk_pwm_set_enable_v3(struct pwm_chip *chip, struct pwm_device *pwm,bool enable)
 459 {
 460         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 461         u32 val;
 462
 463         val = rk_pwm_readl(pc, pwm->hwpwm, VOP_REG_CTRL);
 464         if (enable)
 465                 val |= RK_PWM_ENABLE;
 466         else
 467                 val &= ~RK_PWM_ENABLE;
 468         rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL, val);
 469
 470 }
 471 static void rk_pwm_suspend_v3(struct pwm_chip *chip, struct pwm_device *pwm)
 472 {
 473         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 474         pc->pwm_ctrl      = rk_pwm_readl(pc, pwm->hwpwm,        VOP_REG_CTRL);
 475         pc->pwm_duty    =  rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_DUTY);//0x1900);// dc);
 476         pc->pwm_period = rk_pwm_readl(pc, pwm->hwpwm,  PWM_REG_PERIOD );//0x5dc0);//pv);
 477         pc->pwm_count  =  rk_pwm_readl(pc, pwm->hwpwm, VOP_REG_CNTR);
 478 }
 479 static void rk_pwm_resume_v3(struct pwm_chip *chip, struct pwm_device *pwm)
 480 {
 481         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 482
 483         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_DUTY,    pc->pwm_duty);//0x1900);// dc);
 484         rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_PERIOD, pc->pwm_period);//0x5dc0);//pv);
 485         rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CNTR,pc->pwm_count);
 486         dsb();
 487         rk_pwm_writel(pc, pwm->hwpwm, VOP_REG_CTRL,pc->pwm_ctrl);
 488 }
 489
 490
 491 static int  rk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 492                             int duty_ns, int period_ns)
 493 {
 494         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 495         int ret;
 496
 497         ret = pc->config(chip, pwm, duty_ns, period_ns);
 498
 499         return 0;
 500 }
 501 static int rk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 502 {
 503         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 504         int rc = 0;
 505
 506         rc = clk_enable(pc->clk);
 507         if (rc)
 508                 return rc;
 509
 510         pc->set_enable(chip, pwm,true);
 511         return 0;
 512 }
 513
 514 static void rk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 515 {
 516         struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
 517
 518         pc->set_enable(chip, pwm,false);
 519         clk_disable(pc->clk);
 520 }
 521
 522 static const struct pwm_ops rk_pwm_ops = {
 523         .config = rk_pwm_config,
 524         .enable = rk_pwm_enable,
 525         .disable = rk_pwm_disable,
 526         .owner = THIS_MODULE,
 527 };
 528
 529 struct rk_pwm_data{
 530         int   (*config)(struct pwm_chip *chip,  struct pwm_device *pwm, int duty_ns, int period_ns);
 531         void (*set_enable)(struct pwm_chip *chip, struct pwm_device *pwm,bool enable);
 532         void (*pwm_suspend)(struct pwm_chip *chip, struct pwm_device *pwm);
 533         void (*pwm_resume)(struct pwm_chip *chip, struct pwm_device *pwm);
 534
 535
 536 };
 537
 538 static struct rk_pwm_data rk_pwm_data_v1={
 539         .config = rk_pwm_config_v1,
 540         .set_enable = rk_pwm_set_enable_v1,
 541         .pwm_suspend = rk_pwm_suspend_v1,
 542         .pwm_resume = rk_pwm_resume_v1,
 543
 544 };
 545
 546 static struct rk_pwm_data rk_pwm_data_v2={
 547         .config = rk_pwm_config_v2,
 548         .set_enable = rk_pwm_set_enable_v2,
 549         .pwm_suspend = rk_pwm_suspend_v2,
 550         .pwm_resume = rk_pwm_resume_v2,
 551
 552 };
 553
 554 static struct rk_pwm_data rk_pwm_data_v3={
 555         .config = rk_pwm_config_v3,
 556         .set_enable = rk_pwm_set_enable_v3,
 557         .pwm_suspend = rk_pwm_suspend_v3,
 558         .pwm_resume = rk_pwm_resume_v3,
 559
 560 };
 561
 562 static const struct of_device_id rk_pwm_of_match[] = {
 563         { .compatible = "rockchip,pwm",          .data = &rk_pwm_data_v1,},
 564         { .compatible =  "rockchip,rk-pwm",    .data = &rk_pwm_data_v2,},
 565         { .compatible =  "rockchip,vop-pwm",  .data = &rk_pwm_data_v3,},
 566         { }
 567 };
 568
 569 MODULE_DEVICE_TABLE(of, rk_pwm_of_match);
 570 static int rk_pwm_probe(struct platform_device *pdev)
 571 {
 572         const struct of_device_id *of_id =
 573                 of_match_device(rk_pwm_of_match, &pdev->dev);
 574         struct device_node *np = pdev->dev.of_node;
 575         const struct rk_pwm_data *data;
 576         struct rk_pwm_chip *pc;
 577         int ret;
 578
 579         if (!of_id){
 580                 dev_err(&pdev->dev, "failed to match device\n");
 581                 return -ENODEV;
 582         }
 583         pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
 584         if (!pc) {
 585                 dev_err(&pdev->dev, "failed to allocate memory\n");
 586                 return -ENOMEM;
 587         }
 588 #if 0
 589         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 590         if (!r) {
 591                 dev_err(&pdev->dev, "no memory resources defined\n");
 592                 return -ENODEV;
 593         }
 594         pc->base = devm_ioremap_resource(&pdev->dev, r);
 595         if (IS_ERR(pc->base))
 596                 return PTR_ERR(pc->base);
 597 #endif
 598         pc->base = of_iomap(np, 0);
 599         if (IS_ERR(pc->base)){
 600                 printk("PWM base ERR \n");
 601                 return PTR_ERR(pc->base);
 602         }
 603         pc->clk = devm_clk_get(&pdev->dev,"pclk_pwm");
 604         if (IS_ERR(pc->clk))
 605                 return PTR_ERR(pc->clk);
 606
 607         platform_set_drvdata(pdev, pc);
 608         data = of_id->data;
 609         pc->config = data->config;
 610         pc->set_enable = data->set_enable;
 611         pc->pwm_suspend = data->pwm_suspend;
 612         pc->pwm_resume = data->pwm_resume;
 613         pc->chip.dev = &pdev->dev;
 614         pc->chip.ops = &rk_pwm_ops;
 615         pc->chip.base = -1;
 616         pc->chip.npwm = NUM_PWM;
 617         pc->lock = __SPIN_LOCK_UNLOCKED(PWM##spinlock_num);
 618         spinlock_num ++;
 619 #if PWM_CLK
 620         ret = clk_prepare(pc->clk);
 621         if (ret)
 622                 return ret;
 623 #endif
 624
 625         ret = clk_enable(pc->clk);
 626         if (ret) {
 627                 clk_unprepare(pc->clk);
 628                 return ret;
 629         }
 630         /* Following enables PWM chip, channels would still be enabled individually through their control register */
 631         DBG("npwm = %d, of_pwm_ncells =%d \n", pc->chip.npwm,pc->chip.of_pwm_n_cells);
 632         ret = pwmchip_add(&pc->chip);
 633         if (ret < 0) {
 634                 clk_unprepare(pc->clk);
 635                 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
 636         }
 637
 638         DBG("%s end \n",__FUNCTION__);
 639         return ret;
 640 }
 641 #if 0
 642 //(struct platform_device *, pm_message_t state);
 643 static int rk_pwm_suspend(struct platform_device *pdev, pm_message_t state)
 644 {
 645         struct pwm_device *pwm;
 646         struct rk_pwm_chip *pc;
 647         struct pwm_chip *chip;
 648
 649         pc = platform_get_drvdata(pdev);
 650         chip = &(pc->chip);
 651         pwm = chip->pwms;
 652
 653         pc->pwm_suspend(chip,pwm);
 654
 655         return 0;//pwmchip_remove(&pc->chip);
 656 }
 657 static int rk_pwm_resume(struct platform_device *pdev)
 658 {
 659         struct pwm_device *pwm;
 660         struct rk_pwm_chip *pc;
 661         struct pwm_chip *chip;
 662
 663         pc = platform_get_drvdata(pdev);
 664         chip = &(pc->chip);
 665         pwm = chip->pwms;
 666
 667         pc->pwm_resume(chip,pwm);
 668         return 0;//pwmchip_remove(&pc->chip);
 669 }
 670 #endif
 671 static int rk_pwm_remove(struct platform_device *pdev)
 672 {
 673         return 0;//pwmchip_remove(&pc->chip);
 674 }
 675
 676 static struct platform_driver rk_pwm_driver = {
 677         .driver = {
 678                 .name = "rk-pwm",
 679                 .of_match_table = rk_pwm_of_match,
 680         },
 681         .probe = rk_pwm_probe,
 682         .remove = rk_pwm_remove,
 683 };
 684
 685 module_platform_driver(rk_pwm_driver);
 686
 687 MODULE_LICENSE("GPL");
 688 MODULE_AUTHOR("<xsf@rock-chips.com>");
 689 MODULE_ALIAS("platform:rk-pwm");
 690
 691