5 #include <linux/ioport.h>
6 #include <linux/kernel.h>
7 #include <linux/math64.h>
8 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/pwm.h>
12 #include <linux/slab.h>
13 #include <linux/types.h>
14 #include <linux/spinlock.h>
20 #define PWM_REG_CNTR 0x00 /* Counter Register */
21 #define PWM_REG_PERIOD 0x04 /* Period Register */
22 #define PWM_REG_DUTY 0x08 /* Duty Cycle Register */
23 #define PWM_REG_CTRL 0x0c /* Control Register */
27 #define PWM_ENABLE (1 << 0)
28 #define PWM_DISABLE (0 << 0)
30 #define PWM_SHOT (0x00 << 1)
31 #define PWM_CONTINUMOUS (0x01 << 1)
32 #define PWM_CAPTURE (0x01 << 1)
34 #define PWM_DUTY_POSTIVE (0x01 << 3)
35 #define PWM_DUTY_NEGATIVE (0x00 << 3)
37 #define PWM_INACTIVE_POSTIVE (0x01 << 4)
38 #define PWM_INACTIVE_NEGATIVE (0x00 << 4)
40 #define PWM_OUTPUT_LEFT (0x00 << 5)
41 #define PWM_OUTPUT_ENTER (0x01 << 5)
44 #define PWM_LP_ENABLE (1<<8)
45 #define PWM_LP_DISABLE (0<<8)
47 #define PWM_CLK_SCALE (1 << 9)
48 #define PWM_CLK_NON_SCALE (0 << 9)
52 #define PWMCR_MIN_PRESCALE 0x00
54 #define PWMCR_MIN_PRESCALE 0x00
55 #define PWMCR_MAX_PRESCALE 0x07
57 #define PWMDCR_MIN_DUTY 0x0001
58 #define PWMDCR_MAX_DUTY 0xFFFF
60 #define PWMPCR_MIN_PERIOD 0x0001
61 #define PWMPCR_MAX_PERIOD 0xFFFF
65 PWM_DIV1 = (0x0 << 12),
66 PWM_DIV2 = (0x1 << 12),
67 PWM_DIV4 = (0x2 << 12),
68 PWM_DIV8 = (0x3 << 12),
69 PWM_DIV16 = (0x4 << 12),
70 PWM_DIV32 = (0x5 << 12),
71 PWM_DIV64 = (0x6 << 12),
72 PWM_DIV128 = (0x7 << 12),
75 static int pwm_dbg_level = 0;
76 module_param_named(dbg_level, pwm_dbg_level, int, 0644);
77 #define DBG( args...) \
79 if (pwm_dbg_level) { \
84 #define PWM_REG_CNTR 0x00
85 #define PWM_REG_HRC 0x04
86 #define PWM_REG_LRC 0x08
87 #define PWM_REG_CTRL 0x0c
90 #define PWM_REG_PERIOD PWM_REG_HRC /* Period Register */
91 #define PWM_REG_DUTY PWM_REG_LRC /* Duty Cycle Register */
92 //#define PWM_REG_CTRL 0x0c /* Control Register */
96 #define PWM_DIV_MASK (0xf << 9)
97 #define PWM_CAPTURE (1 << 8)
98 #define PWM_RESET (1 << 7)
99 #define PWM_INTCLR (1 << 6)
100 #define PWM_INTEN (1 << 5)
101 #define PWM_SINGLE (1 << 4)
103 #define PWM_ENABLE (1 << 3)
104 #define PWM_TIMER_EN (1 << 0)
105 #define PWM_TimeEN PWM_TIMER_EN
106 #define PWMCR_MIN_PRESCALE 0x00
108 #define PWMCR_MIN_PRESCALE 0x00
109 #define PWMCR_MAX_PRESCALE 0x07
111 #define PWMDCR_MIN_DUTY 0x0001
112 #define PWMDCR_MAX_DUTY 0xFFFF
114 #define PWMPCR_MIN_PERIOD 0x0001
115 #define PWMPCR_MAX_PERIOD 0xFFFF
118 * struct rk_pwm_chip - struct representing pwm chip
120 * @base: base address of pwm chip
121 * @clk: pointer to clk structure of pwm chip
122 * @chip: linux pwm chip representation
125 static spinlock_t pwm_lock[4] = {
126 __SPIN_LOCK_UNLOCKED(pwm_lock0),
127 __SPIN_LOCK_UNLOCKED(pwm_lock1),
128 __SPIN_LOCK_UNLOCKED(pwm_lock2),
129 __SPIN_LOCK_UNLOCKED(pwm_lock3),
135 struct pwm_chip chip;
140 static void __iomem *rk30_grf_base = NULL;
141 static void __iomem *rk30_cru_base = NULL;
142 static void __iomem *rk30_pwm_base = NULL;
143 //#define SZ_16K 0x4000
144 //#define SZ_8K 0x2000
145 #define RK30_GRF_PHYS 0x20008000
146 #define RK30_GRF_SIZE SZ_8K
147 #define RK30_CRU_PHYS 0x20000000
148 #define RK30_CRU_SIZE SZ_16K
149 #define RK30_PWM_PHYS 0x20050000
150 #define RK30_PWM_SIZE SZ_16K
152 static void dump_register_of_pwm(void)
155 //rk30_grf_base = ioremap(RK30_GRF_PHYS, RK30_GRF_SIZE);
156 // rk30_cru_base = ioremap(RK30_CRU_PHYS, RK30_CRU_SIZE);
157 //rk30_pwm_base = ioremap(RK30_PWM_PHYS, RK30_PWM_SIZE);
159 // DBG("GRF IOMUX GPIO3_D6 = 0x%08x\n",readl_relaxed(rk30_grf_base+ 0x9C) );
160 //DBG("CRU = 0x%08x\n",readl_relaxed(rk30_cru_base+ 0xeC) );
161 //writel_relaxed(0x10001000, rk30_grf_base+ 0x9C);
162 //DBG("GRF IOMUX GPIO3_D6 = 0x%08x\n",readl_relaxed(rk30_grf_base+ 0x9C) );
163 //DBG("CRU = 0x%08x\n",readl_relaxed(rk30_cru_base+ 0xeC) );
167 writel_relaxed(off, rk30_pwm_base+3*0x10+ PWM_REG_CTRL);
170 writel_relaxed(0x1900, rk30_pwm_base+3*0x10+ PWM_REG_HRC);//rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_HRC,0x1900);// dc);
171 writel_relaxed(0x5dc0, rk30_pwm_base+3*0x10+ PWM_REG_LRC);//rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_LRC, 0x5dc0);//pv);
172 writel_relaxed(0, rk30_pwm_base+3*0x10+ PWM_REG_CNTR);//rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,0);
174 writel_relaxed(0x09, rk30_pwm_base+3*0x10+ PWM_REG_CTRL);// rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,on);
178 static void dump_pwm_register(struct rk_pwm_chip *chip)
180 DBG("dump pwm regitster start\n");
183 DBG("PWM_REG_CTRL =0x%08x\n",rk_pwm_readl(chip, 0, PWM_REG_CTRL));
184 DBG("PWM_REG_HRC = 0x%08x\n",rk_pwm_readl(chip,0, PWM_REG_HRC));
185 DBG("PWM_REG_LRC = 0x%08x\n",rk_pwm_readl(chip,0, PWM_REG_LRC));
186 DBG("PWM_REG_CNTR = 0x%08x\n",rk_pwm_readl(chip,0, PWM_REG_CNTR));
189 DBG("PWM_REG_CTRL =0x%08x\n",rk_pwm_readl(chip, 1, PWM_REG_CTRL));
190 DBG("PWM_REG_HRC = 0x%08x\n",rk_pwm_readl(chip,1, PWM_REG_HRC));
191 DBG("PWM_REG_LRC = 0x%08x\n",rk_pwm_readl(chip,1, PWM_REG_LRC));
192 DBG("PWM_REG_CNTR = 0x%08x\n",rk_pwm_readl(chip,1, PWM_REG_CNTR));
195 DBG("PWM_REG_CTRL =0x%08x\n",rk_pwm_readl(chip, 2, PWM_REG_CTRL));
196 DBG("PWM_REG_HRC = 0x%08x\n",rk_pwm_readl(chip,2, PWM_REG_HRC));
197 DBG("PWM_REG_LRC = 0x%08x\n",rk_pwm_readl(chip,2, PWM_REG_LRC));
198 DBG("PWM_REG_CNTR = 0x%08x\n",rk_pwm_readl(chip,2, PWM_REG_CNTR));
201 DBG("PWM_REG_CTRL =0x%08x\n",rk_pwm_readl(chip,3, PWM_REG_CTRL));
202 DBG("PWM_REG_HRC = 0x%08x\n",rk_pwm_readl(chip,3, PWM_REG_HRC));
203 DBG("PWM_REG_LRC = 0x%08x\n",rk_pwm_readl(chip,3, PWM_REG_LRC));
204 DBG("PWM_REG_CNTR = 0x%08x\n",rk_pwm_readl(chip,3, PWM_REG_CNTR));
206 printk("dump pwm regitster end\n");
211 static inline struct rk_pwm_chip *to_rk_pwm_chip(struct pwm_chip *chip)
213 return container_of(chip, struct rk_pwm_chip, chip);
216 static inline u32 rk_pwm_readl(struct rk_pwm_chip *chip, unsigned int num,
217 unsigned long offset)
219 return readl_relaxed(chip->base + (num << 4) + offset);
222 static inline void rk_pwm_writel(struct rk_pwm_chip *chip,
223 unsigned int num, unsigned long offset,
226 writel_relaxed(val, chip->base + (num << 4) + offset);
232 static int __rk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
233 int duty_ns, int period_ns)
235 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
236 u64 val, div, clk_rate;
237 unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc;
243 on = PWM_ENABLE | PWM_TIMER_EN;
245 //dump_pwm_register(pc);
248 * Find pv, dc and prescale to suit duty_ns and period_ns. This is done
249 * according to formulas described below:
251 * period_ns = 10^9 * (PRESCALE ) * PV / PWM_CLK_RATE
252 * duty_ns = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
254 * PV = (PWM_CLK_RATE * period_ns) / (10^9 * (PRESCALE + 1))
255 * DC = (PWM_CLK_RATE * duty_ns) / (10^9 * (PRESCALE + 1))
258 clk_rate = clk_get_rate(pc->clk);
265 val = clk_rate * period_ns;
266 pv = div64_u64(val, div);
267 val = clk_rate * duty_ns;
268 dc = div64_u64(val, div);
270 /* if duty_ns and period_ns are not achievable then return */
271 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY)
275 * if pv and dc have crossed their upper limit, then increase
276 * prescale and recalculate pv and dc.
278 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) {
279 if (++prescale > PWMCR_MAX_PRESCALE)
287 * NOTE: the clock to PWM has to be enabled first before writing to the
290 conf |= (prescale << 9);
292 ret = clk_enable(pc->clk);
298 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,off);
301 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_HRC,dc);//0x1900);// dc);
302 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_LRC, pv);//0x5dc0);//pv);
303 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CNTR,0);
305 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL,on|conf);
309 clk_disable(pc->clk);
315 static int rk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
316 int duty_ns, int period_ns)
321 lock = &pwm_lock[pwm->hwpwm];
322 spin_lock_irqsave(lock, flags);
323 __rk_pwm_config(chip, pwm, duty_ns, period_ns);
324 spin_unlock_irqrestore(lock, flags);
328 static int rk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
330 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
334 rc = clk_enable(pc->clk);
338 val = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
340 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL, val);
345 static void rk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
347 struct rk_pwm_chip *pc = to_rk_pwm_chip(chip);
350 val = rk_pwm_readl(pc, pwm->hwpwm, PWM_REG_CTRL);
352 rk_pwm_writel(pc, pwm->hwpwm, PWM_REG_CTRL, val);
354 clk_disable(pc->clk);
359 static const struct pwm_ops rk_pwm_ops = {
360 .config = rk_pwm_config,
361 .enable = rk_pwm_enable,
362 .disable = rk_pwm_disable,
363 .owner = THIS_MODULE,
368 static int rk_pwm_probe(struct platform_device *pdev)
370 struct device_node *np = pdev->dev.of_node;
371 struct rk_pwm_chip *pc;
374 DBG("%s start \n",__FUNCTION__);
375 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
377 dev_err(&pdev->dev, "no memory resources defined\n");
380 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
382 dev_err(&pdev->dev, "failed to allocate memory\n");
385 pc->base = devm_ioremap_resource(&pdev->dev, r);
386 if (IS_ERR(pc->base))
387 return PTR_ERR(pc->base);
390 //pc->clk = devm_clk_get(&pdev->dev, NULL);
391 pc->clk = clk_get(NULL,"g_p_pwm23");
395 return PTR_ERR(pc->clk);
398 platform_set_drvdata(pdev, pc);
400 pc->chip.dev = &pdev->dev;
401 pc->chip.ops = &rk_pwm_ops;
403 pc->chip.npwm = NUM_PWM;
406 ret = clk_prepare(pc->clk);
412 if (of_device_is_compatible(np, "rockchip,pwm")) {
413 ret = clk_enable(pc->clk);
415 clk_unprepare(pc->clk);
419 * Following enables PWM chip, channels would still be
420 * enabled individually through their control register
423 // clk_disable(pc->clk);
427 DBG("npwm = %d, of_pwm_ncells =%d \n", pc->chip.npwm,pc->chip.of_pwm_n_cells);
428 ret = pwmchip_add(&pc->chip);
430 clk_unprepare(pc->clk);
431 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
433 DBG("%s end \n",__FUNCTION__);
438 static int rk_pwm_remove(struct platform_device *pdev)
440 return 0;//pwmchip_remove(&pc->chip);
444 static const struct of_device_id rk_pwm_of_match[] = {
445 { .compatible = "rockchip,pwm" },
449 MODULE_DEVICE_TABLE(of, rk_pwm_of_match);
451 static struct platform_driver rk_pwm_driver = {
454 .of_match_table = rk_pwm_of_match,
456 .probe = rk_pwm_probe,
457 .remove = rk_pwm_remove,
460 module_platform_driver(rk_pwm_driver);
462 MODULE_LICENSE("GPL");
463 MODULE_AUTHOR("<xsf@rock-chips.com>");
464 MODULE_ALIAS("platform:rk-pwm");