2 * Copyright (C) ST-Ericsson SA 2010
4 * License Terms: GNU General Public License v2
6 * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
7 * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
8 * Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
10 * AB8500 peripheral regulators
12 * AB8500 supports the following regulators:
13 * VAUX1/2/3, VINTCORE, VTVOUT, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
15 * AB8505 supports the following regulators:
16 * VAUX1/2/3/4/5/6, VINTCORE, VADC, VUSB, VAUDIO, VAMIC1/2, VDMIC, VANA
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/err.h>
22 #include <linux/platform_device.h>
23 #include <linux/mfd/abx500.h>
24 #include <linux/mfd/abx500/ab8500.h>
26 #include <linux/regulator/of_regulator.h>
27 #include <linux/regulator/driver.h>
28 #include <linux/regulator/machine.h>
29 #include <linux/regulator/ab8500.h>
30 #include <linux/slab.h>
33 * struct ab8500_regulator_info - ab8500 regulator information
34 * @dev: device pointer
35 * @desc: regulator description
36 * @regulator_dev: regulator device
37 * @is_enabled: status of regulator (on/off)
38 * @load_lp_uA: maximum load in idle (low power) mode
39 * @update_bank: bank to control on/off
40 * @update_reg: register to control on/off
41 * @update_mask: mask to enable/disable and set mode of regulator
42 * @update_val: bits holding the regulator current mode
43 * @update_val_idle: bits to enable the regulator in idle (low power) mode
44 * @update_val_normal: bits to enable the regulator in normal (high power) mode
45 * @voltage_bank: bank to control regulator voltage
46 * @voltage_reg: register to control regulator voltage
47 * @voltage_mask: mask to control regulator voltage
48 * @voltage_shift: shift to control regulator voltage
50 struct ab8500_regulator_info {
52 struct regulator_desc desc;
53 struct regulator_dev *regulator;
68 /* voltage tables for the vauxn/vintcore supplies */
69 static const unsigned int ldo_vauxn_voltages[] = {
88 static const unsigned int ldo_vaux3_voltages[] = {
99 static const unsigned int ldo_vaux56_voltages[] = {
110 static const unsigned int ldo_vaux3_ab8540_voltages[] = {
122 static const unsigned int ldo_vintcore_voltages[] = {
132 static const unsigned int ldo_sdio_voltages[] = {
143 static const unsigned int fixed_1200000_voltage[] = {
147 static const unsigned int fixed_1800000_voltage[] = {
151 static const unsigned int fixed_2000000_voltage[] = {
155 static const unsigned int fixed_2050000_voltage[] = {
159 static const unsigned int fixed_3300000_voltage[] = {
163 static const unsigned int ldo_vana_voltages[] = {
174 static const unsigned int ldo_vaudio_voltages[] = {
182 2600000, /* Duplicated in Vaudio and IsoUicc Control register. */
185 static int ab8500_regulator_enable(struct regulator_dev *rdev)
188 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
191 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
195 ret = abx500_mask_and_set_register_interruptible(info->dev,
196 info->update_bank, info->update_reg,
197 info->update_mask, info->update_val);
199 dev_err(rdev_get_dev(rdev),
200 "couldn't set enable bits for regulator\n");
204 info->is_enabled = true;
206 dev_vdbg(rdev_get_dev(rdev),
207 "%s-enable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
208 info->desc.name, info->update_bank, info->update_reg,
209 info->update_mask, info->update_val);
214 static int ab8500_regulator_disable(struct regulator_dev *rdev)
217 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
220 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
224 ret = abx500_mask_and_set_register_interruptible(info->dev,
225 info->update_bank, info->update_reg,
226 info->update_mask, 0x0);
228 dev_err(rdev_get_dev(rdev),
229 "couldn't set disable bits for regulator\n");
233 info->is_enabled = false;
235 dev_vdbg(rdev_get_dev(rdev),
236 "%s-disable (bank, reg, mask, value): 0x%x, 0x%x, 0x%x, 0x%x\n",
237 info->desc.name, info->update_bank, info->update_reg,
238 info->update_mask, 0x0);
243 static unsigned int ab8500_regulator_get_optimum_mode(
244 struct regulator_dev *rdev, int input_uV,
245 int output_uV, int load_uA)
249 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
252 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
256 if (load_uA <= info->load_lp_uA)
257 mode = REGULATOR_MODE_IDLE;
259 mode = REGULATOR_MODE_NORMAL;
264 static int ab8500_regulator_set_mode(struct regulator_dev *rdev,
269 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
272 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
277 case REGULATOR_MODE_NORMAL:
278 update_val = info->update_val_normal;
280 case REGULATOR_MODE_IDLE:
281 update_val = info->update_val_idle;
287 /* ab8500 regulators share mode and enable in the same register bits.
290 full powermode = 0b01
291 (HW control mode = 0b10)
292 Thus we don't write to the register when regulator is disabled.
294 if (info->is_enabled) {
295 ret = abx500_mask_and_set_register_interruptible(info->dev,
296 info->update_bank, info->update_reg,
297 info->update_mask, update_val);
299 dev_err(rdev_get_dev(rdev),
300 "couldn't set regulator mode\n");
304 dev_vdbg(rdev_get_dev(rdev),
305 "%s-set_mode (bank, reg, mask, value): "
306 "0x%x, 0x%x, 0x%x, 0x%x\n",
307 info->desc.name, info->update_bank, info->update_reg,
308 info->update_mask, update_val);
311 info->update_val = update_val;
316 static unsigned int ab8500_regulator_get_mode(struct regulator_dev *rdev)
318 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
322 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
326 if (info->update_val == info->update_val_normal)
327 ret = REGULATOR_MODE_NORMAL;
328 else if (info->update_val == info->update_val_idle)
329 ret = REGULATOR_MODE_IDLE;
336 static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
339 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
343 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
347 ret = abx500_get_register_interruptible(info->dev,
348 info->update_bank, info->update_reg, ®val);
350 dev_err(rdev_get_dev(rdev),
351 "couldn't read 0x%x register\n", info->update_reg);
355 dev_vdbg(rdev_get_dev(rdev),
356 "%s-is_enabled (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
358 info->desc.name, info->update_bank, info->update_reg,
359 info->update_mask, regval);
361 if (regval & info->update_mask)
362 info->is_enabled = true;
364 info->is_enabled = false;
366 return info->is_enabled;
369 static int ab8500_regulator_get_voltage_sel(struct regulator_dev *rdev)
372 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
376 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
380 ret = abx500_get_register_interruptible(info->dev,
381 info->voltage_bank, info->voltage_reg, ®val);
383 dev_err(rdev_get_dev(rdev),
384 "couldn't read voltage reg for regulator\n");
388 dev_vdbg(rdev_get_dev(rdev),
389 "%s-get_voltage (bank, reg, mask, shift, value): "
390 "0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
391 info->desc.name, info->voltage_bank,
392 info->voltage_reg, info->voltage_mask,
393 info->voltage_shift, regval);
395 val = regval & info->voltage_mask;
396 return val >> info->voltage_shift;
399 static int ab8500_regulator_set_voltage_sel(struct regulator_dev *rdev,
403 struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
407 dev_err(rdev_get_dev(rdev), "regulator info null pointer\n");
411 /* set the registers for the request */
412 regval = (u8)selector << info->voltage_shift;
413 ret = abx500_mask_and_set_register_interruptible(info->dev,
414 info->voltage_bank, info->voltage_reg,
415 info->voltage_mask, regval);
417 dev_err(rdev_get_dev(rdev),
418 "couldn't set voltage reg for regulator\n");
420 dev_vdbg(rdev_get_dev(rdev),
421 "%s-set_voltage (bank, reg, mask, value): 0x%x, 0x%x, 0x%x,"
423 info->desc.name, info->voltage_bank, info->voltage_reg,
424 info->voltage_mask, regval);
429 static struct regulator_ops ab8500_regulator_volt_mode_ops = {
430 .enable = ab8500_regulator_enable,
431 .disable = ab8500_regulator_disable,
432 .is_enabled = ab8500_regulator_is_enabled,
433 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
434 .set_mode = ab8500_regulator_set_mode,
435 .get_mode = ab8500_regulator_get_mode,
436 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
437 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
438 .list_voltage = regulator_list_voltage_table,
441 static struct regulator_ops ab8500_regulator_volt_ops = {
442 .enable = ab8500_regulator_enable,
443 .disable = ab8500_regulator_disable,
444 .is_enabled = ab8500_regulator_is_enabled,
445 .get_voltage_sel = ab8500_regulator_get_voltage_sel,
446 .set_voltage_sel = ab8500_regulator_set_voltage_sel,
447 .list_voltage = regulator_list_voltage_table,
448 .set_voltage_time_sel = ab8500_regulator_set_voltage_time_sel,
451 static struct regulator_ops ab8500_regulator_mode_ops = {
452 .enable = ab8500_regulator_enable,
453 .disable = ab8500_regulator_disable,
454 .is_enabled = ab8500_regulator_is_enabled,
455 .get_optimum_mode = ab8500_regulator_get_optimum_mode,
456 .set_mode = ab8500_regulator_set_mode,
457 .get_mode = ab8500_regulator_get_mode,
458 .list_voltage = regulator_list_voltage_linear,
461 static struct regulator_ops ab8500_regulator_ops = {
462 .enable = ab8500_regulator_enable,
463 .disable = ab8500_regulator_disable,
464 .is_enabled = ab8500_regulator_is_enabled,
465 .list_voltage = regulator_list_voltage_linear,
468 /* AB8500 regulator information */
469 static struct ab8500_regulator_info
470 ab8500_regulator_info[AB8500_NUM_REGULATORS] = {
472 * Variable Voltage Regulators
473 * name, min mV, max mV,
474 * update bank, reg, mask, enable val
475 * volt bank, reg, mask
477 [AB8500_LDO_AUX1] = {
480 .ops = &ab8500_regulator_volt_mode_ops,
481 .type = REGULATOR_VOLTAGE,
482 .id = AB8500_LDO_AUX1,
483 .owner = THIS_MODULE,
484 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
485 .volt_table = ldo_vauxn_voltages,
493 .update_val_idle = 0x03,
494 .update_val_normal = 0x01,
495 .voltage_bank = 0x04,
497 .voltage_mask = 0x0f,
499 [AB8500_LDO_AUX2] = {
502 .ops = &ab8500_regulator_volt_mode_ops,
503 .type = REGULATOR_VOLTAGE,
504 .id = AB8500_LDO_AUX2,
505 .owner = THIS_MODULE,
506 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
507 .volt_table = ldo_vauxn_voltages,
515 .update_val_idle = 0x0c,
516 .update_val_normal = 0x04,
517 .voltage_bank = 0x04,
519 .voltage_mask = 0x0f,
521 [AB8500_LDO_AUX3] = {
524 .ops = &ab8500_regulator_volt_mode_ops,
525 .type = REGULATOR_VOLTAGE,
526 .id = AB8500_LDO_AUX3,
527 .owner = THIS_MODULE,
528 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
529 .volt_table = ldo_vaux3_voltages,
537 .update_val_idle = 0x03,
538 .update_val_normal = 0x01,
539 .voltage_bank = 0x04,
541 .voltage_mask = 0x07,
543 [AB8500_LDO_INTCORE] = {
545 .name = "LDO-INTCORE",
546 .ops = &ab8500_regulator_volt_mode_ops,
547 .type = REGULATOR_VOLTAGE,
548 .id = AB8500_LDO_INTCORE,
549 .owner = THIS_MODULE,
550 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
551 .volt_table = ldo_vintcore_voltages,
559 .update_val_idle = 0x44,
560 .update_val_normal = 0x04,
561 .voltage_bank = 0x03,
563 .voltage_mask = 0x38,
568 * Fixed Voltage Regulators
570 * update bank, reg, mask, enable val
572 [AB8500_LDO_TVOUT] = {
575 .ops = &ab8500_regulator_mode_ops,
576 .type = REGULATOR_VOLTAGE,
577 .id = AB8500_LDO_TVOUT,
578 .owner = THIS_MODULE,
580 .volt_table = fixed_2000000_voltage,
588 .update_val_idle = 0x82,
589 .update_val_normal = 0x02,
591 [AB8500_LDO_AUDIO] = {
594 .ops = &ab8500_regulator_ops,
595 .type = REGULATOR_VOLTAGE,
596 .id = AB8500_LDO_AUDIO,
597 .owner = THIS_MODULE,
600 .volt_table = fixed_2000000_voltage,
607 [AB8500_LDO_ANAMIC1] = {
609 .name = "LDO-ANAMIC1",
610 .ops = &ab8500_regulator_ops,
611 .type = REGULATOR_VOLTAGE,
612 .id = AB8500_LDO_ANAMIC1,
613 .owner = THIS_MODULE,
616 .volt_table = fixed_2050000_voltage,
623 [AB8500_LDO_ANAMIC2] = {
625 .name = "LDO-ANAMIC2",
626 .ops = &ab8500_regulator_ops,
627 .type = REGULATOR_VOLTAGE,
628 .id = AB8500_LDO_ANAMIC2,
629 .owner = THIS_MODULE,
632 .volt_table = fixed_2050000_voltage,
639 [AB8500_LDO_DMIC] = {
642 .ops = &ab8500_regulator_ops,
643 .type = REGULATOR_VOLTAGE,
644 .id = AB8500_LDO_DMIC,
645 .owner = THIS_MODULE,
648 .volt_table = fixed_1800000_voltage,
657 * Regulators with fixed voltage and normal/idle modes
662 .ops = &ab8500_regulator_mode_ops,
663 .type = REGULATOR_VOLTAGE,
664 .id = AB8500_LDO_ANA,
665 .owner = THIS_MODULE,
668 .volt_table = fixed_1200000_voltage,
675 .update_val_idle = 0x0c,
676 .update_val_normal = 0x04,
680 /* AB8505 regulator information */
681 static struct ab8500_regulator_info
682 ab8505_regulator_info[AB8505_NUM_REGULATORS] = {
684 * Variable Voltage Regulators
685 * name, min mV, max mV,
686 * update bank, reg, mask, enable val
687 * volt bank, reg, mask, table, table length
689 [AB8505_LDO_AUX1] = {
692 .ops = &ab8500_regulator_volt_mode_ops,
693 .type = REGULATOR_VOLTAGE,
694 .id = AB8505_LDO_AUX1,
695 .owner = THIS_MODULE,
696 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
697 .volt_table = ldo_vauxn_voltages,
704 .update_val_idle = 0x03,
705 .update_val_normal = 0x01,
706 .voltage_bank = 0x04,
708 .voltage_mask = 0x0f,
710 [AB8505_LDO_AUX2] = {
713 .ops = &ab8500_regulator_volt_mode_ops,
714 .type = REGULATOR_VOLTAGE,
715 .id = AB8505_LDO_AUX2,
716 .owner = THIS_MODULE,
717 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
718 .volt_table = ldo_vauxn_voltages,
725 .update_val_idle = 0x0c,
726 .update_val_normal = 0x04,
727 .voltage_bank = 0x04,
729 .voltage_mask = 0x0f,
731 [AB8505_LDO_AUX3] = {
734 .ops = &ab8500_regulator_volt_mode_ops,
735 .type = REGULATOR_VOLTAGE,
736 .id = AB8505_LDO_AUX3,
737 .owner = THIS_MODULE,
738 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
739 .volt_table = ldo_vaux3_voltages,
746 .update_val_idle = 0x03,
747 .update_val_normal = 0x01,
748 .voltage_bank = 0x04,
750 .voltage_mask = 0x07,
752 [AB8505_LDO_AUX4] = {
755 .ops = &ab8500_regulator_volt_mode_ops,
756 .type = REGULATOR_VOLTAGE,
757 .id = AB8505_LDO_AUX4,
758 .owner = THIS_MODULE,
759 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
760 .volt_table = ldo_vauxn_voltages,
763 /* values for Vaux4Regu register */
768 .update_val_idle = 0x03,
769 .update_val_normal = 0x01,
770 /* values for Vaux4SEL register */
771 .voltage_bank = 0x04,
773 .voltage_mask = 0x0f,
775 [AB8505_LDO_AUX5] = {
778 .ops = &ab8500_regulator_volt_mode_ops,
779 .type = REGULATOR_VOLTAGE,
780 .id = AB8505_LDO_AUX5,
781 .owner = THIS_MODULE,
782 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
783 .volt_table = ldo_vaux56_voltages,
786 /* values for CtrlVaux5 register */
791 .update_val_idle = 0x18,
792 .update_val_normal = 0x10,
793 .voltage_bank = 0x01,
795 .voltage_mask = 0x07,
797 [AB8505_LDO_AUX6] = {
800 .ops = &ab8500_regulator_volt_mode_ops,
801 .type = REGULATOR_VOLTAGE,
802 .id = AB8505_LDO_AUX6,
803 .owner = THIS_MODULE,
804 .n_voltages = ARRAY_SIZE(ldo_vaux56_voltages),
805 .volt_table = ldo_vaux56_voltages,
808 /* values for CtrlVaux6 register */
813 .update_val_idle = 0x18,
814 .update_val_normal = 0x10,
815 .voltage_bank = 0x01,
817 .voltage_mask = 0x07,
819 [AB8505_LDO_INTCORE] = {
821 .name = "LDO-INTCORE",
822 .ops = &ab8500_regulator_volt_mode_ops,
823 .type = REGULATOR_VOLTAGE,
824 .id = AB8505_LDO_INTCORE,
825 .owner = THIS_MODULE,
826 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
827 .volt_table = ldo_vintcore_voltages,
834 .update_val_idle = 0x44,
835 .update_val_normal = 0x04,
836 .voltage_bank = 0x03,
838 .voltage_mask = 0x38,
843 * Fixed Voltage Regulators
845 * update bank, reg, mask, enable val
850 .ops = &ab8500_regulator_mode_ops,
851 .type = REGULATOR_VOLTAGE,
852 .id = AB8505_LDO_ADC,
853 .owner = THIS_MODULE,
855 .volt_table = fixed_2000000_voltage,
863 .update_val_idle = 0x82,
864 .update_val_normal = 0x02,
869 .ops = &ab8500_regulator_mode_ops,
870 .type = REGULATOR_VOLTAGE,
871 .id = AB8505_LDO_USB,
872 .owner = THIS_MODULE,
874 .volt_table = fixed_3300000_voltage,
880 .update_val_idle = 0x03,
881 .update_val_normal = 0x01,
883 [AB8505_LDO_AUDIO] = {
886 .ops = &ab8500_regulator_volt_ops,
887 .type = REGULATOR_VOLTAGE,
888 .id = AB8505_LDO_AUDIO,
889 .owner = THIS_MODULE,
890 .n_voltages = ARRAY_SIZE(ldo_vaudio_voltages),
891 .volt_table = ldo_vaudio_voltages,
897 .voltage_bank = 0x01,
901 .voltages = ldo_vaudio_voltages,
902 .voltages_len = ARRAY_SIZE(ldo_vaudio_voltages),
904 [AB8505_LDO_ANAMIC1] = {
906 .name = "LDO-ANAMIC1",
907 .ops = &ab8500_regulator_ops,
908 .type = REGULATOR_VOLTAGE,
909 .id = AB8505_LDO_ANAMIC1,
910 .owner = THIS_MODULE,
912 .volt_table = fixed_2050000_voltage,
919 [AB8505_LDO_ANAMIC2] = {
921 .name = "LDO-ANAMIC2",
922 .ops = &ab8500_regulator_ops,
923 .type = REGULATOR_VOLTAGE,
924 .id = AB8505_LDO_ANAMIC2,
925 .owner = THIS_MODULE,
927 .volt_table = fixed_2050000_voltage,
934 [AB8505_LDO_AUX8] = {
937 .ops = &ab8500_regulator_ops,
938 .type = REGULATOR_VOLTAGE,
939 .id = AB8505_LDO_AUX8,
940 .owner = THIS_MODULE,
942 .volt_table = fixed_1800000_voltage,
950 * Regulators with fixed voltage and normal/idle modes
955 .ops = &ab8500_regulator_volt_mode_ops,
956 .type = REGULATOR_VOLTAGE,
957 .id = AB8505_LDO_ANA,
958 .owner = THIS_MODULE,
959 .n_voltages = ARRAY_SIZE(ldo_vana_voltages),
960 .volt_table = ldo_vana_voltages,
967 .update_val_idle = 0x0c,
968 .update_val_normal = 0x04,
969 .voltage_bank = 0x04,
972 .voltages = ldo_vana_voltages,
973 .voltages_len = ARRAY_SIZE(ldo_vana_voltages),
977 /* AB9540 regulator information */
978 static struct ab8500_regulator_info
979 ab9540_regulator_info[AB9540_NUM_REGULATORS] = {
981 * Variable Voltage Regulators
982 * name, min mV, max mV,
983 * update bank, reg, mask, enable val
984 * volt bank, reg, mask, table, table length
986 [AB9540_LDO_AUX1] = {
989 .ops = &ab8500_regulator_volt_mode_ops,
990 .type = REGULATOR_VOLTAGE,
991 .id = AB9540_LDO_AUX1,
992 .owner = THIS_MODULE,
993 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
994 .volt_table = ldo_vauxn_voltages,
1001 .update_val_idle = 0x03,
1002 .update_val_normal = 0x01,
1003 .voltage_bank = 0x04,
1004 .voltage_reg = 0x1f,
1005 .voltage_mask = 0x0f,
1007 [AB9540_LDO_AUX2] = {
1010 .ops = &ab8500_regulator_volt_mode_ops,
1011 .type = REGULATOR_VOLTAGE,
1012 .id = AB9540_LDO_AUX2,
1013 .owner = THIS_MODULE,
1014 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1015 .volt_table = ldo_vauxn_voltages,
1018 .update_bank = 0x04,
1020 .update_mask = 0x0c,
1022 .update_val_idle = 0x0c,
1023 .update_val_normal = 0x04,
1024 .voltage_bank = 0x04,
1025 .voltage_reg = 0x20,
1026 .voltage_mask = 0x0f,
1028 [AB9540_LDO_AUX3] = {
1031 .ops = &ab8500_regulator_volt_mode_ops,
1032 .type = REGULATOR_VOLTAGE,
1033 .id = AB9540_LDO_AUX3,
1034 .owner = THIS_MODULE,
1035 .n_voltages = ARRAY_SIZE(ldo_vaux3_voltages),
1036 .volt_table = ldo_vaux3_voltages,
1039 .update_bank = 0x04,
1041 .update_mask = 0x03,
1043 .update_val_idle = 0x03,
1044 .update_val_normal = 0x01,
1045 .voltage_bank = 0x04,
1046 .voltage_reg = 0x21,
1047 .voltage_mask = 0x07,
1049 [AB9540_LDO_AUX4] = {
1052 .ops = &ab8500_regulator_volt_mode_ops,
1053 .type = REGULATOR_VOLTAGE,
1054 .id = AB9540_LDO_AUX4,
1055 .owner = THIS_MODULE,
1056 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1057 .volt_table = ldo_vauxn_voltages,
1060 /* values for Vaux4Regu register */
1061 .update_bank = 0x04,
1063 .update_mask = 0x03,
1065 .update_val_idle = 0x03,
1066 .update_val_normal = 0x01,
1067 /* values for Vaux4SEL register */
1068 .voltage_bank = 0x04,
1069 .voltage_reg = 0x2f,
1070 .voltage_mask = 0x0f,
1072 [AB9540_LDO_INTCORE] = {
1074 .name = "LDO-INTCORE",
1075 .ops = &ab8500_regulator_volt_mode_ops,
1076 .type = REGULATOR_VOLTAGE,
1077 .id = AB9540_LDO_INTCORE,
1078 .owner = THIS_MODULE,
1079 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
1080 .volt_table = ldo_vintcore_voltages,
1083 .update_bank = 0x03,
1085 .update_mask = 0x44,
1087 .update_val_idle = 0x44,
1088 .update_val_normal = 0x04,
1089 .voltage_bank = 0x03,
1090 .voltage_reg = 0x80,
1091 .voltage_mask = 0x38,
1096 * Fixed Voltage Regulators
1098 * update bank, reg, mask, enable val
1100 [AB9540_LDO_TVOUT] = {
1102 .name = "LDO-TVOUT",
1103 .ops = &ab8500_regulator_mode_ops,
1104 .type = REGULATOR_VOLTAGE,
1105 .id = AB9540_LDO_TVOUT,
1106 .owner = THIS_MODULE,
1108 .volt_table = fixed_2000000_voltage,
1112 .update_bank = 0x03,
1114 .update_mask = 0x82,
1116 .update_val_idle = 0x82,
1117 .update_val_normal = 0x02,
1119 [AB9540_LDO_USB] = {
1122 .ops = &ab8500_regulator_ops,
1123 .type = REGULATOR_VOLTAGE,
1124 .id = AB9540_LDO_USB,
1125 .owner = THIS_MODULE,
1127 .volt_table = fixed_3300000_voltage,
1129 .update_bank = 0x03,
1131 .update_mask = 0x03,
1133 .update_val_idle = 0x03,
1134 .update_val_normal = 0x01,
1136 [AB9540_LDO_AUDIO] = {
1138 .name = "LDO-AUDIO",
1139 .ops = &ab8500_regulator_ops,
1140 .type = REGULATOR_VOLTAGE,
1141 .id = AB9540_LDO_AUDIO,
1142 .owner = THIS_MODULE,
1144 .volt_table = fixed_2000000_voltage,
1146 .update_bank = 0x03,
1148 .update_mask = 0x02,
1151 [AB9540_LDO_ANAMIC1] = {
1153 .name = "LDO-ANAMIC1",
1154 .ops = &ab8500_regulator_ops,
1155 .type = REGULATOR_VOLTAGE,
1156 .id = AB9540_LDO_ANAMIC1,
1157 .owner = THIS_MODULE,
1159 .volt_table = fixed_2050000_voltage,
1161 .update_bank = 0x03,
1163 .update_mask = 0x08,
1166 [AB9540_LDO_ANAMIC2] = {
1168 .name = "LDO-ANAMIC2",
1169 .ops = &ab8500_regulator_ops,
1170 .type = REGULATOR_VOLTAGE,
1171 .id = AB9540_LDO_ANAMIC2,
1172 .owner = THIS_MODULE,
1174 .volt_table = fixed_2050000_voltage,
1176 .update_bank = 0x03,
1178 .update_mask = 0x10,
1181 [AB9540_LDO_DMIC] = {
1184 .ops = &ab8500_regulator_ops,
1185 .type = REGULATOR_VOLTAGE,
1186 .id = AB9540_LDO_DMIC,
1187 .owner = THIS_MODULE,
1189 .volt_table = fixed_1800000_voltage,
1191 .update_bank = 0x03,
1193 .update_mask = 0x04,
1198 * Regulators with fixed voltage and normal/idle modes
1200 [AB9540_LDO_ANA] = {
1203 .ops = &ab8500_regulator_mode_ops,
1204 .type = REGULATOR_VOLTAGE,
1205 .id = AB9540_LDO_ANA,
1206 .owner = THIS_MODULE,
1208 .volt_table = fixed_1200000_voltage,
1211 .update_bank = 0x04,
1213 .update_mask = 0x0c,
1215 .update_val_idle = 0x0c,
1216 .update_val_normal = 0x08,
1220 /* AB8540 regulator information */
1221 static struct ab8500_regulator_info
1222 ab8540_regulator_info[AB8540_NUM_REGULATORS] = {
1224 * Variable Voltage Regulators
1225 * name, min mV, max mV,
1226 * update bank, reg, mask, enable val
1227 * volt bank, reg, mask, table, table length
1229 [AB8540_LDO_AUX1] = {
1232 .ops = &ab8500_regulator_volt_mode_ops,
1233 .type = REGULATOR_VOLTAGE,
1234 .id = AB8540_LDO_AUX1,
1235 .owner = THIS_MODULE,
1236 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1237 .volt_table = ldo_vauxn_voltages,
1240 .update_bank = 0x04,
1242 .update_mask = 0x03,
1244 .update_val_idle = 0x03,
1245 .update_val_normal = 0x01,
1246 .voltage_bank = 0x04,
1247 .voltage_reg = 0x1f,
1248 .voltage_mask = 0x0f,
1250 [AB8540_LDO_AUX2] = {
1253 .ops = &ab8500_regulator_volt_mode_ops,
1254 .type = REGULATOR_VOLTAGE,
1255 .id = AB8540_LDO_AUX2,
1256 .owner = THIS_MODULE,
1257 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1258 .volt_table = ldo_vauxn_voltages,
1261 .update_bank = 0x04,
1263 .update_mask = 0x0c,
1265 .update_val_idle = 0x0c,
1266 .update_val_normal = 0x04,
1267 .voltage_bank = 0x04,
1268 .voltage_reg = 0x20,
1269 .voltage_mask = 0x0f,
1271 [AB8540_LDO_AUX3] = {
1274 .ops = &ab8500_regulator_volt_mode_ops,
1275 .type = REGULATOR_VOLTAGE,
1276 .id = AB8540_LDO_AUX3,
1277 .owner = THIS_MODULE,
1278 .n_voltages = ARRAY_SIZE(ldo_vaux3_ab8540_voltages),
1279 .volt_table = ldo_vaux3_ab8540_voltages,
1282 .update_bank = 0x04,
1284 .update_mask = 0x03,
1286 .update_val_idle = 0x03,
1287 .update_val_normal = 0x01,
1288 .voltage_bank = 0x04,
1289 .voltage_reg = 0x21,
1290 .voltage_mask = 0x07,
1292 [AB8540_LDO_AUX4] = {
1295 .ops = &ab8500_regulator_volt_mode_ops,
1296 .type = REGULATOR_VOLTAGE,
1297 .id = AB8540_LDO_AUX4,
1298 .owner = THIS_MODULE,
1299 .n_voltages = ARRAY_SIZE(ldo_vauxn_voltages),
1300 .volt_table = ldo_vauxn_voltages,
1303 /* values for Vaux4Regu register */
1304 .update_bank = 0x04,
1306 .update_mask = 0x03,
1308 .update_val_idle = 0x03,
1309 .update_val_normal = 0x01,
1310 /* values for Vaux4SEL register */
1311 .voltage_bank = 0x04,
1312 .voltage_reg = 0x2f,
1313 .voltage_mask = 0x0f,
1315 [AB8540_LDO_INTCORE] = {
1317 .name = "LDO-INTCORE",
1318 .ops = &ab8500_regulator_volt_mode_ops,
1319 .type = REGULATOR_VOLTAGE,
1320 .id = AB8540_LDO_INTCORE,
1321 .owner = THIS_MODULE,
1322 .n_voltages = ARRAY_SIZE(ldo_vintcore_voltages),
1323 .volt_table = ldo_vintcore_voltages,
1326 .update_bank = 0x03,
1328 .update_mask = 0x44,
1330 .update_val_idle = 0x44,
1331 .update_val_normal = 0x04,
1332 .voltage_bank = 0x03,
1333 .voltage_reg = 0x80,
1334 .voltage_mask = 0x38,
1339 * Fixed Voltage Regulators
1341 * update bank, reg, mask, enable val
1343 [AB8540_LDO_TVOUT] = {
1345 .name = "LDO-TVOUT",
1346 .ops = &ab8500_regulator_mode_ops,
1347 .type = REGULATOR_VOLTAGE,
1348 .id = AB8540_LDO_TVOUT,
1349 .owner = THIS_MODULE,
1354 .update_bank = 0x03,
1356 .update_mask = 0x82,
1358 .update_val_idle = 0x82,
1359 .update_val_normal = 0x02,
1361 [AB8540_LDO_AUDIO] = {
1363 .name = "LDO-AUDIO",
1364 .ops = &ab8500_regulator_ops,
1365 .type = REGULATOR_VOLTAGE,
1366 .id = AB8540_LDO_AUDIO,
1367 .owner = THIS_MODULE,
1369 .volt_table = fixed_2000000_voltage,
1371 .update_bank = 0x03,
1373 .update_mask = 0x02,
1376 [AB8540_LDO_ANAMIC1] = {
1378 .name = "LDO-ANAMIC1",
1379 .ops = &ab8500_regulator_ops,
1380 .type = REGULATOR_VOLTAGE,
1381 .id = AB8540_LDO_ANAMIC1,
1382 .owner = THIS_MODULE,
1384 .volt_table = fixed_2050000_voltage,
1386 .update_bank = 0x03,
1388 .update_mask = 0x08,
1391 [AB8540_LDO_ANAMIC2] = {
1393 .name = "LDO-ANAMIC2",
1394 .ops = &ab8500_regulator_ops,
1395 .type = REGULATOR_VOLTAGE,
1396 .id = AB8540_LDO_ANAMIC2,
1397 .owner = THIS_MODULE,
1399 .volt_table = fixed_2050000_voltage,
1401 .update_bank = 0x03,
1403 .update_mask = 0x10,
1406 [AB8540_LDO_DMIC] = {
1409 .ops = &ab8500_regulator_ops,
1410 .type = REGULATOR_VOLTAGE,
1411 .id = AB8540_LDO_DMIC,
1412 .owner = THIS_MODULE,
1415 .update_bank = 0x03,
1417 .update_mask = 0x04,
1422 * Regulators with fixed voltage and normal/idle modes
1424 [AB8540_LDO_ANA] = {
1427 .ops = &ab8500_regulator_mode_ops,
1428 .type = REGULATOR_VOLTAGE,
1429 .id = AB8540_LDO_ANA,
1430 .owner = THIS_MODULE,
1432 .volt_table = fixed_1200000_voltage,
1435 .update_bank = 0x04,
1437 .update_mask = 0x0c,
1439 .update_val_idle = 0x0c,
1440 .update_val_normal = 0x04,
1442 [AB8540_LDO_SDIO] = {
1445 .ops = &ab8500_regulator_volt_mode_ops,
1446 .type = REGULATOR_VOLTAGE,
1447 .id = AB8540_LDO_SDIO,
1448 .owner = THIS_MODULE,
1449 .n_voltages = ARRAY_SIZE(ldo_sdio_voltages),
1450 .volt_table = ldo_sdio_voltages,
1453 .update_bank = 0x03,
1455 .update_mask = 0x30,
1457 .update_val_idle = 0x30,
1458 .update_val_normal = 0x10,
1459 .voltage_bank = 0x03,
1460 .voltage_reg = 0x88,
1461 .voltage_mask = 0x07,
1465 struct ab8500_reg_init {
1471 #define REG_INIT(_id, _bank, _addr, _mask) \
1478 /* AB8500 register init */
1479 static struct ab8500_reg_init ab8500_reg_init[] = {
1481 * 0x30, VanaRequestCtrl
1482 * 0xc0, VextSupply1RequestCtrl
1484 REG_INIT(AB8500_REGUREQUESTCTRL2, 0x03, 0x04, 0xf0),
1486 * 0x03, VextSupply2RequestCtrl
1487 * 0x0c, VextSupply3RequestCtrl
1488 * 0x30, Vaux1RequestCtrl
1489 * 0xc0, Vaux2RequestCtrl
1491 REG_INIT(AB8500_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1493 * 0x03, Vaux3RequestCtrl
1496 REG_INIT(AB8500_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1498 * 0x08, VanaSysClkReq1HPValid
1499 * 0x20, Vaux1SysClkReq1HPValid
1500 * 0x40, Vaux2SysClkReq1HPValid
1501 * 0x80, Vaux3SysClkReq1HPValid
1503 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xe8),
1505 * 0x10, VextSupply1SysClkReq1HPValid
1506 * 0x20, VextSupply2SysClkReq1HPValid
1507 * 0x40, VextSupply3SysClkReq1HPValid
1509 REG_INIT(AB8500_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x70),
1511 * 0x08, VanaHwHPReq1Valid
1512 * 0x20, Vaux1HwHPReq1Valid
1513 * 0x40, Vaux2HwHPReq1Valid
1514 * 0x80, Vaux3HwHPReq1Valid
1516 REG_INIT(AB8500_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xe8),
1518 * 0x01, VextSupply1HwHPReq1Valid
1519 * 0x02, VextSupply2HwHPReq1Valid
1520 * 0x04, VextSupply3HwHPReq1Valid
1522 REG_INIT(AB8500_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
1524 * 0x08, VanaHwHPReq2Valid
1525 * 0x20, Vaux1HwHPReq2Valid
1526 * 0x40, Vaux2HwHPReq2Valid
1527 * 0x80, Vaux3HwHPReq2Valid
1529 REG_INIT(AB8500_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xe8),
1531 * 0x01, VextSupply1HwHPReq2Valid
1532 * 0x02, VextSupply2HwHPReq2Valid
1533 * 0x04, VextSupply3HwHPReq2Valid
1535 REG_INIT(AB8500_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
1537 * 0x20, VanaSwHPReqValid
1538 * 0x80, Vaux1SwHPReqValid
1540 REG_INIT(AB8500_REGUSWHPREQVALID1, 0x03, 0x0d, 0xa0),
1542 * 0x01, Vaux2SwHPReqValid
1543 * 0x02, Vaux3SwHPReqValid
1544 * 0x04, VextSupply1SwHPReqValid
1545 * 0x08, VextSupply2SwHPReqValid
1546 * 0x10, VextSupply3SwHPReqValid
1548 REG_INIT(AB8500_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
1550 * 0x02, SysClkReq2Valid1
1551 * 0x04, SysClkReq3Valid1
1552 * 0x08, SysClkReq4Valid1
1553 * 0x10, SysClkReq5Valid1
1554 * 0x20, SysClkReq6Valid1
1555 * 0x40, SysClkReq7Valid1
1556 * 0x80, SysClkReq8Valid1
1558 REG_INIT(AB8500_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
1560 * 0x02, SysClkReq2Valid2
1561 * 0x04, SysClkReq3Valid2
1562 * 0x08, SysClkReq4Valid2
1563 * 0x10, SysClkReq5Valid2
1564 * 0x20, SysClkReq6Valid2
1565 * 0x40, SysClkReq7Valid2
1566 * 0x80, SysClkReq8Valid2
1568 REG_INIT(AB8500_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
1571 * 0x04, Vintcore12Ena
1572 * 0x38, Vintcore12Sel
1573 * 0x40, Vintcore12LP
1576 REG_INIT(AB8500_REGUMISC1, 0x03, 0x80, 0xfe),
1583 REG_INIT(AB8500_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1585 * 0x01, Vamic1_dzout
1586 * 0x02, Vamic2_dzout
1588 REG_INIT(AB8500_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
1590 * 0x03, VpllRegu (NOTE! PRCMU register bits)
1593 REG_INIT(AB8500_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1596 * 0x02, VrefDDRSleepMode
1598 REG_INIT(AB8500_VREFDDR, 0x04, 0x07, 0x03),
1600 * 0x03, VextSupply1Regu
1601 * 0x0c, VextSupply2Regu
1602 * 0x30, VextSupply3Regu
1603 * 0x40, ExtSupply2Bypass
1604 * 0x80, ExtSupply3Bypass
1606 REG_INIT(AB8500_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1611 REG_INIT(AB8500_VAUX12REGU, 0x04, 0x09, 0x0f),
1615 REG_INIT(AB8500_VRF1VAUX3REGU, 0x04, 0x0a, 0x03),
1619 REG_INIT(AB8500_VAUX1SEL, 0x04, 0x1f, 0x0f),
1623 REG_INIT(AB8500_VAUX2SEL, 0x04, 0x20, 0x0f),
1627 REG_INIT(AB8500_VRF1VAUX3SEL, 0x04, 0x21, 0x07),
1629 * 0x01, VextSupply12LP
1631 REG_INIT(AB8500_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
1636 * 0x20, Vintcore12Disch
1640 REG_INIT(AB8500_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
1643 * 0x04, VdmicPullDownEna
1646 REG_INIT(AB8500_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
1649 /* AB8505 register init */
1650 static struct ab8500_reg_init ab8505_reg_init[] = {
1652 * 0x03, VarmRequestCtrl
1653 * 0x0c, VsmpsCRequestCtrl
1654 * 0x30, VsmpsARequestCtrl
1655 * 0xc0, VsmpsBRequestCtrl
1657 REG_INIT(AB8505_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1659 * 0x03, VsafeRequestCtrl
1660 * 0x0c, VpllRequestCtrl
1661 * 0x30, VanaRequestCtrl
1663 REG_INIT(AB8505_REGUREQUESTCTRL2, 0x03, 0x04, 0x3f),
1665 * 0x30, Vaux1RequestCtrl
1666 * 0xc0, Vaux2RequestCtrl
1668 REG_INIT(AB8505_REGUREQUESTCTRL3, 0x03, 0x05, 0xf0),
1670 * 0x03, Vaux3RequestCtrl
1673 REG_INIT(AB8505_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1675 * 0x01, VsmpsASysClkReq1HPValid
1676 * 0x02, VsmpsBSysClkReq1HPValid
1677 * 0x04, VsafeSysClkReq1HPValid
1678 * 0x08, VanaSysClkReq1HPValid
1679 * 0x10, VpllSysClkReq1HPValid
1680 * 0x20, Vaux1SysClkReq1HPValid
1681 * 0x40, Vaux2SysClkReq1HPValid
1682 * 0x80, Vaux3SysClkReq1HPValid
1684 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
1686 * 0x01, VsmpsCSysClkReq1HPValid
1687 * 0x02, VarmSysClkReq1HPValid
1688 * 0x04, VbbSysClkReq1HPValid
1689 * 0x08, VsmpsMSysClkReq1HPValid
1691 REG_INIT(AB8505_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x0f),
1693 * 0x01, VsmpsAHwHPReq1Valid
1694 * 0x02, VsmpsBHwHPReq1Valid
1695 * 0x04, VsafeHwHPReq1Valid
1696 * 0x08, VanaHwHPReq1Valid
1697 * 0x10, VpllHwHPReq1Valid
1698 * 0x20, Vaux1HwHPReq1Valid
1699 * 0x40, Vaux2HwHPReq1Valid
1700 * 0x80, Vaux3HwHPReq1Valid
1702 REG_INIT(AB8505_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
1704 * 0x08, VsmpsMHwHPReq1Valid
1706 REG_INIT(AB8505_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x08),
1708 * 0x01, VsmpsAHwHPReq2Valid
1709 * 0x02, VsmpsBHwHPReq2Valid
1710 * 0x04, VsafeHwHPReq2Valid
1711 * 0x08, VanaHwHPReq2Valid
1712 * 0x10, VpllHwHPReq2Valid
1713 * 0x20, Vaux1HwHPReq2Valid
1714 * 0x40, Vaux2HwHPReq2Valid
1715 * 0x80, Vaux3HwHPReq2Valid
1717 REG_INIT(AB8505_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
1719 * 0x08, VsmpsMHwHPReq2Valid
1721 REG_INIT(AB8505_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x08),
1723 * 0x01, VsmpsCSwHPReqValid
1724 * 0x02, VarmSwHPReqValid
1725 * 0x04, VsmpsASwHPReqValid
1726 * 0x08, VsmpsBSwHPReqValid
1727 * 0x10, VsafeSwHPReqValid
1728 * 0x20, VanaSwHPReqValid
1729 * 0x40, VpllSwHPReqValid
1730 * 0x80, Vaux1SwHPReqValid
1732 REG_INIT(AB8505_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
1734 * 0x01, Vaux2SwHPReqValid
1735 * 0x02, Vaux3SwHPReqValid
1736 * 0x20, VsmpsMSwHPReqValid
1738 REG_INIT(AB8505_REGUSWHPREQVALID2, 0x03, 0x0e, 0x23),
1740 * 0x02, SysClkReq2Valid1
1741 * 0x04, SysClkReq3Valid1
1742 * 0x08, SysClkReq4Valid1
1744 REG_INIT(AB8505_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0x0e),
1746 * 0x02, SysClkReq2Valid2
1747 * 0x04, SysClkReq3Valid2
1748 * 0x08, SysClkReq4Valid2
1750 REG_INIT(AB8505_REGUSYSCLKREQVALID2, 0x03, 0x10, 0x0e),
1752 * 0x01, Vaux4SwHPReqValid
1753 * 0x02, Vaux4HwHPReq2Valid
1754 * 0x04, Vaux4HwHPReq1Valid
1755 * 0x08, Vaux4SysClkReq1HPValid
1757 REG_INIT(AB8505_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
1760 * 0x04, VintCore12Ena
1761 * 0x38, VintCore12Sel
1762 * 0x40, VintCore12LP
1765 REG_INIT(AB8505_REGUMISC1, 0x03, 0x80, 0xfe),
1772 REG_INIT(AB8505_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
1774 * 0x01, Vamic1_dzout
1775 * 0x02, Vamic2_dzout
1777 REG_INIT(AB8505_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
1780 * 0x0c, VsmpsASelCtrl
1781 * 0x10, VsmpsAAutoMode
1782 * 0x20, VsmpsAPWMMode
1784 REG_INIT(AB8505_VSMPSAREGU, 0x04, 0x03, 0x3f),
1787 * 0x0c, VsmpsBSelCtrl
1788 * 0x10, VsmpsBAutoMode
1789 * 0x20, VsmpsBPWMMode
1791 REG_INIT(AB8505_VSMPSBREGU, 0x04, 0x04, 0x3f),
1794 * 0x0c, VsafeSelCtrl
1795 * 0x10, VsafeAutoMode
1796 * 0x20, VsafePWMMode
1798 REG_INIT(AB8505_VSAFEREGU, 0x04, 0x05, 0x3f),
1800 * 0x03, VpllRegu (NOTE! PRCMU register bits)
1803 REG_INIT(AB8505_VPLLVANAREGU, 0x04, 0x06, 0x0f),
1805 * 0x03, VextSupply1Regu
1806 * 0x0c, VextSupply2Regu
1807 * 0x30, VextSupply3Regu
1808 * 0x40, ExtSupply2Bypass
1809 * 0x80, ExtSupply3Bypass
1811 REG_INIT(AB8505_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
1816 REG_INIT(AB8505_VAUX12REGU, 0x04, 0x09, 0x0f),
1820 REG_INIT(AB8505_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
1824 REG_INIT(AB8505_VSMPSASEL1, 0x04, 0x13, 0x3f),
1828 REG_INIT(AB8505_VSMPSASEL2, 0x04, 0x14, 0x3f),
1832 REG_INIT(AB8505_VSMPSASEL3, 0x04, 0x15, 0x3f),
1836 REG_INIT(AB8505_VSMPSBSEL1, 0x04, 0x17, 0x3f),
1840 REG_INIT(AB8505_VSMPSBSEL2, 0x04, 0x18, 0x3f),
1844 REG_INIT(AB8505_VSMPSBSEL3, 0x04, 0x19, 0x3f),
1848 REG_INIT(AB8505_VSAFESEL1, 0x04, 0x1b, 0x7f),
1852 REG_INIT(AB8505_VSAFESEL2, 0x04, 0x1c, 0x7f),
1856 REG_INIT(AB8505_VSAFESEL3, 0x04, 0x1d, 0x7f),
1860 REG_INIT(AB8505_VAUX1SEL, 0x04, 0x1f, 0x0f),
1864 REG_INIT(AB8505_VAUX2SEL, 0x04, 0x20, 0x0f),
1869 REG_INIT(AB8505_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
1871 * 0x03, Vaux4RequestCtrl
1873 REG_INIT(AB8505_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
1877 REG_INIT(AB8505_VAUX4REGU, 0x04, 0x2e, 0x03),
1881 REG_INIT(AB8505_VAUX4SEL, 0x04, 0x2f, 0x0f),
1886 * 0x20, Vintcore12Disch
1890 REG_INIT(AB8505_REGUCTRLDISCH, 0x04, 0x43, 0xfc),
1893 * 0x04, VdmicPullDownEna
1896 REG_INIT(AB8505_REGUCTRLDISCH2, 0x04, 0x44, 0x16),
1900 REG_INIT(AB8505_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
1906 * 0x40, Vaux5DisSfst
1907 * 0x80, Vaux5DisPulld
1909 REG_INIT(AB8505_CTRLVAUX5, 0x01, 0x55, 0xff),
1914 * 0x80, Vaux6DisPulld
1916 REG_INIT(AB8505_CTRLVAUX6, 0x01, 0x56, 0x9f),
1919 /* AB9540 register init */
1920 static struct ab8500_reg_init ab9540_reg_init[] = {
1922 * 0x03, VarmRequestCtrl
1923 * 0x0c, VapeRequestCtrl
1924 * 0x30, Vsmps1RequestCtrl
1925 * 0xc0, Vsmps2RequestCtrl
1927 REG_INIT(AB9540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
1929 * 0x03, Vsmps3RequestCtrl
1930 * 0x0c, VpllRequestCtrl
1931 * 0x30, VanaRequestCtrl
1932 * 0xc0, VextSupply1RequestCtrl
1934 REG_INIT(AB9540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
1936 * 0x03, VextSupply2RequestCtrl
1937 * 0x0c, VextSupply3RequestCtrl
1938 * 0x30, Vaux1RequestCtrl
1939 * 0xc0, Vaux2RequestCtrl
1941 REG_INIT(AB9540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
1943 * 0x03, Vaux3RequestCtrl
1946 REG_INIT(AB9540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
1948 * 0x01, Vsmps1SysClkReq1HPValid
1949 * 0x02, Vsmps2SysClkReq1HPValid
1950 * 0x04, Vsmps3SysClkReq1HPValid
1951 * 0x08, VanaSysClkReq1HPValid
1952 * 0x10, VpllSysClkReq1HPValid
1953 * 0x20, Vaux1SysClkReq1HPValid
1954 * 0x40, Vaux2SysClkReq1HPValid
1955 * 0x80, Vaux3SysClkReq1HPValid
1957 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
1959 * 0x01, VapeSysClkReq1HPValid
1960 * 0x02, VarmSysClkReq1HPValid
1961 * 0x04, VbbSysClkReq1HPValid
1962 * 0x08, VmodSysClkReq1HPValid
1963 * 0x10, VextSupply1SysClkReq1HPValid
1964 * 0x20, VextSupply2SysClkReq1HPValid
1965 * 0x40, VextSupply3SysClkReq1HPValid
1967 REG_INIT(AB9540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x7f),
1969 * 0x01, Vsmps1HwHPReq1Valid
1970 * 0x02, Vsmps2HwHPReq1Valid
1971 * 0x04, Vsmps3HwHPReq1Valid
1972 * 0x08, VanaHwHPReq1Valid
1973 * 0x10, VpllHwHPReq1Valid
1974 * 0x20, Vaux1HwHPReq1Valid
1975 * 0x40, Vaux2HwHPReq1Valid
1976 * 0x80, Vaux3HwHPReq1Valid
1978 REG_INIT(AB9540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
1980 * 0x01, VextSupply1HwHPReq1Valid
1981 * 0x02, VextSupply2HwHPReq1Valid
1982 * 0x04, VextSupply3HwHPReq1Valid
1983 * 0x08, VmodHwHPReq1Valid
1985 REG_INIT(AB9540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x0f),
1987 * 0x01, Vsmps1HwHPReq2Valid
1988 * 0x02, Vsmps2HwHPReq2Valid
1989 * 0x03, Vsmps3HwHPReq2Valid
1990 * 0x08, VanaHwHPReq2Valid
1991 * 0x10, VpllHwHPReq2Valid
1992 * 0x20, Vaux1HwHPReq2Valid
1993 * 0x40, Vaux2HwHPReq2Valid
1994 * 0x80, Vaux3HwHPReq2Valid
1996 REG_INIT(AB9540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
1998 * 0x01, VextSupply1HwHPReq2Valid
1999 * 0x02, VextSupply2HwHPReq2Valid
2000 * 0x04, VextSupply3HwHPReq2Valid
2001 * 0x08, VmodHwHPReq2Valid
2003 REG_INIT(AB9540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x0f),
2005 * 0x01, VapeSwHPReqValid
2006 * 0x02, VarmSwHPReqValid
2007 * 0x04, Vsmps1SwHPReqValid
2008 * 0x08, Vsmps2SwHPReqValid
2009 * 0x10, Vsmps3SwHPReqValid
2010 * 0x20, VanaSwHPReqValid
2011 * 0x40, VpllSwHPReqValid
2012 * 0x80, Vaux1SwHPReqValid
2014 REG_INIT(AB9540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2016 * 0x01, Vaux2SwHPReqValid
2017 * 0x02, Vaux3SwHPReqValid
2018 * 0x04, VextSupply1SwHPReqValid
2019 * 0x08, VextSupply2SwHPReqValid
2020 * 0x10, VextSupply3SwHPReqValid
2021 * 0x20, VmodSwHPReqValid
2023 REG_INIT(AB9540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x3f),
2025 * 0x02, SysClkReq2Valid1
2027 * 0x80, SysClkReq8Valid1
2029 REG_INIT(AB9540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xfe),
2031 * 0x02, SysClkReq2Valid2
2033 * 0x80, SysClkReq8Valid2
2035 REG_INIT(AB9540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xfe),
2037 * 0x01, Vaux4SwHPReqValid
2038 * 0x02, Vaux4HwHPReq2Valid
2039 * 0x04, Vaux4HwHPReq1Valid
2040 * 0x08, Vaux4SysClkReq1HPValid
2042 REG_INIT(AB9540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2045 * 0x04, Vintcore12Ena
2046 * 0x38, Vintcore12Sel
2047 * 0x40, Vintcore12LP
2050 REG_INIT(AB9540_REGUMISC1, 0x03, 0x80, 0xfe),
2057 REG_INIT(AB9540_VAUDIOSUPPLY, 0x03, 0x83, 0x1e),
2059 * 0x01, Vamic1_dzout
2060 * 0x02, Vamic2_dzout
2062 REG_INIT(AB9540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2065 * 0x0c, Vsmps1SelCtrl
2066 * 0x10, Vsmps1AutoMode
2067 * 0x20, Vsmps1PWMMode
2069 REG_INIT(AB9540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2072 * 0x0c, Vsmps2SelCtrl
2073 * 0x10, Vsmps2AutoMode
2074 * 0x20, Vsmps2PWMMode
2076 REG_INIT(AB9540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2079 * 0x0c, Vsmps3SelCtrl
2080 * NOTE! PRCMU register
2082 REG_INIT(AB9540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2087 REG_INIT(AB9540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2089 * 0x03, VextSupply1Regu
2090 * 0x0c, VextSupply2Regu
2091 * 0x30, VextSupply3Regu
2092 * 0x40, ExtSupply2Bypass
2093 * 0x80, ExtSupply3Bypass
2095 REG_INIT(AB9540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2100 REG_INIT(AB9540_VAUX12REGU, 0x04, 0x09, 0x0f),
2105 REG_INIT(AB9540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2109 REG_INIT(AB9540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2113 REG_INIT(AB9540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2117 REG_INIT(AB9540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2121 REG_INIT(AB9540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2125 REG_INIT(AB9540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2129 REG_INIT(AB9540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2132 * NOTE! PRCMU register
2134 REG_INIT(AB9540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2137 * NOTE! PRCMU register
2139 REG_INIT(AB9540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2143 REG_INIT(AB9540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2147 REG_INIT(AB9540_VAUX2SEL, 0x04, 0x20, 0x0f),
2152 REG_INIT(AB9540_VRF1VAUX3SEL, 0x04, 0x21, 0x37),
2154 * 0x01, VextSupply12LP
2156 REG_INIT(AB9540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2158 * 0x03, Vaux4RequestCtrl
2160 REG_INIT(AB9540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2164 REG_INIT(AB9540_VAUX4REGU, 0x04, 0x2e, 0x03),
2168 REG_INIT(AB9540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2175 * 0x20, Vintcore12Disch
2179 REG_INIT(AB9540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2183 * 0x04, VdmicPullDownEna
2184 * 0x08, VpllPullDownEna
2187 REG_INIT(AB9540_REGUCTRLDISCH2, 0x04, 0x44, 0x1f),
2191 REG_INIT(AB9540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2194 /* AB8540 register init */
2195 static struct ab8500_reg_init ab8540_reg_init[] = {
2197 * 0x01, VSimSycClkReq1Valid
2198 * 0x02, VSimSycClkReq2Valid
2199 * 0x04, VSimSycClkReq3Valid
2200 * 0x08, VSimSycClkReq4Valid
2201 * 0x10, VSimSycClkReq5Valid
2202 * 0x20, VSimSycClkReq6Valid
2203 * 0x40, VSimSycClkReq7Valid
2204 * 0x80, VSimSycClkReq8Valid
2206 REG_INIT(AB8540_VSIMSYSCLKCTRL, 0x02, 0x33, 0xff),
2208 * 0x03, VarmRequestCtrl
2209 * 0x0c, VapeRequestCtrl
2210 * 0x30, Vsmps1RequestCtrl
2211 * 0xc0, Vsmps2RequestCtrl
2213 REG_INIT(AB8540_REGUREQUESTCTRL1, 0x03, 0x03, 0xff),
2215 * 0x03, Vsmps3RequestCtrl
2216 * 0x0c, VpllRequestCtrl
2217 * 0x30, VanaRequestCtrl
2218 * 0xc0, VextSupply1RequestCtrl
2220 REG_INIT(AB8540_REGUREQUESTCTRL2, 0x03, 0x04, 0xff),
2222 * 0x03, VextSupply2RequestCtrl
2223 * 0x0c, VextSupply3RequestCtrl
2224 * 0x30, Vaux1RequestCtrl
2225 * 0xc0, Vaux2RequestCtrl
2227 REG_INIT(AB8540_REGUREQUESTCTRL3, 0x03, 0x05, 0xff),
2229 * 0x03, Vaux3RequestCtrl
2232 REG_INIT(AB8540_REGUREQUESTCTRL4, 0x03, 0x06, 0x07),
2234 * 0x01, Vsmps1SysClkReq1HPValid
2235 * 0x02, Vsmps2SysClkReq1HPValid
2236 * 0x04, Vsmps3SysClkReq1HPValid
2237 * 0x08, VanaSysClkReq1HPValid
2238 * 0x10, VpllSysClkReq1HPValid
2239 * 0x20, Vaux1SysClkReq1HPValid
2240 * 0x40, Vaux2SysClkReq1HPValid
2241 * 0x80, Vaux3SysClkReq1HPValid
2243 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID1, 0x03, 0x07, 0xff),
2245 * 0x01, VapeSysClkReq1HPValid
2246 * 0x02, VarmSysClkReq1HPValid
2247 * 0x04, VbbSysClkReq1HPValid
2248 * 0x10, VextSupply1SysClkReq1HPValid
2249 * 0x20, VextSupply2SysClkReq1HPValid
2250 * 0x40, VextSupply3SysClkReq1HPValid
2252 REG_INIT(AB8540_REGUSYSCLKREQ1HPVALID2, 0x03, 0x08, 0x77),
2254 * 0x01, Vsmps1HwHPReq1Valid
2255 * 0x02, Vsmps2HwHPReq1Valid
2256 * 0x04, Vsmps3HwHPReq1Valid
2257 * 0x08, VanaHwHPReq1Valid
2258 * 0x10, VpllHwHPReq1Valid
2259 * 0x20, Vaux1HwHPReq1Valid
2260 * 0x40, Vaux2HwHPReq1Valid
2261 * 0x80, Vaux3HwHPReq1Valid
2263 REG_INIT(AB8540_REGUHWHPREQ1VALID1, 0x03, 0x09, 0xff),
2265 * 0x01, VextSupply1HwHPReq1Valid
2266 * 0x02, VextSupply2HwHPReq1Valid
2267 * 0x04, VextSupply3HwHPReq1Valid
2269 REG_INIT(AB8540_REGUHWHPREQ1VALID2, 0x03, 0x0a, 0x07),
2271 * 0x01, Vsmps1HwHPReq2Valid
2272 * 0x02, Vsmps2HwHPReq2Valid
2273 * 0x03, Vsmps3HwHPReq2Valid
2274 * 0x08, VanaHwHPReq2Valid
2275 * 0x10, VpllHwHPReq2Valid
2276 * 0x20, Vaux1HwHPReq2Valid
2277 * 0x40, Vaux2HwHPReq2Valid
2278 * 0x80, Vaux3HwHPReq2Valid
2280 REG_INIT(AB8540_REGUHWHPREQ2VALID1, 0x03, 0x0b, 0xff),
2282 * 0x01, VextSupply1HwHPReq2Valid
2283 * 0x02, VextSupply2HwHPReq2Valid
2284 * 0x04, VextSupply3HwHPReq2Valid
2286 REG_INIT(AB8540_REGUHWHPREQ2VALID2, 0x03, 0x0c, 0x07),
2288 * 0x01, VapeSwHPReqValid
2289 * 0x02, VarmSwHPReqValid
2290 * 0x04, Vsmps1SwHPReqValid
2291 * 0x08, Vsmps2SwHPReqValid
2292 * 0x10, Vsmps3SwHPReqValid
2293 * 0x20, VanaSwHPReqValid
2294 * 0x40, VpllSwHPReqValid
2295 * 0x80, Vaux1SwHPReqValid
2297 REG_INIT(AB8540_REGUSWHPREQVALID1, 0x03, 0x0d, 0xff),
2299 * 0x01, Vaux2SwHPReqValid
2300 * 0x02, Vaux3SwHPReqValid
2301 * 0x04, VextSupply1SwHPReqValid
2302 * 0x08, VextSupply2SwHPReqValid
2303 * 0x10, VextSupply3SwHPReqValid
2305 REG_INIT(AB8540_REGUSWHPREQVALID2, 0x03, 0x0e, 0x1f),
2307 * 0x02, SysClkReq2Valid1
2309 * 0x80, SysClkReq8Valid1
2311 REG_INIT(AB8540_REGUSYSCLKREQVALID1, 0x03, 0x0f, 0xff),
2313 * 0x02, SysClkReq2Valid2
2315 * 0x80, SysClkReq8Valid2
2317 REG_INIT(AB8540_REGUSYSCLKREQVALID2, 0x03, 0x10, 0xff),
2319 * 0x01, Vaux4SwHPReqValid
2320 * 0x02, Vaux4HwHPReq2Valid
2321 * 0x04, Vaux4HwHPReq1Valid
2322 * 0x08, Vaux4SysClkReq1HPValid
2324 REG_INIT(AB8540_REGUVAUX4REQVALID, 0x03, 0x11, 0x0f),
2326 * 0x01, Vaux5SwHPReqValid
2327 * 0x02, Vaux5HwHPReq2Valid
2328 * 0x04, Vaux5HwHPReq1Valid
2329 * 0x08, Vaux5SysClkReq1HPValid
2331 REG_INIT(AB8540_REGUVAUX5REQVALID, 0x03, 0x12, 0x0f),
2333 * 0x01, Vaux6SwHPReqValid
2334 * 0x02, Vaux6HwHPReq2Valid
2335 * 0x04, Vaux6HwHPReq1Valid
2336 * 0x08, Vaux6SysClkReq1HPValid
2338 REG_INIT(AB8540_REGUVAUX6REQVALID, 0x03, 0x13, 0x0f),
2340 * 0x01, VclkbSwHPReqValid
2341 * 0x02, VclkbHwHPReq2Valid
2342 * 0x04, VclkbHwHPReq1Valid
2343 * 0x08, VclkbSysClkReq1HPValid
2345 REG_INIT(AB8540_REGUVCLKBREQVALID, 0x03, 0x14, 0x0f),
2347 * 0x01, Vrf1SwHPReqValid
2348 * 0x02, Vrf1HwHPReq2Valid
2349 * 0x04, Vrf1HwHPReq1Valid
2350 * 0x08, Vrf1SysClkReq1HPValid
2352 REG_INIT(AB8540_REGUVRF1REQVALID, 0x03, 0x15, 0x0f),
2355 * 0x04, Vintcore12Ena
2356 * 0x38, Vintcore12Sel
2357 * 0x40, Vintcore12LP
2360 REG_INIT(AB8540_REGUMISC1, 0x03, 0x80, 0xfe),
2369 REG_INIT(AB8540_VAUDIOSUPPLY, 0x03, 0x83, 0xfe),
2371 * 0x01, Vamic1_dzout
2372 * 0x02, Vamic2_dzout
2374 REG_INIT(AB8540_REGUCTRL1VAMIC, 0x03, 0x84, 0x03),
2377 * 0x08, VHSICOffState
2381 REG_INIT(AB8540_VHSIC, 0x03, 0x87, 0x3f),
2384 * 0x08, VSDIOOffState
2388 REG_INIT(AB8540_VSDIO, 0x03, 0x88, 0x3f),
2391 * 0x0c, Vsmps1SelCtrl
2392 * 0x10, Vsmps1AutoMode
2393 * 0x20, Vsmps1PWMMode
2395 REG_INIT(AB8540_VSMPS1REGU, 0x04, 0x03, 0x3f),
2398 * 0x0c, Vsmps2SelCtrl
2399 * 0x10, Vsmps2AutoMode
2400 * 0x20, Vsmps2PWMMode
2402 REG_INIT(AB8540_VSMPS2REGU, 0x04, 0x04, 0x3f),
2405 * 0x0c, Vsmps3SelCtrl
2406 * 0x10, Vsmps3AutoMode
2407 * 0x20, Vsmps3PWMMode
2408 * NOTE! PRCMU register
2410 REG_INIT(AB8540_VSMPS3REGU, 0x04, 0x05, 0x0f),
2415 REG_INIT(AB8540_VPLLVANAREGU, 0x04, 0x06, 0x0f),
2417 * 0x03, VextSupply1Regu
2418 * 0x0c, VextSupply2Regu
2419 * 0x30, VextSupply3Regu
2420 * 0x40, ExtSupply2Bypass
2421 * 0x80, ExtSupply3Bypass
2423 REG_INIT(AB8540_EXTSUPPLYREGU, 0x04, 0x08, 0xff),
2428 REG_INIT(AB8540_VAUX12REGU, 0x04, 0x09, 0x0f),
2433 REG_INIT(AB8540_VRF1VAUX3REGU, 0x04, 0x0a, 0x0f),
2437 REG_INIT(AB8540_VSMPS1SEL1, 0x04, 0x13, 0x3f),
2441 REG_INIT(AB8540_VSMPS1SEL2, 0x04, 0x14, 0x3f),
2445 REG_INIT(AB8540_VSMPS1SEL3, 0x04, 0x15, 0x3f),
2449 REG_INIT(AB8540_VSMPS2SEL1, 0x04, 0x17, 0x3f),
2453 REG_INIT(AB8540_VSMPS2SEL2, 0x04, 0x18, 0x3f),
2457 REG_INIT(AB8540_VSMPS2SEL3, 0x04, 0x19, 0x3f),
2460 * NOTE! PRCMU register
2462 REG_INIT(AB8540_VSMPS3SEL1, 0x04, 0x1b, 0x7f),
2465 * NOTE! PRCMU register
2467 REG_INIT(AB8540_VSMPS3SEL2, 0x04, 0x1c, 0x7f),
2471 REG_INIT(AB8540_VAUX1SEL, 0x04, 0x1f, 0x0f),
2475 REG_INIT(AB8540_VAUX2SEL, 0x04, 0x20, 0x0f),
2480 REG_INIT(AB8540_VRF1VAUX3SEL, 0x04, 0x21, 0x77),
2482 * 0x01, VextSupply12LP
2484 REG_INIT(AB8540_REGUCTRL2SPARE, 0x04, 0x22, 0x01),
2489 REG_INIT(AB8540_VANAVPLLSEL, 0x04, 0x29, 0x37),
2491 * 0x03, Vaux4RequestCtrl
2493 REG_INIT(AB8540_VAUX4REQCTRL, 0x04, 0x2d, 0x03),
2497 REG_INIT(AB8540_VAUX4REGU, 0x04, 0x2e, 0x03),
2501 REG_INIT(AB8540_VAUX4SEL, 0x04, 0x2f, 0x0f),
2503 * 0x03, Vaux5RequestCtrl
2505 REG_INIT(AB8540_VAUX5REQCTRL, 0x04, 0x31, 0x03),
2509 REG_INIT(AB8540_VAUX5REGU, 0x04, 0x32, 0x03),
2513 REG_INIT(AB8540_VAUX5SEL, 0x04, 0x33, 0x3f),
2515 * 0x03, Vaux6RequestCtrl
2517 REG_INIT(AB8540_VAUX6REQCTRL, 0x04, 0x34, 0x03),
2521 REG_INIT(AB8540_VAUX6REGU, 0x04, 0x35, 0x03),
2525 REG_INIT(AB8540_VAUX6SEL, 0x04, 0x36, 0x3f),
2527 * 0x03, VCLKBRequestCtrl
2529 REG_INIT(AB8540_VCLKBREQCTRL, 0x04, 0x37, 0x03),
2533 REG_INIT(AB8540_VCLKBREGU, 0x04, 0x38, 0x03),
2537 REG_INIT(AB8540_VCLKBSEL, 0x04, 0x39, 0x07),
2539 * 0x03, Vrf1RequestCtrl
2541 REG_INIT(AB8540_VRF1REQCTRL, 0x04, 0x3a, 0x03),
2548 * 0x20, Vintcore12Disch
2552 REG_INIT(AB8540_REGUCTRLDISCH, 0x04, 0x43, 0xff),
2555 * 0x04, VdmicPullDownEna
2556 * 0x08, VpllPullDownEna
2559 REG_INIT(AB8540_REGUCTRLDISCH2, 0x04, 0x44, 0x1e),
2563 REG_INIT(AB8540_REGUCTRLDISCH3, 0x04, 0x48, 0x01),
2569 REG_INIT(AB8540_REGUCTRLDISCH4, 0x04, 0x49, 0x07),
2572 static int ab8500_regulator_init_registers(struct platform_device *pdev,
2573 struct ab8500_reg_init *reg_init,
2574 int id, int mask, int value)
2578 BUG_ON(value & ~mask);
2579 BUG_ON(mask & ~reg_init[id].mask);
2581 /* initialize register */
2582 err = abx500_mask_and_set_register_interruptible(
2589 "Failed to initialize 0x%02x, 0x%02x.\n",
2594 dev_vdbg(&pdev->dev,
2595 " init: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",
2603 static int ab8500_regulator_register(struct platform_device *pdev,
2604 struct regulator_init_data *init_data,
2605 struct ab8500_regulator_info *regulator_info,
2606 int id, struct device_node *np)
2608 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
2609 struct ab8500_regulator_info *info = NULL;
2610 struct regulator_config config = { };
2613 /* assign per-regulator data */
2614 info = ®ulator_info[id];
2615 info->dev = &pdev->dev;
2617 config.dev = &pdev->dev;
2618 config.init_data = init_data;
2619 config.driver_data = info;
2620 config.of_node = np;
2622 /* fix for hardware before ab8500v2.0 */
2623 if (is_ab8500_1p1_or_earlier(ab8500)) {
2624 if (info->desc.id == AB8500_LDO_AUX3) {
2625 info->desc.n_voltages =
2626 ARRAY_SIZE(ldo_vauxn_voltages);
2627 info->desc.volt_table = ldo_vauxn_voltages;
2628 info->voltage_mask = 0xf;
2632 /* register regulator with framework */
2633 info->regulator = regulator_register(&info->desc, &config);
2634 if (IS_ERR(info->regulator)) {
2635 err = PTR_ERR(info->regulator);
2636 dev_err(&pdev->dev, "failed to register regulator %s\n",
2638 /* when we fail, un-register all earlier regulators */
2640 info = ®ulator_info[id];
2641 regulator_unregister(info->regulator);
2649 static struct of_regulator_match ab8500_regulator_match[] = {
2650 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8500_LDO_AUX1, },
2651 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8500_LDO_AUX2, },
2652 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8500_LDO_AUX3, },
2653 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8500_LDO_INTCORE, },
2654 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, },
2655 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, },
2656 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
2657 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
2658 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, },
2659 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, },
2662 static struct of_regulator_match ab8505_regulator_match[] = {
2663 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8505_LDO_AUX1, },
2664 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8505_LDO_AUX2, },
2665 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8505_LDO_AUX3, },
2666 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8505_LDO_AUX4, },
2667 { .name = "ab8500_ldo_aux5", .driver_data = (void *) AB8505_LDO_AUX5, },
2668 { .name = "ab8500_ldo_aux6", .driver_data = (void *) AB8505_LDO_AUX6, },
2669 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8505_LDO_INTCORE, },
2670 { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, },
2671 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, },
2672 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
2673 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
2674 { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, },
2675 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, },
2678 static struct of_regulator_match ab8540_regulator_match[] = {
2679 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB8540_LDO_AUX1, },
2680 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB8540_LDO_AUX2, },
2681 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB8540_LDO_AUX3, },
2682 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB8540_LDO_AUX4, },
2683 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB8540_LDO_INTCORE, },
2684 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, },
2685 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, },
2686 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
2687 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
2688 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, },
2689 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, },
2690 { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, },
2693 static struct of_regulator_match ab9540_regulator_match[] = {
2694 { .name = "ab8500_ldo_aux1", .driver_data = (void *) AB9540_LDO_AUX1, },
2695 { .name = "ab8500_ldo_aux2", .driver_data = (void *) AB9540_LDO_AUX2, },
2696 { .name = "ab8500_ldo_aux3", .driver_data = (void *) AB9540_LDO_AUX3, },
2697 { .name = "ab8500_ldo_aux4", .driver_data = (void *) AB9540_LDO_AUX4, },
2698 { .name = "ab8500_ldo_intcore", .driver_data = (void *) AB9540_LDO_INTCORE, },
2699 { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, },
2700 { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, },
2701 { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
2702 { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
2703 { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, },
2704 { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, },
2708 ab8500_regulator_of_probe(struct platform_device *pdev,
2709 struct ab8500_regulator_info *regulator_info,
2710 int regulator_info_size,
2711 struct of_regulator_match *match,
2712 struct device_node *np)
2716 for (i = 0; i < regulator_info_size; i++) {
2717 err = ab8500_regulator_register(
2718 pdev, match[i].init_data, regulator_info,
2719 i, match[i].of_node);
2727 static int ab8500_regulator_probe(struct platform_device *pdev)
2729 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
2730 struct device_node *np = pdev->dev.of_node;
2731 struct of_regulator_match *match;
2732 struct ab8500_platform_data *ppdata;
2733 struct ab8500_regulator_platform_data *pdata;
2735 struct ab8500_regulator_info *regulator_info;
2736 int regulator_info_size;
2737 struct ab8500_reg_init *reg_init;
2740 if (is_ab9540(ab8500)) {
2741 regulator_info = ab9540_regulator_info;
2742 regulator_info_size = ARRAY_SIZE(ab9540_regulator_info);
2743 reg_init = ab9540_reg_init;
2744 reg_init_size = AB9540_NUM_REGULATOR_REGISTERS;
2745 match = ab9540_regulator_match;
2746 match_size = ARRAY_SIZE(ab9540_regulator_match)
2747 } else if (is_ab8505(ab8500)) {
2748 regulator_info = ab8505_regulator_info;
2749 regulator_info_size = ARRAY_SIZE(ab8505_regulator_info);
2750 reg_init = ab8505_reg_init;
2751 reg_init_size = AB8505_NUM_REGULATOR_REGISTERS;
2752 } else if (is_ab8540(ab8500)) {
2753 regulator_info = ab8540_regulator_info;
2754 regulator_info_size = ARRAY_SIZE(ab8540_regulator_info);
2755 reg_init = ab8540_reg_init;
2756 reg_init_size = AB8540_NUM_REGULATOR_REGISTERS;
2758 regulator_info = ab8500_regulator_info;
2759 regulator_info_size = ARRAY_SIZE(ab8500_regulator_info);
2760 reg_init = ab8500_reg_init;
2761 reg_init_size = AB8500_NUM_REGULATOR_REGISTERS;
2762 match = ab8500_regulator_match;
2763 match_size = ARRAY_SIZE(ab8500_regulator_match)
2767 err = of_regulator_match(&pdev->dev, np, match, match_size);
2770 "Error parsing regulator init data: %d\n", err);
2774 err = ab8500_regulator_of_probe(pdev, regulator_info,
2775 regulator_info_size, match, np);
2780 dev_err(&pdev->dev, "null mfd parent\n");
2784 ppdata = dev_get_platdata(ab8500->dev);
2786 dev_err(&pdev->dev, "null parent pdata\n");
2790 pdata = ppdata->regulator;
2792 dev_err(&pdev->dev, "null pdata\n");
2796 /* make sure the platform data has the correct size */
2797 if (pdata->num_regulator != regulator_info_size) {
2798 dev_err(&pdev->dev, "Configuration error: size mismatch.\n");
2802 /* initialize debug (initial state is recorded with this call) */
2803 err = ab8500_regulator_debug_init(pdev);
2807 /* initialize registers */
2808 for (i = 0; i < pdata->num_reg_init; i++) {
2809 int id, mask, value;
2811 id = pdata->reg_init[i].id;
2812 mask = pdata->reg_init[i].mask;
2813 value = pdata->reg_init[i].value;
2815 /* check for configuration errors */
2816 BUG_ON(id >= AB8500_NUM_REGULATOR_REGISTERS);
2818 err = ab8500_regulator_init_registers(pdev, reg_init, id, mask, value);
2823 if (!is_ab8505(ab8500)) {
2824 /* register external regulators (before Vaux1, 2 and 3) */
2825 err = ab8500_ext_regulator_init(pdev);
2830 /* register all regulators */
2831 for (i = 0; i < regulator_info_size; i++) {
2832 err = ab8500_regulator_register(pdev, &pdata->regulator[i],
2833 regulator_info, i, NULL);
2841 static int ab8500_regulator_remove(struct platform_device *pdev)
2844 struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
2845 struct ab8500_regulator_info *regulator_info;
2846 int regulator_info_size;
2849 if (is_ab9540(ab8500)) {
2850 regulator_info = ab9540_regulator_info;
2851 regulator_info_size = ARRAY_SIZE(ab9540_regulator_info);
2852 } else if (is_ab8505(ab8500)) {
2853 regulator_info = ab8505_regulator_info;
2854 regulator_info_size = ARRAY_SIZE(ab8505_regulator_info);
2856 regulator_info = ab8500_regulator_info;
2857 regulator_info_size = ARRAY_SIZE(ab8500_regulator_info);
2860 for (i = 0; i < regulator_info_size; i++) {
2861 struct ab8500_regulator_info *info = NULL;
2862 info = ®ulator_info[i];
2864 dev_vdbg(rdev_get_dev(info->regulator),
2865 "%s-remove\n", info->desc.name);
2867 regulator_unregister(info->regulator);
2870 if (!is_ab8505(ab8500)) {
2871 /* remove external regulators (after Vaux1, 2 and 3) */
2872 err = ab8500_ext_regulator_exit(pdev);
2877 /* remove regulator debug */
2878 err = ab8500_regulator_debug_exit(pdev);
2885 static struct platform_driver ab8500_regulator_driver = {
2886 .probe = ab8500_regulator_probe,
2887 .remove = ab8500_regulator_remove,
2889 .name = "ab8500-regulator",
2890 .owner = THIS_MODULE,
2894 static int __init ab8500_regulator_init(void)
2898 ret = platform_driver_register(&ab8500_regulator_driver);
2900 pr_err("Failed to register ab8500 regulator: %d\n", ret);
2904 subsys_initcall(ab8500_regulator_init);
2906 static void __exit ab8500_regulator_exit(void)
2908 platform_driver_unregister(&ab8500_regulator_driver);
2910 module_exit(ab8500_regulator_exit);
2912 MODULE_LICENSE("GPL v2");
2913 MODULE_AUTHOR("Sundar Iyer <sundar.iyer@stericsson.com>");
2914 MODULE_AUTHOR("Bengt Jonsson <bengt.g.jonsson@stericsson.com>");
2915 MODULE_AUTHOR("Daniel Willerud <daniel.willerud@stericsson.com>");
2916 MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
2917 MODULE_ALIAS("platform:ab8500-regulator");