drivers/rtc/rtc-pm8xxx.c

   1 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/rtc.h>
  16 #include <linux/pm.h>
  17 #include <linux/slab.h>
  18 #include <linux/spinlock.h>
  19
  20 #include <linux/mfd/pm8xxx/core.h>
  21 #include <linux/mfd/pm8xxx/rtc.h>
  22
  23
  24 /* RTC Register offsets from RTC CTRL REG */
  25 #define PM8XXX_ALARM_CTRL_OFFSET        0x01
  26 #define PM8XXX_RTC_WRITE_OFFSET         0x02
  27 #define PM8XXX_RTC_READ_OFFSET          0x06
  28 #define PM8XXX_ALARM_RW_OFFSET          0x0A
  29
  30 /* RTC_CTRL register bit fields */
  31 #define PM8xxx_RTC_ENABLE               BIT(7)
  32 #define PM8xxx_RTC_ALARM_ENABLE         BIT(1)
  33 #define PM8xxx_RTC_ALARM_CLEAR          BIT(0)
  34
  35 #define NUM_8_BIT_RTC_REGS              0x4
  36
  37 /**
  38  * struct pm8xxx_rtc -  rtc driver internal structure
  39  * @rtc:                rtc device for this driver.
  40  * @rtc_alarm_irq:      rtc alarm irq number.
  41  * @rtc_base:           address of rtc control register.
  42  * @rtc_read_base:      base address of read registers.
  43  * @rtc_write_base:     base address of write registers.
  44  * @alarm_rw_base:      base address of alarm registers.
  45  * @ctrl_reg:           rtc control register.
  46  * @rtc_dev:            device structure.
  47  * @ctrl_reg_lock:      spinlock protecting access to ctrl_reg.
  48  */
  49 struct pm8xxx_rtc {
  50         struct rtc_device *rtc;
  51         int rtc_alarm_irq;
  52         int rtc_base;
  53         int rtc_read_base;
  54         int rtc_write_base;
  55         int alarm_rw_base;
  56         u8 ctrl_reg;
  57         struct device *rtc_dev;
  58         spinlock_t ctrl_reg_lock;
  59 };
  60
  61 /*
  62  * The RTC registers need to be read/written one byte at a time. This is a
  63  * hardware limitation.
  64  */
  65 static int pm8xxx_read_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val,
  66                                int base, int count)
  67 {
  68         int i, rc;
  69         struct device *parent = rtc_dd->rtc_dev->parent;
  70
  71         for (i = 0; i < count; i++) {
  72                 rc = pm8xxx_readb(parent, base + i, &rtc_val[i]);
  73                 if (rc < 0) {
  74                         dev_err(rtc_dd->rtc_dev, "PMIC read failed\n");
  75                         return rc;
  76                 }
  77         }
  78
  79         return 0;
  80 }
  81
  82 static int pm8xxx_write_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val,
  83                                 int base, int count)
  84 {
  85         int i, rc;
  86         struct device *parent = rtc_dd->rtc_dev->parent;
  87
  88         for (i = 0; i < count; i++) {
  89                 rc = pm8xxx_writeb(parent, base + i, rtc_val[i]);
  90                 if (rc < 0) {
  91                         dev_err(rtc_dd->rtc_dev, "PMIC write failed\n");
  92                         return rc;
  93                 }
  94         }
  95
  96         return 0;
  97 }
  98
  99 /*
 100  * Steps to write the RTC registers.
 101  * 1. Disable alarm if enabled.
 102  * 2. Write 0x00 to LSB.
 103  * 3. Write Byte[1], Byte[2], Byte[3] then Byte[0].
 104  * 4. Enable alarm if disabled in step 1.
 105  */
 106 static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
 107 {
 108         int rc, i;
 109         unsigned long secs, irq_flags;
 110         u8 value[NUM_8_BIT_RTC_REGS], reg = 0, alarm_enabled = 0, ctrl_reg;
 111         struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
 112
 113         rtc_tm_to_time(tm, &secs);
 114
 115         for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
 116                 value[i] = secs & 0xFF;
 117                 secs >>= 8;
 118         }
 119
 120         dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
 121
 122         spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
 123         ctrl_reg = rtc_dd->ctrl_reg;
 124
 125         if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) {
 126                 alarm_enabled = 1;
 127                 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
 128                 rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base,
 129                                           1);
 130                 if (rc < 0) {
 131                         dev_err(dev, "Write to RTC control register failed\n");
 132                         goto rtc_rw_fail;
 133                 }
 134                 rtc_dd->ctrl_reg = ctrl_reg;
 135         } else {
 136                 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
 137         }
 138
 139         /* Write 0 to Byte[0] */
 140         reg = 0;
 141         rc = pm8xxx_write_wrapper(rtc_dd, &reg, rtc_dd->rtc_write_base, 1);
 142         if (rc < 0) {
 143                 dev_err(dev, "Write to RTC write data register failed\n");
 144                 goto rtc_rw_fail;
 145         }
 146
 147         /* Write Byte[1], Byte[2], Byte[3] */
 148         rc = pm8xxx_write_wrapper(rtc_dd, value + 1,
 149                                   rtc_dd->rtc_write_base + 1, 3);
 150         if (rc < 0) {
 151                 dev_err(dev, "Write to RTC write data register failed\n");
 152                 goto rtc_rw_fail;
 153         }
 154
 155         /* Write Byte[0] */
 156         rc = pm8xxx_write_wrapper(rtc_dd, value, rtc_dd->rtc_write_base, 1);
 157         if (rc < 0) {
 158                 dev_err(dev, "Write to RTC write data register failed\n");
 159                 goto rtc_rw_fail;
 160         }
 161
 162         if (alarm_enabled) {
 163                 ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
 164                 rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base,
 165                                           1);
 166                 if (rc < 0) {
 167                         dev_err(dev, "Write to RTC control register failed\n");
 168                         goto rtc_rw_fail;
 169                 }
 170                 rtc_dd->ctrl_reg = ctrl_reg;
 171         }
 172
 173 rtc_rw_fail:
 174         if (alarm_enabled)
 175                 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
 176
 177         return rc;
 178 }
 179
 180 static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
 181 {
 182         int rc;
 183         u8 value[NUM_8_BIT_RTC_REGS], reg;
 184         unsigned long secs;
 185         struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
 186
 187         rc = pm8xxx_read_wrapper(rtc_dd, value, rtc_dd->rtc_read_base,
 188                                  NUM_8_BIT_RTC_REGS);
 189         if (rc < 0) {
 190                 dev_err(dev, "RTC read data register failed\n");
 191                 return rc;
 192         }
 193
 194         /*
 195          * Read the LSB again and check if there has been a carry over.
 196          * If there is, redo the read operation.
 197          */
 198         rc = pm8xxx_read_wrapper(rtc_dd, &reg, rtc_dd->rtc_read_base, 1);
 199         if (rc < 0) {
 200                 dev_err(dev, "RTC read data register failed\n");
 201                 return rc;
 202         }
 203
 204         if (unlikely(reg < value[0])) {
 205                 rc = pm8xxx_read_wrapper(rtc_dd, value,
 206                                          rtc_dd->rtc_read_base,
 207                                          NUM_8_BIT_RTC_REGS);
 208                 if (rc < 0) {
 209                         dev_err(dev, "RTC read data register failed\n");
 210                         return rc;
 211                 }
 212         }
 213
 214         secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
 215
 216         rtc_time_to_tm(secs, tm);
 217
 218         rc = rtc_valid_tm(tm);
 219         if (rc < 0) {
 220                 dev_err(dev, "Invalid time read from RTC\n");
 221                 return rc;
 222         }
 223
 224         dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n",
 225                 secs, tm->tm_hour, tm->tm_min, tm->tm_sec,
 226                 tm->tm_mday, tm->tm_mon, tm->tm_year);
 227
 228         return 0;
 229 }
 230
 231 static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 232 {
 233         int rc, i;
 234         u8 value[NUM_8_BIT_RTC_REGS], ctrl_reg;
 235         unsigned long secs, irq_flags;
 236         struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
 237
 238         rtc_tm_to_time(&alarm->time, &secs);
 239
 240         for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
 241                 value[i] = secs & 0xFF;
 242                 secs >>= 8;
 243         }
 244
 245         spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
 246
 247         rc = pm8xxx_write_wrapper(rtc_dd, value, rtc_dd->alarm_rw_base,
 248                                   NUM_8_BIT_RTC_REGS);
 249         if (rc < 0) {
 250                 dev_err(dev, "Write to RTC ALARM register failed\n");
 251                 goto rtc_rw_fail;
 252         }
 253
 254         ctrl_reg = rtc_dd->ctrl_reg;
 255
 256         if (alarm->enabled)
 257                 ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
 258         else
 259                 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
 260
 261         rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1);
 262         if (rc < 0) {
 263                 dev_err(dev, "Write to RTC control register failed\n");
 264                 goto rtc_rw_fail;
 265         }
 266
 267         rtc_dd->ctrl_reg = ctrl_reg;
 268
 269         dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
 270                 alarm->time.tm_hour, alarm->time.tm_min,
 271                 alarm->time.tm_sec, alarm->time.tm_mday,
 272                 alarm->time.tm_mon, alarm->time.tm_year);
 273 rtc_rw_fail:
 274         spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
 275         return rc;
 276 }
 277
 278 static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 279 {
 280         int rc;
 281         u8 value[NUM_8_BIT_RTC_REGS];
 282         unsigned long secs;
 283         struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
 284
 285         rc = pm8xxx_read_wrapper(rtc_dd, value, rtc_dd->alarm_rw_base,
 286                                  NUM_8_BIT_RTC_REGS);
 287         if (rc < 0) {
 288                 dev_err(dev, "RTC alarm time read failed\n");
 289                 return rc;
 290         }
 291
 292         secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
 293
 294         rtc_time_to_tm(secs, &alarm->time);
 295
 296         rc = rtc_valid_tm(&alarm->time);
 297         if (rc < 0) {
 298                 dev_err(dev, "Invalid alarm time read from RTC\n");
 299                 return rc;
 300         }
 301
 302         dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
 303                 alarm->time.tm_hour, alarm->time.tm_min,
 304                 alarm->time.tm_sec, alarm->time.tm_mday,
 305                 alarm->time.tm_mon, alarm->time.tm_year);
 306
 307         return 0;
 308 }
 309
 310 static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 311 {
 312         int rc;
 313         unsigned long irq_flags;
 314         struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
 315         u8 ctrl_reg;
 316
 317         spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
 318
 319         ctrl_reg = rtc_dd->ctrl_reg;
 320
 321         if (enable)
 322                 ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
 323         else
 324                 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
 325
 326         rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1);
 327         if (rc < 0) {
 328                 dev_err(dev, "Write to RTC control register failed\n");
 329                 goto rtc_rw_fail;
 330         }
 331
 332         rtc_dd->ctrl_reg = ctrl_reg;
 333
 334 rtc_rw_fail:
 335         spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
 336         return rc;
 337 }
 338
 339 static struct rtc_class_ops pm8xxx_rtc_ops = {
 340         .read_time      = pm8xxx_rtc_read_time,
 341         .set_alarm      = pm8xxx_rtc_set_alarm,
 342         .read_alarm     = pm8xxx_rtc_read_alarm,
 343         .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
 344 };
 345
 346 static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
 347 {
 348         struct pm8xxx_rtc *rtc_dd = dev_id;
 349         u8 ctrl_reg;
 350         int rc;
 351         unsigned long irq_flags;
 352
 353         rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
 354
 355         spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
 356
 357         /* Clear the alarm enable bit */
 358         ctrl_reg = rtc_dd->ctrl_reg;
 359         ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
 360
 361         rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1);
 362         if (rc < 0) {
 363                 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
 364                 dev_err(rtc_dd->rtc_dev,
 365                         "Write to RTC control register failed\n");
 366                 goto rtc_alarm_handled;
 367         }
 368
 369         rtc_dd->ctrl_reg = ctrl_reg;
 370         spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
 371
 372         /* Clear RTC alarm register */
 373         rc = pm8xxx_read_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base +
 374                                  PM8XXX_ALARM_CTRL_OFFSET, 1);
 375         if (rc < 0) {
 376                 dev_err(rtc_dd->rtc_dev,
 377                         "RTC Alarm control register read failed\n");
 378                 goto rtc_alarm_handled;
 379         }
 380
 381         ctrl_reg &= ~PM8xxx_RTC_ALARM_CLEAR;
 382         rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base +
 383                                   PM8XXX_ALARM_CTRL_OFFSET, 1);
 384         if (rc < 0)
 385                 dev_err(rtc_dd->rtc_dev,
 386                         "Write to RTC Alarm control register failed\n");
 387
 388 rtc_alarm_handled:
 389         return IRQ_HANDLED;
 390 }
 391
 392 static int pm8xxx_rtc_probe(struct platform_device *pdev)
 393 {
 394         int rc;
 395         u8 ctrl_reg;
 396         bool rtc_write_enable = false;
 397         struct pm8xxx_rtc *rtc_dd;
 398         struct resource *rtc_resource;
 399         const struct pm8xxx_rtc_platform_data *pdata =
 400                                                 dev_get_platdata(&pdev->dev);
 401
 402         if (pdata != NULL)
 403                 rtc_write_enable = pdata->rtc_write_enable;
 404
 405         rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
 406         if (rtc_dd == NULL)
 407                 return -ENOMEM;
 408
 409         /* Initialise spinlock to protect RTC control register */
 410         spin_lock_init(&rtc_dd->ctrl_reg_lock);
 411
 412         rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
 413         if (rtc_dd->rtc_alarm_irq < 0) {
 414                 dev_err(&pdev->dev, "Alarm IRQ resource absent!\n");
 415                 return -ENXIO;
 416         }
 417
 418         rtc_resource = platform_get_resource_byname(pdev, IORESOURCE_IO,
 419                                                     "pmic_rtc_base");
 420         if (!(rtc_resource && rtc_resource->start)) {
 421                 dev_err(&pdev->dev, "RTC IO resource absent!\n");
 422                 return -ENXIO;
 423         }
 424
 425         rtc_dd->rtc_base = rtc_resource->start;
 426
 427         /* Setup RTC register addresses */
 428         rtc_dd->rtc_write_base = rtc_dd->rtc_base + PM8XXX_RTC_WRITE_OFFSET;
 429         rtc_dd->rtc_read_base = rtc_dd->rtc_base + PM8XXX_RTC_READ_OFFSET;
 430         rtc_dd->alarm_rw_base = rtc_dd->rtc_base + PM8XXX_ALARM_RW_OFFSET;
 431
 432         rtc_dd->rtc_dev = &pdev->dev;
 433
 434         /* Check if the RTC is on, else turn it on */
 435         rc = pm8xxx_read_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1);
 436         if (rc < 0) {
 437                 dev_err(&pdev->dev, "RTC control register read failed!\n");
 438                 return rc;
 439         }
 440
 441         if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
 442                 ctrl_reg |= PM8xxx_RTC_ENABLE;
 443                 rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base,
 444                                                                         1);
 445                 if (rc < 0) {
 446                         dev_err(&pdev->dev,
 447                                 "Write to RTC control register failed\n");
 448                         return rc;
 449                 }
 450         }
 451
 452         rtc_dd->ctrl_reg = ctrl_reg;
 453         if (rtc_write_enable)
 454                 pm8xxx_rtc_ops.set_time = pm8xxx_rtc_set_time;
 455
 456         platform_set_drvdata(pdev, rtc_dd);
 457
 458         /* Register the RTC device */
 459         rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc",
 460                                                &pm8xxx_rtc_ops, THIS_MODULE);
 461         if (IS_ERR(rtc_dd->rtc)) {
 462                 dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
 463                         __func__, PTR_ERR(rtc_dd->rtc));
 464                 return PTR_ERR(rtc_dd->rtc);
 465         }
 466
 467         /* Request the alarm IRQ */
 468         rc = request_any_context_irq(rtc_dd->rtc_alarm_irq,
 469                                      pm8xxx_alarm_trigger, IRQF_TRIGGER_RISING,
 470                                      "pm8xxx_rtc_alarm", rtc_dd);
 471         if (rc < 0) {
 472                 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
 473                 return rc;
 474         }
 475
 476         device_init_wakeup(&pdev->dev, 1);
 477
 478         dev_dbg(&pdev->dev, "Probe success !!\n");
 479
 480         return 0;
 481 }
 482
 483 static int pm8xxx_rtc_remove(struct platform_device *pdev)
 484 {
 485         struct pm8xxx_rtc *rtc_dd = platform_get_drvdata(pdev);
 486
 487         device_init_wakeup(&pdev->dev, 0);
 488         free_irq(rtc_dd->rtc_alarm_irq, rtc_dd);
 489
 490         return 0;
 491 }
 492
 493 #ifdef CONFIG_PM_SLEEP
 494 static int pm8xxx_rtc_resume(struct device *dev)
 495 {
 496         struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
 497
 498         if (device_may_wakeup(dev))
 499                 disable_irq_wake(rtc_dd->rtc_alarm_irq);
 500
 501         return 0;
 502 }
 503
 504 static int pm8xxx_rtc_suspend(struct device *dev)
 505 {
 506         struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
 507
 508         if (device_may_wakeup(dev))
 509                 enable_irq_wake(rtc_dd->rtc_alarm_irq);
 510
 511         return 0;
 512 }
 513 #endif
 514
 515 static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
 516                          pm8xxx_rtc_suspend,
 517                          pm8xxx_rtc_resume);
 518
 519 static struct platform_driver pm8xxx_rtc_driver = {
 520         .probe          = pm8xxx_rtc_probe,
 521         .remove         = pm8xxx_rtc_remove,
 522         .driver = {
 523                 .name   = PM8XXX_RTC_DEV_NAME,
 524                 .owner  = THIS_MODULE,
 525                 .pm     = &pm8xxx_rtc_pm_ops,
 526         },
 527 };
 528
 529 module_platform_driver(pm8xxx_rtc_driver);
 530
 531 MODULE_ALIAS("platform:rtc-pm8xxx");
 532 MODULE_DESCRIPTION("PMIC8xxx RTC driver");
 533 MODULE_LICENSE("GPL v2");
 534 MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");