2 * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
4 * Copyright (c) 2010, NVIDIA Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/irq.h>
26 #include <linux/delay.h>
27 #include <linux/rtc.h>
28 #include <linux/platform_device.h>
31 /* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
32 #define TEGRA_RTC_REG_BUSY 0x004
33 #define TEGRA_RTC_REG_SECONDS 0x008
34 /* when msec is read, the seconds are buffered into shadow seconds. */
35 #define TEGRA_RTC_REG_SHADOW_SECONDS 0x00c
36 #define TEGRA_RTC_REG_MILLI_SECONDS 0x010
37 #define TEGRA_RTC_REG_SECONDS_ALARM0 0x014
38 #define TEGRA_RTC_REG_SECONDS_ALARM1 0x018
39 #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 0x01c
40 #define TEGRA_RTC_REG_INTR_MASK 0x028
41 /* write 1 bits to clear status bits */
42 #define TEGRA_RTC_REG_INTR_STATUS 0x02c
44 /* bits in INTR_MASK */
45 #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM (1<<4)
46 #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM (1<<3)
47 #define TEGRA_RTC_INTR_MASK_MSEC_ALARM (1<<2)
48 #define TEGRA_RTC_INTR_MASK_SEC_ALARM1 (1<<1)
49 #define TEGRA_RTC_INTR_MASK_SEC_ALARM0 (1<<0)
51 /* bits in INTR_STATUS */
52 #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
53 #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM (1<<3)
54 #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM (1<<2)
55 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 (1<<1)
56 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 (1<<0)
58 struct tegra_rtc_info {
59 struct platform_device *pdev;
60 struct rtc_device *rtc_dev;
61 void __iomem *rtc_base; /* NULL if not initialized. */
62 int tegra_rtc_irq; /* alarm and periodic irq */
63 spinlock_t tegra_rtc_lock;
66 /* RTC hardware is busy when it is updating its values over AHB once
67 * every eight 32kHz clocks (~250uS).
68 * outside of these updates the CPU is free to write.
69 * CPU is always free to read.
71 static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
73 return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
76 /* Wait for hardware to be ready for writing.
77 * This function tries to maximize the amount of time before the next update.
78 * It does this by waiting for the RTC to become busy with its periodic update,
79 * then returning once the RTC first becomes not busy.
80 * This periodic update (where the seconds and milliseconds are copied to the
81 * AHB side) occurs every eight 32kHz clocks (~250uS).
82 * The behavior of this function allows us to make some assumptions without
83 * introducing a race, because 250uS is plenty of time to read/write a value.
85 static int tegra_rtc_wait_while_busy(struct device *dev)
87 struct tegra_rtc_info *info = dev_get_drvdata(dev);
89 int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
91 /* first wait for the RTC to become busy. this is when it
92 * posts its updated seconds+msec registers to AHB side. */
93 while (tegra_rtc_check_busy(info)) {
99 /* now we have about 250 us to manipulate registers */
103 dev_err(dev, "write failed:retry count exceeded.\n");
107 static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
109 struct tegra_rtc_info *info = dev_get_drvdata(dev);
110 unsigned long sec, msec;
111 unsigned long sl_irq_flags;
113 /* RTC hardware copies seconds to shadow seconds when a read
114 * of milliseconds occurs. use a lock to keep other threads out. */
115 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
117 msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
118 sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);
120 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
122 rtc_time_to_tm(sec, tm);
124 dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n",
137 static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
139 struct tegra_rtc_info *info = dev_get_drvdata(dev);
143 /* convert tm to seconds. */
144 ret = rtc_valid_tm(tm);
148 rtc_tm_to_time(tm, &sec);
150 dev_vdbg(dev, "time set to %lu. %d/%d/%d %d:%02u:%02u\n",
160 /* seconds only written if wait succeeded. */
161 ret = tegra_rtc_wait_while_busy(dev);
163 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);
165 dev_vdbg(dev, "time read back as %d\n",
166 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));
171 static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
173 struct tegra_rtc_info *info = dev_get_drvdata(dev);
177 sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
180 /* alarm is disabled. */
182 alarm->time.tm_mon = -1;
183 alarm->time.tm_mday = -1;
184 alarm->time.tm_year = -1;
185 alarm->time.tm_hour = -1;
186 alarm->time.tm_min = -1;
187 alarm->time.tm_sec = -1;
189 /* alarm is enabled. */
191 rtc_time_to_tm(sec, &alarm->time);
194 tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
195 alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
200 static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
202 struct tegra_rtc_info *info = dev_get_drvdata(dev);
204 unsigned long sl_irq_flags;
206 tegra_rtc_wait_while_busy(dev);
207 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
209 /* read the original value, and OR in the flag. */
210 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
212 status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
214 status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
216 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
218 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
223 static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
225 struct tegra_rtc_info *info = dev_get_drvdata(dev);
229 rtc_tm_to_time(&alarm->time, &sec);
233 tegra_rtc_wait_while_busy(dev);
234 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
235 dev_vdbg(dev, "alarm read back as %d\n",
236 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
238 /* if successfully written and alarm is enabled ... */
240 tegra_rtc_alarm_irq_enable(dev, 1);
242 dev_vdbg(dev, "alarm set as %lu. %d/%d/%d %d:%02u:%02u\n",
244 alarm->time.tm_mon+1,
246 alarm->time.tm_year+1900,
251 /* disable alarm if 0 or write error. */
252 dev_vdbg(dev, "alarm disabled\n");
253 tegra_rtc_alarm_irq_enable(dev, 0);
259 static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
261 if (!dev || !dev->driver)
264 return seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
267 static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
269 struct device *dev = data;
270 struct tegra_rtc_info *info = dev_get_drvdata(dev);
271 unsigned long events = 0;
273 unsigned long sl_irq_flags;
275 status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
277 /* clear the interrupt masks and status on any irq. */
278 tegra_rtc_wait_while_busy(dev);
279 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
280 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
281 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
282 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
286 if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
287 events |= RTC_IRQF | RTC_AF;
289 /* check if Periodic */
290 if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
291 events |= RTC_IRQF | RTC_PF;
293 rtc_update_irq(info->rtc_dev, 1, events);
298 static struct rtc_class_ops tegra_rtc_ops = {
299 .read_time = tegra_rtc_read_time,
300 .set_time = tegra_rtc_set_time,
301 .read_alarm = tegra_rtc_read_alarm,
302 .set_alarm = tegra_rtc_set_alarm,
303 .proc = tegra_rtc_proc,
304 .alarm_irq_enable = tegra_rtc_alarm_irq_enable,
307 static const struct of_device_id tegra_rtc_dt_match[] = {
308 { .compatible = "nvidia,tegra20-rtc", },
311 MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
313 static int __init tegra_rtc_probe(struct platform_device *pdev)
315 struct tegra_rtc_info *info;
316 struct resource *res;
319 info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
324 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
327 "Unable to allocate resources for device.\n");
331 info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
332 if (IS_ERR(info->rtc_base))
333 return PTR_ERR(info->rtc_base);
335 info->tegra_rtc_irq = platform_get_irq(pdev, 0);
336 if (info->tegra_rtc_irq <= 0)
339 /* set context info. */
341 spin_lock_init(&info->tegra_rtc_lock);
343 platform_set_drvdata(pdev, info);
345 /* clear out the hardware. */
346 writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
347 writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
348 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
350 device_init_wakeup(&pdev->dev, 1);
352 info->rtc_dev = rtc_device_register(
353 pdev->name, &pdev->dev, &tegra_rtc_ops, THIS_MODULE);
354 if (IS_ERR(info->rtc_dev)) {
355 ret = PTR_ERR(info->rtc_dev);
356 info->rtc_dev = NULL;
358 "Unable to register device (err=%d).\n",
363 ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
364 tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
365 dev_name(&pdev->dev), &pdev->dev);
368 "Unable to request interrupt for device (err=%d).\n",
373 dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
378 rtc_device_unregister(info->rtc_dev);
383 static int __exit tegra_rtc_remove(struct platform_device *pdev)
385 struct tegra_rtc_info *info = platform_get_drvdata(pdev);
387 rtc_device_unregister(info->rtc_dev);
389 platform_set_drvdata(pdev, NULL);
394 #ifdef CONFIG_PM_SLEEP
395 static int tegra_rtc_suspend(struct device *dev)
397 struct tegra_rtc_info *info = dev_get_drvdata(dev);
399 tegra_rtc_wait_while_busy(dev);
401 /* only use ALARM0 as a wake source. */
402 writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
403 writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
404 info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
406 dev_vdbg(dev, "alarm sec = %d\n",
407 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
409 dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
410 device_may_wakeup(dev), info->tegra_rtc_irq);
412 /* leave the alarms on as a wake source. */
413 if (device_may_wakeup(dev))
414 enable_irq_wake(info->tegra_rtc_irq);
419 static int tegra_rtc_resume(struct device *dev)
421 struct tegra_rtc_info *info = dev_get_drvdata(dev);
423 dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
424 device_may_wakeup(dev));
425 /* alarms were left on as a wake source, turn them off. */
426 if (device_may_wakeup(dev))
427 disable_irq_wake(info->tegra_rtc_irq);
433 static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
435 static void tegra_rtc_shutdown(struct platform_device *pdev)
437 dev_vdbg(&pdev->dev, "disabling interrupts.\n");
438 tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
441 MODULE_ALIAS("platform:tegra_rtc");
442 static struct platform_driver tegra_rtc_driver = {
443 .remove = __exit_p(tegra_rtc_remove),
444 .shutdown = tegra_rtc_shutdown,
447 .owner = THIS_MODULE,
448 .of_match_table = tegra_rtc_dt_match,
449 .pm = &tegra_rtc_pm_ops,
453 module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);
455 MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
456 MODULE_DESCRIPTION("driver for Tegra internal RTC");
457 MODULE_LICENSE("GPL");