2 * Copyright (C) 2005 - 2012 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
18 #include <scsi/iscsi_proto.h>
24 int beiscsi_pci_soft_reset(struct beiscsi_hba *phba)
27 u8 *pci_reset_offset = 0;
28 u8 *pci_online0_offset = 0;
29 u8 *pci_online1_offset = 0;
34 pci_reset_offset = (u8 *)phba->pci_va + BE2_SOFT_RESET;
35 pci_online0_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE0;
36 pci_online1_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE1;
37 sreset = readl((void *)pci_reset_offset);
38 sreset |= BE2_SET_RESET;
39 writel(sreset, (void *)pci_reset_offset);
42 while (sreset & BE2_SET_RESET) {
46 sreset = readl((void *)pci_reset_offset);
50 if (sreset & BE2_SET_RESET) {
51 printk(KERN_ERR DRV_NAME
52 " Soft Reset did not deassert\n");
55 pconline1 = BE2_MPU_IRAM_ONLINE;
56 writel(pconline0, (void *)pci_online0_offset);
57 writel(pconline1, (void *)pci_online1_offset);
59 sreset |= BE2_SET_RESET;
60 writel(sreset, (void *)pci_reset_offset);
63 while (sreset & BE2_SET_RESET) {
67 sreset = readl((void *)pci_reset_offset);
70 if (sreset & BE2_SET_RESET) {
71 printk(KERN_ERR DRV_NAME
72 " MPU Online Soft Reset did not deassert\n");
78 int be_chk_reset_complete(struct beiscsi_hba *phba)
80 unsigned int num_loop;
85 mpu_sem = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
89 status = readl((void *)mpu_sem);
91 if ((status & 0x80000000) || (status & 0x0000FFFF) == 0xC000)
97 if ((status & 0x80000000) || (!num_loop)) {
98 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
99 "BC_%d : Failed in be_chk_reset_complete"
100 "status = 0x%x\n", status);
107 void be_mcc_notify(struct beiscsi_hba *phba)
109 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
112 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
113 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
114 iowrite32(val, phba->db_va + DB_MCCQ_OFFSET);
117 unsigned int alloc_mcc_tag(struct beiscsi_hba *phba)
119 unsigned int tag = 0;
121 if (phba->ctrl.mcc_tag_available) {
122 tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index];
123 phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0;
124 phba->ctrl.mcc_numtag[tag] = 0;
127 phba->ctrl.mcc_tag_available--;
128 if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1))
129 phba->ctrl.mcc_alloc_index = 0;
131 phba->ctrl.mcc_alloc_index++;
136 void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag)
138 spin_lock(&ctrl->mbox_lock);
139 tag = tag & 0x000000FF;
140 ctrl->mcc_tag[ctrl->mcc_free_index] = tag;
141 if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1))
142 ctrl->mcc_free_index = 0;
144 ctrl->mcc_free_index++;
145 ctrl->mcc_tag_available++;
146 spin_unlock(&ctrl->mbox_lock);
149 bool is_link_state_evt(u32 trailer)
151 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
152 ASYNC_TRAILER_EVENT_CODE_MASK) ==
153 ASYNC_EVENT_CODE_LINK_STATE);
156 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
158 if (compl->flags != 0) {
159 compl->flags = le32_to_cpu(compl->flags);
160 WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
166 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
171 static int be_mcc_compl_process(struct be_ctrl_info *ctrl,
172 struct be_mcc_compl *compl)
174 u16 compl_status, extd_status;
175 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
177 be_dws_le_to_cpu(compl, 4);
179 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
180 CQE_STATUS_COMPL_MASK;
181 if (compl_status != MCC_STATUS_SUCCESS) {
182 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
183 CQE_STATUS_EXTD_MASK;
185 beiscsi_log(phba, KERN_ERR,
186 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
187 "BC_%d : error in cmd completion: status(compl/extd)=%d/%d\n",
188 compl_status, extd_status);
195 int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl,
196 struct be_mcc_compl *compl)
198 u16 compl_status, extd_status;
201 be_dws_le_to_cpu(compl, 4);
203 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
204 CQE_STATUS_COMPL_MASK;
205 /* The ctrl.mcc_numtag[tag] is filled with
206 * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
207 * [7:0] = compl_status
209 tag = (compl->tag0 & 0x000000FF);
210 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
211 CQE_STATUS_EXTD_MASK;
213 ctrl->mcc_numtag[tag] = 0x80000000;
214 ctrl->mcc_numtag[tag] |= (compl->tag0 & 0x00FF0000);
215 ctrl->mcc_numtag[tag] |= (extd_status & 0x000000FF) << 8;
216 ctrl->mcc_numtag[tag] |= (compl_status & 0x000000FF);
217 wake_up_interruptible(&ctrl->mcc_wait[tag]);
221 static struct be_mcc_compl *be_mcc_compl_get(struct beiscsi_hba *phba)
223 struct be_queue_info *mcc_cq = &phba->ctrl.mcc_obj.cq;
224 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
226 if (be_mcc_compl_is_new(compl)) {
227 queue_tail_inc(mcc_cq);
233 static void be2iscsi_fail_session(struct iscsi_cls_session *cls_session)
235 iscsi_session_failure(cls_session->dd_data, ISCSI_ERR_CONN_FAILED);
238 void beiscsi_async_link_state_process(struct beiscsi_hba *phba,
239 struct be_async_event_link_state *evt)
241 switch (evt->port_link_status) {
242 case ASYNC_EVENT_LINK_DOWN:
243 beiscsi_log(phba, KERN_ERR,
244 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
245 "BC_%d : Link Down on Physical Port %d\n",
248 phba->state |= BE_ADAPTER_LINK_DOWN;
249 iscsi_host_for_each_session(phba->shost,
250 be2iscsi_fail_session);
252 case ASYNC_EVENT_LINK_UP:
253 phba->state = BE_ADAPTER_UP;
254 beiscsi_log(phba, KERN_ERR,
255 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
256 "BC_%d : Link UP on Physical Port %d\n",
260 beiscsi_log(phba, KERN_ERR,
261 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
262 "BC_%d : Unexpected Async Notification %d on"
263 "Physical Port %d\n",
264 evt->port_link_status,
269 static void beiscsi_cq_notify(struct beiscsi_hba *phba, u16 qid, bool arm,
273 val |= qid & DB_CQ_RING_ID_MASK;
275 val |= 1 << DB_CQ_REARM_SHIFT;
276 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
277 iowrite32(val, phba->db_va + DB_CQ_OFFSET);
281 int beiscsi_process_mcc(struct beiscsi_hba *phba)
283 struct be_mcc_compl *compl;
284 int num = 0, status = 0;
285 struct be_ctrl_info *ctrl = &phba->ctrl;
287 spin_lock_bh(&phba->ctrl.mcc_cq_lock);
288 while ((compl = be_mcc_compl_get(phba))) {
289 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
290 /* Interpret flags as an async trailer */
291 if (is_link_state_evt(compl->flags))
292 /* Interpret compl as a async link evt */
293 beiscsi_async_link_state_process(phba,
294 (struct be_async_event_link_state *) compl);
296 beiscsi_log(phba, KERN_ERR,
299 "BC_%d : Unsupported Async Event, flags"
300 " = 0x%08x\n", compl->flags);
302 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
303 status = be_mcc_compl_process(ctrl, compl);
304 atomic_dec(&phba->ctrl.mcc_obj.q.used);
306 be_mcc_compl_use(compl);
311 beiscsi_cq_notify(phba, phba->ctrl.mcc_obj.cq.id, true, num);
313 spin_unlock_bh(&phba->ctrl.mcc_cq_lock);
317 /* Wait till no more pending mcc requests are present */
318 static int be_mcc_wait_compl(struct beiscsi_hba *phba)
321 for (i = 0; i < mcc_timeout; i++) {
322 status = beiscsi_process_mcc(phba);
326 if (atomic_read(&phba->ctrl.mcc_obj.q.used) == 0)
330 if (i == mcc_timeout) {
331 beiscsi_log(phba, KERN_ERR,
332 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
333 "BC_%d : mccq poll timed out\n");
340 /* Notify MCC requests and wait for completion */
341 int be_mcc_notify_wait(struct beiscsi_hba *phba)
344 return be_mcc_wait_compl(phba);
347 static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl)
349 #define long_delay 2000
350 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
351 int cnt = 0, wait = 5; /* in usecs */
355 ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
359 if (cnt > 12000000) {
360 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
361 beiscsi_log(phba, KERN_ERR,
362 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
363 "BC_%d : mbox_db poll timed out\n");
370 mdelay(long_delay / 1000);
378 int be_mbox_notify(struct be_ctrl_info *ctrl)
382 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
383 struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
384 struct be_mcc_mailbox *mbox = mbox_mem->va;
385 struct be_mcc_compl *compl = &mbox->compl;
386 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
388 val &= ~MPU_MAILBOX_DB_RDY_MASK;
389 val |= MPU_MAILBOX_DB_HI_MASK;
390 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
393 status = be_mbox_db_ready_wait(ctrl);
395 beiscsi_log(phba, KERN_ERR,
396 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
397 "BC_%d : be_mbox_db_ready_wait failed\n");
402 val &= ~MPU_MAILBOX_DB_RDY_MASK;
403 val &= ~MPU_MAILBOX_DB_HI_MASK;
404 val |= (u32) (mbox_mem->dma >> 4) << 2;
407 status = be_mbox_db_ready_wait(ctrl);
409 beiscsi_log(phba, KERN_ERR,
410 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
411 "BC_%d : be_mbox_db_ready_wait failed\n");
415 if (be_mcc_compl_is_new(compl)) {
416 status = be_mcc_compl_process(ctrl, &mbox->compl);
417 be_mcc_compl_use(compl);
419 beiscsi_log(phba, KERN_ERR,
420 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
421 "BC_%d : After be_mcc_compl_process\n");
426 beiscsi_log(phba, KERN_ERR,
427 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
428 "BC_%d : Invalid Mailbox Completion\n");
436 * Insert the mailbox address into the doorbell in two steps
437 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
439 static int be_mbox_notify_wait(struct beiscsi_hba *phba)
443 void __iomem *db = phba->ctrl.db + MPU_MAILBOX_DB_OFFSET;
444 struct be_dma_mem *mbox_mem = &phba->ctrl.mbox_mem;
445 struct be_mcc_mailbox *mbox = mbox_mem->va;
446 struct be_mcc_compl *compl = &mbox->compl;
447 struct be_ctrl_info *ctrl = &phba->ctrl;
449 val |= MPU_MAILBOX_DB_HI_MASK;
450 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
451 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
454 /* wait for ready to be set */
455 status = be_mbox_db_ready_wait(ctrl);
460 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
461 val |= (u32)(mbox_mem->dma >> 4) << 2;
464 status = be_mbox_db_ready_wait(ctrl);
468 /* A cq entry has been made now */
469 if (be_mcc_compl_is_new(compl)) {
470 status = be_mcc_compl_process(ctrl, &mbox->compl);
471 be_mcc_compl_use(compl);
475 beiscsi_log(phba, KERN_ERR,
476 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
477 "BC_%d : invalid mailbox completion\n");
484 void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
485 bool embedded, u8 sge_cnt)
488 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
490 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
491 MCC_WRB_SGE_CNT_SHIFT;
492 wrb->payload_length = payload_len;
493 be_dws_cpu_to_le(wrb, 8);
496 void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
497 u8 subsystem, u8 opcode, int cmd_len)
499 req_hdr->opcode = opcode;
500 req_hdr->subsystem = subsystem;
501 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
502 req_hdr->timeout = 120;
505 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
506 struct be_dma_mem *mem)
509 u64 dma = (u64) mem->dma;
511 buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
512 for (i = 0; i < buf_pages; i++) {
513 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
514 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
519 static u32 eq_delay_to_mult(u32 usec_delay)
521 #define MAX_INTR_RATE 651042
522 const u32 round = 10;
528 u32 interrupt_rate = 1000000 / usec_delay;
529 if (interrupt_rate == 0)
532 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
533 multiplier /= interrupt_rate;
534 multiplier = (multiplier + round / 2) / round;
535 multiplier = min(multiplier, (u32) 1023);
541 struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
543 return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
546 struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba)
548 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
549 struct be_mcc_wrb *wrb;
551 BUG_ON(atomic_read(&mccq->used) >= mccq->len);
552 wrb = queue_head_node(mccq);
553 memset(wrb, 0, sizeof(*wrb));
554 wrb->tag0 = (mccq->head & 0x000000FF) << 16;
555 queue_head_inc(mccq);
556 atomic_inc(&mccq->used);
561 int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
562 struct be_queue_info *eq, int eq_delay)
564 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
565 struct be_cmd_req_eq_create *req = embedded_payload(wrb);
566 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
567 struct be_dma_mem *q_mem = &eq->dma_mem;
570 spin_lock(&ctrl->mbox_lock);
571 memset(wrb, 0, sizeof(*wrb));
573 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
575 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
576 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
578 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
580 AMAP_SET_BITS(struct amap_eq_context, func, req->context,
581 PCI_FUNC(ctrl->pdev->devfn));
582 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
583 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
584 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
585 __ilog2_u32(eq->len / 256));
586 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
587 eq_delay_to_mult(eq_delay));
588 be_dws_cpu_to_le(req->context, sizeof(req->context));
590 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
592 status = be_mbox_notify(ctrl);
594 eq->id = le16_to_cpu(resp->eq_id);
597 spin_unlock(&ctrl->mbox_lock);
601 int be_cmd_fw_initialize(struct be_ctrl_info *ctrl)
603 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
604 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
608 spin_lock(&ctrl->mbox_lock);
609 memset(wrb, 0, sizeof(*wrb));
611 endian_check = (u8 *) wrb;
612 *endian_check++ = 0xFF;
613 *endian_check++ = 0x12;
614 *endian_check++ = 0x34;
615 *endian_check++ = 0xFF;
616 *endian_check++ = 0xFF;
617 *endian_check++ = 0x56;
618 *endian_check++ = 0x78;
619 *endian_check++ = 0xFF;
620 be_dws_cpu_to_le(wrb, sizeof(*wrb));
622 status = be_mbox_notify(ctrl);
624 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
625 "BC_%d : be_cmd_fw_initialize Failed\n");
627 spin_unlock(&ctrl->mbox_lock);
631 int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
632 struct be_queue_info *cq, struct be_queue_info *eq,
633 bool sol_evts, bool no_delay, int coalesce_wm)
635 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
636 struct be_cmd_req_cq_create *req = embedded_payload(wrb);
637 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
638 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
639 struct be_dma_mem *q_mem = &cq->dma_mem;
640 void *ctxt = &req->context;
643 spin_lock(&ctrl->mbox_lock);
644 memset(wrb, 0, sizeof(*wrb));
646 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
648 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
649 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
651 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
652 if (chip_skh_r(ctrl->pdev)) {
653 req->hdr.version = MBX_CMD_VER2;
655 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
657 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay,
659 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
660 __ilog2_u32(cq->len / 256));
661 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
662 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
663 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
664 AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1);
666 AMAP_SET_BITS(struct amap_cq_context, coalescwm,
668 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
669 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
670 __ilog2_u32(cq->len / 256));
671 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
672 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
673 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
674 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
675 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
676 AMAP_SET_BITS(struct amap_cq_context, func, ctxt,
677 PCI_FUNC(ctrl->pdev->devfn));
680 be_dws_cpu_to_le(ctxt, sizeof(req->context));
682 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
684 status = be_mbox_notify(ctrl);
686 cq->id = le16_to_cpu(resp->cq_id);
689 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
690 "BC_%d : In be_cmd_cq_create, status=ox%08x\n",
693 spin_unlock(&ctrl->mbox_lock);
698 static u32 be_encoded_q_len(int q_len)
700 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
701 if (len_encoded == 16)
706 int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba,
707 struct be_queue_info *mccq,
708 struct be_queue_info *cq)
710 struct be_mcc_wrb *wrb;
711 struct be_cmd_req_mcc_create *req;
712 struct be_dma_mem *q_mem = &mccq->dma_mem;
713 struct be_ctrl_info *ctrl;
717 spin_lock(&phba->ctrl.mbox_lock);
719 wrb = wrb_from_mbox(&ctrl->mbox_mem);
720 memset(wrb, 0, sizeof(*wrb));
721 req = embedded_payload(wrb);
722 ctxt = &req->context;
724 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
726 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
727 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
729 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
731 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt,
732 PCI_FUNC(phba->pcidev->devfn));
733 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
734 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
735 be_encoded_q_len(mccq->len));
736 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
738 be_dws_cpu_to_le(ctxt, sizeof(req->context));
740 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
742 status = be_mbox_notify_wait(phba);
744 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
745 mccq->id = le16_to_cpu(resp->id);
746 mccq->created = true;
748 spin_unlock(&phba->ctrl.mbox_lock);
753 int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
756 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
757 struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
758 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
759 u8 subsys = 0, opcode = 0;
762 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
763 "BC_%d : In beiscsi_cmd_q_destroy "
764 "queue_type : %d\n", queue_type);
766 spin_lock(&ctrl->mbox_lock);
767 memset(wrb, 0, sizeof(*wrb));
768 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
770 switch (queue_type) {
772 subsys = CMD_SUBSYSTEM_COMMON;
773 opcode = OPCODE_COMMON_EQ_DESTROY;
776 subsys = CMD_SUBSYSTEM_COMMON;
777 opcode = OPCODE_COMMON_CQ_DESTROY;
780 subsys = CMD_SUBSYSTEM_COMMON;
781 opcode = OPCODE_COMMON_MCC_DESTROY;
784 subsys = CMD_SUBSYSTEM_ISCSI;
785 opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY;
788 subsys = CMD_SUBSYSTEM_ISCSI;
789 opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY;
792 subsys = CMD_SUBSYSTEM_ISCSI;
793 opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES;
796 spin_unlock(&ctrl->mbox_lock);
800 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
801 if (queue_type != QTYPE_SGL)
802 req->id = cpu_to_le16(q->id);
804 status = be_mbox_notify(ctrl);
806 spin_unlock(&ctrl->mbox_lock);
810 int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
811 struct be_queue_info *cq,
812 struct be_queue_info *dq, int length,
815 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
816 struct be_defq_create_req *req = embedded_payload(wrb);
817 struct be_dma_mem *q_mem = &dq->dma_mem;
818 void *ctxt = &req->context;
821 spin_lock(&ctrl->mbox_lock);
822 memset(wrb, 0, sizeof(*wrb));
824 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
826 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
827 OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req));
829 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
830 AMAP_SET_BITS(struct amap_be_default_pdu_context, rx_pdid, ctxt, 0);
831 AMAP_SET_BITS(struct amap_be_default_pdu_context, rx_pdid_valid, ctxt,
833 AMAP_SET_BITS(struct amap_be_default_pdu_context, pci_func_id, ctxt,
834 PCI_FUNC(ctrl->pdev->devfn));
835 AMAP_SET_BITS(struct amap_be_default_pdu_context, ring_size, ctxt,
836 be_encoded_q_len(length / sizeof(struct phys_addr)));
837 AMAP_SET_BITS(struct amap_be_default_pdu_context, default_buffer_size,
839 AMAP_SET_BITS(struct amap_be_default_pdu_context, cq_id_recv, ctxt,
842 be_dws_cpu_to_le(ctxt, sizeof(req->context));
844 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
846 status = be_mbox_notify(ctrl);
848 struct be_defq_create_resp *resp = embedded_payload(wrb);
850 dq->id = le16_to_cpu(resp->id);
853 spin_unlock(&ctrl->mbox_lock);
858 int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, struct be_dma_mem *q_mem,
859 struct be_queue_info *wrbq)
861 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
862 struct be_wrbq_create_req *req = embedded_payload(wrb);
863 struct be_wrbq_create_resp *resp = embedded_payload(wrb);
866 spin_lock(&ctrl->mbox_lock);
867 memset(wrb, 0, sizeof(*wrb));
869 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
871 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
872 OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req));
873 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
874 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
876 status = be_mbox_notify(ctrl);
878 wrbq->id = le16_to_cpu(resp->cid);
879 wrbq->created = true;
881 spin_unlock(&ctrl->mbox_lock);
885 int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
886 struct be_dma_mem *q_mem,
887 u32 page_offset, u32 num_pages)
889 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
890 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
891 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
893 unsigned int curr_pages;
894 u32 internal_page_offset = 0;
895 u32 temp_num_pages = num_pages;
897 if (num_pages == 0xff)
900 spin_lock(&ctrl->mbox_lock);
902 memset(wrb, 0, sizeof(*wrb));
903 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
904 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
905 OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES,
907 curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req,
909 req->num_pages = min(num_pages, curr_pages);
910 req->page_offset = page_offset;
911 be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem);
912 q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE);
913 internal_page_offset += req->num_pages;
914 page_offset += req->num_pages;
915 num_pages -= req->num_pages;
917 if (temp_num_pages == 0xff)
918 req->num_pages = temp_num_pages;
920 status = be_mbox_notify(ctrl);
922 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
923 "BC_%d : FW CMD to map iscsi frags failed.\n");
927 } while (num_pages > 0);
929 spin_unlock(&ctrl->mbox_lock);
931 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
935 int beiscsi_cmd_reset_function(struct beiscsi_hba *phba)
937 struct be_ctrl_info *ctrl = &phba->ctrl;
938 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
939 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
942 spin_lock(&ctrl->mbox_lock);
944 req = embedded_payload(wrb);
945 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
946 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
947 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
948 status = be_mbox_notify_wait(phba);
950 spin_unlock(&ctrl->mbox_lock);
955 * be_cmd_set_vlan()- Configure VLAN paramters on the adapter
956 * @phba: device priv structure instance
957 * @vlan_tag: TAG to be set
959 * Set the VLAN_TAG for the adapter or Disable VLAN on adapter
962 * TAG for the MBX Cmd
964 int be_cmd_set_vlan(struct beiscsi_hba *phba,
967 unsigned int tag = 0;
968 struct be_mcc_wrb *wrb;
969 struct be_cmd_set_vlan_req *req;
970 struct be_ctrl_info *ctrl = &phba->ctrl;
972 spin_lock(&ctrl->mbox_lock);
973 tag = alloc_mcc_tag(phba);
975 spin_unlock(&ctrl->mbox_lock);
979 wrb = wrb_from_mccq(phba);
980 req = embedded_payload(wrb);
982 be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0);
983 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
984 OPCODE_COMMON_ISCSI_NTWK_SET_VLAN,
987 req->interface_hndl = phba->interface_handle;
988 req->vlan_priority = vlan_tag;
991 spin_unlock(&ctrl->mbox_lock);