2 * Copyright (C) 2005 - 2015 Avago Technologies
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@avagotech.com
15 * Costa Mesa, CA 92626
18 #include <scsi/iscsi_proto.h>
24 int beiscsi_pci_soft_reset(struct beiscsi_hba *phba)
27 u8 *pci_reset_offset = 0;
28 u8 *pci_online0_offset = 0;
29 u8 *pci_online1_offset = 0;
34 pci_reset_offset = (u8 *)phba->pci_va + BE2_SOFT_RESET;
35 pci_online0_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE0;
36 pci_online1_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE1;
37 sreset = readl((void *)pci_reset_offset);
38 sreset |= BE2_SET_RESET;
39 writel(sreset, (void *)pci_reset_offset);
42 while (sreset & BE2_SET_RESET) {
46 sreset = readl((void *)pci_reset_offset);
50 if (sreset & BE2_SET_RESET) {
51 printk(KERN_ERR DRV_NAME
52 " Soft Reset did not deassert\n");
55 pconline1 = BE2_MPU_IRAM_ONLINE;
56 writel(pconline0, (void *)pci_online0_offset);
57 writel(pconline1, (void *)pci_online1_offset);
59 sreset |= BE2_SET_RESET;
60 writel(sreset, (void *)pci_reset_offset);
63 while (sreset & BE2_SET_RESET) {
67 sreset = readl((void *)pci_reset_offset);
70 if (sreset & BE2_SET_RESET) {
71 printk(KERN_ERR DRV_NAME
72 " MPU Online Soft Reset did not deassert\n");
78 int be_chk_reset_complete(struct beiscsi_hba *phba)
80 unsigned int num_loop;
85 mpu_sem = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
89 status = readl((void *)mpu_sem);
91 if ((status & 0x80000000) || (status & 0x0000FFFF) == 0xC000)
97 if ((status & 0x80000000) || (!num_loop)) {
98 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
99 "BC_%d : Failed in be_chk_reset_complete"
100 "status = 0x%x\n", status);
107 void be_mcc_notify(struct beiscsi_hba *phba)
109 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
112 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
113 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
114 iowrite32(val, phba->db_va + DB_MCCQ_OFFSET);
117 unsigned int alloc_mcc_tag(struct beiscsi_hba *phba)
119 unsigned int tag = 0;
121 if (phba->ctrl.mcc_tag_available) {
122 tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index];
123 phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0;
124 phba->ctrl.mcc_numtag[tag] = 0;
127 phba->ctrl.mcc_tag_available--;
128 if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1))
129 phba->ctrl.mcc_alloc_index = 0;
131 phba->ctrl.mcc_alloc_index++;
137 * beiscsi_mccq_compl()- Wait for completion of MBX
138 * @phba: Driver private structure
139 * @tag: Tag for the MBX Command
140 * @wrb: the WRB used for the MBX Command
141 * @mbx_cmd_mem: ptr to memory allocated for MBX Cmd
143 * Waits for MBX completion with the passed TAG.
149 int beiscsi_mccq_compl(struct beiscsi_hba *phba,
150 uint32_t tag, struct be_mcc_wrb **wrb,
151 struct be_dma_mem *mbx_cmd_mem)
154 uint32_t mcc_tag_response;
155 uint16_t status = 0, addl_status = 0, wrb_num = 0;
156 struct be_mcc_wrb *temp_wrb;
157 struct be_cmd_req_hdr *mbx_hdr;
158 struct be_cmd_resp_hdr *mbx_resp_hdr;
159 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
161 if (beiscsi_error(phba)) {
162 free_mcc_tag(&phba->ctrl, tag);
166 /* Set MBX Tag state to Active */
167 spin_lock(&phba->ctrl.mbox_lock);
168 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_RUNNING;
169 spin_unlock(&phba->ctrl.mbox_lock);
171 /* wait for the mccq completion */
172 rc = wait_event_interruptible_timeout(
173 phba->ctrl.mcc_wait[tag],
174 phba->ctrl.mcc_numtag[tag],
176 BEISCSI_HOST_MBX_TIMEOUT));
179 struct be_dma_mem *tag_mem;
180 /* Set MBX Tag state to timeout */
181 spin_lock(&phba->ctrl.mbox_lock);
182 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_TIMEOUT;
183 spin_unlock(&phba->ctrl.mbox_lock);
185 /* Store resource addr to be freed later */
186 tag_mem = &phba->ctrl.ptag_state[tag].tag_mem_state;
188 tag_mem->size = mbx_cmd_mem->size;
189 tag_mem->va = mbx_cmd_mem->va;
190 tag_mem->dma = mbx_cmd_mem->dma;
194 beiscsi_log(phba, KERN_ERR,
195 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
197 "BC_%d : MBX Cmd Completion timed out\n");
201 /* Set MBX Tag state to completed */
202 spin_lock(&phba->ctrl.mbox_lock);
203 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_COMPLETED;
204 spin_unlock(&phba->ctrl.mbox_lock);
207 mcc_tag_response = phba->ctrl.mcc_numtag[tag];
208 status = (mcc_tag_response & CQE_STATUS_MASK);
209 addl_status = ((mcc_tag_response & CQE_STATUS_ADDL_MASK) >>
210 CQE_STATUS_ADDL_SHIFT);
213 mbx_hdr = (struct be_cmd_req_hdr *)mbx_cmd_mem->va;
215 wrb_num = (mcc_tag_response & CQE_STATUS_WRB_MASK) >>
216 CQE_STATUS_WRB_SHIFT;
217 temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num);
218 mbx_hdr = embedded_payload(temp_wrb);
224 if (status || addl_status) {
225 beiscsi_log(phba, KERN_WARNING,
226 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
228 "BC_%d : MBX Cmd Failed for "
229 "Subsys : %d Opcode : %d with "
230 "Status : %d and Extd_Status : %d\n",
233 status, addl_status);
235 if (status == MCC_STATUS_INSUFFICIENT_BUFFER) {
236 mbx_resp_hdr = (struct be_cmd_resp_hdr *) mbx_hdr;
237 beiscsi_log(phba, KERN_WARNING,
238 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
240 "BC_%d : Insufficient Buffer Error "
241 "Resp_Len : %d Actual_Resp_Len : %d\n",
242 mbx_resp_hdr->response_length,
243 mbx_resp_hdr->actual_resp_len);
246 goto release_mcc_tag;
252 /* Release the MCC entry */
253 free_mcc_tag(&phba->ctrl, tag);
258 void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag)
260 spin_lock(&ctrl->mbox_lock);
261 tag = tag & 0x000000FF;
262 ctrl->mcc_tag[ctrl->mcc_free_index] = tag;
263 if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1))
264 ctrl->mcc_free_index = 0;
266 ctrl->mcc_free_index++;
267 ctrl->mcc_tag_available++;
268 spin_unlock(&ctrl->mbox_lock);
271 bool is_link_state_evt(u32 trailer)
273 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
274 ASYNC_TRAILER_EVENT_CODE_MASK) ==
275 ASYNC_EVENT_CODE_LINK_STATE);
278 static bool is_iscsi_evt(u32 trailer)
280 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
281 ASYNC_TRAILER_EVENT_CODE_MASK) ==
282 ASYNC_EVENT_CODE_ISCSI;
285 static int iscsi_evt_type(u32 trailer)
287 return (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
288 ASYNC_TRAILER_EVENT_TYPE_MASK;
291 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
293 if (compl->flags != 0) {
294 compl->flags = le32_to_cpu(compl->flags);
295 WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
301 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
307 * be_mcc_compl_process()- Check the MBX comapletion status
308 * @ctrl: Function specific MBX data structure
309 * @compl: Completion status of MBX Command
311 * Check for the MBX completion status when BMBX method used
317 static int be_mcc_compl_process(struct be_ctrl_info *ctrl,
318 struct be_mcc_compl *compl)
320 u16 compl_status, extd_status;
321 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
322 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
323 struct be_cmd_req_hdr *hdr = embedded_payload(wrb);
324 struct be_cmd_resp_hdr *resp_hdr;
326 be_dws_le_to_cpu(compl, 4);
328 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
329 CQE_STATUS_COMPL_MASK;
330 if (compl_status != MCC_STATUS_SUCCESS) {
331 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
332 CQE_STATUS_EXTD_MASK;
334 beiscsi_log(phba, KERN_ERR,
335 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
336 "BC_%d : error in cmd completion: "
337 "Subsystem : %d Opcode : %d "
338 "status(compl/extd)=%d/%d\n",
339 hdr->subsystem, hdr->opcode,
340 compl_status, extd_status);
342 if (compl_status == MCC_STATUS_INSUFFICIENT_BUFFER) {
343 resp_hdr = (struct be_cmd_resp_hdr *) hdr;
344 if (resp_hdr->response_length)
352 int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl,
353 struct be_mcc_compl *compl)
355 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
356 u16 compl_status, extd_status;
359 be_dws_le_to_cpu(compl, 4);
361 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
362 CQE_STATUS_COMPL_MASK;
363 /* The ctrl.mcc_numtag[tag] is filled with
364 * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
365 * [7:0] = compl_status
367 tag = (compl->tag0 & 0x000000FF);
368 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
369 CQE_STATUS_EXTD_MASK;
371 ctrl->mcc_numtag[tag] = 0x80000000;
372 ctrl->mcc_numtag[tag] |= (compl->tag0 & 0x00FF0000);
373 ctrl->mcc_numtag[tag] |= (extd_status & 0x000000FF) << 8;
374 ctrl->mcc_numtag[tag] |= (compl_status & 0x000000FF);
376 if (ctrl->ptag_state[tag].tag_state == MCC_TAG_STATE_RUNNING) {
377 wake_up_interruptible(&ctrl->mcc_wait[tag]);
378 } else if (ctrl->ptag_state[tag].tag_state == MCC_TAG_STATE_TIMEOUT) {
379 struct be_dma_mem *tag_mem;
380 tag_mem = &ctrl->ptag_state[tag].tag_mem_state;
382 beiscsi_log(phba, KERN_WARNING,
383 BEISCSI_LOG_MBOX | BEISCSI_LOG_INIT |
385 "BC_%d : MBX Completion for timeout Command "
387 /* Check if memory needs to be freed */
389 pci_free_consistent(ctrl->pdev, tag_mem->size,
390 tag_mem->va, tag_mem->dma);
392 /* Change tag state */
393 spin_lock(&phba->ctrl.mbox_lock);
394 ctrl->ptag_state[tag].tag_state = MCC_TAG_STATE_COMPLETED;
395 spin_unlock(&phba->ctrl.mbox_lock);
398 free_mcc_tag(ctrl, tag);
404 static struct be_mcc_compl *be_mcc_compl_get(struct beiscsi_hba *phba)
406 struct be_queue_info *mcc_cq = &phba->ctrl.mcc_obj.cq;
407 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
409 if (be_mcc_compl_is_new(compl)) {
410 queue_tail_inc(mcc_cq);
417 * be2iscsi_fail_session(): Closing session with appropriate error
418 * @cls_session: ptr to session
420 * Depending on adapter state appropriate error flag is passed.
422 void be2iscsi_fail_session(struct iscsi_cls_session *cls_session)
424 struct Scsi_Host *shost = iscsi_session_to_shost(cls_session);
425 struct beiscsi_hba *phba = iscsi_host_priv(shost);
426 uint32_t iscsi_err_flag;
428 if (phba->state & BE_ADAPTER_STATE_SHUTDOWN)
429 iscsi_err_flag = ISCSI_ERR_INVALID_HOST;
431 iscsi_err_flag = ISCSI_ERR_CONN_FAILED;
433 iscsi_session_failure(cls_session->dd_data, ISCSI_ERR_CONN_FAILED);
436 void beiscsi_async_link_state_process(struct beiscsi_hba *phba,
437 struct be_async_event_link_state *evt)
439 if ((evt->port_link_status == ASYNC_EVENT_LINK_DOWN) ||
440 ((evt->port_link_status & ASYNC_EVENT_LOGICAL) &&
441 (evt->port_fault != BEISCSI_PHY_LINK_FAULT_NONE))) {
442 phba->state = BE_ADAPTER_LINK_DOWN;
444 beiscsi_log(phba, KERN_ERR,
445 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
446 "BC_%d : Link Down on Port %d\n",
449 iscsi_host_for_each_session(phba->shost,
450 be2iscsi_fail_session);
451 } else if ((evt->port_link_status & ASYNC_EVENT_LINK_UP) ||
452 ((evt->port_link_status & ASYNC_EVENT_LOGICAL) &&
453 (evt->port_fault == BEISCSI_PHY_LINK_FAULT_NONE))) {
454 phba->state = BE_ADAPTER_LINK_UP | BE_ADAPTER_CHECK_BOOT;
455 phba->get_boot = BE_GET_BOOT_RETRIES;
457 beiscsi_log(phba, KERN_ERR,
458 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
459 "BC_%d : Link UP on Port %d\n",
464 int beiscsi_process_mcc(struct beiscsi_hba *phba)
466 struct be_mcc_compl *compl;
467 int num = 0, status = 0;
468 struct be_ctrl_info *ctrl = &phba->ctrl;
470 spin_lock_bh(&phba->ctrl.mcc_cq_lock);
471 while ((compl = be_mcc_compl_get(phba))) {
472 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
473 /* Interpret flags as an async trailer */
474 if (is_link_state_evt(compl->flags))
475 /* Interpret compl as a async link evt */
476 beiscsi_async_link_state_process(phba,
477 (struct be_async_event_link_state *) compl);
478 else if (is_iscsi_evt(compl->flags)) {
479 switch (iscsi_evt_type(compl->flags)) {
480 case ASYNC_EVENT_NEW_ISCSI_TGT_DISC:
481 case ASYNC_EVENT_NEW_ISCSI_CONN:
482 case ASYNC_EVENT_NEW_TCP_CONN:
483 phba->state |= BE_ADAPTER_CHECK_BOOT;
484 phba->get_boot = BE_GET_BOOT_RETRIES;
485 beiscsi_log(phba, KERN_ERR,
488 "BC_%d : Async iscsi Event,"
489 " flags handled = 0x%08x\n",
493 phba->state |= BE_ADAPTER_CHECK_BOOT;
494 phba->get_boot = BE_GET_BOOT_RETRIES;
495 beiscsi_log(phba, KERN_ERR,
498 "BC_%d : Unsupported Async"
499 " Event, flags = 0x%08x\n",
503 beiscsi_log(phba, KERN_ERR,
506 "BC_%d : Unsupported Async Event, flags"
507 " = 0x%08x\n", compl->flags);
509 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
510 status = be_mcc_compl_process(ctrl, compl);
511 atomic_dec(&phba->ctrl.mcc_obj.q.used);
513 be_mcc_compl_use(compl);
518 hwi_ring_cq_db(phba, phba->ctrl.mcc_obj.cq.id, num, 1, 0);
520 spin_unlock_bh(&phba->ctrl.mcc_cq_lock);
525 * be_mcc_wait_compl()- Wait for MBX completion
526 * @phba: driver private structure
528 * Wait till no more pending mcc requests are present
535 static int be_mcc_wait_compl(struct beiscsi_hba *phba)
538 for (i = 0; i < mcc_timeout; i++) {
539 if (beiscsi_error(phba))
542 status = beiscsi_process_mcc(phba);
546 if (atomic_read(&phba->ctrl.mcc_obj.q.used) == 0)
550 if (i == mcc_timeout) {
551 beiscsi_log(phba, KERN_ERR,
552 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
553 "BC_%d : FW Timed Out\n");
554 phba->fw_timeout = true;
555 beiscsi_ue_detect(phba);
562 * be_mcc_notify_wait()- Notify and wait for Compl
563 * @phba: driver private structure
565 * Notify MCC requests and wait for completion
571 int be_mcc_notify_wait(struct beiscsi_hba *phba)
574 return be_mcc_wait_compl(phba);
578 * be_mbox_db_ready_wait()- Check ready status
579 * @ctrl: Function specific MBX data structure
581 * Check for the ready status of FW to send BMBX
582 * commands to adapter.
588 static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl)
590 #define BEISCSI_MBX_RDY_BIT_TIMEOUT 4000 /* 4sec */
591 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
592 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
593 unsigned long timeout;
594 bool read_flag = false;
597 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(rdybit_check_q);
599 if (beiscsi_error(phba))
602 timeout = jiffies + (HZ * 110);
605 for (i = 0; i < BEISCSI_MBX_RDY_BIT_TIMEOUT; i++) {
606 ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
615 wait_event_timeout(rdybit_check_q,
619 } while ((time_before(jiffies, timeout)) && !read_flag);
622 beiscsi_log(phba, KERN_ERR,
623 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
624 "BC_%d : FW Timed Out\n");
625 phba->fw_timeout = true;
626 beiscsi_ue_detect(phba);
634 * be_mbox_notify: Notify adapter of new BMBX command
635 * @ctrl: Function specific MBX data structure
637 * Ring doorbell to inform adapter of a BMBX command
644 int be_mbox_notify(struct be_ctrl_info *ctrl)
648 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
649 struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
650 struct be_mcc_mailbox *mbox = mbox_mem->va;
651 struct be_mcc_compl *compl = &mbox->compl;
652 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
654 status = be_mbox_db_ready_wait(ctrl);
658 val &= ~MPU_MAILBOX_DB_RDY_MASK;
659 val |= MPU_MAILBOX_DB_HI_MASK;
660 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
663 status = be_mbox_db_ready_wait(ctrl);
668 val &= ~MPU_MAILBOX_DB_RDY_MASK;
669 val &= ~MPU_MAILBOX_DB_HI_MASK;
670 val |= (u32) (mbox_mem->dma >> 4) << 2;
673 status = be_mbox_db_ready_wait(ctrl);
677 if (be_mcc_compl_is_new(compl)) {
678 status = be_mcc_compl_process(ctrl, &mbox->compl);
679 be_mcc_compl_use(compl);
681 beiscsi_log(phba, KERN_ERR,
682 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
683 "BC_%d : After be_mcc_compl_process\n");
688 beiscsi_log(phba, KERN_ERR,
689 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
690 "BC_%d : Invalid Mailbox Completion\n");
698 * Insert the mailbox address into the doorbell in two steps
699 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
701 static int be_mbox_notify_wait(struct beiscsi_hba *phba)
705 void __iomem *db = phba->ctrl.db + MPU_MAILBOX_DB_OFFSET;
706 struct be_dma_mem *mbox_mem = &phba->ctrl.mbox_mem;
707 struct be_mcc_mailbox *mbox = mbox_mem->va;
708 struct be_mcc_compl *compl = &mbox->compl;
709 struct be_ctrl_info *ctrl = &phba->ctrl;
711 status = be_mbox_db_ready_wait(ctrl);
715 val |= MPU_MAILBOX_DB_HI_MASK;
716 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
717 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
720 /* wait for ready to be set */
721 status = be_mbox_db_ready_wait(ctrl);
726 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
727 val |= (u32)(mbox_mem->dma >> 4) << 2;
730 status = be_mbox_db_ready_wait(ctrl);
734 /* A cq entry has been made now */
735 if (be_mcc_compl_is_new(compl)) {
736 status = be_mcc_compl_process(ctrl, &mbox->compl);
737 be_mcc_compl_use(compl);
741 beiscsi_log(phba, KERN_ERR,
742 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
743 "BC_%d : invalid mailbox completion\n");
750 void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
751 bool embedded, u8 sge_cnt)
754 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
756 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
757 MCC_WRB_SGE_CNT_SHIFT;
758 wrb->payload_length = payload_len;
759 be_dws_cpu_to_le(wrb, 8);
762 void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
763 u8 subsystem, u8 opcode, int cmd_len)
765 req_hdr->opcode = opcode;
766 req_hdr->subsystem = subsystem;
767 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
768 req_hdr->timeout = BEISCSI_FW_MBX_TIMEOUT;
771 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
772 struct be_dma_mem *mem)
775 u64 dma = (u64) mem->dma;
777 buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
778 for (i = 0; i < buf_pages; i++) {
779 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
780 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
785 static u32 eq_delay_to_mult(u32 usec_delay)
787 #define MAX_INTR_RATE 651042
788 const u32 round = 10;
794 u32 interrupt_rate = 1000000 / usec_delay;
795 if (interrupt_rate == 0)
798 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
799 multiplier /= interrupt_rate;
800 multiplier = (multiplier + round / 2) / round;
801 multiplier = min(multiplier, (u32) 1023);
807 struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
809 return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
812 struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba)
814 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
815 struct be_mcc_wrb *wrb;
817 WARN_ON(atomic_read(&mccq->used) >= mccq->len);
818 wrb = queue_head_node(mccq);
819 memset(wrb, 0, sizeof(*wrb));
820 wrb->tag0 = (mccq->head & 0x000000FF) << 16;
821 queue_head_inc(mccq);
822 atomic_inc(&mccq->used);
827 int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
828 struct be_queue_info *eq, int eq_delay)
830 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
831 struct be_cmd_req_eq_create *req = embedded_payload(wrb);
832 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
833 struct be_dma_mem *q_mem = &eq->dma_mem;
836 spin_lock(&ctrl->mbox_lock);
837 memset(wrb, 0, sizeof(*wrb));
839 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
841 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
842 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
844 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
846 AMAP_SET_BITS(struct amap_eq_context, func, req->context,
847 PCI_FUNC(ctrl->pdev->devfn));
848 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
849 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
850 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
851 __ilog2_u32(eq->len / 256));
852 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
853 eq_delay_to_mult(eq_delay));
854 be_dws_cpu_to_le(req->context, sizeof(req->context));
856 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
858 status = be_mbox_notify(ctrl);
860 eq->id = le16_to_cpu(resp->eq_id);
863 spin_unlock(&ctrl->mbox_lock);
868 * be_cmd_fw_initialize()- Initialize FW
869 * @ctrl: Pointer to function control structure
871 * Send FW initialize pattern for the function.
875 * Failure: Non-Zero value
877 int be_cmd_fw_initialize(struct be_ctrl_info *ctrl)
879 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
880 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
884 spin_lock(&ctrl->mbox_lock);
885 memset(wrb, 0, sizeof(*wrb));
887 endian_check = (u8 *) wrb;
888 *endian_check++ = 0xFF;
889 *endian_check++ = 0x12;
890 *endian_check++ = 0x34;
891 *endian_check++ = 0xFF;
892 *endian_check++ = 0xFF;
893 *endian_check++ = 0x56;
894 *endian_check++ = 0x78;
895 *endian_check++ = 0xFF;
896 be_dws_cpu_to_le(wrb, sizeof(*wrb));
898 status = be_mbox_notify(ctrl);
900 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
901 "BC_%d : be_cmd_fw_initialize Failed\n");
903 spin_unlock(&ctrl->mbox_lock);
908 * be_cmd_fw_uninit()- Uinitialize FW
909 * @ctrl: Pointer to function control structure
911 * Send FW uninitialize pattern for the function
915 * Failure: Non-Zero value
917 int be_cmd_fw_uninit(struct be_ctrl_info *ctrl)
919 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
920 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
924 spin_lock(&ctrl->mbox_lock);
925 memset(wrb, 0, sizeof(*wrb));
927 endian_check = (u8 *) wrb;
928 *endian_check++ = 0xFF;
929 *endian_check++ = 0xAA;
930 *endian_check++ = 0xBB;
931 *endian_check++ = 0xFF;
932 *endian_check++ = 0xFF;
933 *endian_check++ = 0xCC;
934 *endian_check++ = 0xDD;
935 *endian_check = 0xFF;
937 be_dws_cpu_to_le(wrb, sizeof(*wrb));
939 status = be_mbox_notify(ctrl);
941 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
942 "BC_%d : be_cmd_fw_uninit Failed\n");
944 spin_unlock(&ctrl->mbox_lock);
948 int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
949 struct be_queue_info *cq, struct be_queue_info *eq,
950 bool sol_evts, bool no_delay, int coalesce_wm)
952 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
953 struct be_cmd_req_cq_create *req = embedded_payload(wrb);
954 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
955 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
956 struct be_dma_mem *q_mem = &cq->dma_mem;
957 void *ctxt = &req->context;
960 spin_lock(&ctrl->mbox_lock);
961 memset(wrb, 0, sizeof(*wrb));
963 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
965 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
966 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
968 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
969 if (is_chip_be2_be3r(phba)) {
970 AMAP_SET_BITS(struct amap_cq_context, coalescwm,
972 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
973 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
974 __ilog2_u32(cq->len / 256));
975 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
976 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
977 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
978 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
979 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
980 AMAP_SET_BITS(struct amap_cq_context, func, ctxt,
981 PCI_FUNC(ctrl->pdev->devfn));
983 req->hdr.version = MBX_CMD_VER2;
985 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
987 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay,
989 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
990 __ilog2_u32(cq->len / 256));
991 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
992 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
993 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
994 AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1);
997 be_dws_cpu_to_le(ctxt, sizeof(req->context));
999 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1001 status = be_mbox_notify(ctrl);
1003 cq->id = le16_to_cpu(resp->cq_id);
1006 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1007 "BC_%d : In be_cmd_cq_create, status=ox%08x\n",
1010 spin_unlock(&ctrl->mbox_lock);
1015 static u32 be_encoded_q_len(int q_len)
1017 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1018 if (len_encoded == 16)
1023 int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba,
1024 struct be_queue_info *mccq,
1025 struct be_queue_info *cq)
1027 struct be_mcc_wrb *wrb;
1028 struct be_cmd_req_mcc_create *req;
1029 struct be_dma_mem *q_mem = &mccq->dma_mem;
1030 struct be_ctrl_info *ctrl;
1034 spin_lock(&phba->ctrl.mbox_lock);
1036 wrb = wrb_from_mbox(&ctrl->mbox_mem);
1037 memset(wrb, 0, sizeof(*wrb));
1038 req = embedded_payload(wrb);
1039 ctxt = &req->context;
1041 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1043 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1044 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
1046 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1048 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt,
1049 PCI_FUNC(phba->pcidev->devfn));
1050 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
1051 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
1052 be_encoded_q_len(mccq->len));
1053 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
1055 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1057 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1059 status = be_mbox_notify_wait(phba);
1061 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1062 mccq->id = le16_to_cpu(resp->id);
1063 mccq->created = true;
1065 spin_unlock(&phba->ctrl.mbox_lock);
1070 int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
1073 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1074 struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
1075 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1076 u8 subsys = 0, opcode = 0;
1079 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1080 "BC_%d : In beiscsi_cmd_q_destroy "
1081 "queue_type : %d\n", queue_type);
1083 spin_lock(&ctrl->mbox_lock);
1084 memset(wrb, 0, sizeof(*wrb));
1085 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1087 switch (queue_type) {
1089 subsys = CMD_SUBSYSTEM_COMMON;
1090 opcode = OPCODE_COMMON_EQ_DESTROY;
1093 subsys = CMD_SUBSYSTEM_COMMON;
1094 opcode = OPCODE_COMMON_CQ_DESTROY;
1097 subsys = CMD_SUBSYSTEM_COMMON;
1098 opcode = OPCODE_COMMON_MCC_DESTROY;
1101 subsys = CMD_SUBSYSTEM_ISCSI;
1102 opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY;
1105 subsys = CMD_SUBSYSTEM_ISCSI;
1106 opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY;
1109 subsys = CMD_SUBSYSTEM_ISCSI;
1110 opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES;
1113 spin_unlock(&ctrl->mbox_lock);
1117 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
1118 if (queue_type != QTYPE_SGL)
1119 req->id = cpu_to_le16(q->id);
1121 status = be_mbox_notify(ctrl);
1123 spin_unlock(&ctrl->mbox_lock);
1128 * be_cmd_create_default_pdu_queue()- Create DEFQ for the adapter
1129 * @ctrl: ptr to ctrl_info
1130 * @cq: Completion Queue
1131 * @dq: Default Queue
1132 * @lenght: ring size
1133 * @entry_size: size of each entry in DEFQ
1134 * @is_header: Header or Data DEFQ
1135 * @ulp_num: Bind to which ULP
1137 * Create HDR/Data DEFQ for the passed ULP. Unsol PDU are posted
1138 * on this queue by the FW
1142 * Failure: Non-Zero Value
1145 int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
1146 struct be_queue_info *cq,
1147 struct be_queue_info *dq, int length,
1148 int entry_size, uint8_t is_header,
1151 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1152 struct be_defq_create_req *req = embedded_payload(wrb);
1153 struct be_dma_mem *q_mem = &dq->dma_mem;
1154 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1155 void *ctxt = &req->context;
1158 spin_lock(&ctrl->mbox_lock);
1159 memset(wrb, 0, sizeof(*wrb));
1161 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1163 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1164 OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req));
1166 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1167 if (phba->fw_config.dual_ulp_aware) {
1168 req->ulp_num = ulp_num;
1169 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
1170 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
1173 if (is_chip_be2_be3r(phba)) {
1174 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1176 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1177 rx_pdid_valid, ctxt, 1);
1178 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1179 pci_func_id, ctxt, PCI_FUNC(ctrl->pdev->devfn));
1180 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1182 be_encoded_q_len(length /
1183 sizeof(struct phys_addr)));
1184 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1185 default_buffer_size, ctxt, entry_size);
1186 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1187 cq_id_recv, ctxt, cq->id);
1189 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1191 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1192 rx_pdid_valid, ctxt, 1);
1193 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1195 be_encoded_q_len(length /
1196 sizeof(struct phys_addr)));
1197 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1198 default_buffer_size, ctxt, entry_size);
1199 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1200 cq_id_recv, ctxt, cq->id);
1203 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1205 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1207 status = be_mbox_notify(ctrl);
1209 struct be_ring *defq_ring;
1210 struct be_defq_create_resp *resp = embedded_payload(wrb);
1212 dq->id = le16_to_cpu(resp->id);
1215 defq_ring = &phba->phwi_ctrlr->default_pdu_hdr[ulp_num];
1217 defq_ring = &phba->phwi_ctrlr->
1218 default_pdu_data[ulp_num];
1220 defq_ring->id = dq->id;
1222 if (!phba->fw_config.dual_ulp_aware) {
1223 defq_ring->ulp_num = BEISCSI_ULP0;
1224 defq_ring->doorbell_offset = DB_RXULP0_OFFSET;
1226 defq_ring->ulp_num = resp->ulp_num;
1227 defq_ring->doorbell_offset = resp->doorbell_offset;
1230 spin_unlock(&ctrl->mbox_lock);
1236 * be_cmd_wrbq_create()- Create WRBQ
1237 * @ctrl: ptr to ctrl_info
1238 * @q_mem: memory details for the queue
1240 * @pwrb_context: ptr to wrb_context
1241 * @ulp_num: ULP on which the WRBQ is to be created
1243 * Create WRBQ on the passed ULP_NUM.
1246 int be_cmd_wrbq_create(struct be_ctrl_info *ctrl,
1247 struct be_dma_mem *q_mem,
1248 struct be_queue_info *wrbq,
1249 struct hwi_wrb_context *pwrb_context,
1252 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1253 struct be_wrbq_create_req *req = embedded_payload(wrb);
1254 struct be_wrbq_create_resp *resp = embedded_payload(wrb);
1255 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1258 spin_lock(&ctrl->mbox_lock);
1259 memset(wrb, 0, sizeof(*wrb));
1261 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1263 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1264 OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req));
1265 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1267 if (phba->fw_config.dual_ulp_aware) {
1268 req->ulp_num = ulp_num;
1269 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
1270 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
1273 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1275 status = be_mbox_notify(ctrl);
1277 wrbq->id = le16_to_cpu(resp->cid);
1278 wrbq->created = true;
1280 pwrb_context->cid = wrbq->id;
1281 if (!phba->fw_config.dual_ulp_aware) {
1282 pwrb_context->doorbell_offset = DB_TXULP0_OFFSET;
1283 pwrb_context->ulp_num = BEISCSI_ULP0;
1285 pwrb_context->ulp_num = resp->ulp_num;
1286 pwrb_context->doorbell_offset = resp->doorbell_offset;
1289 spin_unlock(&ctrl->mbox_lock);
1293 int be_cmd_iscsi_post_template_hdr(struct be_ctrl_info *ctrl,
1294 struct be_dma_mem *q_mem)
1296 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1297 struct be_post_template_pages_req *req = embedded_payload(wrb);
1300 spin_lock(&ctrl->mbox_lock);
1302 memset(wrb, 0, sizeof(*wrb));
1303 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1304 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1305 OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS,
1308 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1309 req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
1310 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1312 status = be_mbox_notify(ctrl);
1313 spin_unlock(&ctrl->mbox_lock);
1317 int be_cmd_iscsi_remove_template_hdr(struct be_ctrl_info *ctrl)
1319 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1320 struct be_remove_template_pages_req *req = embedded_payload(wrb);
1323 spin_lock(&ctrl->mbox_lock);
1325 memset(wrb, 0, sizeof(*wrb));
1326 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1327 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1328 OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS,
1331 req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
1333 status = be_mbox_notify(ctrl);
1334 spin_unlock(&ctrl->mbox_lock);
1338 int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
1339 struct be_dma_mem *q_mem,
1340 u32 page_offset, u32 num_pages)
1342 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1343 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
1344 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
1346 unsigned int curr_pages;
1347 u32 internal_page_offset = 0;
1348 u32 temp_num_pages = num_pages;
1350 if (num_pages == 0xff)
1353 spin_lock(&ctrl->mbox_lock);
1355 memset(wrb, 0, sizeof(*wrb));
1356 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1357 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1358 OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES,
1360 curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req,
1362 req->num_pages = min(num_pages, curr_pages);
1363 req->page_offset = page_offset;
1364 be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem);
1365 q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE);
1366 internal_page_offset += req->num_pages;
1367 page_offset += req->num_pages;
1368 num_pages -= req->num_pages;
1370 if (temp_num_pages == 0xff)
1371 req->num_pages = temp_num_pages;
1373 status = be_mbox_notify(ctrl);
1375 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1376 "BC_%d : FW CMD to map iscsi frags failed.\n");
1380 } while (num_pages > 0);
1382 spin_unlock(&ctrl->mbox_lock);
1384 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
1388 int beiscsi_cmd_reset_function(struct beiscsi_hba *phba)
1390 struct be_ctrl_info *ctrl = &phba->ctrl;
1391 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1392 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
1395 spin_lock(&ctrl->mbox_lock);
1397 req = embedded_payload(wrb);
1398 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1399 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1400 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1401 status = be_mbox_notify_wait(phba);
1403 spin_unlock(&ctrl->mbox_lock);
1408 * be_cmd_set_vlan()- Configure VLAN paramters on the adapter
1409 * @phba: device priv structure instance
1410 * @vlan_tag: TAG to be set
1412 * Set the VLAN_TAG for the adapter or Disable VLAN on adapter
1415 * TAG for the MBX Cmd
1417 int be_cmd_set_vlan(struct beiscsi_hba *phba,
1420 unsigned int tag = 0;
1421 struct be_mcc_wrb *wrb;
1422 struct be_cmd_set_vlan_req *req;
1423 struct be_ctrl_info *ctrl = &phba->ctrl;
1425 spin_lock(&ctrl->mbox_lock);
1426 tag = alloc_mcc_tag(phba);
1428 spin_unlock(&ctrl->mbox_lock);
1432 wrb = wrb_from_mccq(phba);
1433 req = embedded_payload(wrb);
1435 be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0);
1436 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1437 OPCODE_COMMON_ISCSI_NTWK_SET_VLAN,
1440 req->interface_hndl = phba->interface_handle;
1441 req->vlan_priority = vlan_tag;
1443 be_mcc_notify(phba);
1444 spin_unlock(&ctrl->mbox_lock);