2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Written by: Jayamohan Kallickal (jayamohank@serverengines.com)
12 * Contact Information:
13 * linux-drivers@serverengines.com
16 * 209 N. Fair Oaks Ave
21 #ifndef _BEISCSI_MAIN_
22 #define _BEISCSI_MAIN_
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
27 #include <scsi/scsi.h>
28 #include <scsi/scsi_cmnd.h>
29 #include <scsi/scsi_device.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/iscsi_proto.h>
32 #include <scsi/libiscsi.h>
33 #include <scsi/scsi_transport_iscsi.h>
36 #define DRV_NAME "be2iscsi"
37 #define BUILD_STR "2.0.527.0"
38 #define BE_NAME "ServerEngines BladeEngine2" \
39 "Linux iSCSI Driver version" BUILD_STR
40 #define DRV_DESC BE_NAME " " "Driver"
42 #define BE_VENDOR_ID 0x19A2
43 /* DEVICE ID's for BE2 */
44 #define BE_DEVICE_ID1 0x212
45 #define OC_DEVICE_ID1 0x702
46 #define OC_DEVICE_ID2 0x703
48 /* DEVICE ID's for BE3 */
49 #define BE_DEVICE_ID2 0x222
50 #define OC_DEVICE_ID3 0x712
52 #define BE2_IO_DEPTH 1024
53 #define BE2_MAX_SESSIONS 256
54 #define BE2_CMDS_PER_CXN 128
56 #define BE2_NOPOUT_REQ 16
58 #define BE2_DEFPDU_HDR_SZ 64
59 #define BE2_DEFPDU_DATA_SZ 8192
62 #define BEISCSI_SGLIST_ELEMENTS 30
64 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
65 #define BEISCSI_MAX_SECTORS 256 /* scsi_host->max_sectors */
67 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
68 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
69 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
70 #define BEISCSI_MAX_FRAGS_INIT 192
71 #define BE_NUM_MSIX_ENTRIES 1
73 #define MPU_EP_CONTROL 0
74 #define MPU_EP_SEMAPHORE 0xac
75 #define BE2_SOFT_RESET 0x5c
76 #define BE2_PCI_ONLINE0 0xb0
77 #define BE2_PCI_ONLINE1 0xb4
78 #define BE2_SET_RESET 0x80
79 #define BE2_MPU_IRAM_ONLINE 0x00000080
81 #define BE_SENSE_INFO_SIZE 258
82 #define BE_ISCSI_PDU_HEADER_SIZE 64
83 #define BE_MIN_MEM_SIZE 16384
84 #define MAX_CMD_SZ 65536
85 #define IIOC_SCSI_DATA 0x05 /* Write Operation */
87 #define DBG_LVL 0x00000001
88 #define DBG_LVL_1 0x00000001
89 #define DBG_LVL_2 0x00000002
90 #define DBG_LVL_3 0x00000004
91 #define DBG_LVL_4 0x00000008
92 #define DBG_LVL_5 0x00000010
93 #define DBG_LVL_6 0x00000020
94 #define DBG_LVL_7 0x00000040
95 #define DBG_LVL_8 0x00000080
97 #define SE_DEBUG(debug_mask, fmt, args...) \
99 if (debug_mask & DBG_LVL) { \
100 printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\
101 printk(fmt, ##args); \
105 #define BE_ADAPTER_UP 0x00000000
106 #define BE_ADAPTER_LINK_DOWN 0x00000001
108 * hardware needs the async PDU buffers to be posted in multiples of 8
109 * So have atleast 8 of them by default
112 #define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
114 /********* Memory BAR register ************/
115 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
117 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
118 * Disable" may still globally block interrupts in addition to individual
119 * interrupt masks; a mechanism for the device driver to block all interrupts
120 * atomically without having to arbitrate for the PCI Interrupt Disable bit
123 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
125 /********* ISR0 Register offset **********/
126 #define CEV_ISR0_OFFSET 0xC18
127 #define CEV_ISR_SIZE 4
130 * Macros for reading/writing a protection domain or CSR registers
134 #define DB_TXULP0_OFFSET 0x40
135 #define DB_RXULP0_OFFSET 0xA0
136 /********* Event Q door bell *************/
137 #define DB_EQ_OFFSET DB_CQ_OFFSET
138 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
139 /* Clear the interrupt for this eq */
140 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
142 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
143 /* Number of event entries processed */
144 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
146 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
148 /********* Compl Q door bell *************/
149 #define DB_CQ_OFFSET 0x120
150 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
151 /* Number of event entries processed */
152 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
154 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
156 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
157 #define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
158 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
159 #define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
160 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
162 #define PAGES_REQUIRED(x) \
163 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
166 HWI_MEM_ADDN_CONTEXT,
171 HWI_MEM_ASYNC_HEADER_BUF, /* 5 */
172 HWI_MEM_ASYNC_DATA_BUF,
173 HWI_MEM_ASYNC_HEADER_RING,
174 HWI_MEM_ASYNC_DATA_RING,
175 HWI_MEM_ASYNC_HEADER_HANDLE,
176 HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */
177 HWI_MEM_ASYNC_PDU_CONTEXT,
178 ISCSI_MEM_GLOBAL_HEADER,
182 struct be_bus_address32 {
183 unsigned int address_lo;
184 unsigned int address_hi;
187 struct be_bus_address64 {
188 unsigned long long address;
191 struct be_bus_address {
193 struct be_bus_address32 a32;
194 struct be_bus_address64 a64;
199 struct be_bus_address bus_address; /* Bus address of location */
200 void *virtual_address; /* virtual address to the location */
201 unsigned int size; /* Size required by memory block */
204 struct be_mem_descriptor {
205 unsigned int index; /* Index of this memory parameter */
206 unsigned int category; /* type indicates cached/non-cached */
207 unsigned int num_elements; /* number of elements in this
210 unsigned int alignment_mask; /* Alignment mask for this block */
211 unsigned int size_in_bytes; /* Size required by memory block */
212 struct mem_array *mem_array;
216 unsigned int sgl_index;
219 struct iscsi_task *task;
220 struct iscsi_sge *pfrag;
223 struct hba_parameters {
224 unsigned int ios_per_ctrl;
225 unsigned int cxns_per_ctrl;
226 unsigned int asyncpdus_per_ctrl;
227 unsigned int icds_per_ctrl;
228 unsigned int num_sge_per_io;
229 unsigned int defpdu_hdr_sz;
230 unsigned int defpdu_data_sz;
231 unsigned int num_cq_entries;
232 unsigned int num_eq_entries;
233 unsigned int wrbs_per_cxn;
234 unsigned int crashmode;
235 unsigned int hba_num;
237 unsigned int mgmt_ws_sz;
238 unsigned int hwi_ws_sz;
243 unsigned int dbg_flags;
244 unsigned int num_cxn;
246 unsigned int eq_timer;
248 * These are calculated from other params. They're here
251 unsigned int num_mcc_pages;
252 unsigned int num_mcc_cq_pages;
253 unsigned int num_cq_pages;
254 unsigned int num_eq_pages;
256 unsigned int num_async_pdu_buf_pages;
257 unsigned int num_async_pdu_buf_sgl_pages;
258 unsigned int num_async_pdu_buf_cq_pages;
260 unsigned int num_async_pdu_hdr_pages;
261 unsigned int num_async_pdu_hdr_sgl_pages;
262 unsigned int num_async_pdu_hdr_cq_pages;
264 unsigned int num_sge;
267 struct invalidate_command_table {
273 struct hba_parameters params;
274 struct hwi_controller *phwi_ctrlr;
275 unsigned int mem_req[SE_MEM_MAX];
276 /* PCI BAR mapped addresses */
277 u8 __iomem *csr_va; /* CSR */
278 u8 __iomem *db_va; /* Door Bell */
279 u8 __iomem *pci_va; /* PCI Config */
280 struct be_bus_address csr_pa; /* CSR */
281 struct be_bus_address db_pa; /* CSR */
282 struct be_bus_address pci_pa; /* CSR */
283 /* PCI representation of our HBA */
284 struct pci_dev *pcidev;
286 unsigned short asic_revision;
287 unsigned int num_cpus;
288 unsigned int nxt_cqid;
289 struct msix_entry msix_entries[MAX_CPUS + 1];
291 struct be_mem_descriptor *init_mem;
293 unsigned short io_sgl_alloc_index;
294 unsigned short io_sgl_free_index;
295 unsigned short io_sgl_hndl_avbl;
296 struct sgl_handle **io_sgl_hndl_base;
297 struct sgl_handle **sgl_hndl_array;
299 unsigned short eh_sgl_alloc_index;
300 unsigned short eh_sgl_free_index;
301 unsigned short eh_sgl_hndl_avbl;
302 struct sgl_handle **eh_sgl_hndl_base;
303 spinlock_t io_sgl_lock;
304 spinlock_t mgmt_sgl_lock;
307 unsigned short avlbl_cids;
308 unsigned short cid_alloc;
309 unsigned short cid_free;
310 struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
311 struct list_head hba_queue;
312 unsigned short *cid_array;
313 struct iscsi_endpoint **ep_array;
314 struct Scsi_Host *shost;
317 * group together since they are used most frequently
318 * for cid to cri conversion
320 unsigned int iscsi_cid_start;
321 unsigned int phys_port;
323 unsigned int isr_offset;
324 unsigned int iscsi_icd_start;
325 unsigned int iscsi_cid_count;
326 unsigned int iscsi_icd_count;
327 unsigned int pci_function;
329 unsigned short cid_alloc;
330 unsigned short cid_free;
331 unsigned short avlbl_cids;
332 unsigned short iscsi_features;
336 u8 mac_address[ETH_ALEN];
337 unsigned short todo_cq;
338 unsigned short todo_mcc_cq;
340 struct workqueue_struct *wq; /* The actuak work queue */
341 struct work_struct work_cqs; /* The work being queued */
342 struct be_ctrl_info ctrl;
343 unsigned int generation;
344 struct invalidate_command_table inv_tbl[128];
348 struct beiscsi_session {
349 struct pci_pool *bhs_pool;
353 * struct beiscsi_conn - iscsi connection structure
355 struct beiscsi_conn {
356 struct iscsi_conn *conn;
357 struct beiscsi_hba *phba;
359 u32 beiscsi_conn_cid;
360 struct beiscsi_endpoint *ep;
361 unsigned short login_in_progress;
362 struct wrb_handle *plogin_wrb_handle;
363 struct sgl_handle *plogin_sgl_handle;
364 struct beiscsi_session *beiscsi_sess;
365 struct iscsi_task *task;
368 /* This structure is used by the chip */
369 struct pdu_data_out {
373 * Pseudo amap definition in which each bit of the actual structure is defined
374 * as a byte: used to calculate offset/shift/mask of each field
376 struct amap_pdu_data_out {
377 u8 opcode[6]; /* opcode */
378 u8 rsvd0[2]; /* should be 0 */
380 u8 final_bit; /* F bit */
382 u8 ahs_length[8]; /* no AHS */
384 u8 data_len_lo[16]; /* DataSegmentLength */
386 u8 itt[32]; /* ITT; initiator task tag */
387 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
392 u8 buffer_offset[32];
397 struct iscsi_cmd iscsi_hdr;
398 unsigned char pad1[16];
399 struct pdu_data_out iscsi_data_pdu;
400 unsigned char pad2[BE_SENSE_INFO_SIZE -
401 sizeof(struct pdu_data_out)];
404 struct beiscsi_io_task {
405 struct wrb_handle *pwrb_handle;
406 struct sgl_handle *psgl_handle;
407 struct beiscsi_conn *conn;
408 struct scsi_cmnd *scsi_cmnd;
412 unsigned short header_len;
414 struct be_cmd_bhs *cmd_bhs;
415 struct be_bus_address bhs_pa;
416 unsigned short bhs_len;
419 struct be_nonio_bhs {
420 struct iscsi_hdr iscsi_hdr;
421 unsigned char pad1[16];
422 struct pdu_data_out iscsi_data_pdu;
423 unsigned char pad2[BE_SENSE_INFO_SIZE -
424 sizeof(struct pdu_data_out)];
427 struct be_status_bhs {
428 struct iscsi_cmd iscsi_hdr;
429 unsigned char pad1[16];
431 * The plus 2 below is to hold the sense info length that gets
434 unsigned char sense_info[BE_SENSE_INFO_SIZE];
442 * Pseudo amap definition in which each bit of the actual structure is defined
443 * as a byte: used to calculate offset/shift/mask of each field
445 struct amap_iscsi_sge {
448 u8 sge_offset[22]; /* DWORD 2 */
449 u8 rsvd0[9]; /* DWORD 2 */
450 u8 last_sge; /* DWORD 2 */
451 u8 len[17]; /* DWORD 3 */
452 u8 rsvd1[15]; /* DWORD 3 */
455 struct beiscsi_offload_params {
459 #define OFFLD_PARAMS_ERL 0x00000003
460 #define OFFLD_PARAMS_DDE 0x00000004
461 #define OFFLD_PARAMS_HDE 0x00000008
462 #define OFFLD_PARAMS_IR2T 0x00000010
463 #define OFFLD_PARAMS_IMD 0x00000020
466 * Pseudo amap definition in which each bit of the actual structure is defined
467 * as a byte: used to calculate offset/shift/mask of each field
469 struct amap_beiscsi_offload_params {
470 u8 max_burst_length[32];
471 u8 max_send_data_segment_length[32];
472 u8 first_burst_length[32];
482 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
483 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
485 struct async_pdu_handle {
486 struct list_head link;
487 struct be_bus_address pa;
489 unsigned int consumed;
491 unsigned char is_header;
493 unsigned long buffer_len;
496 struct hwi_async_entry {
498 unsigned char hdr_received;
499 unsigned char hdr_len;
500 unsigned short bytes_received;
501 unsigned int bytes_needed;
502 struct list_head list;
505 struct list_head header_busy_list;
506 struct list_head data_busy_list;
509 struct hwi_async_pdu_context {
511 struct be_bus_address pa_base;
514 struct async_pdu_handle *handle_base;
516 unsigned int host_write_ptr;
517 unsigned int ep_read_ptr;
518 unsigned int writables;
520 unsigned int free_entries;
521 unsigned int busy_entries;
522 unsigned int buffer_size;
523 unsigned int num_entries;
525 struct list_head free_list;
529 struct be_bus_address pa_base;
532 struct async_pdu_handle *handle_base;
534 unsigned int host_write_ptr;
535 unsigned int ep_read_ptr;
536 unsigned int writables;
538 unsigned int free_entries;
539 unsigned int busy_entries;
540 unsigned int buffer_size;
541 struct list_head free_list;
542 unsigned int num_entries;
546 * This is a varying size list! Do not add anything
549 struct hwi_async_entry async_entry[BE2_MAX_SESSIONS * 2];
552 #define PDUCQE_CODE_MASK 0x0000003F
553 #define PDUCQE_DPL_MASK 0xFFFF0000
554 #define PDUCQE_INDEX_MASK 0x0000FFFF
556 struct i_t_dpdu_cqe {
561 * Pseudo amap definition in which each bit of the actual structure is defined
562 * as a byte: used to calculate offset/shift/mask of each field
564 struct amap_i_t_dpdu_cqe {
577 #define CQE_VALID_MASK 0x80000000
578 #define CQE_CODE_MASK 0x0000003F
579 #define CQE_CID_MASK 0x0000FFC0
581 #define EQE_VALID_MASK 0x00000001
582 #define EQE_MAJORCODE_MASK 0x0000000E
583 #define EQE_RESID_MASK 0xFFFF0000
590 * Pseudo amap definition in which each bit of the actual structure is defined
591 * as a byte: used to calculate offset/shift/mask of each field
593 struct amap_eq_entry {
594 u8 valid; /* DWORD 0 */
595 u8 major_code[3]; /* DWORD 0 */
596 u8 minor_code[12]; /* DWORD 0 */
597 u8 resource_id[16]; /* DWORD 0 */
606 * Pseudo amap definition in which each bit of the actual structure is defined
607 * as a byte: used to calculate offset/shift/mask of each field
618 void beiscsi_process_eq(struct beiscsi_hba *phba);
624 #define WRB_TYPE_MASK 0xF0000000
627 * Pseudo amap definition in which each bit of the actual structure is defined
628 * as a byte: used to calculate offset/shift/mask of each field
630 struct amap_iscsi_wrb {
631 u8 lun[14]; /* DWORD 0 */
633 u8 invld; /* DWORD 0 */
634 u8 wrb_idx[8]; /* DWORD 0 */
635 u8 dsp; /* DWORD 0 */
636 u8 dmsg; /* DWORD 0 */
637 u8 undr_run; /* DWORD 0 */
638 u8 over_run; /* DWORD 0 */
639 u8 type[4]; /* DWORD 0 */
640 u8 ptr2nextwrb[8]; /* DWORD 1 */
641 u8 r2t_exp_dtl[24]; /* DWORD 1 */
642 u8 sgl_icd_idx[12]; /* DWORD 2 */
643 u8 rsvd0[20]; /* DWORD 2 */
644 u8 exp_data_sn[32]; /* DWORD 3 */
645 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
646 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
647 u8 cmdsn_itt[32]; /* DWORD 6 */
648 u8 dif_ref_tag[32]; /* DWORD 7 */
649 u8 sge0_addr_hi[32]; /* DWORD 8 */
650 u8 sge0_addr_lo[32]; /* DWORD 9 */
651 u8 sge0_offset[22]; /* DWORD 10 */
652 u8 pbs; /* DWORD 10 */
653 u8 dif_mode[2]; /* DWORD 10 */
654 u8 rsvd1[6]; /* DWORD 10 */
655 u8 sge0_last; /* DWORD 10 */
656 u8 sge0_len[17]; /* DWORD 11 */
657 u8 dif_meta_tag[14]; /* DWORD 11 */
658 u8 sge0_in_ddr; /* DWORD 11 */
659 u8 sge1_addr_hi[32]; /* DWORD 12 */
660 u8 sge1_addr_lo[32]; /* DWORD 13 */
661 u8 sge1_r2t_offset[22]; /* DWORD 14 */
662 u8 rsvd2[9]; /* DWORD 14 */
663 u8 sge1_last; /* DWORD 14 */
664 u8 sge1_len[17]; /* DWORD 15 */
665 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
666 u8 rsvd3[2]; /* DWORD 15 */
667 u8 sge1_in_ddr; /* DWORD 15 */
671 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
673 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
675 void beiscsi_process_all_cqs(struct work_struct *work);
682 * Pseudo amap definition in which each bit of the actual structure is defined
683 * as a byte: used to calculate offset/shift/mask of each field
685 struct amap_pdu_nop_out {
686 u8 opcode[6]; /* opcode 0x00 */
687 u8 i_bit; /* I Bit */
688 u8 x_bit; /* reserved; should be 0 */
689 u8 fp_bit_filler1[7];
690 u8 f_bit; /* always 1 */
692 u8 ahs_length[8]; /* no AHS */
694 u8 data_len_lo[16]; /* DataSegmentLength */
696 u8 itt[32]; /* initiator id for ping or 0xffffffff */
697 u8 ttt[32]; /* target id for ping or 0xffffffff */
703 #define PDUBASE_OPCODE_MASK 0x0000003F
704 #define PDUBASE_DATALENHI_MASK 0x0000FF00
705 #define PDUBASE_DATALENLO_MASK 0xFFFF0000
712 * Pseudo amap definition in which each bit of the actual structure is defined
713 * as a byte: used to calculate offset/shift/mask of each field
715 struct amap_pdu_base {
717 u8 i_bit; /* immediate bit */
718 u8 x_bit; /* reserved, always 0 */
719 u8 reserved1[24]; /* opcode-specific fields */
720 u8 ahs_length[8]; /* length units is 4 byte words */
722 u8 data_len_lo[16]; /* DatasegmentLength */
723 u8 lun[64]; /* lun or opcode-specific fields */
724 u8 itt[32]; /* initiator task tag */
728 struct iscsi_target_context_update_wrb {
733 * Pseudo amap definition in which each bit of the actual structure is defined
734 * as a byte: used to calculate offset/shift/mask of each field
736 struct amap_iscsi_target_context_update_wrb {
737 u8 lun[14]; /* DWORD 0 */
739 u8 invld; /* DWORD 0 */
740 u8 wrb_idx[8]; /* DWORD 0 */
741 u8 dsp; /* DWORD 0 */
742 u8 dmsg; /* DWORD 0 */
743 u8 undr_run; /* DWORD 0 */
744 u8 over_run; /* DWORD 0 */
745 u8 type[4]; /* DWORD 0 */
746 u8 ptr2nextwrb[8]; /* DWORD 1 */
747 u8 max_burst_length[19]; /* DWORD 1 */
748 u8 rsvd0[5]; /* DWORD 1 */
749 u8 rsvd1[15]; /* DWORD 2 */
750 u8 max_send_data_segment_length[17]; /* DWORD 2 */
751 u8 first_burst_length[14]; /* DWORD 3 */
752 u8 rsvd2[2]; /* DWORD 3 */
753 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
754 u8 rsvd3[5]; /* DWORD 3 */
755 u8 session_state[3]; /* DWORD 3 */
756 u8 rsvd4[16]; /* DWORD 4 */
757 u8 tx_jumbo; /* DWORD 4 */
758 u8 hde; /* DWORD 4 */
759 u8 dde; /* DWORD 4 */
760 u8 erl[2]; /* DWORD 4 */
761 u8 domain_id[5]; /* DWORD 4 */
762 u8 mode; /* DWORD 4 */
763 u8 imd; /* DWORD 4 */
764 u8 ir2t; /* DWORD 4 */
765 u8 notpredblq[2]; /* DWORD 4 */
766 u8 compltonack; /* DWORD 4 */
767 u8 stat_sn[32]; /* DWORD 5 */
768 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
769 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
770 u8 pad_addr_hi[32]; /* DWORD 8 */
771 u8 pad_addr_lo[32]; /* DWORD 9 */
772 u8 rsvd5[32]; /* DWORD 10 */
773 u8 rsvd6[32]; /* DWORD 11 */
774 u8 rsvd7[32]; /* DWORD 12 */
775 u8 rsvd8[32]; /* DWORD 13 */
776 u8 rsvd9[32]; /* DWORD 14 */
777 u8 rsvd10[32]; /* DWORD 15 */
782 u32 pages; /* queue size in pages */
783 u32 id; /* queue id assigned by beklib */
784 u32 num; /* number of elements in queue */
785 u32 cidx; /* consumer index */
786 u32 pidx; /* producer index -- not used by most rings */
787 u32 item_size; /* size in bytes of one object */
789 void *va; /* The virtual address of the ring. This
790 * should be last to allow 32 & 64 bit debugger
791 * extensions to work.
795 struct hwi_wrb_context {
796 struct list_head wrb_handle_list;
797 struct list_head wrb_handle_drvr_list;
798 struct wrb_handle **pwrb_handle_base;
799 struct wrb_handle **pwrb_handle_basestd;
800 struct iscsi_wrb *plast_wrb;
801 unsigned short alloc_index;
802 unsigned short free_index;
803 unsigned short wrb_handles_available;
807 struct hwi_controller {
808 struct list_head io_sgl_list;
809 struct list_head eh_sgl_list;
810 struct sgl_handle *psgl_handle_base;
811 unsigned int wrb_mem_index;
813 struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
814 struct mcc_wrb *pmcc_wrb_base;
815 struct be_ring default_pdu_hdr;
816 struct be_ring default_pdu_data;
817 struct hwi_context_memory *phwi_ctxt;
827 HWH_TYPE_INVALID = 0xFFFFFFFF
831 enum hwh_type_enum type;
832 unsigned short wrb_index;
833 unsigned short nxt_wrb_index;
835 struct iscsi_task *pio_handle;
836 struct iscsi_wrb *pwrb;
839 struct hwi_context_memory {
840 /* Adaptive interrupt coalescing (AIC) info */
841 u16 min_eqd; /* in usecs */
842 u16 max_eqd; /* in usecs */
843 u16 cur_eqd; /* in usecs */
844 struct be_eq_obj be_eq[MAX_CPUS];
845 struct be_queue_info be_cq[MAX_CPUS];
847 struct be_queue_info be_def_hdrq;
848 struct be_queue_info be_def_dataq;
850 struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
851 struct be_mcc_wrb_context *pbe_mcc_context;
853 struct hwi_async_pdu_context *pasync_ctx;