2 * Copyright (C) 2005 - 2011 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
12 * Contact Information:
13 * linux-drivers@emulex.com
17 * Costa Mesa, CA 92626
20 #ifndef _BEISCSI_MAIN_
21 #define _BEISCSI_MAIN_
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/if_ether.h>
27 #include <linux/ctype.h>
28 #include <linux/module.h>
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/iscsi_proto.h>
34 #include <scsi/libiscsi.h>
35 #include <scsi/scsi_transport_iscsi.h>
38 #define DRV_NAME "be2iscsi"
39 #define BUILD_STR "4.4.58.0"
40 #define BE_NAME "Emulex OneConnect" \
41 "Open-iSCSI Driver version" BUILD_STR
42 #define DRV_DESC BE_NAME " " "Driver"
44 #define BE_VENDOR_ID 0x19A2
45 #define ELX_VENDOR_ID 0x10DF
46 /* DEVICE ID's for BE2 */
47 #define BE_DEVICE_ID1 0x212
48 #define OC_DEVICE_ID1 0x702
49 #define OC_DEVICE_ID2 0x703
51 /* DEVICE ID's for BE3 */
52 #define BE_DEVICE_ID2 0x222
53 #define OC_DEVICE_ID3 0x712
55 /* DEVICE ID for SKH */
56 #define OC_SKH_ID1 0x722
58 #define BE2_IO_DEPTH 1024
59 #define BE2_MAX_SESSIONS 256
60 #define BE2_CMDS_PER_CXN 128
62 #define BE2_NOPOUT_REQ 16
64 #define BE2_DEFPDU_HDR_SZ 64
65 #define BE2_DEFPDU_DATA_SZ 8192
68 #define BEISCSI_MAX_NUM_CPUS 7
69 #define OC_SKH_MAX_NUM_CPUS 63
72 #define BEISCSI_SGLIST_ELEMENTS 30
74 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
75 #define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */
77 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
78 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
79 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
80 #define BEISCSI_MAX_FRAGS_INIT 192
81 #define BE_NUM_MSIX_ENTRIES 1
83 #define MPU_EP_CONTROL 0
84 #define MPU_EP_SEMAPHORE 0xac
85 #define BE2_SOFT_RESET 0x5c
86 #define BE2_PCI_ONLINE0 0xb0
87 #define BE2_PCI_ONLINE1 0xb4
88 #define BE2_SET_RESET 0x80
89 #define BE2_MPU_IRAM_ONLINE 0x00000080
91 #define BE_SENSE_INFO_SIZE 258
92 #define BE_ISCSI_PDU_HEADER_SIZE 64
93 #define BE_MIN_MEM_SIZE 16384
94 #define MAX_CMD_SZ 65536
95 #define IIOC_SCSI_DATA 0x05 /* Write Operation */
97 #define INVALID_SESS_HANDLE 0xFFFFFFFF
99 #define BE_ADAPTER_UP 0x00000000
100 #define BE_ADAPTER_LINK_DOWN 0x00000001
102 * hardware needs the async PDU buffers to be posted in multiples of 8
103 * So have atleast 8 of them by default
106 #define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
108 /********* Memory BAR register ************/
109 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
111 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
112 * Disable" may still globally block interrupts in addition to individual
113 * interrupt masks; a mechanism for the device driver to block all interrupts
114 * atomically without having to arbitrate for the PCI Interrupt Disable bit
117 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
119 /********* ISR0 Register offset **********/
120 #define CEV_ISR0_OFFSET 0xC18
121 #define CEV_ISR_SIZE 4
124 * Macros for reading/writing a protection domain or CSR registers
128 #define DB_TXULP0_OFFSET 0x40
129 #define DB_RXULP0_OFFSET 0xA0
130 /********* Event Q door bell *************/
131 #define DB_EQ_OFFSET DB_CQ_OFFSET
132 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
133 /* Clear the interrupt for this eq */
134 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
136 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
137 /* Number of event entries processed */
138 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
140 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
142 /********* Compl Q door bell *************/
143 #define DB_CQ_OFFSET 0x120
144 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
145 /* Number of event entries processed */
146 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
148 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
150 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
151 #define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
152 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
153 #define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
154 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
156 #define PAGES_REQUIRED(x) \
157 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
159 #define BEISCSI_MSI_NAME 20 /* size of msi_name string */
162 HWI_MEM_ADDN_CONTEXT,
167 HWI_MEM_ASYNC_HEADER_BUF, /* 5 */
168 HWI_MEM_ASYNC_DATA_BUF,
169 HWI_MEM_ASYNC_HEADER_RING,
170 HWI_MEM_ASYNC_DATA_RING,
171 HWI_MEM_ASYNC_HEADER_HANDLE,
172 HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */
173 HWI_MEM_ASYNC_PDU_CONTEXT,
174 ISCSI_MEM_GLOBAL_HEADER,
178 struct be_bus_address32 {
179 unsigned int address_lo;
180 unsigned int address_hi;
183 struct be_bus_address64 {
184 unsigned long long address;
187 struct be_bus_address {
189 struct be_bus_address32 a32;
190 struct be_bus_address64 a64;
195 struct be_bus_address bus_address; /* Bus address of location */
196 void *virtual_address; /* virtual address to the location */
197 unsigned int size; /* Size required by memory block */
200 struct be_mem_descriptor {
201 unsigned int index; /* Index of this memory parameter */
202 unsigned int category; /* type indicates cached/non-cached */
203 unsigned int num_elements; /* number of elements in this
206 unsigned int alignment_mask; /* Alignment mask for this block */
207 unsigned int size_in_bytes; /* Size required by memory block */
208 struct mem_array *mem_array;
212 unsigned int sgl_index;
215 struct iscsi_task *task;
216 struct iscsi_sge *pfrag;
219 struct hba_parameters {
220 unsigned int ios_per_ctrl;
221 unsigned int cxns_per_ctrl;
222 unsigned int asyncpdus_per_ctrl;
223 unsigned int icds_per_ctrl;
224 unsigned int num_sge_per_io;
225 unsigned int defpdu_hdr_sz;
226 unsigned int defpdu_data_sz;
227 unsigned int num_cq_entries;
228 unsigned int num_eq_entries;
229 unsigned int wrbs_per_cxn;
230 unsigned int crashmode;
231 unsigned int hba_num;
233 unsigned int mgmt_ws_sz;
234 unsigned int hwi_ws_sz;
239 unsigned int dbg_flags;
240 unsigned int num_cxn;
242 unsigned int eq_timer;
244 * These are calculated from other params. They're here
247 unsigned int num_mcc_pages;
248 unsigned int num_mcc_cq_pages;
249 unsigned int num_cq_pages;
250 unsigned int num_eq_pages;
252 unsigned int num_async_pdu_buf_pages;
253 unsigned int num_async_pdu_buf_sgl_pages;
254 unsigned int num_async_pdu_buf_cq_pages;
256 unsigned int num_async_pdu_hdr_pages;
257 unsigned int num_async_pdu_hdr_sgl_pages;
258 unsigned int num_async_pdu_hdr_cq_pages;
260 unsigned int num_sge;
263 struct invalidate_command_table {
268 #define chip_skh_r(pdev) (pdev->device == OC_SKH_ID1)
270 struct hba_parameters params;
271 struct hwi_controller *phwi_ctrlr;
272 unsigned int mem_req[SE_MEM_MAX];
273 /* PCI BAR mapped addresses */
274 u8 __iomem *csr_va; /* CSR */
275 u8 __iomem *db_va; /* Door Bell */
276 u8 __iomem *pci_va; /* PCI Config */
277 struct be_bus_address csr_pa; /* CSR */
278 struct be_bus_address db_pa; /* CSR */
279 struct be_bus_address pci_pa; /* CSR */
280 /* PCI representation of our HBA */
281 struct pci_dev *pcidev;
283 unsigned short asic_revision;
284 unsigned int num_cpus;
285 unsigned int nxt_cqid;
286 struct msix_entry msix_entries[MAX_CPUS];
287 char *msi_name[MAX_CPUS];
289 struct be_mem_descriptor *init_mem;
291 unsigned short io_sgl_alloc_index;
292 unsigned short io_sgl_free_index;
293 unsigned short io_sgl_hndl_avbl;
294 struct sgl_handle **io_sgl_hndl_base;
295 struct sgl_handle **sgl_hndl_array;
297 unsigned short eh_sgl_alloc_index;
298 unsigned short eh_sgl_free_index;
299 unsigned short eh_sgl_hndl_avbl;
300 struct sgl_handle **eh_sgl_hndl_base;
301 spinlock_t io_sgl_lock;
302 spinlock_t mgmt_sgl_lock;
305 unsigned short avlbl_cids;
306 unsigned short cid_alloc;
307 unsigned short cid_free;
308 struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
309 struct list_head hba_queue;
310 unsigned short *cid_array;
311 struct iscsi_endpoint **ep_array;
312 struct iscsi_boot_kset *boot_kset;
313 struct Scsi_Host *shost;
314 struct iscsi_iface *ipv4_iface;
315 struct iscsi_iface *ipv6_iface;
318 * group together since they are used most frequently
319 * for cid to cri conversion
321 unsigned int iscsi_cid_start;
322 unsigned int phys_port;
324 unsigned int isr_offset;
325 unsigned int iscsi_icd_start;
326 unsigned int iscsi_cid_count;
327 unsigned int iscsi_icd_count;
328 unsigned int pci_function;
330 unsigned short cid_alloc;
331 unsigned short cid_free;
332 unsigned short avlbl_cids;
333 unsigned short iscsi_features;
337 u8 mac_address[ETH_ALEN];
339 struct workqueue_struct *wq; /* The actuak work queue */
340 struct be_ctrl_info ctrl;
341 unsigned int generation;
342 unsigned int interface_handle;
343 struct mgmt_session_info boot_sess;
344 struct invalidate_command_table inv_tbl[128];
346 unsigned int attr_log_enable;
347 int (*iotask_fn)(struct iscsi_task *,
348 struct scatterlist *sg,
349 uint32_t num_sg, uint32_t xferlen,
353 struct beiscsi_session {
354 struct pci_pool *bhs_pool;
358 * struct beiscsi_conn - iscsi connection structure
360 struct beiscsi_conn {
361 struct iscsi_conn *conn;
362 struct beiscsi_hba *phba;
364 u32 beiscsi_conn_cid;
365 struct beiscsi_endpoint *ep;
366 unsigned short login_in_progress;
367 struct wrb_handle *plogin_wrb_handle;
368 struct sgl_handle *plogin_sgl_handle;
369 struct beiscsi_session *beiscsi_sess;
370 struct iscsi_task *task;
373 /* This structure is used by the chip */
374 struct pdu_data_out {
378 * Pseudo amap definition in which each bit of the actual structure is defined
379 * as a byte: used to calculate offset/shift/mask of each field
381 struct amap_pdu_data_out {
382 u8 opcode[6]; /* opcode */
383 u8 rsvd0[2]; /* should be 0 */
385 u8 final_bit; /* F bit */
387 u8 ahs_length[8]; /* no AHS */
389 u8 data_len_lo[16]; /* DataSegmentLength */
391 u8 itt[32]; /* ITT; initiator task tag */
392 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
397 u8 buffer_offset[32];
402 struct iscsi_scsi_req iscsi_hdr;
403 unsigned char pad1[16];
404 struct pdu_data_out iscsi_data_pdu;
405 unsigned char pad2[BE_SENSE_INFO_SIZE -
406 sizeof(struct pdu_data_out)];
409 struct beiscsi_io_task {
410 struct wrb_handle *pwrb_handle;
411 struct sgl_handle *psgl_handle;
412 struct beiscsi_conn *conn;
413 struct scsi_cmnd *scsi_cmnd;
417 unsigned short header_len;
419 struct be_cmd_bhs *cmd_bhs;
420 struct be_bus_address bhs_pa;
421 unsigned short bhs_len;
422 dma_addr_t mtask_addr;
423 uint32_t mtask_data_count;
427 struct be_nonio_bhs {
428 struct iscsi_hdr iscsi_hdr;
429 unsigned char pad1[16];
430 struct pdu_data_out iscsi_data_pdu;
431 unsigned char pad2[BE_SENSE_INFO_SIZE -
432 sizeof(struct pdu_data_out)];
435 struct be_status_bhs {
436 struct iscsi_scsi_req iscsi_hdr;
437 unsigned char pad1[16];
439 * The plus 2 below is to hold the sense info length that gets
442 unsigned char sense_info[BE_SENSE_INFO_SIZE];
450 * Pseudo amap definition in which each bit of the actual structure is defined
451 * as a byte: used to calculate offset/shift/mask of each field
453 struct amap_iscsi_sge {
456 u8 sge_offset[22]; /* DWORD 2 */
457 u8 rsvd0[9]; /* DWORD 2 */
458 u8 last_sge; /* DWORD 2 */
459 u8 len[17]; /* DWORD 3 */
460 u8 rsvd1[15]; /* DWORD 3 */
463 struct beiscsi_offload_params {
467 #define OFFLD_PARAMS_ERL 0x00000003
468 #define OFFLD_PARAMS_DDE 0x00000004
469 #define OFFLD_PARAMS_HDE 0x00000008
470 #define OFFLD_PARAMS_IR2T 0x00000010
471 #define OFFLD_PARAMS_IMD 0x00000020
472 #define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040
473 #define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080
474 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
477 * Pseudo amap definition in which each bit of the actual structure is defined
478 * as a byte: used to calculate offset/shift/mask of each field
480 struct amap_beiscsi_offload_params {
481 u8 max_burst_length[32];
482 u8 max_send_data_segment_length[32];
483 u8 first_burst_length[32];
489 u8 data_seq_inorder[1];
490 u8 pdu_seq_inorder[1];
496 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
497 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
499 struct async_pdu_handle {
500 struct list_head link;
501 struct be_bus_address pa;
503 unsigned int consumed;
505 unsigned char is_header;
507 unsigned long buffer_len;
510 struct hwi_async_entry {
512 unsigned char hdr_received;
513 unsigned char hdr_len;
514 unsigned short bytes_received;
515 unsigned int bytes_needed;
516 struct list_head list;
519 struct list_head header_busy_list;
520 struct list_head data_busy_list;
523 struct hwi_async_pdu_context {
525 struct be_bus_address pa_base;
528 struct async_pdu_handle *handle_base;
530 unsigned int host_write_ptr;
531 unsigned int ep_read_ptr;
532 unsigned int writables;
534 unsigned int free_entries;
535 unsigned int busy_entries;
537 struct list_head free_list;
541 struct be_bus_address pa_base;
544 struct async_pdu_handle *handle_base;
546 unsigned int host_write_ptr;
547 unsigned int ep_read_ptr;
548 unsigned int writables;
550 unsigned int free_entries;
551 unsigned int busy_entries;
552 struct list_head free_list;
555 unsigned int buffer_size;
556 unsigned int num_entries;
559 * This is a varying size list! Do not add anything
562 struct hwi_async_entry async_entry[BE2_MAX_SESSIONS * 2];
565 #define PDUCQE_CODE_MASK 0x0000003F
566 #define PDUCQE_DPL_MASK 0xFFFF0000
567 #define PDUCQE_INDEX_MASK 0x0000FFFF
569 struct i_t_dpdu_cqe {
574 * Pseudo amap definition in which each bit of the actual structure is defined
575 * as a byte: used to calculate offset/shift/mask of each field
577 struct amap_i_t_dpdu_cqe {
590 #define CQE_VALID_MASK 0x80000000
591 #define CQE_CODE_MASK 0x0000003F
592 #define CQE_CID_MASK 0x0000FFC0
594 #define EQE_VALID_MASK 0x00000001
595 #define EQE_MAJORCODE_MASK 0x0000000E
596 #define EQE_RESID_MASK 0xFFFF0000
603 * Pseudo amap definition in which each bit of the actual structure is defined
604 * as a byte: used to calculate offset/shift/mask of each field
606 struct amap_eq_entry {
607 u8 valid; /* DWORD 0 */
608 u8 major_code[3]; /* DWORD 0 */
609 u8 minor_code[12]; /* DWORD 0 */
610 u8 resource_id[16]; /* DWORD 0 */
619 * Pseudo amap definition in which each bit of the actual structure is defined
620 * as a byte: used to calculate offset/shift/mask of each field
631 void beiscsi_process_eq(struct beiscsi_hba *phba);
637 #define WRB_TYPE_MASK 0xF0000000
638 #define SKH_WRB_TYPE_OFFSET 27
639 #define BE_WRB_TYPE_OFFSET 28
641 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
642 (pwrb->dw[0] |= (wrb_type << type_offset))
645 * Pseudo amap definition in which each bit of the actual structure is defined
646 * as a byte: used to calculate offset/shift/mask of each field
648 struct amap_iscsi_wrb {
649 u8 lun[14]; /* DWORD 0 */
651 u8 invld; /* DWORD 0 */
652 u8 wrb_idx[8]; /* DWORD 0 */
653 u8 dsp; /* DWORD 0 */
654 u8 dmsg; /* DWORD 0 */
655 u8 undr_run; /* DWORD 0 */
656 u8 over_run; /* DWORD 0 */
657 u8 type[4]; /* DWORD 0 */
658 u8 ptr2nextwrb[8]; /* DWORD 1 */
659 u8 r2t_exp_dtl[24]; /* DWORD 1 */
660 u8 sgl_icd_idx[12]; /* DWORD 2 */
661 u8 rsvd0[20]; /* DWORD 2 */
662 u8 exp_data_sn[32]; /* DWORD 3 */
663 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
664 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
665 u8 cmdsn_itt[32]; /* DWORD 6 */
666 u8 dif_ref_tag[32]; /* DWORD 7 */
667 u8 sge0_addr_hi[32]; /* DWORD 8 */
668 u8 sge0_addr_lo[32]; /* DWORD 9 */
669 u8 sge0_offset[22]; /* DWORD 10 */
670 u8 pbs; /* DWORD 10 */
671 u8 dif_mode[2]; /* DWORD 10 */
672 u8 rsvd1[6]; /* DWORD 10 */
673 u8 sge0_last; /* DWORD 10 */
674 u8 sge0_len[17]; /* DWORD 11 */
675 u8 dif_meta_tag[14]; /* DWORD 11 */
676 u8 sge0_in_ddr; /* DWORD 11 */
677 u8 sge1_addr_hi[32]; /* DWORD 12 */
678 u8 sge1_addr_lo[32]; /* DWORD 13 */
679 u8 sge1_r2t_offset[22]; /* DWORD 14 */
680 u8 rsvd2[9]; /* DWORD 14 */
681 u8 sge1_last; /* DWORD 14 */
682 u8 sge1_len[17]; /* DWORD 15 */
683 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
684 u8 rsvd3[2]; /* DWORD 15 */
685 u8 sge1_in_ddr; /* DWORD 15 */
689 struct amap_iscsi_wrb_v2 {
690 u8 r2t_exp_dtl[25]; /* DWORD 0 */
691 u8 rsvd0[2]; /* DWORD 0*/
692 u8 type[5]; /* DWORD 0 */
693 u8 ptr2nextwrb[8]; /* DWORD 1 */
694 u8 wrb_idx[8]; /* DWORD 1 */
695 u8 lun[16]; /* DWORD 1 */
696 u8 sgl_idx[16]; /* DWORD 2 */
697 u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
698 u8 exp_data_sn[32]; /* DWORD 3 */
699 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
700 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
701 u8 cq_id[16]; /* DWORD 6 */
702 u8 rsvd1[16]; /* DWORD 6 */
703 u8 cmdsn_itt[32]; /* DWORD 7 */
704 u8 sge0_addr_hi[32]; /* DWORD 8 */
705 u8 sge0_addr_lo[32]; /* DWORD 9 */
706 u8 sge0_offset[24]; /* DWORD 10 */
707 u8 rsvd2[7]; /* DWORD 10 */
708 u8 sge0_last; /* DWORD 10 */
709 u8 sge0_len[17]; /* DWORD 11 */
710 u8 rsvd3[7]; /* DWORD 11 */
711 u8 diff_enbl; /* DWORD 11 */
712 u8 u_run; /* DWORD 11 */
713 u8 o_run; /* DWORD 11 */
714 u8 invalid; /* DWORD 11 */
715 u8 dsp; /* DWORD 11 */
716 u8 dmsg; /* DWORD 11 */
717 u8 rsvd4; /* DWORD 11 */
718 u8 lt; /* DWORD 11 */
719 u8 sge1_addr_hi[32]; /* DWORD 12 */
720 u8 sge1_addr_lo[32]; /* DWORD 13 */
721 u8 sge1_r2t_offset[24]; /* DWORD 14 */
722 u8 rsvd5[7]; /* DWORD 14 */
723 u8 sge1_last; /* DWORD 14 */
724 u8 sge1_len[17]; /* DWORD 15 */
725 u8 rsvd6[15]; /* DWORD 15 */
729 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
731 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
733 void beiscsi_process_all_cqs(struct work_struct *work);
740 * Pseudo amap definition in which each bit of the actual structure is defined
741 * as a byte: used to calculate offset/shift/mask of each field
743 struct amap_pdu_nop_out {
744 u8 opcode[6]; /* opcode 0x00 */
745 u8 i_bit; /* I Bit */
746 u8 x_bit; /* reserved; should be 0 */
747 u8 fp_bit_filler1[7];
748 u8 f_bit; /* always 1 */
750 u8 ahs_length[8]; /* no AHS */
752 u8 data_len_lo[16]; /* DataSegmentLength */
754 u8 itt[32]; /* initiator id for ping or 0xffffffff */
755 u8 ttt[32]; /* target id for ping or 0xffffffff */
761 #define PDUBASE_OPCODE_MASK 0x0000003F
762 #define PDUBASE_DATALENHI_MASK 0x0000FF00
763 #define PDUBASE_DATALENLO_MASK 0xFFFF0000
770 * Pseudo amap definition in which each bit of the actual structure is defined
771 * as a byte: used to calculate offset/shift/mask of each field
773 struct amap_pdu_base {
775 u8 i_bit; /* immediate bit */
776 u8 x_bit; /* reserved, always 0 */
777 u8 reserved1[24]; /* opcode-specific fields */
778 u8 ahs_length[8]; /* length units is 4 byte words */
780 u8 data_len_lo[16]; /* DatasegmentLength */
781 u8 lun[64]; /* lun or opcode-specific fields */
782 u8 itt[32]; /* initiator task tag */
786 struct iscsi_target_context_update_wrb {
791 * Pseudo amap definition in which each bit of the actual structure is defined
792 * as a byte: used to calculate offset/shift/mask of each field
794 #define BE_TGT_CTX_UPDT_CMD 0x07
795 struct amap_iscsi_target_context_update_wrb {
796 u8 lun[14]; /* DWORD 0 */
798 u8 invld; /* DWORD 0 */
799 u8 wrb_idx[8]; /* DWORD 0 */
800 u8 dsp; /* DWORD 0 */
801 u8 dmsg; /* DWORD 0 */
802 u8 undr_run; /* DWORD 0 */
803 u8 over_run; /* DWORD 0 */
804 u8 type[4]; /* DWORD 0 */
805 u8 ptr2nextwrb[8]; /* DWORD 1 */
806 u8 max_burst_length[19]; /* DWORD 1 */
807 u8 rsvd0[5]; /* DWORD 1 */
808 u8 rsvd1[15]; /* DWORD 2 */
809 u8 max_send_data_segment_length[17]; /* DWORD 2 */
810 u8 first_burst_length[14]; /* DWORD 3 */
811 u8 rsvd2[2]; /* DWORD 3 */
812 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
813 u8 rsvd3[5]; /* DWORD 3 */
814 u8 session_state[3]; /* DWORD 3 */
815 u8 rsvd4[16]; /* DWORD 4 */
816 u8 tx_jumbo; /* DWORD 4 */
817 u8 hde; /* DWORD 4 */
818 u8 dde; /* DWORD 4 */
819 u8 erl[2]; /* DWORD 4 */
820 u8 domain_id[5]; /* DWORD 4 */
821 u8 mode; /* DWORD 4 */
822 u8 imd; /* DWORD 4 */
823 u8 ir2t; /* DWORD 4 */
824 u8 notpredblq[2]; /* DWORD 4 */
825 u8 compltonack; /* DWORD 4 */
826 u8 stat_sn[32]; /* DWORD 5 */
827 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
828 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
829 u8 pad_addr_hi[32]; /* DWORD 8 */
830 u8 pad_addr_lo[32]; /* DWORD 9 */
831 u8 rsvd5[32]; /* DWORD 10 */
832 u8 rsvd6[32]; /* DWORD 11 */
833 u8 rsvd7[32]; /* DWORD 12 */
834 u8 rsvd8[32]; /* DWORD 13 */
835 u8 rsvd9[32]; /* DWORD 14 */
836 u8 rsvd10[32]; /* DWORD 15 */
840 #define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024)
841 #define BEISCSI_MAX_CXNS 1
842 struct amap_iscsi_target_context_update_wrb_v2 {
843 u8 max_burst_length[24]; /* DWORD 0 */
844 u8 rsvd0[3]; /* DWORD 0 */
845 u8 type[5]; /* DWORD 0 */
846 u8 ptr2nextwrb[8]; /* DWORD 1 */
847 u8 wrb_idx[8]; /* DWORD 1 */
848 u8 rsvd1[16]; /* DWORD 1 */
849 u8 max_send_data_segment_length[24]; /* DWORD 2 */
850 u8 rsvd2[8]; /* DWORD 2 */
851 u8 first_burst_length[24]; /* DWORD 3 */
852 u8 rsvd3[8]; /* DOWRD 3 */
853 u8 max_r2t[16]; /* DWORD 4 */
854 u8 rsvd4[10]; /* DWORD 4 */
855 u8 hde; /* DWORD 4 */
856 u8 dde; /* DWORD 4 */
857 u8 erl[2]; /* DWORD 4 */
858 u8 imd; /* DWORD 4 */
859 u8 ir2t; /* DWORD 4 */
860 u8 stat_sn[32]; /* DWORD 5 */
861 u8 rsvd5[32]; /* DWORD 6 */
862 u8 rsvd6[32]; /* DWORD 7 */
863 u8 max_recv_dataseg_len[24]; /* DWORD 8 */
864 u8 rsvd7[8]; /* DWORD 8 */
865 u8 rsvd8[32]; /* DWORD 9 */
866 u8 rsvd9[32]; /* DWORD 10 */
867 u8 max_cxns[16]; /* DWORD 11 */
868 u8 rsvd10[11]; /* DWORD 11*/
869 u8 invld; /* DWORD 11 */
870 u8 rsvd11;/* DWORD 11*/
871 u8 dmsg; /* DWORD 11 */
872 u8 data_seq_inorder; /* DWORD 11 */
873 u8 pdu_seq_inorder; /* DWORD 11 */
874 u8 rsvd12[32]; /*DWORD 12 */
875 u8 rsvd13[32]; /* DWORD 13 */
876 u8 rsvd14[32]; /* DWORD 14 */
877 u8 rsvd15[32]; /* DWORD 15 */
882 u32 pages; /* queue size in pages */
883 u32 id; /* queue id assigned by beklib */
884 u32 num; /* number of elements in queue */
885 u32 cidx; /* consumer index */
886 u32 pidx; /* producer index -- not used by most rings */
887 u32 item_size; /* size in bytes of one object */
889 void *va; /* The virtual address of the ring. This
890 * should be last to allow 32 & 64 bit debugger
891 * extensions to work.
895 struct hwi_wrb_context {
896 struct list_head wrb_handle_list;
897 struct list_head wrb_handle_drvr_list;
898 struct wrb_handle **pwrb_handle_base;
899 struct wrb_handle **pwrb_handle_basestd;
900 struct iscsi_wrb *plast_wrb;
901 unsigned short alloc_index;
902 unsigned short free_index;
903 unsigned short wrb_handles_available;
907 struct hwi_controller {
908 struct list_head io_sgl_list;
909 struct list_head eh_sgl_list;
910 struct sgl_handle *psgl_handle_base;
911 unsigned int wrb_mem_index;
913 struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
914 struct mcc_wrb *pmcc_wrb_base;
915 struct be_ring default_pdu_hdr;
916 struct be_ring default_pdu_data;
917 struct hwi_context_memory *phwi_ctxt;
927 HWH_TYPE_INVALID = 0xFFFFFFFF
931 enum hwh_type_enum type;
932 unsigned short wrb_index;
933 unsigned short nxt_wrb_index;
935 struct iscsi_task *pio_handle;
936 struct iscsi_wrb *pwrb;
939 struct hwi_context_memory {
940 /* Adaptive interrupt coalescing (AIC) info */
941 u16 min_eqd; /* in usecs */
942 u16 max_eqd; /* in usecs */
943 u16 cur_eqd; /* in usecs */
944 struct be_eq_obj be_eq[MAX_CPUS];
945 struct be_queue_info be_cq[MAX_CPUS - 1];
947 struct be_queue_info be_def_hdrq;
948 struct be_queue_info be_def_dataq;
950 struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
951 struct be_mcc_wrb_context *pbe_mcc_context;
953 struct hwi_async_pdu_context *pasync_ctx;
956 /* Logging related definitions */
957 #define BEISCSI_LOG_INIT 0x0001 /* Initialization events */
958 #define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */
959 #define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */
960 #define BEISCSI_LOG_EH 0x0008 /* Error Handler */
961 #define BEISCSI_LOG_IO 0x0010 /* IO Code Path */
962 #define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */
964 #define beiscsi_log(phba, level, mask, fmt, arg...) \
966 uint32_t log_value = phba->attr_log_enable; \
967 if (((mask) & log_value) || (level[1] <= '3')) \
968 shost_printk(level, phba->shost, \
969 fmt, __LINE__, ##arg); \