2 * Copyright (C) 2005 - 2011 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
12 * Contact Information:
13 * linux-drivers@emulex.com
17 * Costa Mesa, CA 92626
20 #ifndef _BEISCSI_MAIN_
21 #define _BEISCSI_MAIN_
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/if_ether.h>
27 #include <linux/ctype.h>
28 #include <linux/module.h>
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/iscsi_proto.h>
34 #include <scsi/libiscsi.h>
35 #include <scsi/scsi_transport_iscsi.h>
38 #define DRV_NAME "be2iscsi"
39 #define BUILD_STR "4.4.58.0"
40 #define BE_NAME "Emulex OneConnect" \
41 "Open-iSCSI Driver version" BUILD_STR
42 #define DRV_DESC BE_NAME " " "Driver"
44 #define BE_VENDOR_ID 0x19A2
45 #define ELX_VENDOR_ID 0x10DF
46 /* DEVICE ID's for BE2 */
47 #define BE_DEVICE_ID1 0x212
48 #define OC_DEVICE_ID1 0x702
49 #define OC_DEVICE_ID2 0x703
51 /* DEVICE ID's for BE3 */
52 #define BE_DEVICE_ID2 0x222
53 #define OC_DEVICE_ID3 0x712
55 /* DEVICE ID for SKH */
56 #define OC_SKH_ID1 0x722
58 #define BE2_IO_DEPTH 1024
59 #define BE2_MAX_SESSIONS 256
60 #define BE2_CMDS_PER_CXN 128
62 #define BE2_NOPOUT_REQ 16
64 #define BE2_DEFPDU_HDR_SZ 64
65 #define BE2_DEFPDU_DATA_SZ 8192
68 #define BEISCSI_MAX_NUM_CPUS 7
69 #define OC_SKH_MAX_NUM_CPUS 63
72 #define BEISCSI_SGLIST_ELEMENTS 30
74 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
75 #define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */
77 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
78 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
79 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
80 #define BEISCSI_MAX_FRAGS_INIT 192
81 #define BE_NUM_MSIX_ENTRIES 1
83 #define MPU_EP_CONTROL 0
84 #define MPU_EP_SEMAPHORE 0xac
85 #define BE2_SOFT_RESET 0x5c
86 #define BE2_PCI_ONLINE0 0xb0
87 #define BE2_PCI_ONLINE1 0xb4
88 #define BE2_SET_RESET 0x80
89 #define BE2_MPU_IRAM_ONLINE 0x00000080
91 #define BE_SENSE_INFO_SIZE 258
92 #define BE_ISCSI_PDU_HEADER_SIZE 64
93 #define BE_MIN_MEM_SIZE 16384
94 #define MAX_CMD_SZ 65536
95 #define IIOC_SCSI_DATA 0x05 /* Write Operation */
97 #define INVALID_SESS_HANDLE 0xFFFFFFFF
99 #define BE_ADAPTER_UP 0x00000000
100 #define BE_ADAPTER_LINK_DOWN 0x00000001
102 * hardware needs the async PDU buffers to be posted in multiples of 8
103 * So have atleast 8 of them by default
106 #define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
108 /********* Memory BAR register ************/
109 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
111 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
112 * Disable" may still globally block interrupts in addition to individual
113 * interrupt masks; a mechanism for the device driver to block all interrupts
114 * atomically without having to arbitrate for the PCI Interrupt Disable bit
117 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
119 /********* ISR0 Register offset **********/
120 #define CEV_ISR0_OFFSET 0xC18
121 #define CEV_ISR_SIZE 4
124 * Macros for reading/writing a protection domain or CSR registers
128 #define DB_TXULP0_OFFSET 0x40
129 #define DB_RXULP0_OFFSET 0xA0
130 /********* Event Q door bell *************/
131 #define DB_EQ_OFFSET DB_CQ_OFFSET
132 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
133 /* Clear the interrupt for this eq */
134 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
136 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
137 /* Number of event entries processed */
138 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
140 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
142 /********* Compl Q door bell *************/
143 #define DB_CQ_OFFSET 0x120
144 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
145 /* Number of event entries processed */
146 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
148 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
150 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
151 #define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
152 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
153 #define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
154 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
156 #define PAGES_REQUIRED(x) \
157 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
159 #define BEISCSI_MSI_NAME 20 /* size of msi_name string */
162 HWI_MEM_ADDN_CONTEXT,
167 HWI_MEM_ASYNC_HEADER_BUF, /* 5 */
168 HWI_MEM_ASYNC_DATA_BUF,
169 HWI_MEM_ASYNC_HEADER_RING,
170 HWI_MEM_ASYNC_DATA_RING,
171 HWI_MEM_ASYNC_HEADER_HANDLE,
172 HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */
173 HWI_MEM_ASYNC_PDU_CONTEXT,
174 ISCSI_MEM_GLOBAL_HEADER,
178 struct be_bus_address32 {
179 unsigned int address_lo;
180 unsigned int address_hi;
183 struct be_bus_address64 {
184 unsigned long long address;
187 struct be_bus_address {
189 struct be_bus_address32 a32;
190 struct be_bus_address64 a64;
195 struct be_bus_address bus_address; /* Bus address of location */
196 void *virtual_address; /* virtual address to the location */
197 unsigned int size; /* Size required by memory block */
200 struct be_mem_descriptor {
201 unsigned int index; /* Index of this memory parameter */
202 unsigned int category; /* type indicates cached/non-cached */
203 unsigned int num_elements; /* number of elements in this
206 unsigned int alignment_mask; /* Alignment mask for this block */
207 unsigned int size_in_bytes; /* Size required by memory block */
208 struct mem_array *mem_array;
212 unsigned int sgl_index;
215 struct iscsi_task *task;
216 struct iscsi_sge *pfrag;
219 struct hba_parameters {
220 unsigned int ios_per_ctrl;
221 unsigned int cxns_per_ctrl;
222 unsigned int asyncpdus_per_ctrl;
223 unsigned int icds_per_ctrl;
224 unsigned int num_sge_per_io;
225 unsigned int defpdu_hdr_sz;
226 unsigned int defpdu_data_sz;
227 unsigned int num_cq_entries;
228 unsigned int num_eq_entries;
229 unsigned int wrbs_per_cxn;
230 unsigned int crashmode;
231 unsigned int hba_num;
233 unsigned int mgmt_ws_sz;
234 unsigned int hwi_ws_sz;
239 unsigned int dbg_flags;
240 unsigned int num_cxn;
242 unsigned int eq_timer;
244 * These are calculated from other params. They're here
247 unsigned int num_mcc_pages;
248 unsigned int num_mcc_cq_pages;
249 unsigned int num_cq_pages;
250 unsigned int num_eq_pages;
252 unsigned int num_async_pdu_buf_pages;
253 unsigned int num_async_pdu_buf_sgl_pages;
254 unsigned int num_async_pdu_buf_cq_pages;
256 unsigned int num_async_pdu_hdr_pages;
257 unsigned int num_async_pdu_hdr_sgl_pages;
258 unsigned int num_async_pdu_hdr_cq_pages;
260 unsigned int num_sge;
263 struct invalidate_command_table {
269 struct hba_parameters params;
270 struct hwi_controller *phwi_ctrlr;
271 unsigned int mem_req[SE_MEM_MAX];
272 /* PCI BAR mapped addresses */
273 u8 __iomem *csr_va; /* CSR */
274 u8 __iomem *db_va; /* Door Bell */
275 u8 __iomem *pci_va; /* PCI Config */
276 struct be_bus_address csr_pa; /* CSR */
277 struct be_bus_address db_pa; /* CSR */
278 struct be_bus_address pci_pa; /* CSR */
279 /* PCI representation of our HBA */
280 struct pci_dev *pcidev;
282 unsigned short asic_revision;
283 unsigned int num_cpus;
284 unsigned int nxt_cqid;
285 struct msix_entry msix_entries[MAX_CPUS];
286 char *msi_name[MAX_CPUS];
288 struct be_mem_descriptor *init_mem;
290 unsigned short io_sgl_alloc_index;
291 unsigned short io_sgl_free_index;
292 unsigned short io_sgl_hndl_avbl;
293 struct sgl_handle **io_sgl_hndl_base;
294 struct sgl_handle **sgl_hndl_array;
296 unsigned short eh_sgl_alloc_index;
297 unsigned short eh_sgl_free_index;
298 unsigned short eh_sgl_hndl_avbl;
299 struct sgl_handle **eh_sgl_hndl_base;
300 spinlock_t io_sgl_lock;
301 spinlock_t mgmt_sgl_lock;
304 unsigned short avlbl_cids;
305 unsigned short cid_alloc;
306 unsigned short cid_free;
307 struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
308 struct list_head hba_queue;
309 unsigned short *cid_array;
310 struct iscsi_endpoint **ep_array;
311 struct iscsi_boot_kset *boot_kset;
312 struct Scsi_Host *shost;
313 struct iscsi_iface *ipv4_iface;
314 struct iscsi_iface *ipv6_iface;
317 * group together since they are used most frequently
318 * for cid to cri conversion
320 unsigned int iscsi_cid_start;
321 unsigned int phys_port;
323 unsigned int isr_offset;
324 unsigned int iscsi_icd_start;
325 unsigned int iscsi_cid_count;
326 unsigned int iscsi_icd_count;
327 unsigned int pci_function;
329 unsigned short cid_alloc;
330 unsigned short cid_free;
331 unsigned short avlbl_cids;
332 unsigned short iscsi_features;
336 u8 mac_address[ETH_ALEN];
338 struct workqueue_struct *wq; /* The actuak work queue */
339 struct be_ctrl_info ctrl;
340 unsigned int generation;
341 unsigned int interface_handle;
342 struct mgmt_session_info boot_sess;
343 struct invalidate_command_table inv_tbl[128];
345 unsigned int attr_log_enable;
349 struct beiscsi_session {
350 struct pci_pool *bhs_pool;
354 * struct beiscsi_conn - iscsi connection structure
356 struct beiscsi_conn {
357 struct iscsi_conn *conn;
358 struct beiscsi_hba *phba;
360 u32 beiscsi_conn_cid;
361 struct beiscsi_endpoint *ep;
362 unsigned short login_in_progress;
363 struct wrb_handle *plogin_wrb_handle;
364 struct sgl_handle *plogin_sgl_handle;
365 struct beiscsi_session *beiscsi_sess;
366 struct iscsi_task *task;
369 /* This structure is used by the chip */
370 struct pdu_data_out {
374 * Pseudo amap definition in which each bit of the actual structure is defined
375 * as a byte: used to calculate offset/shift/mask of each field
377 struct amap_pdu_data_out {
378 u8 opcode[6]; /* opcode */
379 u8 rsvd0[2]; /* should be 0 */
381 u8 final_bit; /* F bit */
383 u8 ahs_length[8]; /* no AHS */
385 u8 data_len_lo[16]; /* DataSegmentLength */
387 u8 itt[32]; /* ITT; initiator task tag */
388 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
393 u8 buffer_offset[32];
398 struct iscsi_scsi_req iscsi_hdr;
399 unsigned char pad1[16];
400 struct pdu_data_out iscsi_data_pdu;
401 unsigned char pad2[BE_SENSE_INFO_SIZE -
402 sizeof(struct pdu_data_out)];
405 struct beiscsi_io_task {
406 struct wrb_handle *pwrb_handle;
407 struct sgl_handle *psgl_handle;
408 struct beiscsi_conn *conn;
409 struct scsi_cmnd *scsi_cmnd;
413 unsigned short header_len;
415 struct be_cmd_bhs *cmd_bhs;
416 struct be_bus_address bhs_pa;
417 unsigned short bhs_len;
418 dma_addr_t mtask_addr;
419 uint32_t mtask_data_count;
422 struct be_nonio_bhs {
423 struct iscsi_hdr iscsi_hdr;
424 unsigned char pad1[16];
425 struct pdu_data_out iscsi_data_pdu;
426 unsigned char pad2[BE_SENSE_INFO_SIZE -
427 sizeof(struct pdu_data_out)];
430 struct be_status_bhs {
431 struct iscsi_scsi_req iscsi_hdr;
432 unsigned char pad1[16];
434 * The plus 2 below is to hold the sense info length that gets
437 unsigned char sense_info[BE_SENSE_INFO_SIZE];
445 * Pseudo amap definition in which each bit of the actual structure is defined
446 * as a byte: used to calculate offset/shift/mask of each field
448 struct amap_iscsi_sge {
451 u8 sge_offset[22]; /* DWORD 2 */
452 u8 rsvd0[9]; /* DWORD 2 */
453 u8 last_sge; /* DWORD 2 */
454 u8 len[17]; /* DWORD 3 */
455 u8 rsvd1[15]; /* DWORD 3 */
458 struct beiscsi_offload_params {
462 #define OFFLD_PARAMS_ERL 0x00000003
463 #define OFFLD_PARAMS_DDE 0x00000004
464 #define OFFLD_PARAMS_HDE 0x00000008
465 #define OFFLD_PARAMS_IR2T 0x00000010
466 #define OFFLD_PARAMS_IMD 0x00000020
469 * Pseudo amap definition in which each bit of the actual structure is defined
470 * as a byte: used to calculate offset/shift/mask of each field
472 struct amap_beiscsi_offload_params {
473 u8 max_burst_length[32];
474 u8 max_send_data_segment_length[32];
475 u8 first_burst_length[32];
485 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
486 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
488 struct async_pdu_handle {
489 struct list_head link;
490 struct be_bus_address pa;
492 unsigned int consumed;
494 unsigned char is_header;
496 unsigned long buffer_len;
499 struct hwi_async_entry {
501 unsigned char hdr_received;
502 unsigned char hdr_len;
503 unsigned short bytes_received;
504 unsigned int bytes_needed;
505 struct list_head list;
508 struct list_head header_busy_list;
509 struct list_head data_busy_list;
512 struct hwi_async_pdu_context {
514 struct be_bus_address pa_base;
517 struct async_pdu_handle *handle_base;
519 unsigned int host_write_ptr;
520 unsigned int ep_read_ptr;
521 unsigned int writables;
523 unsigned int free_entries;
524 unsigned int busy_entries;
526 struct list_head free_list;
530 struct be_bus_address pa_base;
533 struct async_pdu_handle *handle_base;
535 unsigned int host_write_ptr;
536 unsigned int ep_read_ptr;
537 unsigned int writables;
539 unsigned int free_entries;
540 unsigned int busy_entries;
541 struct list_head free_list;
544 unsigned int buffer_size;
545 unsigned int num_entries;
548 * This is a varying size list! Do not add anything
551 struct hwi_async_entry async_entry[BE2_MAX_SESSIONS * 2];
554 #define PDUCQE_CODE_MASK 0x0000003F
555 #define PDUCQE_DPL_MASK 0xFFFF0000
556 #define PDUCQE_INDEX_MASK 0x0000FFFF
558 struct i_t_dpdu_cqe {
563 * Pseudo amap definition in which each bit of the actual structure is defined
564 * as a byte: used to calculate offset/shift/mask of each field
566 struct amap_i_t_dpdu_cqe {
579 #define CQE_VALID_MASK 0x80000000
580 #define CQE_CODE_MASK 0x0000003F
581 #define CQE_CID_MASK 0x0000FFC0
583 #define EQE_VALID_MASK 0x00000001
584 #define EQE_MAJORCODE_MASK 0x0000000E
585 #define EQE_RESID_MASK 0xFFFF0000
592 * Pseudo amap definition in which each bit of the actual structure is defined
593 * as a byte: used to calculate offset/shift/mask of each field
595 struct amap_eq_entry {
596 u8 valid; /* DWORD 0 */
597 u8 major_code[3]; /* DWORD 0 */
598 u8 minor_code[12]; /* DWORD 0 */
599 u8 resource_id[16]; /* DWORD 0 */
608 * Pseudo amap definition in which each bit of the actual structure is defined
609 * as a byte: used to calculate offset/shift/mask of each field
620 void beiscsi_process_eq(struct beiscsi_hba *phba);
626 #define WRB_TYPE_MASK 0xF0000000
629 * Pseudo amap definition in which each bit of the actual structure is defined
630 * as a byte: used to calculate offset/shift/mask of each field
632 struct amap_iscsi_wrb {
633 u8 lun[14]; /* DWORD 0 */
635 u8 invld; /* DWORD 0 */
636 u8 wrb_idx[8]; /* DWORD 0 */
637 u8 dsp; /* DWORD 0 */
638 u8 dmsg; /* DWORD 0 */
639 u8 undr_run; /* DWORD 0 */
640 u8 over_run; /* DWORD 0 */
641 u8 type[4]; /* DWORD 0 */
642 u8 ptr2nextwrb[8]; /* DWORD 1 */
643 u8 r2t_exp_dtl[24]; /* DWORD 1 */
644 u8 sgl_icd_idx[12]; /* DWORD 2 */
645 u8 rsvd0[20]; /* DWORD 2 */
646 u8 exp_data_sn[32]; /* DWORD 3 */
647 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
648 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
649 u8 cmdsn_itt[32]; /* DWORD 6 */
650 u8 dif_ref_tag[32]; /* DWORD 7 */
651 u8 sge0_addr_hi[32]; /* DWORD 8 */
652 u8 sge0_addr_lo[32]; /* DWORD 9 */
653 u8 sge0_offset[22]; /* DWORD 10 */
654 u8 pbs; /* DWORD 10 */
655 u8 dif_mode[2]; /* DWORD 10 */
656 u8 rsvd1[6]; /* DWORD 10 */
657 u8 sge0_last; /* DWORD 10 */
658 u8 sge0_len[17]; /* DWORD 11 */
659 u8 dif_meta_tag[14]; /* DWORD 11 */
660 u8 sge0_in_ddr; /* DWORD 11 */
661 u8 sge1_addr_hi[32]; /* DWORD 12 */
662 u8 sge1_addr_lo[32]; /* DWORD 13 */
663 u8 sge1_r2t_offset[22]; /* DWORD 14 */
664 u8 rsvd2[9]; /* DWORD 14 */
665 u8 sge1_last; /* DWORD 14 */
666 u8 sge1_len[17]; /* DWORD 15 */
667 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
668 u8 rsvd3[2]; /* DWORD 15 */
669 u8 sge1_in_ddr; /* DWORD 15 */
673 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
675 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
677 void beiscsi_process_all_cqs(struct work_struct *work);
684 * Pseudo amap definition in which each bit of the actual structure is defined
685 * as a byte: used to calculate offset/shift/mask of each field
687 struct amap_pdu_nop_out {
688 u8 opcode[6]; /* opcode 0x00 */
689 u8 i_bit; /* I Bit */
690 u8 x_bit; /* reserved; should be 0 */
691 u8 fp_bit_filler1[7];
692 u8 f_bit; /* always 1 */
694 u8 ahs_length[8]; /* no AHS */
696 u8 data_len_lo[16]; /* DataSegmentLength */
698 u8 itt[32]; /* initiator id for ping or 0xffffffff */
699 u8 ttt[32]; /* target id for ping or 0xffffffff */
705 #define PDUBASE_OPCODE_MASK 0x0000003F
706 #define PDUBASE_DATALENHI_MASK 0x0000FF00
707 #define PDUBASE_DATALENLO_MASK 0xFFFF0000
714 * Pseudo amap definition in which each bit of the actual structure is defined
715 * as a byte: used to calculate offset/shift/mask of each field
717 struct amap_pdu_base {
719 u8 i_bit; /* immediate bit */
720 u8 x_bit; /* reserved, always 0 */
721 u8 reserved1[24]; /* opcode-specific fields */
722 u8 ahs_length[8]; /* length units is 4 byte words */
724 u8 data_len_lo[16]; /* DatasegmentLength */
725 u8 lun[64]; /* lun or opcode-specific fields */
726 u8 itt[32]; /* initiator task tag */
730 struct iscsi_target_context_update_wrb {
735 * Pseudo amap definition in which each bit of the actual structure is defined
736 * as a byte: used to calculate offset/shift/mask of each field
738 struct amap_iscsi_target_context_update_wrb {
739 u8 lun[14]; /* DWORD 0 */
741 u8 invld; /* DWORD 0 */
742 u8 wrb_idx[8]; /* DWORD 0 */
743 u8 dsp; /* DWORD 0 */
744 u8 dmsg; /* DWORD 0 */
745 u8 undr_run; /* DWORD 0 */
746 u8 over_run; /* DWORD 0 */
747 u8 type[4]; /* DWORD 0 */
748 u8 ptr2nextwrb[8]; /* DWORD 1 */
749 u8 max_burst_length[19]; /* DWORD 1 */
750 u8 rsvd0[5]; /* DWORD 1 */
751 u8 rsvd1[15]; /* DWORD 2 */
752 u8 max_send_data_segment_length[17]; /* DWORD 2 */
753 u8 first_burst_length[14]; /* DWORD 3 */
754 u8 rsvd2[2]; /* DWORD 3 */
755 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
756 u8 rsvd3[5]; /* DWORD 3 */
757 u8 session_state[3]; /* DWORD 3 */
758 u8 rsvd4[16]; /* DWORD 4 */
759 u8 tx_jumbo; /* DWORD 4 */
760 u8 hde; /* DWORD 4 */
761 u8 dde; /* DWORD 4 */
762 u8 erl[2]; /* DWORD 4 */
763 u8 domain_id[5]; /* DWORD 4 */
764 u8 mode; /* DWORD 4 */
765 u8 imd; /* DWORD 4 */
766 u8 ir2t; /* DWORD 4 */
767 u8 notpredblq[2]; /* DWORD 4 */
768 u8 compltonack; /* DWORD 4 */
769 u8 stat_sn[32]; /* DWORD 5 */
770 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
771 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
772 u8 pad_addr_hi[32]; /* DWORD 8 */
773 u8 pad_addr_lo[32]; /* DWORD 9 */
774 u8 rsvd5[32]; /* DWORD 10 */
775 u8 rsvd6[32]; /* DWORD 11 */
776 u8 rsvd7[32]; /* DWORD 12 */
777 u8 rsvd8[32]; /* DWORD 13 */
778 u8 rsvd9[32]; /* DWORD 14 */
779 u8 rsvd10[32]; /* DWORD 15 */
784 u32 pages; /* queue size in pages */
785 u32 id; /* queue id assigned by beklib */
786 u32 num; /* number of elements in queue */
787 u32 cidx; /* consumer index */
788 u32 pidx; /* producer index -- not used by most rings */
789 u32 item_size; /* size in bytes of one object */
791 void *va; /* The virtual address of the ring. This
792 * should be last to allow 32 & 64 bit debugger
793 * extensions to work.
797 struct hwi_wrb_context {
798 struct list_head wrb_handle_list;
799 struct list_head wrb_handle_drvr_list;
800 struct wrb_handle **pwrb_handle_base;
801 struct wrb_handle **pwrb_handle_basestd;
802 struct iscsi_wrb *plast_wrb;
803 unsigned short alloc_index;
804 unsigned short free_index;
805 unsigned short wrb_handles_available;
809 struct hwi_controller {
810 struct list_head io_sgl_list;
811 struct list_head eh_sgl_list;
812 struct sgl_handle *psgl_handle_base;
813 unsigned int wrb_mem_index;
815 struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
816 struct mcc_wrb *pmcc_wrb_base;
817 struct be_ring default_pdu_hdr;
818 struct be_ring default_pdu_data;
819 struct hwi_context_memory *phwi_ctxt;
829 HWH_TYPE_INVALID = 0xFFFFFFFF
833 enum hwh_type_enum type;
834 unsigned short wrb_index;
835 unsigned short nxt_wrb_index;
837 struct iscsi_task *pio_handle;
838 struct iscsi_wrb *pwrb;
841 struct hwi_context_memory {
842 /* Adaptive interrupt coalescing (AIC) info */
843 u16 min_eqd; /* in usecs */
844 u16 max_eqd; /* in usecs */
845 u16 cur_eqd; /* in usecs */
846 struct be_eq_obj be_eq[MAX_CPUS];
847 struct be_queue_info be_cq[MAX_CPUS - 1];
849 struct be_queue_info be_def_hdrq;
850 struct be_queue_info be_def_dataq;
852 struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
853 struct be_mcc_wrb_context *pbe_mcc_context;
855 struct hwi_async_pdu_context *pasync_ctx;
858 /* Logging related definitions */
859 #define BEISCSI_LOG_INIT 0x0001 /* Initialization events */
860 #define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */
861 #define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */
862 #define BEISCSI_LOG_EH 0x0008 /* Error Handler */
863 #define BEISCSI_LOG_IO 0x0010 /* IO Code Path */
864 #define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */
866 #define beiscsi_log(phba, level, mask, fmt, arg...) \
868 uint32_t log_value = phba->attr_log_enable; \
869 if (((mask) & log_value) || (level[1] <= '3')) \
870 shost_printk(level, phba->shost, \
871 fmt, __LINE__, ##arg); \