2 * This file is part of the Chelsio FCoE driver for Linux.
4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #ifndef __CSIO_HW_CHIP_H__
35 #define __CSIO_HW_CHIP_H__
37 #include "csio_defs.h"
39 /* Define MACRO values */
40 #define CSIO_HW_T5 0x5000
41 #define CSIO_T5_FCOE_ASIC 0x5600
42 #define CSIO_HW_CHIP_MASK 0xF000
44 #define T5_REGMAP_SIZE (332 * 1024)
45 #define FW_FNAME_T5 "cxgb4/t5fw.bin"
46 #define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
48 #define T5FW_VERSION_MAJOR 0x01
49 #define T5FW_VERSION_MINOR 0x0B
50 #define T5FW_VERSION_MICRO 0x1B
51 #define T5FW_VERSION_BUILD 0x00
53 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
54 #define CHELSIO_CHIP_FPGA 0x100
55 #define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf)
56 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
58 #define CHELSIO_T5 0x5
61 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
62 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
67 static inline int csio_is_t5(uint16_t chip)
69 return (chip == CSIO_HW_T5);
72 /* Define MACRO DEFINITIONS */
73 #define CSIO_DEVICE(devid, idx) \
74 { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
78 #define FW_VERSION(chip) ( \
79 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
80 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
81 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
82 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
83 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
93 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
96 MEMWIN_APERTURE = 2048,
97 MEMWIN_BASE = 0x1b800,
98 MEMWIN_CSIOSTOR = 6, /* PCI-e Memory Window access */
101 /* Slow path handlers */
103 unsigned int mask; /* bits to check in interrupt status */
104 const char *msg; /* message to print or NULL */
105 short stat_idx; /* stat counter to increment or -1 */
106 unsigned short fatal; /* whether the condition reported is fatal */
109 /* T4/T5 Chip specific ops */
111 struct csio_hw_chip_ops {
112 int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
113 void (*chip_pcie_intr_handler)(struct csio_hw *);
114 uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
115 int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
116 __be32 *, uint64_t *);
117 int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
118 __be32 *, uint64_t *);
119 int (*chip_memory_rw)(struct csio_hw *, u32, int, u32,
120 u32, uint32_t *, int);
121 void (*chip_dfs_create_ext_mem)(struct csio_hw *);
124 extern struct csio_hw_chip_ops t5_ops;
126 #endif /* #ifndef __CSIO_HW_CHIP_H__ */