2 * This file is part of the Chelsio FCoE driver for Linux.
4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/kernel.h>
36 #include <linux/string.h>
37 #include <linux/compiler.h>
38 #include <linux/slab.h>
40 #include <linux/cache.h>
45 #include "csio_defs.h"
47 int csio_intr_coalesce_cnt; /* value:SGE_INGRESS_RX_THRESHOLD[0] */
48 static int csio_sge_thresh_reg; /* SGE_INGRESS_RX_THRESHOLD[0] */
50 int csio_intr_coalesce_time = 10; /* value:SGE_TIMER_VALUE_1 */
51 static int csio_sge_timer_reg = 1;
53 #define CSIO_SET_FLBUF_SIZE(_hw, _reg, _val) \
54 csio_wr_reg32((_hw), (_val), SGE_FL_BUFFER_SIZE##_reg)
57 csio_get_flbuf_size(struct csio_hw *hw, struct csio_sge *sge, uint32_t reg)
59 sge->sge_fl_buf_size[reg] = csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE0 +
60 reg * sizeof(uint32_t));
63 /* Free list buffer size */
64 static inline uint32_t
65 csio_wr_fl_bufsz(struct csio_sge *sge, struct csio_dma_buf *buf)
67 return sge->sge_fl_buf_size[buf->paddr & 0xF];
70 /* Size of the egress queue status page */
71 static inline uint32_t
72 csio_wr_qstat_pgsz(struct csio_hw *hw)
74 return (hw->wrm.sge.sge_control & EGRSTATUSPAGESIZE(1)) ? 128 : 64;
77 /* Ring freelist doorbell */
79 csio_wr_ring_fldb(struct csio_hw *hw, struct csio_q *flq)
82 * Ring the doorbell only when we have atleast CSIO_QCREDIT_SZ
83 * number of bytes in the freelist queue. This translates to atleast
84 * 8 freelist buffer pointers (since each pointer is 8 bytes).
86 if (flq->inc_idx >= 8) {
87 csio_wr_reg32(hw, DBPRIO(1) | QID(flq->un.fl.flid) |
88 PIDX(flq->inc_idx / 8),
89 MYPF_REG(SGE_PF_KDOORBELL));
94 /* Write a 0 cidx increment value to enable SGE interrupts for this queue */
96 csio_wr_sge_intr_enable(struct csio_hw *hw, uint16_t iqid)
98 csio_wr_reg32(hw, CIDXINC(0) |
100 TIMERREG(X_TIMERREG_RESTART_COUNTER),
101 MYPF_REG(SGE_PF_GTS));
105 * csio_wr_fill_fl - Populate the FL buffers of a FL queue.
107 * @flq: Freelist queue.
109 * Fill up freelist buffer entries with buffers of size specified
110 * in the size register.
114 csio_wr_fill_fl(struct csio_hw *hw, struct csio_q *flq)
116 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
117 struct csio_sge *sge = &wrm->sge;
118 __be64 *d = (__be64 *)(flq->vstart);
119 struct csio_dma_buf *buf = &flq->un.fl.bufs[0];
121 int sreg = flq->un.fl.sreg;
122 int n = flq->credits;
125 buf->len = sge->sge_fl_buf_size[sreg];
126 buf->vaddr = pci_alloc_consistent(hw->pdev, buf->len,
129 csio_err(hw, "Could only fill %d buffers!\n", n + 1);
133 paddr = buf->paddr | (sreg & 0xF);
135 *d++ = cpu_to_be64(paddr);
143 * csio_wr_update_fl -
145 * @flq: Freelist queue.
150 csio_wr_update_fl(struct csio_hw *hw, struct csio_q *flq, uint16_t n)
155 if (unlikely(flq->pidx >= flq->credits))
156 flq->pidx -= (uint16_t)flq->credits;
158 CSIO_INC_STATS(flq, n_flq_refill);
162 * csio_wr_alloc_q - Allocate a WR queue and initialize it.
164 * @qsize: Size of the queue in bytes
165 * @wrsize: Since of WR in this queue, if fixed.
166 * @type: Type of queue (Ingress/Egress/Freelist)
167 * @owner: Module that owns this queue.
168 * @nflb: Number of freelist buffers for FL.
169 * @sreg: What is the FL buffer size register?
170 * @iq_int_handler: Ingress queue handler in INTx mode.
172 * This function allocates and sets up a queue for the caller
173 * of size qsize, aligned at the required boundary. This is subject to
174 * be free entries being available in the queue array. If one is found,
175 * it is initialized with the allocated queue, marked as being used (owner),
176 * and a handle returned to the caller in form of the queue's index
177 * into the q_arr array.
178 * If user has indicated a freelist (by specifying nflb > 0), create
179 * another queue (with its own index into q_arr) for the freelist. Allocate
180 * memory for DMA buffer metadata (vaddr, len etc). Save off the freelist
181 * idx in the ingress queue's flq.idx. This is how a Freelist is associated
182 * with its owning ingress queue.
185 csio_wr_alloc_q(struct csio_hw *hw, uint32_t qsize, uint32_t wrsize,
186 uint16_t type, void *owner, uint32_t nflb, int sreg,
187 iq_handler_t iq_intx_handler)
189 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
190 struct csio_q *q, *flq;
191 int free_idx = wrm->free_qidx;
192 int ret_idx = free_idx;
196 if (free_idx >= wrm->num_q) {
197 csio_err(hw, "No more free queues.\n");
203 qsz = ALIGN(qsize, CSIO_QCREDIT_SZ) + csio_wr_qstat_pgsz(hw);
213 csio_err(hw, "Invalid Ingress queue WR size:%d\n",
219 * Number of elements must be a multiple of 16
220 * So this includes status page size
222 qsz = ALIGN(qsize/wrsize, 16) * wrsize;
226 qsz = ALIGN(qsize/wrsize, 8) * wrsize + csio_wr_qstat_pgsz(hw);
229 csio_err(hw, "Invalid queue type: 0x%x\n", type);
233 q = wrm->q_arr[free_idx];
235 q->vstart = pci_alloc_consistent(hw->pdev, qsz, &q->pstart);
238 "Failed to allocate DMA memory for "
239 "queue at id: %d size: %d\n", free_idx, qsize);
244 * We need to zero out the contents, importantly for ingress,
245 * since we start with a generatiom bit of 1 for ingress.
247 memset(q->vstart, 0, qsz);
251 q->pidx = q->cidx = q->inc_idx = 0;
253 q->wr_sz = wrsize; /* If using fixed size WRs */
257 if (type == CSIO_INGRESS) {
258 /* Since queue area is set to zero */
262 * Ingress queue status page size is always the size of
263 * the ingress queue entry.
265 q->credits = (qsz - q->wr_sz) / q->wr_sz;
266 q->vwrap = (void *)((uintptr_t)(q->vstart) + qsz
269 /* Allocate memory for FL if requested */
271 flq_idx = csio_wr_alloc_q(hw, nflb * sizeof(__be64),
272 sizeof(__be64), CSIO_FREELIST,
273 owner, 0, sreg, NULL);
276 "Failed to allocate FL queue"
277 " for IQ idx:%d\n", free_idx);
281 /* Associate the new FL with the Ingress quue */
282 q->un.iq.flq_idx = flq_idx;
284 flq = wrm->q_arr[q->un.iq.flq_idx];
285 flq->un.fl.bufs = kzalloc(flq->credits *
286 sizeof(struct csio_dma_buf),
288 if (!flq->un.fl.bufs) {
290 "Failed to allocate FL queue bufs"
291 " for IQ idx:%d\n", free_idx);
295 flq->un.fl.packen = 0;
296 flq->un.fl.offset = 0;
297 flq->un.fl.sreg = sreg;
299 /* Fill up the free list buffers */
300 if (csio_wr_fill_fl(hw, flq))
304 * Make sure in a FLQ, atleast 1 credit (8 FL buffers)
305 * remains unpopulated,otherwise HW thinks
308 flq->pidx = flq->inc_idx = flq->credits - 8;
310 q->un.iq.flq_idx = -1;
313 /* Associate the IQ INTx handler. */
314 q->un.iq.iq_intx_handler = iq_intx_handler;
316 csio_q_iqid(hw, ret_idx) = CSIO_MAX_QID;
318 } else if (type == CSIO_EGRESS) {
319 q->credits = (qsz - csio_wr_qstat_pgsz(hw)) / CSIO_QCREDIT_SZ;
320 q->vwrap = (void *)((uintptr_t)(q->vstart) + qsz
321 - csio_wr_qstat_pgsz(hw));
322 csio_q_eqid(hw, ret_idx) = CSIO_MAX_QID;
323 } else { /* Freelist */
324 q->credits = (qsz - csio_wr_qstat_pgsz(hw)) / sizeof(__be64);
325 q->vwrap = (void *)((uintptr_t)(q->vstart) + qsz
326 - csio_wr_qstat_pgsz(hw));
327 csio_q_flid(hw, ret_idx) = CSIO_MAX_QID;
334 * csio_wr_iq_create_rsp - Response handler for IQ creation.
335 * @hw: The HW module.
337 * @iq_idx: Ingress queue that got created.
339 * Handle FW_IQ_CMD mailbox completion. Save off the assigned IQ/FL ids.
342 csio_wr_iq_create_rsp(struct csio_hw *hw, struct csio_mb *mbp, int iq_idx)
344 struct csio_iq_params iqp;
345 enum fw_retval retval;
349 memset(&iqp, 0, sizeof(struct csio_iq_params));
351 csio_mb_iq_alloc_write_rsp(hw, mbp, &retval, &iqp);
353 if (retval != FW_SUCCESS) {
354 csio_err(hw, "IQ cmd returned 0x%x!\n", retval);
355 mempool_free(mbp, hw->mb_mempool);
359 csio_q_iqid(hw, iq_idx) = iqp.iqid;
360 csio_q_physiqid(hw, iq_idx) = iqp.physiqid;
361 csio_q_pidx(hw, iq_idx) = csio_q_cidx(hw, iq_idx) = 0;
362 csio_q_inc_idx(hw, iq_idx) = 0;
365 iq_id = iqp.iqid - hw->wrm.fw_iq_start;
367 /* Set the iq-id to iq map table. */
368 if (iq_id >= CSIO_MAX_IQ) {
370 "Exceeding MAX_IQ(%d) supported!"
371 " iqid:%d rel_iqid:%d FW iq_start:%d\n",
372 CSIO_MAX_IQ, iq_id, iqp.iqid, hw->wrm.fw_iq_start);
373 mempool_free(mbp, hw->mb_mempool);
376 csio_q_set_intr_map(hw, iq_idx, iq_id);
379 * During FW_IQ_CMD, FW sets interrupt_sent bit to 1 in the SGE
380 * ingress context of this queue. This will block interrupts to
381 * this queue until the next GTS write. Therefore, we do a
382 * 0-cidx increment GTS write for this queue just to clear the
383 * interrupt_sent bit. This will re-enable interrupts to this
386 csio_wr_sge_intr_enable(hw, iqp.physiqid);
388 flq_idx = csio_q_iq_flq_idx(hw, iq_idx);
390 struct csio_q *flq = hw->wrm.q_arr[flq_idx];
392 csio_q_flid(hw, flq_idx) = iqp.fl0id;
393 csio_q_cidx(hw, flq_idx) = 0;
394 csio_q_pidx(hw, flq_idx) = csio_q_credits(hw, flq_idx) - 8;
395 csio_q_inc_idx(hw, flq_idx) = csio_q_credits(hw, flq_idx) - 8;
397 /* Now update SGE about the buffers allocated during init */
398 csio_wr_ring_fldb(hw, flq);
401 mempool_free(mbp, hw->mb_mempool);
407 * csio_wr_iq_create - Configure an Ingress queue with FW.
408 * @hw: The HW module.
409 * @priv: Private data object.
410 * @iq_idx: Ingress queue index in the WR module.
412 * @portid: PCIE Channel to be associated with this queue.
413 * @async: Is this a FW asynchronous message handling queue?
414 * @cbfn: Completion callback.
416 * This API configures an ingress queue with FW by issuing a FW_IQ_CMD mailbox
417 * with alloc/write bits set.
420 csio_wr_iq_create(struct csio_hw *hw, void *priv, int iq_idx,
421 uint32_t vec, uint8_t portid, bool async,
422 void (*cbfn) (struct csio_hw *, struct csio_mb *))
425 struct csio_iq_params iqp;
428 memset(&iqp, 0, sizeof(struct csio_iq_params));
429 csio_q_portid(hw, iq_idx) = portid;
431 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
433 csio_err(hw, "IQ command out of memory!\n");
437 switch (hw->intr_mode) {
440 /* For interrupt forwarding queue only */
441 if (hw->intr_iq_idx == iq_idx)
442 iqp.iqandst = X_INTERRUPTDESTINATION_PCIE;
444 iqp.iqandst = X_INTERRUPTDESTINATION_IQ;
446 csio_q_physiqid(hw, hw->intr_iq_idx);
449 iqp.iqandst = X_INTERRUPTDESTINATION_PCIE;
450 iqp.iqandstindex = (uint16_t)vec;
453 mempool_free(mbp, hw->mb_mempool);
457 /* Pass in the ingress queue cmd parameters */
462 iqp.type = FW_IQ_TYPE_FL_INT_CAP;
463 iqp.iqasynch = async;
464 if (csio_intr_coalesce_cnt)
465 iqp.iqanus = X_UPDATESCHEDULING_COUNTER_OPTTIMER;
467 iqp.iqanus = X_UPDATESCHEDULING_TIMER;
468 iqp.iqanud = X_UPDATEDELIVERY_INTERRUPT;
469 iqp.iqpciech = portid;
470 iqp.iqintcntthresh = (uint8_t)csio_sge_thresh_reg;
472 switch (csio_q_wr_sz(hw, iq_idx)) {
474 iqp.iqesize = 0; break;
476 iqp.iqesize = 1; break;
478 iqp.iqesize = 2; break;
480 iqp.iqesize = 3; break;
483 iqp.iqsize = csio_q_size(hw, iq_idx) /
484 csio_q_wr_sz(hw, iq_idx);
485 iqp.iqaddr = csio_q_pstart(hw, iq_idx);
487 flq_idx = csio_q_iq_flq_idx(hw, iq_idx);
489 struct csio_q *flq = hw->wrm.q_arr[flq_idx];
492 iqp.fl0packen = flq->un.fl.packen ? 1 : 0;
493 iqp.fl0fbmin = X_FETCHBURSTMIN_64B;
494 iqp.fl0fbmax = X_FETCHBURSTMAX_512B;
495 iqp.fl0size = csio_q_size(hw, flq_idx) / CSIO_QCREDIT_SZ;
496 iqp.fl0addr = csio_q_pstart(hw, flq_idx);
499 csio_mb_iq_alloc_write(hw, mbp, priv, CSIO_MB_DEFAULT_TMO, &iqp, cbfn);
501 if (csio_mb_issue(hw, mbp)) {
502 csio_err(hw, "Issue of IQ cmd failed!\n");
503 mempool_free(mbp, hw->mb_mempool);
510 return csio_wr_iq_create_rsp(hw, mbp, iq_idx);
514 * csio_wr_eq_create_rsp - Response handler for EQ creation.
515 * @hw: The HW module.
517 * @eq_idx: Egress queue that got created.
519 * Handle FW_EQ_OFLD_CMD mailbox completion. Save off the assigned EQ ids.
522 csio_wr_eq_cfg_rsp(struct csio_hw *hw, struct csio_mb *mbp, int eq_idx)
524 struct csio_eq_params eqp;
525 enum fw_retval retval;
527 memset(&eqp, 0, sizeof(struct csio_eq_params));
529 csio_mb_eq_ofld_alloc_write_rsp(hw, mbp, &retval, &eqp);
531 if (retval != FW_SUCCESS) {
532 csio_err(hw, "EQ OFLD cmd returned 0x%x!\n", retval);
533 mempool_free(mbp, hw->mb_mempool);
537 csio_q_eqid(hw, eq_idx) = (uint16_t)eqp.eqid;
538 csio_q_physeqid(hw, eq_idx) = (uint16_t)eqp.physeqid;
539 csio_q_pidx(hw, eq_idx) = csio_q_cidx(hw, eq_idx) = 0;
540 csio_q_inc_idx(hw, eq_idx) = 0;
542 mempool_free(mbp, hw->mb_mempool);
548 * csio_wr_eq_create - Configure an Egress queue with FW.
550 * @priv: Private data.
551 * @eq_idx: Egress queue index in the WR module.
552 * @iq_idx: Associated ingress queue index.
553 * @cbfn: Completion callback.
555 * This API configures a offload egress queue with FW by issuing a
556 * FW_EQ_OFLD_CMD (with alloc + write ) mailbox.
559 csio_wr_eq_create(struct csio_hw *hw, void *priv, int eq_idx,
560 int iq_idx, uint8_t portid,
561 void (*cbfn) (struct csio_hw *, struct csio_mb *))
564 struct csio_eq_params eqp;
566 memset(&eqp, 0, sizeof(struct csio_eq_params));
568 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
570 csio_err(hw, "EQ command out of memory!\n");
577 eqp.hostfcmode = X_HOSTFCMODE_STATUS_PAGE;
578 eqp.iqid = csio_q_iqid(hw, iq_idx);
579 eqp.fbmin = X_FETCHBURSTMIN_64B;
580 eqp.fbmax = X_FETCHBURSTMAX_512B;
582 eqp.pciechn = portid;
583 eqp.eqsize = csio_q_size(hw, eq_idx) / CSIO_QCREDIT_SZ;
584 eqp.eqaddr = csio_q_pstart(hw, eq_idx);
586 csio_mb_eq_ofld_alloc_write(hw, mbp, priv, CSIO_MB_DEFAULT_TMO,
589 if (csio_mb_issue(hw, mbp)) {
590 csio_err(hw, "Issue of EQ OFLD cmd failed!\n");
591 mempool_free(mbp, hw->mb_mempool);
598 return csio_wr_eq_cfg_rsp(hw, mbp, eq_idx);
602 * csio_wr_iq_destroy_rsp - Response handler for IQ removal.
603 * @hw: The HW module.
605 * @iq_idx: Ingress queue that was freed.
607 * Handle FW_IQ_CMD (free) mailbox completion.
610 csio_wr_iq_destroy_rsp(struct csio_hw *hw, struct csio_mb *mbp, int iq_idx)
612 enum fw_retval retval = csio_mb_fw_retval(mbp);
615 if (retval != FW_SUCCESS)
618 mempool_free(mbp, hw->mb_mempool);
624 * csio_wr_iq_destroy - Free an ingress queue.
625 * @hw: The HW module.
626 * @priv: Private data object.
627 * @iq_idx: Ingress queue index to destroy
628 * @cbfn: Completion callback.
630 * This API frees an ingress queue by issuing the FW_IQ_CMD
631 * with the free bit set.
634 csio_wr_iq_destroy(struct csio_hw *hw, void *priv, int iq_idx,
635 void (*cbfn)(struct csio_hw *, struct csio_mb *))
639 struct csio_iq_params iqp;
642 memset(&iqp, 0, sizeof(struct csio_iq_params));
644 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
650 iqp.iqid = csio_q_iqid(hw, iq_idx);
651 iqp.type = FW_IQ_TYPE_FL_INT_CAP;
653 flq_idx = csio_q_iq_flq_idx(hw, iq_idx);
655 iqp.fl0id = csio_q_flid(hw, flq_idx);
661 csio_mb_iq_free(hw, mbp, priv, CSIO_MB_DEFAULT_TMO, &iqp, cbfn);
663 rv = csio_mb_issue(hw, mbp);
665 mempool_free(mbp, hw->mb_mempool);
672 return csio_wr_iq_destroy_rsp(hw, mbp, iq_idx);
676 * csio_wr_eq_destroy_rsp - Response handler for OFLD EQ creation.
677 * @hw: The HW module.
679 * @eq_idx: Egress queue that was freed.
681 * Handle FW_OFLD_EQ_CMD (free) mailbox completion.
684 csio_wr_eq_destroy_rsp(struct csio_hw *hw, struct csio_mb *mbp, int eq_idx)
686 enum fw_retval retval = csio_mb_fw_retval(mbp);
689 if (retval != FW_SUCCESS)
692 mempool_free(mbp, hw->mb_mempool);
698 * csio_wr_eq_destroy - Free an Egress queue.
699 * @hw: The HW module.
700 * @priv: Private data object.
701 * @eq_idx: Egress queue index to destroy
702 * @cbfn: Completion callback.
704 * This API frees an Egress queue by issuing the FW_EQ_OFLD_CMD
705 * with the free bit set.
708 csio_wr_eq_destroy(struct csio_hw *hw, void *priv, int eq_idx,
709 void (*cbfn) (struct csio_hw *, struct csio_mb *))
713 struct csio_eq_params eqp;
715 memset(&eqp, 0, sizeof(struct csio_eq_params));
717 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
723 eqp.eqid = csio_q_eqid(hw, eq_idx);
725 csio_mb_eq_ofld_free(hw, mbp, priv, CSIO_MB_DEFAULT_TMO, &eqp, cbfn);
727 rv = csio_mb_issue(hw, mbp);
729 mempool_free(mbp, hw->mb_mempool);
736 return csio_wr_eq_destroy_rsp(hw, mbp, eq_idx);
740 * csio_wr_cleanup_eq_stpg - Cleanup Egress queue status page
742 * @qidx: Egress queue index
744 * Cleanup the Egress queue status page.
747 csio_wr_cleanup_eq_stpg(struct csio_hw *hw, int qidx)
749 struct csio_q *q = csio_hw_to_wrm(hw)->q_arr[qidx];
750 struct csio_qstatus_page *stp = (struct csio_qstatus_page *)q->vwrap;
752 memset(stp, 0, sizeof(*stp));
756 * csio_wr_cleanup_iq_ftr - Cleanup Footer entries in IQ
758 * @qidx: Ingress queue index
760 * Cleanup the footer entries in the given ingress queue,
761 * set to 1 the internal copy of genbit.
764 csio_wr_cleanup_iq_ftr(struct csio_hw *hw, int qidx)
766 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
767 struct csio_q *q = wrm->q_arr[qidx];
769 struct csio_iqwr_footer *ftr;
772 /* set to 1 since we are just about zero out genbit */
775 for (i = 0; i < q->credits; i++) {
777 wr = (void *)((uintptr_t)q->vstart +
780 ftr = (struct csio_iqwr_footer *)((uintptr_t)wr +
781 (q->wr_sz - sizeof(*ftr)));
782 /* Zero out footer */
783 memset(ftr, 0, sizeof(*ftr));
788 csio_wr_destroy_queues(struct csio_hw *hw, bool cmd)
792 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
795 for (i = 0; i < wrm->free_qidx; i++) {
800 if (csio_q_eqid(hw, i) != CSIO_MAX_QID) {
801 csio_wr_cleanup_eq_stpg(hw, i);
803 csio_q_eqid(hw, i) = CSIO_MAX_QID;
807 rv = csio_wr_eq_destroy(hw, NULL, i, NULL);
808 if ((rv == -EBUSY) || (rv == -ETIMEDOUT))
811 csio_q_eqid(hw, i) = CSIO_MAX_QID;
814 if (csio_q_iqid(hw, i) != CSIO_MAX_QID) {
815 csio_wr_cleanup_iq_ftr(hw, i);
817 csio_q_iqid(hw, i) = CSIO_MAX_QID;
818 flq_idx = csio_q_iq_flq_idx(hw, i);
820 csio_q_flid(hw, flq_idx) =
825 rv = csio_wr_iq_destroy(hw, NULL, i, NULL);
826 if ((rv == -EBUSY) || (rv == -ETIMEDOUT))
829 csio_q_iqid(hw, i) = CSIO_MAX_QID;
830 flq_idx = csio_q_iq_flq_idx(hw, i);
832 csio_q_flid(hw, flq_idx) = CSIO_MAX_QID;
839 hw->flags &= ~CSIO_HWF_Q_FW_ALLOCED;
845 * csio_wr_get - Get requested size of WR entry/entries from queue.
847 * @qidx: Index of queue.
848 * @size: Cumulative size of Work request(s).
849 * @wrp: Work request pair.
851 * If requested credits are available, return the start address of the
852 * work request in the work request pair. Set pidx accordingly and
855 * NOTE about WR pair:
857 * A WR can start towards the end of a queue, and then continue at the
858 * beginning, since the queue is considered to be circular. This will
859 * require a pair of address/size to be passed back to the caller -
860 * hence Work request pair format.
863 csio_wr_get(struct csio_hw *hw, int qidx, uint32_t size,
864 struct csio_wr_pair *wrp)
866 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
867 struct csio_q *q = wrm->q_arr[qidx];
868 void *cwr = (void *)((uintptr_t)(q->vstart) +
869 (q->pidx * CSIO_QCREDIT_SZ));
870 struct csio_qstatus_page *stp = (struct csio_qstatus_page *)q->vwrap;
871 uint16_t cidx = q->cidx = ntohs(stp->cidx);
872 uint16_t pidx = q->pidx;
873 uint32_t req_sz = ALIGN(size, CSIO_QCREDIT_SZ);
874 int req_credits = req_sz / CSIO_QCREDIT_SZ;
877 CSIO_DB_ASSERT(q->owner != NULL);
878 CSIO_DB_ASSERT((qidx >= 0) && (qidx < wrm->free_qidx));
879 CSIO_DB_ASSERT(cidx <= q->credits);
881 /* Calculate credits */
883 credits = q->credits - (pidx - cidx) - 1;
884 } else if (cidx > pidx) {
885 credits = cidx - pidx - 1;
887 /* cidx == pidx, empty queue */
888 credits = q->credits;
889 CSIO_INC_STATS(q, n_qempty);
893 * Check if we have enough credits.
894 * credits = 1 implies queue is full.
896 if (!credits || (req_credits > credits)) {
897 CSIO_INC_STATS(q, n_qfull);
902 * If we are here, we have enough credits to satisfy the
903 * request. Check if we are near the end of q, and if WR spills over.
904 * If it does, use the first addr/size to cover the queue until
905 * the end. Fit the remainder portion of the request at the top
906 * of queue and return it in the second addr/len. Set pidx
909 if (unlikely(((uintptr_t)cwr + req_sz) > (uintptr_t)(q->vwrap))) {
911 wrp->size1 = (uint32_t)((uintptr_t)q->vwrap - (uintptr_t)cwr);
912 wrp->addr2 = q->vstart;
913 wrp->size2 = req_sz - wrp->size1;
914 q->pidx = (uint16_t)(ALIGN(wrp->size2, CSIO_QCREDIT_SZ) /
916 CSIO_INC_STATS(q, n_qwrap);
917 CSIO_INC_STATS(q, n_eq_wr_split);
923 q->pidx += (uint16_t)req_credits;
925 /* We are the end of queue, roll back pidx to top of queue */
926 if (unlikely(q->pidx == q->credits)) {
928 CSIO_INC_STATS(q, n_qwrap);
932 q->inc_idx = (uint16_t)req_credits;
934 CSIO_INC_STATS(q, n_tot_reqs);
940 * csio_wr_copy_to_wrp - Copies given data into WR.
941 * @data_buf - Data buffer
942 * @wrp - Work request pair.
943 * @wr_off - Work request offset.
944 * @data_len - Data length.
946 * Copies the given data in Work Request. Work request pair(wrp) specifies
947 * address information of Work request.
951 csio_wr_copy_to_wrp(void *data_buf, struct csio_wr_pair *wrp,
952 uint32_t wr_off, uint32_t data_len)
956 /* Number of space available in buffer addr1 of WRP */
957 nbytes = ((wrp->size1 - wr_off) >= data_len) ?
958 data_len : (wrp->size1 - wr_off);
960 memcpy((uint8_t *) wrp->addr1 + wr_off, data_buf, nbytes);
963 /* Write the remaining data from the begining of circular buffer */
965 CSIO_DB_ASSERT(data_len <= wrp->size2);
966 CSIO_DB_ASSERT(wrp->addr2 != NULL);
967 memcpy(wrp->addr2, (uint8_t *) data_buf + nbytes, data_len);
972 * csio_wr_issue - Notify chip of Work request.
974 * @qidx: Index of queue.
975 * @prio: 0: Low priority, 1: High priority
977 * Rings the SGE Doorbell by writing the current producer index of the passed
978 * in queue into the register.
982 csio_wr_issue(struct csio_hw *hw, int qidx, bool prio)
984 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
985 struct csio_q *q = wrm->q_arr[qidx];
987 CSIO_DB_ASSERT((qidx >= 0) && (qidx < wrm->free_qidx));
990 /* Ring SGE Doorbell writing q->pidx into it */
991 csio_wr_reg32(hw, DBPRIO(prio) | QID(q->un.eq.physeqid) |
992 PIDX(q->inc_idx), MYPF_REG(SGE_PF_KDOORBELL));
998 static inline uint32_t
999 csio_wr_avail_qcredits(struct csio_q *q)
1001 if (q->pidx > q->cidx)
1002 return q->pidx - q->cidx;
1003 else if (q->cidx > q->pidx)
1004 return q->credits - (q->cidx - q->pidx);
1006 return 0; /* cidx == pidx, empty queue */
1010 * csio_wr_inval_flq_buf - Invalidate a free list buffer entry.
1012 * @flq: The freelist queue.
1014 * Invalidate the driver's version of a freelist buffer entry,
1015 * without freeing the associated the DMA memory. The entry
1016 * to be invalidated is picked up from the current Free list
1021 csio_wr_inval_flq_buf(struct csio_hw *hw, struct csio_q *flq)
1024 if (flq->cidx == flq->credits) {
1026 CSIO_INC_STATS(flq, n_qwrap);
1031 * csio_wr_process_fl - Process a freelist completion.
1033 * @q: The ingress queue attached to the Freelist.
1034 * @wr: The freelist completion WR in the ingress queue.
1035 * @len_to_qid: The lower 32-bits of the first flit of the RSP footer
1036 * @iq_handler: Caller's handler for this completion.
1037 * @priv: Private pointer of caller
1041 csio_wr_process_fl(struct csio_hw *hw, struct csio_q *q,
1042 void *wr, uint32_t len_to_qid,
1043 void (*iq_handler)(struct csio_hw *, void *,
1044 uint32_t, struct csio_fl_dma_buf *,
1048 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
1049 struct csio_sge *sge = &wrm->sge;
1050 struct csio_fl_dma_buf flb;
1051 struct csio_dma_buf *buf, *fbuf;
1052 uint32_t bufsz, len, lastlen = 0;
1054 struct csio_q *flq = hw->wrm.q_arr[q->un.iq.flq_idx];
1056 CSIO_DB_ASSERT(flq != NULL);
1060 if (len & IQWRF_NEWBUF) {
1061 if (flq->un.fl.offset > 0) {
1062 csio_wr_inval_flq_buf(hw, flq);
1063 flq->un.fl.offset = 0;
1065 len = IQWRF_LEN_GET(len);
1068 CSIO_DB_ASSERT(len != 0);
1072 /* Consume all freelist buffers used for len bytes */
1073 for (n = 0, fbuf = flb.flbufs; ; n++, fbuf++) {
1074 buf = &flq->un.fl.bufs[flq->cidx];
1075 bufsz = csio_wr_fl_bufsz(sge, buf);
1077 fbuf->paddr = buf->paddr;
1078 fbuf->vaddr = buf->vaddr;
1080 flb.offset = flq->un.fl.offset;
1081 lastlen = min(bufsz, len);
1082 fbuf->len = lastlen;
1087 csio_wr_inval_flq_buf(hw, flq);
1090 flb.defer_free = flq->un.fl.packen ? 0 : 1;
1092 iq_handler(hw, wr, q->wr_sz - sizeof(struct csio_iqwr_footer),
1095 if (flq->un.fl.packen)
1096 flq->un.fl.offset += ALIGN(lastlen, sge->csio_fl_align);
1098 csio_wr_inval_flq_buf(hw, flq);
1103 * csio_is_new_iqwr - Is this a new Ingress queue entry ?
1104 * @q: Ingress quueue.
1105 * @ftr: Ingress queue WR SGE footer.
1107 * The entry is new if our generation bit matches the corresponding
1108 * bit in the footer of the current WR.
1111 csio_is_new_iqwr(struct csio_q *q, struct csio_iqwr_footer *ftr)
1113 return (q->un.iq.genbit == (ftr->u.type_gen >> IQWRF_GEN_SHIFT));
1117 * csio_wr_process_iq - Process elements in Ingress queue.
1119 * @qidx: Index of queue
1120 * @iq_handler: Handler for this queue
1121 * @priv: Caller's private pointer
1123 * This routine walks through every entry of the ingress queue, calling
1124 * the provided iq_handler with the entry, until the generation bit
1128 csio_wr_process_iq(struct csio_hw *hw, struct csio_q *q,
1129 void (*iq_handler)(struct csio_hw *, void *,
1130 uint32_t, struct csio_fl_dma_buf *,
1134 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
1135 void *wr = (void *)((uintptr_t)q->vstart + (q->cidx * q->wr_sz));
1136 struct csio_iqwr_footer *ftr;
1137 uint32_t wr_type, fw_qid, qid;
1138 struct csio_q *q_completed;
1139 struct csio_q *flq = csio_iq_has_fl(q) ?
1140 wrm->q_arr[q->un.iq.flq_idx] : NULL;
1143 /* Get the footer */
1144 ftr = (struct csio_iqwr_footer *)((uintptr_t)wr +
1145 (q->wr_sz - sizeof(*ftr)));
1148 * When q wrapped around last time, driver should have inverted
1149 * ic.genbit as well.
1151 while (csio_is_new_iqwr(q, ftr)) {
1153 CSIO_DB_ASSERT(((uintptr_t)wr + q->wr_sz) <=
1154 (uintptr_t)q->vwrap);
1156 wr_type = IQWRF_TYPE_GET(ftr->u.type_gen);
1159 case X_RSPD_TYPE_CPL:
1160 /* Subtract footer from WR len */
1161 iq_handler(hw, wr, q->wr_sz - sizeof(*ftr), NULL, priv);
1163 case X_RSPD_TYPE_FLBUF:
1164 csio_wr_process_fl(hw, q, wr,
1165 ntohl(ftr->pldbuflen_qid),
1168 case X_RSPD_TYPE_INTR:
1169 fw_qid = ntohl(ftr->pldbuflen_qid);
1170 qid = fw_qid - wrm->fw_iq_start;
1171 q_completed = hw->wrm.intr_map[qid];
1174 csio_q_physiqid(hw, hw->intr_iq_idx))) {
1176 * We are already in the Forward Interrupt
1177 * Interrupt Queue Service! Do-not service
1182 CSIO_DB_ASSERT(q_completed);
1184 q_completed->un.iq.iq_intx_handler);
1186 /* Call the queue handler. */
1187 q_completed->un.iq.iq_intx_handler(hw, NULL,
1188 0, NULL, (void *)q_completed);
1192 csio_warn(hw, "Unknown resp type 0x%x received\n",
1194 CSIO_INC_STATS(q, n_rsp_unknown);
1199 * Ingress *always* has fixed size WR entries. Therefore,
1200 * there should always be complete WRs towards the end of
1203 if (((uintptr_t)wr + q->wr_sz) == (uintptr_t)q->vwrap) {
1205 /* Roll over to start of queue */
1210 q->un.iq.genbit ^= 0x1;
1212 CSIO_INC_STATS(q, n_qwrap);
1215 wr = (void *)((uintptr_t)(q->vstart) +
1216 (q->cidx * q->wr_sz));
1219 ftr = (struct csio_iqwr_footer *)((uintptr_t)wr +
1220 (q->wr_sz - sizeof(*ftr)));
1223 } /* while (q->un.iq.genbit == hdr->genbit) */
1226 * We need to re-arm SGE interrupts in case we got a stray interrupt,
1227 * especially in msix mode. With INTx, this may be a common occurence.
1229 if (unlikely(!q->inc_idx)) {
1230 CSIO_INC_STATS(q, n_stray_comp);
1235 /* Replenish free list buffers if pending falls below low water mark */
1237 uint32_t avail = csio_wr_avail_qcredits(flq);
1239 /* Make sure in FLQ, atleast 1 credit (8 FL buffers)
1240 * remains unpopulated otherwise HW thinks
1243 csio_wr_update_fl(hw, flq, (flq->credits - 8) - avail);
1244 csio_wr_ring_fldb(hw, flq);
1249 /* Now inform SGE about our incremental index value */
1250 csio_wr_reg32(hw, CIDXINC(q->inc_idx) |
1251 INGRESSQID(q->un.iq.physiqid) |
1252 TIMERREG(csio_sge_timer_reg),
1253 MYPF_REG(SGE_PF_GTS));
1254 q->stats.n_tot_rsps += q->inc_idx;
1262 csio_wr_process_iq_idx(struct csio_hw *hw, int qidx,
1263 void (*iq_handler)(struct csio_hw *, void *,
1264 uint32_t, struct csio_fl_dma_buf *,
1268 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
1269 struct csio_q *iq = wrm->q_arr[qidx];
1271 return csio_wr_process_iq(hw, iq, iq_handler, priv);
1275 csio_closest_timer(struct csio_sge *s, int time)
1277 int i, delta, match = 0, min_delta = INT_MAX;
1279 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1280 delta = time - s->timer_val[i];
1283 if (delta < min_delta) {
1292 csio_closest_thresh(struct csio_sge *s, int cnt)
1294 int i, delta, match = 0, min_delta = INT_MAX;
1296 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1297 delta = cnt - s->counter_val[i];
1300 if (delta < min_delta) {
1309 csio_wr_fixup_host_params(struct csio_hw *hw)
1311 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
1312 struct csio_sge *sge = &wrm->sge;
1313 uint32_t clsz = L1_CACHE_BYTES;
1314 uint32_t s_hps = PAGE_SHIFT - 10;
1315 uint32_t ingpad = 0;
1316 uint32_t stat_len = clsz > 64 ? 128 : 64;
1318 csio_wr_reg32(hw, HOSTPAGESIZEPF0(s_hps) | HOSTPAGESIZEPF1(s_hps) |
1319 HOSTPAGESIZEPF2(s_hps) | HOSTPAGESIZEPF3(s_hps) |
1320 HOSTPAGESIZEPF4(s_hps) | HOSTPAGESIZEPF5(s_hps) |
1321 HOSTPAGESIZEPF6(s_hps) | HOSTPAGESIZEPF7(s_hps),
1322 SGE_HOST_PAGE_SIZE);
1324 sge->csio_fl_align = clsz < 32 ? 32 : clsz;
1325 ingpad = ilog2(sge->csio_fl_align) - 5;
1327 csio_set_reg_field(hw, SGE_CONTROL, INGPADBOUNDARY_MASK |
1328 EGRSTATUSPAGESIZE(1),
1329 INGPADBOUNDARY(ingpad) |
1330 EGRSTATUSPAGESIZE(stat_len != 64));
1332 /* FL BUFFER SIZE#0 is Page size i,e already aligned to cache line */
1333 csio_wr_reg32(hw, PAGE_SIZE, SGE_FL_BUFFER_SIZE0);
1335 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2) +
1336 sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),
1337 SGE_FL_BUFFER_SIZE2);
1339 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3) +
1340 sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),
1341 SGE_FL_BUFFER_SIZE3);
1343 csio_wr_reg32(hw, HPZ0(PAGE_SHIFT - 12), ULP_RX_TDDP_PSZ);
1345 /* default value of rx_dma_offset of the NIC driver */
1346 csio_set_reg_field(hw, SGE_CONTROL, PKTSHIFT_MASK,
1347 PKTSHIFT(CSIO_SGE_RX_DMA_OFFSET));
1351 csio_init_intr_coalesce_parms(struct csio_hw *hw)
1353 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
1354 struct csio_sge *sge = &wrm->sge;
1356 csio_sge_thresh_reg = csio_closest_thresh(sge, csio_intr_coalesce_cnt);
1357 if (csio_intr_coalesce_cnt) {
1358 csio_sge_thresh_reg = 0;
1359 csio_sge_timer_reg = X_TIMERREG_RESTART_COUNTER;
1363 csio_sge_timer_reg = csio_closest_timer(sge, csio_intr_coalesce_time);
1367 * csio_wr_get_sge - Get SGE register values.
1370 * Used by non-master functions and by master-functions relying on config file.
1373 csio_wr_get_sge(struct csio_hw *hw)
1375 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
1376 struct csio_sge *sge = &wrm->sge;
1379 u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5;
1380 u32 ingress_rx_threshold;
1382 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL);
1384 ingpad = INGPADBOUNDARY_GET(sge->sge_control);
1387 case X_INGPCIEBOUNDARY_32B:
1388 sge->csio_fl_align = 32; break;
1389 case X_INGPCIEBOUNDARY_64B:
1390 sge->csio_fl_align = 64; break;
1391 case X_INGPCIEBOUNDARY_128B:
1392 sge->csio_fl_align = 128; break;
1393 case X_INGPCIEBOUNDARY_256B:
1394 sge->csio_fl_align = 256; break;
1395 case X_INGPCIEBOUNDARY_512B:
1396 sge->csio_fl_align = 512; break;
1397 case X_INGPCIEBOUNDARY_1024B:
1398 sge->csio_fl_align = 1024; break;
1399 case X_INGPCIEBOUNDARY_2048B:
1400 sge->csio_fl_align = 2048; break;
1401 case X_INGPCIEBOUNDARY_4096B:
1402 sge->csio_fl_align = 4096; break;
1405 for (i = 0; i < CSIO_SGE_FL_SIZE_REGS; i++)
1406 csio_get_flbuf_size(hw, sge, i);
1408 timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1);
1409 timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3);
1410 timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5);
1412 sge->timer_val[0] = (uint16_t)csio_core_ticks_to_us(hw,
1413 TIMERVALUE0_GET(timer_value_0_and_1));
1414 sge->timer_val[1] = (uint16_t)csio_core_ticks_to_us(hw,
1415 TIMERVALUE1_GET(timer_value_0_and_1));
1416 sge->timer_val[2] = (uint16_t)csio_core_ticks_to_us(hw,
1417 TIMERVALUE2_GET(timer_value_2_and_3));
1418 sge->timer_val[3] = (uint16_t)csio_core_ticks_to_us(hw,
1419 TIMERVALUE3_GET(timer_value_2_and_3));
1420 sge->timer_val[4] = (uint16_t)csio_core_ticks_to_us(hw,
1421 TIMERVALUE4_GET(timer_value_4_and_5));
1422 sge->timer_val[5] = (uint16_t)csio_core_ticks_to_us(hw,
1423 TIMERVALUE5_GET(timer_value_4_and_5));
1425 ingress_rx_threshold = csio_rd_reg32(hw, SGE_INGRESS_RX_THRESHOLD);
1426 sge->counter_val[0] = THRESHOLD_0_GET(ingress_rx_threshold);
1427 sge->counter_val[1] = THRESHOLD_1_GET(ingress_rx_threshold);
1428 sge->counter_val[2] = THRESHOLD_2_GET(ingress_rx_threshold);
1429 sge->counter_val[3] = THRESHOLD_3_GET(ingress_rx_threshold);
1431 csio_init_intr_coalesce_parms(hw);
1435 * csio_wr_set_sge - Initialize SGE registers
1438 * Used by Master function to initialize SGE registers in the absence
1442 csio_wr_set_sge(struct csio_hw *hw)
1444 struct csio_wrm *wrm = csio_hw_to_wrm(hw);
1445 struct csio_sge *sge = &wrm->sge;
1449 * Set up our basic SGE mode to deliver CPL messages to our Ingress
1450 * Queue and Packet Date to the Free List.
1452 csio_set_reg_field(hw, SGE_CONTROL, RXPKTCPLMODE(1), RXPKTCPLMODE(1));
1454 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL);
1456 /* sge->csio_fl_align is set up by csio_wr_fixup_host_params(). */
1459 * Set up to drop DOORBELL writes when the DOORBELL FIFO overflows
1460 * and generate an interrupt when this occurs so we can recover.
1462 csio_set_reg_field(hw, SGE_DBFIFO_STATUS,
1463 HP_INT_THRESH(HP_INT_THRESH_MASK) |
1464 LP_INT_THRESH(LP_INT_THRESH_MASK),
1465 HP_INT_THRESH(CSIO_SGE_DBFIFO_INT_THRESH) |
1466 LP_INT_THRESH(CSIO_SGE_DBFIFO_INT_THRESH));
1467 csio_set_reg_field(hw, SGE_DOORBELL_CONTROL, ENABLE_DROP,
1470 /* SGE_FL_BUFFER_SIZE0 is set up by csio_wr_fixup_host_params(). */
1472 CSIO_SET_FLBUF_SIZE(hw, 1, CSIO_SGE_FLBUF_SIZE1);
1473 CSIO_SET_FLBUF_SIZE(hw, 2, CSIO_SGE_FLBUF_SIZE2);
1474 CSIO_SET_FLBUF_SIZE(hw, 3, CSIO_SGE_FLBUF_SIZE3);
1475 CSIO_SET_FLBUF_SIZE(hw, 4, CSIO_SGE_FLBUF_SIZE4);
1476 CSIO_SET_FLBUF_SIZE(hw, 5, CSIO_SGE_FLBUF_SIZE5);
1477 CSIO_SET_FLBUF_SIZE(hw, 6, CSIO_SGE_FLBUF_SIZE6);
1478 CSIO_SET_FLBUF_SIZE(hw, 7, CSIO_SGE_FLBUF_SIZE7);
1479 CSIO_SET_FLBUF_SIZE(hw, 8, CSIO_SGE_FLBUF_SIZE8);
1481 for (i = 0; i < CSIO_SGE_FL_SIZE_REGS; i++)
1482 csio_get_flbuf_size(hw, sge, i);
1484 /* Initialize interrupt coalescing attributes */
1485 sge->timer_val[0] = CSIO_SGE_TIMER_VAL_0;
1486 sge->timer_val[1] = CSIO_SGE_TIMER_VAL_1;
1487 sge->timer_val[2] = CSIO_SGE_TIMER_VAL_2;
1488 sge->timer_val[3] = CSIO_SGE_TIMER_VAL_3;
1489 sge->timer_val[4] = CSIO_SGE_TIMER_VAL_4;
1490 sge->timer_val[5] = CSIO_SGE_TIMER_VAL_5;
1492 sge->counter_val[0] = CSIO_SGE_INT_CNT_VAL_0;
1493 sge->counter_val[1] = CSIO_SGE_INT_CNT_VAL_1;
1494 sge->counter_val[2] = CSIO_SGE_INT_CNT_VAL_2;
1495 sge->counter_val[3] = CSIO_SGE_INT_CNT_VAL_3;
1497 csio_wr_reg32(hw, THRESHOLD_0(sge->counter_val[0]) |
1498 THRESHOLD_1(sge->counter_val[1]) |
1499 THRESHOLD_2(sge->counter_val[2]) |
1500 THRESHOLD_3(sge->counter_val[3]),
1501 SGE_INGRESS_RX_THRESHOLD);
1504 TIMERVALUE0(csio_us_to_core_ticks(hw, sge->timer_val[0])) |
1505 TIMERVALUE1(csio_us_to_core_ticks(hw, sge->timer_val[1])),
1506 SGE_TIMER_VALUE_0_AND_1);
1509 TIMERVALUE2(csio_us_to_core_ticks(hw, sge->timer_val[2])) |
1510 TIMERVALUE3(csio_us_to_core_ticks(hw, sge->timer_val[3])),
1511 SGE_TIMER_VALUE_2_AND_3);
1514 TIMERVALUE4(csio_us_to_core_ticks(hw, sge->timer_val[4])) |
1515 TIMERVALUE5(csio_us_to_core_ticks(hw, sge->timer_val[5])),
1516 SGE_TIMER_VALUE_4_AND_5);
1518 csio_init_intr_coalesce_parms(hw);
1522 csio_wr_sge_init(struct csio_hw *hw)
1526 * - If we plan to use the config file, we need to fixup some
1527 * host specific registers, and read the rest of the SGE
1529 * - If we dont plan to use the config file, we need to initialize
1530 * SGE entirely, including fixing the host specific registers.
1531 * If we arent the master, we are only allowed to read and work off of
1532 * the already initialized SGE values.
1534 * Therefore, before calling this function, we assume that the master-
1535 * ship of the card, and whether to use config file or not, have
1536 * already been decided. In other words, CSIO_HWF_USING_SOFT_PARAMS and
1537 * CSIO_HWF_MASTER should be set/unset.
1539 if (csio_is_hw_master(hw)) {
1540 csio_wr_fixup_host_params(hw);
1542 if (hw->flags & CSIO_HWF_USING_SOFT_PARAMS)
1543 csio_wr_get_sge(hw);
1545 csio_wr_set_sge(hw);
1547 csio_wr_get_sge(hw);
1551 * csio_wrm_init - Initialize Work request module.
1555 * Allocates memory for an array of queue pointers starting at q_arr.
1558 csio_wrm_init(struct csio_wrm *wrm, struct csio_hw *hw)
1563 csio_err(hw, "Num queues is not set\n");
1567 wrm->q_arr = kzalloc(sizeof(struct csio_q *) * wrm->num_q, GFP_KERNEL);
1571 for (i = 0; i < wrm->num_q; i++) {
1572 wrm->q_arr[i] = kzalloc(sizeof(struct csio_q), GFP_KERNEL);
1573 if (!wrm->q_arr[i]) {
1575 kfree(wrm->q_arr[i]);
1590 * csio_wrm_exit - Initialize Work request module.
1594 * Uninitialize WR module. Free q_arr and pointers in it.
1595 * We have the additional job of freeing the DMA memory associated
1599 csio_wrm_exit(struct csio_wrm *wrm, struct csio_hw *hw)
1604 struct csio_dma_buf *buf;
1606 for (i = 0; i < wrm->num_q; i++) {
1609 if (wrm->free_qidx && (i < wrm->free_qidx)) {
1610 if (q->type == CSIO_FREELIST) {
1613 for (j = 0; j < q->credits; j++) {
1614 buf = &q->un.fl.bufs[j];
1617 pci_free_consistent(hw->pdev, buf->len,
1621 kfree(q->un.fl.bufs);
1623 pci_free_consistent(hw->pdev, q->size,
1624 q->vstart, q->pstart);
1629 hw->flags &= ~CSIO_HWF_Q_MEM_ALLOCED;