2 * ipr.h -- driver for IBM Power Linux RAID adapters
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
6 * Copyright (C) 2003, 2004 IBM Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
29 #include <asm/unaligned.h>
30 #include <linux/types.h>
31 #include <linux/completion.h>
32 #include <linux/libata.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/blk-iopoll.h>
36 #include <scsi/scsi.h>
37 #include <scsi/scsi_cmnd.h>
42 #define IPR_DRIVER_VERSION "2.6.0"
43 #define IPR_DRIVER_DATE "(November 16, 2012)"
46 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
47 * ops per device for devices not running tagged command queuing.
48 * This can be adjusted at runtime through sysfs device attributes.
50 #define IPR_MAX_CMD_PER_LUN 6
51 #define IPR_MAX_CMD_PER_ATA_LUN 1
54 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
55 * ops the mid-layer can send to the adapter.
57 #define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds)
59 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
61 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
62 #define PCI_DEVICE_ID_IBM_CROCODILE 0x034A
64 #define IPR_SUBS_DEV_ID_2780 0x0264
65 #define IPR_SUBS_DEV_ID_5702 0x0266
66 #define IPR_SUBS_DEV_ID_5703 0x0278
67 #define IPR_SUBS_DEV_ID_572E 0x028D
68 #define IPR_SUBS_DEV_ID_573E 0x02D3
69 #define IPR_SUBS_DEV_ID_573D 0x02D4
70 #define IPR_SUBS_DEV_ID_571A 0x02C0
71 #define IPR_SUBS_DEV_ID_571B 0x02BE
72 #define IPR_SUBS_DEV_ID_571E 0x02BF
73 #define IPR_SUBS_DEV_ID_571F 0x02D5
74 #define IPR_SUBS_DEV_ID_572A 0x02C1
75 #define IPR_SUBS_DEV_ID_572B 0x02C2
76 #define IPR_SUBS_DEV_ID_572F 0x02C3
77 #define IPR_SUBS_DEV_ID_574E 0x030A
78 #define IPR_SUBS_DEV_ID_575B 0x030D
79 #define IPR_SUBS_DEV_ID_575C 0x0338
80 #define IPR_SUBS_DEV_ID_57B3 0x033A
81 #define IPR_SUBS_DEV_ID_57B7 0x0360
82 #define IPR_SUBS_DEV_ID_57B8 0x02C2
84 #define IPR_SUBS_DEV_ID_57B4 0x033B
85 #define IPR_SUBS_DEV_ID_57B2 0x035F
86 #define IPR_SUBS_DEV_ID_57C0 0x0352
87 #define IPR_SUBS_DEV_ID_57C3 0x0353
88 #define IPR_SUBS_DEV_ID_57C4 0x0354
89 #define IPR_SUBS_DEV_ID_57C6 0x0357
90 #define IPR_SUBS_DEV_ID_57CC 0x035C
92 #define IPR_SUBS_DEV_ID_57B5 0x033C
93 #define IPR_SUBS_DEV_ID_57CE 0x035E
94 #define IPR_SUBS_DEV_ID_57B1 0x0355
96 #define IPR_SUBS_DEV_ID_574D 0x0356
97 #define IPR_SUBS_DEV_ID_57C8 0x035D
99 #define IPR_SUBS_DEV_ID_57D5 0x03FB
100 #define IPR_SUBS_DEV_ID_57D6 0x03FC
101 #define IPR_SUBS_DEV_ID_57D7 0x03FF
102 #define IPR_SUBS_DEV_ID_57D8 0x03FE
103 #define IPR_SUBS_DEV_ID_57D9 0x046D
104 #define IPR_SUBS_DEV_ID_57DA 0x04CA
105 #define IPR_SUBS_DEV_ID_57EB 0x0474
106 #define IPR_SUBS_DEV_ID_57EC 0x0475
107 #define IPR_SUBS_DEV_ID_57ED 0x0499
108 #define IPR_SUBS_DEV_ID_57EE 0x049A
109 #define IPR_SUBS_DEV_ID_57EF 0x049B
110 #define IPR_SUBS_DEV_ID_57F0 0x049C
111 #define IPR_SUBS_DEV_ID_2CCA 0x04C7
112 #define IPR_SUBS_DEV_ID_2CD2 0x04C8
113 #define IPR_SUBS_DEV_ID_2CCD 0x04C9
114 #define IPR_NAME "ipr"
119 #define IPR_RC_JOB_CONTINUE 1
120 #define IPR_RC_JOB_RETURN 2
125 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
126 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
127 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
128 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
129 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
130 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
131 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
132 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
133 #define IPR_IOASC_HW_CMD_FAILED 0x046E0000
134 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
135 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
136 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
137 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
138 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
139 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
140 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
142 #define IPR_FIRST_DRIVER_IOASC 0x10000000
143 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
144 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
146 /* Driver data flags */
147 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
148 #define IPR_USE_PCI_WARM_RESET 0x00000002
150 #define IPR_DEFAULT_MAX_ERROR_DUMP 984
151 #define IPR_NUM_LOG_HCAMS 2
152 #define IPR_NUM_CFG_CHG_HCAMS 2
153 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
155 #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
156 #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
158 #define IPR_MAX_NUM_TARGETS_PER_BUS 256
159 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
160 #define IPR_VSET_BUS 0xff
161 #define IPR_IOA_BUS 0xff
162 #define IPR_IOA_TARGET 0xff
163 #define IPR_IOA_LUN 0xff
164 #define IPR_MAX_NUM_BUSES 16
166 #define IPR_NUM_RESET_RELOAD_RETRIES 3
168 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
169 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
170 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
172 #define IPR_MAX_COMMANDS 100
173 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
174 IPR_NUM_INTERNAL_CMD_BLKS)
176 #define IPR_MAX_PHYSICAL_DEVS 192
177 #define IPR_DEFAULT_SIS64_DEVS 1024
178 #define IPR_MAX_SIS64_DEVS 4096
180 #define IPR_MAX_SGLIST 64
181 #define IPR_IOA_MAX_SECTORS 32767
182 #define IPR_VSET_MAX_SECTORS 512
183 #define IPR_MAX_CDB_LEN 16
184 #define IPR_MAX_HRRQ_RETRIES 3
186 #define IPR_DEFAULT_BUS_WIDTH 16
187 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
188 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
189 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
190 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
192 #define IPR_IOA_RES_HANDLE 0xffffffff
193 #define IPR_INVALID_RES_HANDLE 0
194 #define IPR_IOA_RES_ADDR 0x00ffffff
199 #define IPR_CANCEL_REQUEST 0xC0
200 #define IPR_CANCEL_64BIT_IOARCB 0x01
201 #define IPR_QUERY_RSRC_STATE 0xC2
202 #define IPR_RESET_DEVICE 0xC3
203 #define IPR_RESET_TYPE_SELECT 0x80
204 #define IPR_LUN_RESET 0x40
205 #define IPR_TARGET_RESET 0x20
206 #define IPR_BUS_RESET 0x10
207 #define IPR_ATA_PHY_RESET 0x80
208 #define IPR_ID_HOST_RR_Q 0xC4
209 #define IPR_QUERY_IOA_CONFIG 0xC5
210 #define IPR_CANCEL_ALL_REQUESTS 0xCE
211 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
212 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
213 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
214 #define IPR_SET_SUPPORTED_DEVICES 0xFB
215 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
216 #define IPR_IOA_SHUTDOWN 0xF7
217 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
222 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
223 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
224 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
225 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
226 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
227 #define IPR_CANCEL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
228 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
229 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
230 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
231 #define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ)
232 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
233 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
234 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
235 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
236 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
237 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
238 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
239 #define IPR_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ)
240 #define IPR_PCI_RESET_TIMEOUT (HZ / 2)
241 #define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
242 #define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
243 #define IPR_DUMP_DELAY_SECONDS 4
244 #define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
249 #define IPR_VENDOR_ID_LEN 8
250 #define IPR_PROD_ID_LEN 16
251 #define IPR_SERIAL_NUM_LEN 8
256 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
257 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
258 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
259 #define IPR_GET_FMT2_BAR_SEL(mbx) \
260 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
261 #define IPR_SDT_FMT2_BAR0_SEL 0x0
262 #define IPR_SDT_FMT2_BAR1_SEL 0x1
263 #define IPR_SDT_FMT2_BAR2_SEL 0x2
264 #define IPR_SDT_FMT2_BAR3_SEL 0x3
265 #define IPR_SDT_FMT2_BAR4_SEL 0x4
266 #define IPR_SDT_FMT2_BAR5_SEL 0x5
267 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
268 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
269 #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
270 #define IPR_DOORBELL 0x82800000
271 #define IPR_RUNTIME_RESET 0x40000000
273 #define IPR_IPL_INIT_MIN_STAGE_TIME 5
274 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
275 #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
276 #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
277 #define IPR_IPL_INIT_STAGE_MASK 0xff000000
278 #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
279 #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
281 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
282 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
283 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
284 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
285 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
286 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
287 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
288 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
289 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
290 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
291 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
293 #define IPR_PCII_ERROR_INTERRUPTS \
294 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
295 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
297 #define IPR_PCII_OPER_INTERRUPTS \
298 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
300 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
301 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
302 #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
304 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
305 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
310 #define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
311 #define IPR_FMT3_MAX_IOA_DUMP_SIZE (80 * 1024 * 1024)
312 #define IPR_FMT2_NUM_SDT_ENTRIES 511
313 #define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
314 #define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
315 #define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
320 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
321 #define IPR_MAX_MSIX_VECTORS 0x10
322 #define IPR_MAX_HRRQ_NUM 0x10
323 #define IPR_INIT_HRRQ 0x0
326 * Adapter interface types
329 struct ipr_res_addr {
334 #define IPR_GET_PHYS_LOC(res_addr) \
335 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
336 }__attribute__((packed, aligned (4)));
338 struct ipr_std_inq_vpids {
339 u8 vendor_id[IPR_VENDOR_ID_LEN];
340 u8 product_id[IPR_PROD_ID_LEN];
341 }__attribute__((packed));
344 struct ipr_std_inq_vpids vpids;
345 u8 sn[IPR_SERIAL_NUM_LEN];
346 }__attribute__((packed));
351 }__attribute__((packed));
353 struct ipr_ext_vpd64 {
356 }__attribute__((packed));
358 struct ipr_std_inq_data {
359 u8 peri_qual_dev_type;
360 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
361 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
363 u8 removeable_medium_rsvd;
364 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
366 #define IPR_IS_DASD_DEVICE(std_inq) \
367 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
368 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
370 #define IPR_IS_SES_DEVICE(std_inq) \
371 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
380 struct ipr_std_inq_vpids vpids;
382 u8 ros_rsvd_ram_rsvd[4];
384 u8 serial_num[IPR_SERIAL_NUM_LEN];
385 }__attribute__ ((packed));
387 #define IPR_RES_TYPE_AF_DASD 0x00
388 #define IPR_RES_TYPE_GENERIC_SCSI 0x01
389 #define IPR_RES_TYPE_VOLUME_SET 0x02
390 #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
391 #define IPR_RES_TYPE_GENERIC_ATA 0x04
392 #define IPR_RES_TYPE_ARRAY 0x05
393 #define IPR_RES_TYPE_IOAFP 0xff
395 struct ipr_config_table_entry {
397 #define IPR_PROTO_SATA 0x02
398 #define IPR_PROTO_SATA_ATAPI 0x03
399 #define IPR_PROTO_SAS_STP 0x06
400 #define IPR_PROTO_SAS_STP_ATAPI 0x07
403 #define IPR_IS_IOA_RESOURCE 0x80
406 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
407 #define IPR_QUEUE_FROZEN_MODEL 0
408 #define IPR_QUEUE_NACA_MODEL 1
410 struct ipr_res_addr res_addr;
413 struct ipr_std_inq_data std_inq_data;
414 }__attribute__ ((packed, aligned (4)));
416 struct ipr_config_table_entry64 {
423 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
430 #define IPR_MAX_RES_PATH_LENGTH 48
432 struct ipr_std_inq_data std_inq_data;
436 }__attribute__ ((packed, aligned (8)));
438 struct ipr_config_table_hdr {
441 #define IPR_UCODE_DOWNLOAD_REQ 0x10
443 }__attribute__((packed, aligned (4)));
445 struct ipr_config_table_hdr64 {
450 }__attribute__((packed, aligned (4)));
452 struct ipr_config_table {
453 struct ipr_config_table_hdr hdr;
454 struct ipr_config_table_entry dev[0];
455 }__attribute__((packed, aligned (4)));
457 struct ipr_config_table64 {
458 struct ipr_config_table_hdr64 hdr64;
459 struct ipr_config_table_entry64 dev[0];
460 }__attribute__((packed, aligned (8)));
462 struct ipr_config_table_entry_wrapper {
464 struct ipr_config_table_entry *cfgte;
465 struct ipr_config_table_entry64 *cfgte64;
469 struct ipr_hostrcb_cfg_ch_not {
471 struct ipr_config_table_entry cfgte;
472 struct ipr_config_table_entry64 cfgte64;
475 }__attribute__((packed, aligned (4)));
477 struct ipr_supported_device {
481 struct ipr_std_inq_vpids vpids;
483 }__attribute__((packed, aligned (4)));
485 struct ipr_hrr_queue {
486 struct ipr_ioa_cfg *ioa_cfg;
488 dma_addr_t host_rrq_dma;
489 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
490 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
491 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
492 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
493 #define IPR_ID_HRRQ_SELE_ENABLE 0x02
494 volatile __be32 *hrrq_start;
495 volatile __be32 *hrrq_end;
496 volatile __be32 *hrrq_curr;
498 struct list_head hrrq_free_q;
499 struct list_head hrrq_pending_q;
503 volatile u32 toggle_bit;
507 u8 allow_interrupts:1;
512 struct blk_iopoll iopoll;
515 /* Command packet structure */
517 u8 reserved; /* Reserved by IOA */
520 #define IPR_RQTYPE_SCSICDB 0x00
521 #define IPR_RQTYPE_IOACMD 0x01
522 #define IPR_RQTYPE_HCAM 0x02
523 #define IPR_RQTYPE_ATA_PASSTHRU 0x04
528 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
529 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
530 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
531 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
532 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
535 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
536 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
537 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
538 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
539 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
540 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
541 #define IPR_FLAGS_LO_ACA_TASK 0x08
545 }__attribute__ ((packed, aligned(4)));
547 struct ipr_ioarcb_ata_regs { /* 22 bytes */
549 #define IPR_ATA_FLAG_PACKET_CMD 0x80
550 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
551 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
569 }__attribute__ ((packed, aligned(2)));
571 struct ipr_ioadl_desc {
572 __be32 flags_and_data_len;
573 #define IPR_IOADL_FLAGS_MASK 0xff000000
574 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
575 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
576 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
577 #define IPR_IOADL_FLAGS_READ 0x48000000
578 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
579 #define IPR_IOADL_FLAGS_WRITE 0x68000000
580 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
581 #define IPR_IOADL_FLAGS_LAST 0x01000000
584 }__attribute__((packed, aligned (8)));
586 struct ipr_ioadl64_desc {
590 }__attribute__((packed, aligned (16)));
592 struct ipr_ata64_ioadl {
593 struct ipr_ioarcb_ata_regs regs;
595 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
596 }__attribute__((packed, aligned (16)));
598 struct ipr_ioarcb_add_data {
600 struct ipr_ioarcb_ata_regs regs;
601 struct ipr_ioadl_desc ioadl[5];
602 __be32 add_cmd_parms[10];
604 }__attribute__ ((packed, aligned (4)));
606 struct ipr_ioarcb_sis64_add_addr_ecb {
607 __be64 ioasa_host_pci_addr;
608 __be64 data_ioadl_addr;
610 __be32 ext_control_buf[4];
611 }__attribute__((packed, aligned (8)));
613 /* IOA Request Control Block 128 bytes */
616 __be32 ioarcb_host_pci_addr;
617 __be64 ioarcb_host_pci_addr64;
620 __be32 host_response_handle;
625 __be32 data_transfer_length;
626 __be32 read_data_transfer_length;
627 __be32 write_ioadl_addr;
629 __be32 read_ioadl_addr;
630 __be32 read_ioadl_len;
632 __be32 ioasa_host_pci_addr;
636 struct ipr_cmd_pkt cmd_pkt;
638 __be16 add_cmd_parms_offset;
639 __be16 add_cmd_parms_len;
642 struct ipr_ioarcb_add_data add_data;
643 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
646 }__attribute__((packed, aligned (4)));
648 struct ipr_ioasa_vset {
649 __be32 failing_lba_hi;
650 __be32 failing_lba_lo;
652 }__attribute__((packed, aligned (4)));
654 struct ipr_ioasa_af_dasd {
657 }__attribute__((packed, aligned (4)));
659 struct ipr_ioasa_gpdd {
664 }__attribute__((packed, aligned (4)));
666 struct ipr_ioasa_gata {
668 u8 nsect; /* Interrupt reason */
674 u8 alt_status; /* ATA CTL */
679 }__attribute__((packed, aligned (4)));
681 struct ipr_auto_sense {
682 __be16 auto_sense_len;
684 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
687 struct ipr_ioasa_hdr {
689 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
690 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
691 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
692 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
694 __be16 ret_stat_len; /* Length of the returned IOASA */
696 __be16 avail_stat_len; /* Total Length of status available. */
698 __be32 residual_data_len; /* number of bytes in the host data */
699 /* buffers that were not used by the IOARCB command. */
702 #define IPR_NO_ILID 0
703 #define IPR_DRIVER_ILID 0xffffffff
707 __be32 fd_phys_locator;
709 __be32 fd_res_handle;
711 __be32 ioasc_specific; /* status code specific field */
712 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
713 #define IPR_AUTOSENSE_VALID 0x40000000
714 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000
715 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
716 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
717 #define IPR_FIELD_POINTER_MASK 0x0000ffff
719 }__attribute__((packed, aligned (4)));
722 struct ipr_ioasa_hdr hdr;
725 struct ipr_ioasa_vset vset;
726 struct ipr_ioasa_af_dasd dasd;
727 struct ipr_ioasa_gpdd gpdd;
728 struct ipr_ioasa_gata gata;
731 struct ipr_auto_sense auto_sense;
732 }__attribute__((packed, aligned (4)));
735 struct ipr_ioasa_hdr hdr;
739 struct ipr_ioasa_vset vset;
740 struct ipr_ioasa_af_dasd dasd;
741 struct ipr_ioasa_gpdd gpdd;
742 struct ipr_ioasa_gata gata;
745 struct ipr_auto_sense auto_sense;
746 }__attribute__((packed, aligned (4)));
748 struct ipr_mode_parm_hdr {
751 u8 device_spec_parms;
753 }__attribute__((packed));
755 struct ipr_mode_pages {
756 struct ipr_mode_parm_hdr hdr;
757 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
758 }__attribute__((packed));
760 struct ipr_mode_page_hdr {
762 #define IPR_MODE_PAGE_PS 0x80
763 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
765 }__attribute__ ((packed));
767 struct ipr_dev_bus_entry {
768 struct ipr_res_addr res_addr;
770 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
771 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
772 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
773 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
774 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
775 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
776 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
780 u8 extended_reset_delay;
781 #define IPR_EXTENDED_RESET_DELAY 7
783 __be32 max_xfer_rate;
788 }__attribute__((packed, aligned (4)));
790 struct ipr_mode_page28 {
791 struct ipr_mode_page_hdr hdr;
794 struct ipr_dev_bus_entry bus[0];
795 }__attribute__((packed));
797 struct ipr_mode_page24 {
798 struct ipr_mode_page_hdr hdr;
800 #define IPR_ENABLE_DUAL_IOA_AF 0x80
801 }__attribute__((packed));
804 struct ipr_std_inq_data std_inq_data;
805 u8 ascii_part_num[12];
807 u8 ascii_plant_code[4];
808 }__attribute__((packed));
810 struct ipr_inquiry_page3 {
811 u8 peri_qual_dev_type;
823 }__attribute__((packed));
825 struct ipr_inquiry_cap {
826 u8 peri_qual_dev_type;
834 #define IPR_CAP_DUAL_IOA_RAID 0x80
836 }__attribute__((packed));
838 #define IPR_INQUIRY_PAGE0_ENTRIES 20
839 struct ipr_inquiry_page0 {
840 u8 peri_qual_dev_type;
844 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
845 }__attribute__((packed));
847 struct ipr_hostrcb_device_data_entry {
849 struct ipr_res_addr dev_res_addr;
850 struct ipr_vpd new_vpd;
851 struct ipr_vpd ioa_last_with_dev_vpd;
852 struct ipr_vpd cfc_last_with_dev_vpd;
854 }__attribute__((packed, aligned (4)));
856 struct ipr_hostrcb_device_data_entry_enhanced {
857 struct ipr_ext_vpd vpd;
859 struct ipr_res_addr dev_res_addr;
860 struct ipr_ext_vpd new_vpd;
862 struct ipr_ext_vpd ioa_last_with_dev_vpd;
863 struct ipr_ext_vpd cfc_last_with_dev_vpd;
864 }__attribute__((packed, aligned (4)));
866 struct ipr_hostrcb64_device_data_entry_enhanced {
867 struct ipr_ext_vpd vpd;
870 struct ipr_ext_vpd new_vpd;
872 struct ipr_ext_vpd ioa_last_with_dev_vpd;
873 struct ipr_ext_vpd cfc_last_with_dev_vpd;
874 }__attribute__((packed, aligned (4)));
876 struct ipr_hostrcb_array_data_entry {
878 struct ipr_res_addr expected_dev_res_addr;
879 struct ipr_res_addr dev_res_addr;
880 }__attribute__((packed, aligned (4)));
882 struct ipr_hostrcb64_array_data_entry {
883 struct ipr_ext_vpd vpd;
885 u8 expected_res_path[8];
887 }__attribute__((packed, aligned (4)));
889 struct ipr_hostrcb_array_data_entry_enhanced {
890 struct ipr_ext_vpd vpd;
892 struct ipr_res_addr expected_dev_res_addr;
893 struct ipr_res_addr dev_res_addr;
894 }__attribute__((packed, aligned (4)));
896 struct ipr_hostrcb_type_ff_error {
897 __be32 ioa_data[758];
898 }__attribute__((packed, aligned (4)));
900 struct ipr_hostrcb_type_01_error {
904 __be32 ioa_data[236];
905 }__attribute__((packed, aligned (4)));
907 struct ipr_hostrcb_type_21_error {
910 u8 primary_problem_desc[32];
911 u8 second_problem_desc[32];
912 __be32 sense_data[8];
914 __be32 residual_trans_length;
915 __be32 length_of_error;
916 __be32 ioa_data[236];
917 }__attribute__((packed, aligned (4)));
919 struct ipr_hostrcb_type_02_error {
920 struct ipr_vpd ioa_vpd;
921 struct ipr_vpd cfc_vpd;
922 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
923 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
925 }__attribute__((packed, aligned (4)));
927 struct ipr_hostrcb_type_12_error {
928 struct ipr_ext_vpd ioa_vpd;
929 struct ipr_ext_vpd cfc_vpd;
930 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
931 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
933 }__attribute__((packed, aligned (4)));
935 struct ipr_hostrcb_type_03_error {
936 struct ipr_vpd ioa_vpd;
937 struct ipr_vpd cfc_vpd;
938 __be32 errors_detected;
939 __be32 errors_logged;
941 struct ipr_hostrcb_device_data_entry dev[3];
942 }__attribute__((packed, aligned (4)));
944 struct ipr_hostrcb_type_13_error {
945 struct ipr_ext_vpd ioa_vpd;
946 struct ipr_ext_vpd cfc_vpd;
947 __be32 errors_detected;
948 __be32 errors_logged;
949 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
950 }__attribute__((packed, aligned (4)));
952 struct ipr_hostrcb_type_23_error {
953 struct ipr_ext_vpd ioa_vpd;
954 struct ipr_ext_vpd cfc_vpd;
955 __be32 errors_detected;
956 __be32 errors_logged;
957 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
958 }__attribute__((packed, aligned (4)));
960 struct ipr_hostrcb_type_04_error {
961 struct ipr_vpd ioa_vpd;
962 struct ipr_vpd cfc_vpd;
964 struct ipr_hostrcb_array_data_entry array_member[10];
965 __be32 exposed_mode_adn;
967 struct ipr_vpd incomp_dev_vpd;
969 struct ipr_hostrcb_array_data_entry array_member2[8];
970 struct ipr_res_addr last_func_vset_res_addr;
971 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
972 u8 protection_level[8];
973 }__attribute__((packed, aligned (4)));
975 struct ipr_hostrcb_type_14_error {
976 struct ipr_ext_vpd ioa_vpd;
977 struct ipr_ext_vpd cfc_vpd;
978 __be32 exposed_mode_adn;
980 struct ipr_res_addr last_func_vset_res_addr;
981 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
982 u8 protection_level[8];
984 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
985 }__attribute__((packed, aligned (4)));
987 struct ipr_hostrcb_type_24_error {
988 struct ipr_ext_vpd ioa_vpd;
989 struct ipr_ext_vpd cfc_vpd;
992 #define IPR_INVALID_ARRAY_DEV_NUM 0xff
995 u8 protection_level[8];
996 struct ipr_ext_vpd64 array_vpd;
1000 struct ipr_hostrcb64_array_data_entry array_member[32];
1001 }__attribute__((packed, aligned (4)));
1003 struct ipr_hostrcb_type_07_error {
1004 u8 failure_reason[64];
1007 }__attribute__((packed, aligned (4)));
1009 struct ipr_hostrcb_type_17_error {
1010 u8 failure_reason[64];
1011 struct ipr_ext_vpd vpd;
1013 }__attribute__((packed, aligned (4)));
1015 struct ipr_hostrcb_config_element {
1017 #define IPR_PATH_CFG_TYPE_MASK 0xF0
1018 #define IPR_PATH_CFG_NOT_EXIST 0x00
1019 #define IPR_PATH_CFG_IOA_PORT 0x10
1020 #define IPR_PATH_CFG_EXP_PORT 0x20
1021 #define IPR_PATH_CFG_DEVICE_PORT 0x30
1022 #define IPR_PATH_CFG_DEVICE_LUN 0x40
1024 #define IPR_PATH_CFG_STATUS_MASK 0x0F
1025 #define IPR_PATH_CFG_NO_PROB 0x00
1026 #define IPR_PATH_CFG_DEGRADED 0x01
1027 #define IPR_PATH_CFG_FAILED 0x02
1028 #define IPR_PATH_CFG_SUSPECT 0x03
1029 #define IPR_PATH_NOT_DETECTED 0x04
1030 #define IPR_PATH_INCORRECT_CONN 0x05
1032 u8 cascaded_expander;
1035 #define IPR_PHY_LINK_RATE_MASK 0x0F
1038 }__attribute__((packed, aligned (4)));
1040 struct ipr_hostrcb64_config_element {
1043 #define IPR_DESCRIPTOR_MASK 0xC0
1044 #define IPR_DESCRIPTOR_SIS64 0x00
1054 }__attribute__((packed, aligned (8)));
1056 struct ipr_hostrcb_fabric_desc {
1059 u8 cascaded_expander;
1062 #define IPR_PATH_ACTIVE_MASK 0xC0
1063 #define IPR_PATH_NO_INFO 0x00
1064 #define IPR_PATH_ACTIVE 0x40
1065 #define IPR_PATH_NOT_ACTIVE 0x80
1067 #define IPR_PATH_STATE_MASK 0x0F
1068 #define IPR_PATH_STATE_NO_INFO 0x00
1069 #define IPR_PATH_HEALTHY 0x01
1070 #define IPR_PATH_DEGRADED 0x02
1071 #define IPR_PATH_FAILED 0x03
1074 struct ipr_hostrcb_config_element elem[1];
1075 }__attribute__((packed, aligned (4)));
1077 struct ipr_hostrcb64_fabric_desc {
1088 struct ipr_hostrcb64_config_element elem[1];
1089 }__attribute__((packed, aligned (8)));
1091 #define for_each_hrrq(hrrq, ioa_cfg) \
1092 for (hrrq = (ioa_cfg)->hrrq; \
1093 hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
1095 #define for_each_fabric_cfg(fabric, cfg) \
1096 for (cfg = (fabric)->elem; \
1097 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1100 struct ipr_hostrcb_type_20_error {
1101 u8 failure_reason[64];
1104 struct ipr_hostrcb_fabric_desc desc[1];
1105 }__attribute__((packed, aligned (4)));
1107 struct ipr_hostrcb_type_30_error {
1108 u8 failure_reason[64];
1111 struct ipr_hostrcb64_fabric_desc desc[1];
1112 }__attribute__((packed, aligned (4)));
1114 struct ipr_hostrcb_error {
1116 struct ipr_res_addr fd_res_addr;
1117 __be32 fd_res_handle;
1120 struct ipr_hostrcb_type_ff_error type_ff_error;
1121 struct ipr_hostrcb_type_01_error type_01_error;
1122 struct ipr_hostrcb_type_02_error type_02_error;
1123 struct ipr_hostrcb_type_03_error type_03_error;
1124 struct ipr_hostrcb_type_04_error type_04_error;
1125 struct ipr_hostrcb_type_07_error type_07_error;
1126 struct ipr_hostrcb_type_12_error type_12_error;
1127 struct ipr_hostrcb_type_13_error type_13_error;
1128 struct ipr_hostrcb_type_14_error type_14_error;
1129 struct ipr_hostrcb_type_17_error type_17_error;
1130 struct ipr_hostrcb_type_20_error type_20_error;
1132 }__attribute__((packed, aligned (4)));
1134 struct ipr_hostrcb64_error {
1136 __be32 ioa_fw_level;
1137 __be32 fd_res_handle;
1145 struct ipr_hostrcb_type_ff_error type_ff_error;
1146 struct ipr_hostrcb_type_12_error type_12_error;
1147 struct ipr_hostrcb_type_17_error type_17_error;
1148 struct ipr_hostrcb_type_21_error type_21_error;
1149 struct ipr_hostrcb_type_23_error type_23_error;
1150 struct ipr_hostrcb_type_24_error type_24_error;
1151 struct ipr_hostrcb_type_30_error type_30_error;
1153 }__attribute__((packed, aligned (8)));
1155 struct ipr_hostrcb_raw {
1156 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1157 }__attribute__((packed, aligned (4)));
1161 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1162 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1165 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1166 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1167 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1168 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1169 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1171 u8 notifications_lost;
1172 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1173 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1176 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
1177 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1180 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1181 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1182 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1183 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1184 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1185 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1186 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1187 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1188 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1189 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1190 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1191 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1192 #define IPR_HOST_RCB_OVERLAY_ID_21 0x21
1193 #define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1194 #define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1195 #define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1196 #define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1197 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1201 __be32 time_since_last_ioa_reset;
1206 struct ipr_hostrcb_error error;
1207 struct ipr_hostrcb64_error error64;
1208 struct ipr_hostrcb_cfg_ch_not ccn;
1209 struct ipr_hostrcb_raw raw;
1211 }__attribute__((packed, aligned (4)));
1213 struct ipr_hostrcb {
1214 struct ipr_hcam hcam;
1215 dma_addr_t hostrcb_dma;
1216 struct list_head queue;
1217 struct ipr_ioa_cfg *ioa_cfg;
1218 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1221 /* IPR smart dump table structures */
1222 struct ipr_sdt_entry {
1228 #define IPR_SDT_ENDIAN 0x80
1229 #define IPR_SDT_VALID_ENTRY 0x20
1233 }__attribute__((packed, aligned (4)));
1235 struct ipr_sdt_header {
1238 __be32 num_entries_used;
1240 }__attribute__((packed, aligned (4)));
1243 struct ipr_sdt_header hdr;
1244 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1245 }__attribute__((packed, aligned (4)));
1248 struct ipr_sdt_header hdr;
1249 struct ipr_sdt_entry entry[1];
1250 }__attribute__((packed, aligned (4)));
1255 struct ipr_bus_attributes {
1263 struct ipr_sata_port {
1264 struct ipr_ioa_cfg *ioa_cfg;
1265 struct ata_port *ap;
1266 struct ipr_resource_entry *res;
1267 struct ipr_ioasa_gata ioasa;
1270 struct ipr_resource_entry {
1271 u8 needs_sync_complete:1;
1275 u8 resetting_device:1;
1276 u8 reset_occurred:1;
1278 u32 bus; /* AKA channel */
1279 u32 target; /* AKA id */
1281 #define IPR_ARRAY_VIRTUAL_BUS 0x1
1282 #define IPR_VSET_VIRTUAL_BUS 0x2
1283 #define IPR_IOAFP_VIRTUAL_BUS 0x3
1285 #define IPR_GET_RES_PHYS_LOC(res) \
1286 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1296 struct ipr_std_inq_data std_inq_data;
1301 struct scsi_lun dev_lun;
1304 struct ipr_ioa_cfg *ioa_cfg;
1305 struct scsi_device *sdev;
1306 struct ipr_sata_port *sata_port;
1307 struct list_head queue;
1308 }; /* struct ipr_resource_entry */
1310 struct ipr_resource_hdr {
1315 struct ipr_misc_cbs {
1316 struct ipr_ioa_vpd ioa_vpd;
1317 struct ipr_inquiry_page0 page0_data;
1318 struct ipr_inquiry_page3 page3_data;
1319 struct ipr_inquiry_cap cap;
1320 struct ipr_mode_pages mode_pages;
1321 struct ipr_supported_device supp_dev;
1324 struct ipr_interrupt_offsets {
1325 unsigned long set_interrupt_mask_reg;
1326 unsigned long clr_interrupt_mask_reg;
1327 unsigned long clr_interrupt_mask_reg32;
1328 unsigned long sense_interrupt_mask_reg;
1329 unsigned long sense_interrupt_mask_reg32;
1330 unsigned long clr_interrupt_reg;
1331 unsigned long clr_interrupt_reg32;
1333 unsigned long sense_interrupt_reg;
1334 unsigned long sense_interrupt_reg32;
1335 unsigned long ioarrin_reg;
1336 unsigned long sense_uproc_interrupt_reg;
1337 unsigned long sense_uproc_interrupt_reg32;
1338 unsigned long set_uproc_interrupt_reg;
1339 unsigned long set_uproc_interrupt_reg32;
1340 unsigned long clr_uproc_interrupt_reg;
1341 unsigned long clr_uproc_interrupt_reg32;
1343 unsigned long init_feedback_reg;
1345 unsigned long dump_addr_reg;
1346 unsigned long dump_data_reg;
1348 #define IPR_ENDIAN_SWAP_KEY 0x00080800
1349 unsigned long endian_swap_reg;
1352 struct ipr_interrupts {
1353 void __iomem *set_interrupt_mask_reg;
1354 void __iomem *clr_interrupt_mask_reg;
1355 void __iomem *clr_interrupt_mask_reg32;
1356 void __iomem *sense_interrupt_mask_reg;
1357 void __iomem *sense_interrupt_mask_reg32;
1358 void __iomem *clr_interrupt_reg;
1359 void __iomem *clr_interrupt_reg32;
1361 void __iomem *sense_interrupt_reg;
1362 void __iomem *sense_interrupt_reg32;
1363 void __iomem *ioarrin_reg;
1364 void __iomem *sense_uproc_interrupt_reg;
1365 void __iomem *sense_uproc_interrupt_reg32;
1366 void __iomem *set_uproc_interrupt_reg;
1367 void __iomem *set_uproc_interrupt_reg32;
1368 void __iomem *clr_uproc_interrupt_reg;
1369 void __iomem *clr_uproc_interrupt_reg32;
1371 void __iomem *init_feedback_reg;
1373 void __iomem *dump_addr_reg;
1374 void __iomem *dump_data_reg;
1376 void __iomem *endian_swap_reg;
1379 struct ipr_chip_cfg_t {
1385 struct ipr_interrupt_offsets regs;
1392 #define IPR_USE_LSI 0x00
1393 #define IPR_USE_MSI 0x01
1394 #define IPR_USE_MSIX 0x02
1396 #define IPR_SIS32 0x00
1397 #define IPR_SIS64 0x01
1399 #define IPR_PCI_CFG 0x00
1400 #define IPR_MMIO 0x01
1401 const struct ipr_chip_cfg_t *cfg;
1404 enum ipr_shutdown_type {
1405 IPR_SHUTDOWN_NORMAL = 0x00,
1406 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1407 IPR_SHUTDOWN_ABBREV = 0x80,
1408 IPR_SHUTDOWN_NONE = 0x100,
1409 IPR_SHUTDOWN_QUIESCE = 0x101,
1412 struct ipr_trace_entry {
1418 #define IPR_TRACE_START 0x00
1419 #define IPR_TRACE_FINISH 0xff
1435 struct scatterlist scatterlist[1];
1438 enum ipr_sdt_state {
1447 /* Per-controller data */
1448 struct ipr_ioa_cfg {
1449 char eye_catcher[8];
1450 #define IPR_EYECATCHER "iprcfg"
1452 struct list_head queue;
1454 u8 in_reset_reload:1;
1455 u8 in_ioa_bringdown:1;
1456 u8 ioa_unit_checked:1;
1459 u8 needs_hard_reset:1;
1461 u8 needs_warm_reset:1;
1472 * Bitmaps for SIS64 generated target values
1474 unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1475 unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1476 unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1478 u16 type; /* CCIN of the card */
1481 #define IPR_MAX_LOG_LEVEL 4
1482 #define IPR_DEFAULT_LOG_LEVEL 2
1484 #define IPR_NUM_TRACE_INDEX_BITS 8
1485 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1486 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1487 char trace_start[8];
1488 #define IPR_TRACE_START_LABEL "trace"
1489 struct ipr_trace_entry *trace;
1490 atomic_t trace_index;
1492 char cfg_table_start[8];
1493 #define IPR_CFG_TBL_START "cfg"
1495 struct ipr_config_table *cfg_table;
1496 struct ipr_config_table64 *cfg_table64;
1498 dma_addr_t cfg_table_dma;
1500 u32 max_devs_supported;
1502 char resource_table_label[8];
1503 #define IPR_RES_TABLE_LABEL "res_tbl"
1504 struct ipr_resource_entry *res_entries;
1505 struct list_head free_res_q;
1506 struct list_head used_res_q;
1508 char ipr_hcam_label[8];
1509 #define IPR_HCAM_LABEL "hcams"
1510 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1511 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1512 struct list_head hostrcb_free_q;
1513 struct list_head hostrcb_pending_q;
1515 struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1517 atomic_t hrrq_index;
1518 u16 identify_hrrq_index;
1520 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1522 unsigned int transop_timeout;
1523 const struct ipr_chip_cfg_t *chip_cfg;
1524 const struct ipr_chip_t *ipr_chip;
1526 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1527 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1528 void __iomem *ioa_mailbox;
1529 struct ipr_interrupts regs;
1531 u16 saved_pcix_cmd_reg;
1537 struct Scsi_Host *host;
1538 struct pci_dev *pdev;
1539 struct ipr_sglist *ucode_sglist;
1540 u8 saved_mode_page_len;
1542 struct work_struct work_q;
1543 struct workqueue_struct *reset_work_q;
1545 wait_queue_head_t reset_wait_q;
1546 wait_queue_head_t msi_wait_q;
1547 wait_queue_head_t eeh_wait_q;
1549 struct ipr_dump *dump;
1550 enum ipr_sdt_state sdt_state;
1552 struct ipr_misc_cbs *vpd_cbs;
1553 dma_addr_t vpd_cbs_dma;
1555 struct dma_pool *ipr_cmd_pool;
1557 struct ipr_cmnd *reset_cmd;
1558 int (*reset) (struct ipr_cmnd *);
1560 struct ata_host ata_host;
1561 char ipr_cmd_label[8];
1562 #define IPR_CMD_LABEL "ipr_cmd"
1564 struct ipr_cmnd **ipr_cmnd_list;
1565 dma_addr_t *ipr_cmnd_list_dma;
1568 unsigned int nvectors;
1573 } vectors_info[IPR_MAX_MSIX_VECTORS];
1577 }; /* struct ipr_ioa_cfg */
1580 struct ipr_ioarcb ioarcb;
1582 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1583 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1584 struct ipr_ata64_ioadl ata_ioadl;
1587 struct ipr_ioasa ioasa;
1588 struct ipr_ioasa64 ioasa64;
1590 struct list_head queue;
1591 struct scsi_cmnd *scsi_cmd;
1592 struct ata_queued_cmd *qc;
1593 struct completion completion;
1594 struct timer_list timer;
1595 struct work_struct work;
1596 void (*fast_done) (struct ipr_cmnd *);
1597 void (*done) (struct ipr_cmnd *);
1598 int (*job_step) (struct ipr_cmnd *);
1599 int (*job_step_failed) (struct ipr_cmnd *);
1601 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1602 dma_addr_t sense_buffer_dma;
1603 unsigned short dma_use_sg;
1604 dma_addr_t dma_addr;
1605 struct ipr_cmnd *sibling;
1607 enum ipr_shutdown_type shutdown_type;
1608 struct ipr_hostrcb *hostrcb;
1609 unsigned long time_left;
1610 unsigned long scratch;
1611 struct ipr_resource_entry *res;
1612 struct scsi_device *sdev;
1615 struct completion *eh_comp;
1616 struct ipr_hrr_queue *hrrq;
1617 struct ipr_ioa_cfg *ioa_cfg;
1620 struct ipr_ses_table_entry {
1621 char product_id[17];
1622 char compare_product_id_byte[17];
1623 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1626 struct ipr_dump_header {
1628 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1631 u32 first_entry_offset;
1633 #define IPR_DUMP_STATUS_SUCCESS 0
1634 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1635 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1637 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1639 #define IPR_DUMP_DRIVER_NAME 0x49505232
1640 }__attribute__((packed, aligned (4)));
1642 struct ipr_dump_entry_header {
1644 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1649 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1650 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1652 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1653 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1654 #define IPR_DUMP_TRACE_ID 0x54524143
1655 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1656 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1657 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1658 #define IPR_DUMP_PEND_OPS 0x414F5053
1660 }__attribute__((packed, aligned (4)));
1662 struct ipr_dump_location_entry {
1663 struct ipr_dump_entry_header hdr;
1665 }__attribute__((packed));
1667 struct ipr_dump_trace_entry {
1668 struct ipr_dump_entry_header hdr;
1669 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1670 }__attribute__((packed, aligned (4)));
1672 struct ipr_dump_version_entry {
1673 struct ipr_dump_entry_header hdr;
1674 u8 version[sizeof(IPR_DRIVER_VERSION)];
1677 struct ipr_dump_ioa_type_entry {
1678 struct ipr_dump_entry_header hdr;
1683 struct ipr_driver_dump {
1684 struct ipr_dump_header hdr;
1685 struct ipr_dump_version_entry version_entry;
1686 struct ipr_dump_location_entry location_entry;
1687 struct ipr_dump_ioa_type_entry ioa_type_entry;
1688 struct ipr_dump_trace_entry trace_entry;
1689 }__attribute__((packed));
1691 struct ipr_ioa_dump {
1692 struct ipr_dump_entry_header hdr;
1696 u32 next_page_index;
1699 }__attribute__((packed, aligned (4)));
1703 struct ipr_ioa_cfg *ioa_cfg;
1704 struct ipr_driver_dump driver_dump;
1705 struct ipr_ioa_dump ioa_dump;
1708 struct ipr_error_table_t {
1715 struct ipr_software_inq_lid_info {
1717 __be32 timestamp[3];
1718 }__attribute__((packed, aligned (4)));
1720 struct ipr_ucode_image_header {
1721 __be32 header_length;
1722 __be32 lid_table_offset;
1725 u8 minor_release[2];
1727 char eyecatcher[16];
1729 struct ipr_software_inq_lid_info lid[1];
1730 }__attribute__((packed, aligned (4)));
1735 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1737 #ifdef CONFIG_SCSI_IPR_TRACE
1738 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1739 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1741 #define ipr_create_trace_file(kobj, attr) 0
1742 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1745 #ifdef CONFIG_SCSI_IPR_DUMP
1746 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1747 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1749 #define ipr_create_dump_file(kobj, attr) 0
1750 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1754 * Error logging macros
1756 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1757 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1758 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1760 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1761 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1762 bus, target, lun, ##__VA_ARGS__)
1764 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1765 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1767 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1768 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1769 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1771 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1772 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1774 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1776 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1777 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1779 ipr_err(fmt": %d:%d:%d:%d\n", \
1780 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1781 (res).bus, (res).target, (res).lun); \
1785 #define ipr_hcam_err(hostrcb, fmt, ...) \
1787 if (ipr_is_device(hostrcb)) { \
1788 if ((hostrcb)->ioa_cfg->sis64) { \
1789 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1790 ipr_format_res_path(hostrcb->ioa_cfg, \
1791 hostrcb->hcam.u.error64.fd_res_path, \
1792 hostrcb->rp_buffer, \
1793 sizeof(hostrcb->rp_buffer)), \
1796 ipr_ra_err((hostrcb)->ioa_cfg, \
1797 (hostrcb)->hcam.u.error.fd_res_addr, \
1798 fmt, __VA_ARGS__); \
1801 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1805 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1806 __FILE__, __func__, __LINE__)
1808 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1809 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1811 #define ipr_err_separator \
1812 ipr_err("----------------------------------------------------------\n")
1820 * ipr_is_ioa_resource - Determine if a resource is the IOA
1821 * @res: resource entry struct
1824 * 1 if IOA / 0 if not IOA
1826 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1828 return res->type == IPR_RES_TYPE_IOAFP;
1832 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1833 * @res: resource entry struct
1836 * 1 if AF DASD / 0 if not AF DASD
1838 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1840 return res->type == IPR_RES_TYPE_AF_DASD ||
1841 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1845 * ipr_is_vset_device - Determine if a resource is a VSET
1846 * @res: resource entry struct
1849 * 1 if VSET / 0 if not VSET
1851 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1853 return res->type == IPR_RES_TYPE_VOLUME_SET;
1857 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1858 * @res: resource entry struct
1861 * 1 if GSCSI / 0 if not GSCSI
1863 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1865 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1869 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1870 * @res: resource entry struct
1873 * 1 if SCSI disk / 0 if not SCSI disk
1875 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1877 if (ipr_is_af_dasd_device(res) ||
1878 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1885 * ipr_is_gata - Determine if a resource is a generic ATA resource
1886 * @res: resource entry struct
1889 * 1 if GATA / 0 if not GATA
1891 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1893 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1897 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1898 * @res: resource entry struct
1901 * 1 if NACA queueing model / 0 if not NACA queueing model
1903 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1905 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1911 * ipr_is_device - Determine if the hostrcb structure is related to a device
1912 * @hostrcb: host resource control blocks struct
1915 * 1 if AF / 0 if not AF
1917 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1919 struct ipr_res_addr *res_addr;
1922 if (hostrcb->ioa_cfg->sis64) {
1923 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1924 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1925 res_path[0] == 0x81) && res_path[2] != 0xFF)
1928 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1930 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1931 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1938 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1939 * @sdt_word: SDT address
1942 * 1 if format 2 / 0 if not
1944 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1946 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1949 case IPR_SDT_FMT2_BAR0_SEL:
1950 case IPR_SDT_FMT2_BAR1_SEL:
1951 case IPR_SDT_FMT2_BAR2_SEL:
1952 case IPR_SDT_FMT2_BAR3_SEL:
1953 case IPR_SDT_FMT2_BAR4_SEL:
1954 case IPR_SDT_FMT2_BAR5_SEL:
1955 case IPR_SDT_FMT2_EXP_ROM_SEL:
1963 static inline void writeq(u64 val, void __iomem *addr)
1965 writel(((u32) (val >> 32)), addr);
1966 writel(((u32) (val)), (addr + 4));