drivers/scsi/megaraid/megaraid_sas.h

   1 /*
   2  *  Linux MegaRAID driver for SAS based RAID controllers
   3  *
   4  *  Copyright (c) 2003-2012  LSI Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version 2
   9  *  of the License, or (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19  *
  20  *  FILE: megaraid_sas.h
  21  *
  22  *  Authors: LSI Corporation
  23  *
  24  *  Send feedback to: <megaraidlinux@lsi.com>
  25  *
  26  *  Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
  27  *     ATTN: Linuxraid
  28  */
  29
  30 #ifndef LSI_MEGARAID_SAS_H
  31 #define LSI_MEGARAID_SAS_H
  32
  33 /*
  34  * MegaRAID SAS Driver meta data
  35  */
  36 #define MEGASAS_VERSION                         "06.600.18.00-rc1"
  37 #define MEGASAS_RELDATE                         "May. 15, 2013"
  38 #define MEGASAS_EXT_VERSION                     "Wed. May. 15 17:00:00 PDT 2013"
  39
  40 /*
  41  * Device IDs
  42  */
  43 #define PCI_DEVICE_ID_LSI_SAS1078R              0x0060
  44 #define PCI_DEVICE_ID_LSI_SAS1078DE             0x007C
  45 #define PCI_DEVICE_ID_LSI_VERDE_ZCR             0x0413
  46 #define PCI_DEVICE_ID_LSI_SAS1078GEN2           0x0078
  47 #define PCI_DEVICE_ID_LSI_SAS0079GEN2           0x0079
  48 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY         0x0073
  49 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY         0x0071
  50 #define PCI_DEVICE_ID_LSI_FUSION                0x005b
  51 #define PCI_DEVICE_ID_LSI_INVADER               0x005d
  52 #define PCI_DEVICE_ID_LSI_FURY                  0x005f
  53
  54 /*
  55  * Intel HBA SSDIDs
  56  */
  57 #define MEGARAID_INTEL_RS3DC080_SSDID           0x9360
  58 #define MEGARAID_INTEL_RS3DC040_SSDID           0x9362
  59 #define MEGARAID_INTEL_RS3SC008_SSDID           0x9380
  60 #define MEGARAID_INTEL_RS3MC044_SSDID           0x9381
  61 #define MEGARAID_INTEL_RS3WC080_SSDID           0x9341
  62 #define MEGARAID_INTEL_RS3WC040_SSDID           0x9343
  63
  64 /*
  65  * Intel HBA branding
  66  */
  67 #define MEGARAID_INTEL_RS3DC080_BRANDING        \
  68         "Intel(R) RAID Controller RS3DC080"
  69 #define MEGARAID_INTEL_RS3DC040_BRANDING        \
  70         "Intel(R) RAID Controller RS3DC040"
  71 #define MEGARAID_INTEL_RS3SC008_BRANDING        \
  72         "Intel(R) RAID Controller RS3SC008"
  73 #define MEGARAID_INTEL_RS3MC044_BRANDING        \
  74         "Intel(R) RAID Controller RS3MC044"
  75 #define MEGARAID_INTEL_RS3WC080_BRANDING        \
  76         "Intel(R) RAID Controller RS3WC080"
  77 #define MEGARAID_INTEL_RS3WC040_BRANDING        \
  78         "Intel(R) RAID Controller RS3WC040"
  79
  80 /*
  81  * =====================================
  82  * MegaRAID SAS MFI firmware definitions
  83  * =====================================
  84  */
  85
  86 /*
  87  * MFI stands for  MegaRAID SAS FW Interface. This is just a moniker for
  88  * protocol between the software and firmware. Commands are issued using
  89  * "message frames"
  90  */
  91
  92 /*
  93  * FW posts its state in upper 4 bits of outbound_msg_0 register
  94  */
  95 #define MFI_STATE_MASK                          0xF0000000
  96 #define MFI_STATE_UNDEFINED                     0x00000000
  97 #define MFI_STATE_BB_INIT                       0x10000000
  98 #define MFI_STATE_FW_INIT                       0x40000000
  99 #define MFI_STATE_WAIT_HANDSHAKE                0x60000000
 100 #define MFI_STATE_FW_INIT_2                     0x70000000
 101 #define MFI_STATE_DEVICE_SCAN                   0x80000000
 102 #define MFI_STATE_BOOT_MESSAGE_PENDING          0x90000000
 103 #define MFI_STATE_FLUSH_CACHE                   0xA0000000
 104 #define MFI_STATE_READY                         0xB0000000
 105 #define MFI_STATE_OPERATIONAL                   0xC0000000
 106 #define MFI_STATE_FAULT                         0xF0000000
 107 #define MFI_RESET_REQUIRED                      0x00000001
 108 #define MFI_RESET_ADAPTER                       0x00000002
 109 #define MEGAMFI_FRAME_SIZE                      64
 110
 111 /*
 112  * During FW init, clear pending cmds & reset state using inbound_msg_0
 113  *
 114  * ABORT        : Abort all pending cmds
 115  * READY        : Move from OPERATIONAL to READY state; discard queue info
 116  * MFIMODE      : Discard (possible) low MFA posted in 64-bit mode (??)
 117  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
 118  * HOTPLUG      : Resume from Hotplug
 119  * MFI_STOP_ADP : Send signal to FW to stop processing
 120  */
 121 #define WRITE_SEQUENCE_OFFSET           (0x0000000FC) /* I20 */
 122 #define HOST_DIAGNOSTIC_OFFSET          (0x000000F8)  /* I20 */
 123 #define DIAG_WRITE_ENABLE                       (0x00000080)
 124 #define DIAG_RESET_ADAPTER                      (0x00000004)
 125
 126 #define MFI_ADP_RESET                           0x00000040
 127 #define MFI_INIT_ABORT                          0x00000001
 128 #define MFI_INIT_READY                          0x00000002
 129 #define MFI_INIT_MFIMODE                        0x00000004
 130 #define MFI_INIT_CLEAR_HANDSHAKE                0x00000008
 131 #define MFI_INIT_HOTPLUG                        0x00000010
 132 #define MFI_STOP_ADP                            0x00000020
 133 #define MFI_RESET_FLAGS                         MFI_INIT_READY| \
 134                                                 MFI_INIT_MFIMODE| \
 135                                                 MFI_INIT_ABORT
 136
 137 /*
 138  * MFI frame flags
 139  */
 140 #define MFI_FRAME_POST_IN_REPLY_QUEUE           0x0000
 141 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE      0x0001
 142 #define MFI_FRAME_SGL32                         0x0000
 143 #define MFI_FRAME_SGL64                         0x0002
 144 #define MFI_FRAME_SENSE32                       0x0000
 145 #define MFI_FRAME_SENSE64                       0x0004
 146 #define MFI_FRAME_DIR_NONE                      0x0000
 147 #define MFI_FRAME_DIR_WRITE                     0x0008
 148 #define MFI_FRAME_DIR_READ                      0x0010
 149 #define MFI_FRAME_DIR_BOTH                      0x0018
 150 #define MFI_FRAME_IEEE                          0x0020
 151
 152 /*
 153  * Definition for cmd_status
 154  */
 155 #define MFI_CMD_STATUS_POLL_MODE                0xFF
 156
 157 /*
 158  * MFI command opcodes
 159  */
 160 #define MFI_CMD_INIT                            0x00
 161 #define MFI_CMD_LD_READ                         0x01
 162 #define MFI_CMD_LD_WRITE                        0x02
 163 #define MFI_CMD_LD_SCSI_IO                      0x03
 164 #define MFI_CMD_PD_SCSI_IO                      0x04
 165 #define MFI_CMD_DCMD                            0x05
 166 #define MFI_CMD_ABORT                           0x06
 167 #define MFI_CMD_SMP                             0x07
 168 #define MFI_CMD_STP                             0x08
 169 #define MFI_CMD_INVALID                         0xff
 170
 171 #define MR_DCMD_CTRL_GET_INFO                   0x01010000
 172 #define MR_DCMD_LD_GET_LIST                     0x03010000
 173
 174 #define MR_DCMD_CTRL_CACHE_FLUSH                0x01101000
 175 #define MR_FLUSH_CTRL_CACHE                     0x01
 176 #define MR_FLUSH_DISK_CACHE                     0x02
 177
 178 #define MR_DCMD_CTRL_SHUTDOWN                   0x01050000
 179 #define MR_DCMD_HIBERNATE_SHUTDOWN              0x01060000
 180 #define MR_ENABLE_DRIVE_SPINDOWN                0x01
 181
 182 #define MR_DCMD_CTRL_EVENT_GET_INFO             0x01040100
 183 #define MR_DCMD_CTRL_EVENT_GET                  0x01040300
 184 #define MR_DCMD_CTRL_EVENT_WAIT                 0x01040500
 185 #define MR_DCMD_LD_GET_PROPERTIES               0x03030000
 186
 187 #define MR_DCMD_CLUSTER                         0x08000000
 188 #define MR_DCMD_CLUSTER_RESET_ALL               0x08010100
 189 #define MR_DCMD_CLUSTER_RESET_LD                0x08010200
 190 #define MR_DCMD_PD_LIST_QUERY                   0x02010100
 191
 192 /*
 193  * Global functions
 194  */
 195 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
 196
 197
 198 /*
 199  * MFI command completion codes
 200  */
 201 enum MFI_STAT {
 202         MFI_STAT_OK = 0x00,
 203         MFI_STAT_INVALID_CMD = 0x01,
 204         MFI_STAT_INVALID_DCMD = 0x02,
 205         MFI_STAT_INVALID_PARAMETER = 0x03,
 206         MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
 207         MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
 208         MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
 209         MFI_STAT_APP_IN_USE = 0x07,
 210         MFI_STAT_APP_NOT_INITIALIZED = 0x08,
 211         MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
 212         MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
 213         MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
 214         MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
 215         MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
 216         MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
 217         MFI_STAT_FLASH_BUSY = 0x0f,
 218         MFI_STAT_FLASH_ERROR = 0x10,
 219         MFI_STAT_FLASH_IMAGE_BAD = 0x11,
 220         MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
 221         MFI_STAT_FLASH_NOT_OPEN = 0x13,
 222         MFI_STAT_FLASH_NOT_STARTED = 0x14,
 223         MFI_STAT_FLUSH_FAILED = 0x15,
 224         MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
 225         MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
 226         MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
 227         MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
 228         MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
 229         MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
 230         MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
 231         MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
 232         MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
 233         MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
 234         MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
 235         MFI_STAT_MFC_HW_ERROR = 0x21,
 236         MFI_STAT_NO_HW_PRESENT = 0x22,
 237         MFI_STAT_NOT_FOUND = 0x23,
 238         MFI_STAT_NOT_IN_ENCL = 0x24,
 239         MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
 240         MFI_STAT_PD_TYPE_WRONG = 0x26,
 241         MFI_STAT_PR_DISABLED = 0x27,
 242         MFI_STAT_ROW_INDEX_INVALID = 0x28,
 243         MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
 244         MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
 245         MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
 246         MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
 247         MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
 248         MFI_STAT_SCSI_IO_FAILED = 0x2e,
 249         MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
 250         MFI_STAT_SHUTDOWN_FAILED = 0x30,
 251         MFI_STAT_TIME_NOT_SET = 0x31,
 252         MFI_STAT_WRONG_STATE = 0x32,
 253         MFI_STAT_LD_OFFLINE = 0x33,
 254         MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
 255         MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
 256         MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
 257         MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
 258         MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
 259         MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
 260
 261         MFI_STAT_INVALID_STATUS = 0xFF
 262 };
 263
 264 /*
 265  * Number of mailbox bytes in DCMD message frame
 266  */
 267 #define MFI_MBOX_SIZE                           12
 268
 269 enum MR_EVT_CLASS {
 270
 271         MR_EVT_CLASS_DEBUG = -2,
 272         MR_EVT_CLASS_PROGRESS = -1,
 273         MR_EVT_CLASS_INFO = 0,
 274         MR_EVT_CLASS_WARNING = 1,
 275         MR_EVT_CLASS_CRITICAL = 2,
 276         MR_EVT_CLASS_FATAL = 3,
 277         MR_EVT_CLASS_DEAD = 4,
 278
 279 };
 280
 281 enum MR_EVT_LOCALE {
 282
 283         MR_EVT_LOCALE_LD = 0x0001,
 284         MR_EVT_LOCALE_PD = 0x0002,
 285         MR_EVT_LOCALE_ENCL = 0x0004,
 286         MR_EVT_LOCALE_BBU = 0x0008,
 287         MR_EVT_LOCALE_SAS = 0x0010,
 288         MR_EVT_LOCALE_CTRL = 0x0020,
 289         MR_EVT_LOCALE_CONFIG = 0x0040,
 290         MR_EVT_LOCALE_CLUSTER = 0x0080,
 291         MR_EVT_LOCALE_ALL = 0xffff,
 292
 293 };
 294
 295 enum MR_EVT_ARGS {
 296
 297         MR_EVT_ARGS_NONE,
 298         MR_EVT_ARGS_CDB_SENSE,
 299         MR_EVT_ARGS_LD,
 300         MR_EVT_ARGS_LD_COUNT,
 301         MR_EVT_ARGS_LD_LBA,
 302         MR_EVT_ARGS_LD_OWNER,
 303         MR_EVT_ARGS_LD_LBA_PD_LBA,
 304         MR_EVT_ARGS_LD_PROG,
 305         MR_EVT_ARGS_LD_STATE,
 306         MR_EVT_ARGS_LD_STRIP,
 307         MR_EVT_ARGS_PD,
 308         MR_EVT_ARGS_PD_ERR,
 309         MR_EVT_ARGS_PD_LBA,
 310         MR_EVT_ARGS_PD_LBA_LD,
 311         MR_EVT_ARGS_PD_PROG,
 312         MR_EVT_ARGS_PD_STATE,
 313         MR_EVT_ARGS_PCI,
 314         MR_EVT_ARGS_RATE,
 315         MR_EVT_ARGS_STR,
 316         MR_EVT_ARGS_TIME,
 317         MR_EVT_ARGS_ECC,
 318         MR_EVT_ARGS_LD_PROP,
 319         MR_EVT_ARGS_PD_SPARE,
 320         MR_EVT_ARGS_PD_INDEX,
 321         MR_EVT_ARGS_DIAG_PASS,
 322         MR_EVT_ARGS_DIAG_FAIL,
 323         MR_EVT_ARGS_PD_LBA_LBA,
 324         MR_EVT_ARGS_PORT_PHY,
 325         MR_EVT_ARGS_PD_MISSING,
 326         MR_EVT_ARGS_PD_ADDRESS,
 327         MR_EVT_ARGS_BITMAP,
 328         MR_EVT_ARGS_CONNECTOR,
 329         MR_EVT_ARGS_PD_PD,
 330         MR_EVT_ARGS_PD_FRU,
 331         MR_EVT_ARGS_PD_PATHINFO,
 332         MR_EVT_ARGS_PD_POWER_STATE,
 333         MR_EVT_ARGS_GENERIC,
 334 };
 335
 336 /*
 337  * define constants for device list query options
 338  */
 339 enum MR_PD_QUERY_TYPE {
 340         MR_PD_QUERY_TYPE_ALL                = 0,
 341         MR_PD_QUERY_TYPE_STATE              = 1,
 342         MR_PD_QUERY_TYPE_POWER_STATE        = 2,
 343         MR_PD_QUERY_TYPE_MEDIA_TYPE         = 3,
 344         MR_PD_QUERY_TYPE_SPEED              = 4,
 345         MR_PD_QUERY_TYPE_EXPOSED_TO_HOST    = 5,
 346 };
 347
 348 #define MR_EVT_CFG_CLEARED                              0x0004
 349 #define MR_EVT_LD_STATE_CHANGE                          0x0051
 350 #define MR_EVT_PD_INSERTED                              0x005b
 351 #define MR_EVT_PD_REMOVED                               0x0070
 352 #define MR_EVT_LD_CREATED                               0x008a
 353 #define MR_EVT_LD_DELETED                               0x008b
 354 #define MR_EVT_FOREIGN_CFG_IMPORTED                     0x00db
 355 #define MR_EVT_LD_OFFLINE                               0x00fc
 356 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED             0x0152
 357 #define MAX_LOGICAL_DRIVES                              64
 358
 359 enum MR_PD_STATE {
 360         MR_PD_STATE_UNCONFIGURED_GOOD   = 0x00,
 361         MR_PD_STATE_UNCONFIGURED_BAD    = 0x01,
 362         MR_PD_STATE_HOT_SPARE           = 0x02,
 363         MR_PD_STATE_OFFLINE             = 0x10,
 364         MR_PD_STATE_FAILED              = 0x11,
 365         MR_PD_STATE_REBUILD             = 0x14,
 366         MR_PD_STATE_ONLINE              = 0x18,
 367         MR_PD_STATE_COPYBACK            = 0x20,
 368         MR_PD_STATE_SYSTEM              = 0x40,
 369  };
 370
 371
 372  /*
 373  * defines the physical drive address structure
 374  */
 375 struct MR_PD_ADDRESS {
 376         u16     deviceId;
 377         u16     enclDeviceId;
 378
 379         union {
 380                 struct {
 381                         u8  enclIndex;
 382                         u8  slotNumber;
 383                 } mrPdAddress;
 384                 struct {
 385                         u8  enclPosition;
 386                         u8  enclConnectorIndex;
 387                 } mrEnclAddress;
 388         };
 389         u8      scsiDevType;
 390         union {
 391                 u8      connectedPortBitmap;
 392                 u8      connectedPortNumbers;
 393         };
 394         u64     sasAddr[2];
 395 } __packed;
 396
 397 /*
 398  * defines the physical drive list structure
 399  */
 400 struct MR_PD_LIST {
 401         u32             size;
 402         u32             count;
 403         struct MR_PD_ADDRESS   addr[1];
 404 } __packed;
 405
 406 struct megasas_pd_list {
 407         u16             tid;
 408         u8             driveType;
 409         u8             driveState;
 410 } __packed;
 411
 412  /*
 413  * defines the logical drive reference structure
 414  */
 415 union  MR_LD_REF {
 416         struct {
 417                 u8      targetId;
 418                 u8      reserved;
 419                 u16     seqNum;
 420         };
 421         u32     ref;
 422 } __packed;
 423
 424 /*
 425  * defines the logical drive list structure
 426  */
 427 struct MR_LD_LIST {
 428         u32     ldCount;
 429         u32     reserved;
 430         struct {
 431                 union MR_LD_REF   ref;
 432                 u8          state;
 433                 u8          reserved[3];
 434                 u64         size;
 435         } ldList[MAX_LOGICAL_DRIVES];
 436 } __packed;
 437
 438 /*
 439  * SAS controller properties
 440  */
 441 struct megasas_ctrl_prop {
 442
 443         u16 seq_num;
 444         u16 pred_fail_poll_interval;
 445         u16 intr_throttle_count;
 446         u16 intr_throttle_timeouts;
 447         u8 rebuild_rate;
 448         u8 patrol_read_rate;
 449         u8 bgi_rate;
 450         u8 cc_rate;
 451         u8 recon_rate;
 452         u8 cache_flush_interval;
 453         u8 spinup_drv_count;
 454         u8 spinup_delay;
 455         u8 cluster_enable;
 456         u8 coercion_mode;
 457         u8 alarm_enable;
 458         u8 disable_auto_rebuild;
 459         u8 disable_battery_warn;
 460         u8 ecc_bucket_size;
 461         u16 ecc_bucket_leak_rate;
 462         u8 restore_hotspare_on_insertion;
 463         u8 expose_encl_devices;
 464         u8 maintainPdFailHistory;
 465         u8 disallowHostRequestReordering;
 466         u8 abortCCOnError;
 467         u8 loadBalanceMode;
 468         u8 disableAutoDetectBackplane;
 469
 470         u8 snapVDSpace;
 471
 472         /*
 473         * Add properties that can be controlled by
 474         * a bit in the following structure.
 475         */
 476         struct {
 477                 u32     copyBackDisabled            : 1;
 478                 u32     SMARTerEnabled              : 1;
 479                 u32     prCorrectUnconfiguredAreas  : 1;
 480                 u32     useFdeOnly                  : 1;
 481                 u32     disableNCQ                  : 1;
 482                 u32     SSDSMARTerEnabled           : 1;
 483                 u32     SSDPatrolReadEnabled        : 1;
 484                 u32     enableSpinDownUnconfigured  : 1;
 485                 u32     autoEnhancedImport          : 1;
 486                 u32     enableSecretKeyControl      : 1;
 487                 u32     disableOnlineCtrlReset      : 1;
 488                 u32     allowBootWithPinnedCache    : 1;
 489                 u32     disableSpinDownHS           : 1;
 490                 u32     enableJBOD                  : 1;
 491                 u32     reserved                    :18;
 492         } OnOffProperties;
 493         u8 autoSnapVDSpace;
 494         u8 viewSpace;
 495         u16 spinDownTime;
 496         u8  reserved[24];
 497 } __packed;
 498
 499 /*
 500  * SAS controller information
 501  */
 502 struct megasas_ctrl_info {
 503
 504         /*
 505          * PCI device information
 506          */
 507         struct {
 508
 509                 u16 vendor_id;
 510                 u16 device_id;
 511                 u16 sub_vendor_id;
 512                 u16 sub_device_id;
 513                 u8 reserved[24];
 514
 515         } __attribute__ ((packed)) pci;
 516
 517         /*
 518          * Host interface information
 519          */
 520         struct {
 521
 522                 u8 PCIX:1;
 523                 u8 PCIE:1;
 524                 u8 iSCSI:1;
 525                 u8 SAS_3G:1;
 526                 u8 reserved_0:4;
 527                 u8 reserved_1[6];
 528                 u8 port_count;
 529                 u64 port_addr[8];
 530
 531         } __attribute__ ((packed)) host_interface;
 532
 533         /*
 534          * Device (backend) interface information
 535          */
 536         struct {
 537
 538                 u8 SPI:1;
 539                 u8 SAS_3G:1;
 540                 u8 SATA_1_5G:1;
 541                 u8 SATA_3G:1;
 542                 u8 reserved_0:4;
 543                 u8 reserved_1[6];
 544                 u8 port_count;
 545                 u64 port_addr[8];
 546
 547         } __attribute__ ((packed)) device_interface;
 548
 549         /*
 550          * List of components residing in flash. All str are null terminated
 551          */
 552         u32 image_check_word;
 553         u32 image_component_count;
 554
 555         struct {
 556
 557                 char name[8];
 558                 char version[32];
 559                 char build_date[16];
 560                 char built_time[16];
 561
 562         } __attribute__ ((packed)) image_component[8];
 563
 564         /*
 565          * List of flash components that have been flashed on the card, but
 566          * are not in use, pending reset of the adapter. This list will be
 567          * empty if a flash operation has not occurred. All stings are null
 568          * terminated
 569          */
 570         u32 pending_image_component_count;
 571
 572         struct {
 573
 574                 char name[8];
 575                 char version[32];
 576                 char build_date[16];
 577                 char build_time[16];
 578
 579         } __attribute__ ((packed)) pending_image_component[8];
 580
 581         u8 max_arms;
 582         u8 max_spans;
 583         u8 max_arrays;
 584         u8 max_lds;
 585
 586         char product_name[80];
 587         char serial_no[32];
 588
 589         /*
 590          * Other physical/controller/operation information. Indicates the
 591          * presence of the hardware
 592          */
 593         struct {
 594
 595                 u32 bbu:1;
 596                 u32 alarm:1;
 597                 u32 nvram:1;
 598                 u32 uart:1;
 599                 u32 reserved:28;
 600
 601         } __attribute__ ((packed)) hw_present;
 602
 603         u32 current_fw_time;
 604
 605         /*
 606          * Maximum data transfer sizes
 607          */
 608         u16 max_concurrent_cmds;
 609         u16 max_sge_count;
 610         u32 max_request_size;
 611
 612         /*
 613          * Logical and physical device counts
 614          */
 615         u16 ld_present_count;
 616         u16 ld_degraded_count;
 617         u16 ld_offline_count;
 618
 619         u16 pd_present_count;
 620         u16 pd_disk_present_count;
 621         u16 pd_disk_pred_failure_count;
 622         u16 pd_disk_failed_count;
 623
 624         /*
 625          * Memory size information
 626          */
 627         u16 nvram_size;
 628         u16 memory_size;
 629         u16 flash_size;
 630
 631         /*
 632          * Error counters
 633          */
 634         u16 mem_correctable_error_count;
 635         u16 mem_uncorrectable_error_count;
 636
 637         /*
 638          * Cluster information
 639          */
 640         u8 cluster_permitted;
 641         u8 cluster_active;
 642
 643         /*
 644          * Additional max data transfer sizes
 645          */
 646         u16 max_strips_per_io;
 647
 648         /*
 649          * Controller capabilities structures
 650          */
 651         struct {
 652
 653                 u32 raid_level_0:1;
 654                 u32 raid_level_1:1;
 655                 u32 raid_level_5:1;
 656                 u32 raid_level_1E:1;
 657                 u32 raid_level_6:1;
 658                 u32 reserved:27;
 659
 660         } __attribute__ ((packed)) raid_levels;
 661
 662         struct {
 663
 664                 u32 rbld_rate:1;
 665                 u32 cc_rate:1;
 666                 u32 bgi_rate:1;
 667                 u32 recon_rate:1;
 668                 u32 patrol_rate:1;
 669                 u32 alarm_control:1;
 670                 u32 cluster_supported:1;
 671                 u32 bbu:1;
 672                 u32 spanning_allowed:1;
 673                 u32 dedicated_hotspares:1;
 674                 u32 revertible_hotspares:1;
 675                 u32 foreign_config_import:1;
 676                 u32 self_diagnostic:1;
 677                 u32 mixed_redundancy_arr:1;
 678                 u32 global_hot_spares:1;
 679                 u32 reserved:17;
 680
 681         } __attribute__ ((packed)) adapter_operations;
 682
 683         struct {
 684
 685                 u32 read_policy:1;
 686                 u32 write_policy:1;
 687                 u32 io_policy:1;
 688                 u32 access_policy:1;
 689                 u32 disk_cache_policy:1;
 690                 u32 reserved:27;
 691
 692         } __attribute__ ((packed)) ld_operations;
 693
 694         struct {
 695
 696                 u8 min;
 697                 u8 max;
 698                 u8 reserved[2];
 699
 700         } __attribute__ ((packed)) stripe_sz_ops;
 701
 702         struct {
 703
 704                 u32 force_online:1;
 705                 u32 force_offline:1;
 706                 u32 force_rebuild:1;
 707                 u32 reserved:29;
 708
 709         } __attribute__ ((packed)) pd_operations;
 710
 711         struct {
 712
 713                 u32 ctrl_supports_sas:1;
 714                 u32 ctrl_supports_sata:1;
 715                 u32 allow_mix_in_encl:1;
 716                 u32 allow_mix_in_ld:1;
 717                 u32 allow_sata_in_cluster:1;
 718                 u32 reserved:27;
 719
 720         } __attribute__ ((packed)) pd_mix_support;
 721
 722         /*
 723          * Define ECC single-bit-error bucket information
 724          */
 725         u8 ecc_bucket_count;
 726         u8 reserved_2[11];
 727
 728         /*
 729          * Include the controller properties (changeable items)
 730          */
 731         struct megasas_ctrl_prop properties;
 732
 733         /*
 734          * Define FW pkg version (set in envt v'bles on OEM basis)
 735          */
 736         char package_version[0x60];
 737
 738
 739         /*
 740         * If adapterOperations.supportMoreThan8Phys is set,
 741         * and deviceInterface.portCount is greater than 8,
 742         * SAS Addrs for first 8 ports shall be populated in
 743         * deviceInterface.portAddr, and the rest shall be
 744         * populated in deviceInterfacePortAddr2.
 745         */
 746         u64         deviceInterfacePortAddr2[8]; /*6a0h */
 747         u8          reserved3[128];              /*6e0h */
 748
 749         struct {                                /*760h */
 750                 u16 minPdRaidLevel_0:4;
 751                 u16 maxPdRaidLevel_0:12;
 752
 753                 u16 minPdRaidLevel_1:4;
 754                 u16 maxPdRaidLevel_1:12;
 755
 756                 u16 minPdRaidLevel_5:4;
 757                 u16 maxPdRaidLevel_5:12;
 758
 759                 u16 minPdRaidLevel_1E:4;
 760                 u16 maxPdRaidLevel_1E:12;
 761
 762                 u16 minPdRaidLevel_6:4;
 763                 u16 maxPdRaidLevel_6:12;
 764
 765                 u16 minPdRaidLevel_10:4;
 766                 u16 maxPdRaidLevel_10:12;
 767
 768                 u16 minPdRaidLevel_50:4;
 769                 u16 maxPdRaidLevel_50:12;
 770
 771                 u16 minPdRaidLevel_60:4;
 772                 u16 maxPdRaidLevel_60:12;
 773
 774                 u16 minPdRaidLevel_1E_RLQ0:4;
 775                 u16 maxPdRaidLevel_1E_RLQ0:12;
 776
 777                 u16 minPdRaidLevel_1E0_RLQ0:4;
 778                 u16 maxPdRaidLevel_1E0_RLQ0:12;
 779
 780                 u16 reserved[6];
 781         } pdsForRaidLevels;
 782
 783         u16 maxPds;                             /*780h */
 784         u16 maxDedHSPs;                         /*782h */
 785         u16 maxGlobalHSPs;                      /*784h */
 786         u16 ddfSize;                            /*786h */
 787         u8  maxLdsPerArray;                     /*788h */
 788         u8  partitionsInDDF;                    /*789h */
 789         u8  lockKeyBinding;                     /*78ah */
 790         u8  maxPITsPerLd;                       /*78bh */
 791         u8  maxViewsPerLd;                      /*78ch */
 792         u8  maxTargetId;                        /*78dh */
 793         u16 maxBvlVdSize;                       /*78eh */
 794
 795         u16 maxConfigurableSSCSize;             /*790h */
 796         u16 currentSSCsize;                     /*792h */
 797
 798         char    expanderFwVersion[12];          /*794h */
 799
 800         u16 PFKTrialTimeRemaining;              /*7A0h */
 801
 802         u16 cacheMemorySize;                    /*7A2h */
 803
 804         struct {                                /*7A4h */
 805                 u32     supportPIcontroller:1;
 806                 u32     supportLdPIType1:1;
 807                 u32     supportLdPIType2:1;
 808                 u32     supportLdPIType3:1;
 809                 u32     supportLdBBMInfo:1;
 810                 u32     supportShieldState:1;
 811                 u32     blockSSDWriteCacheChange:1;
 812                 u32     supportSuspendResumeBGops:1;
 813                 u32     supportEmergencySpares:1;
 814                 u32     supportSetLinkSpeed:1;
 815                 u32     supportBootTimePFKChange:1;
 816                 u32     supportJBOD:1;
 817                 u32     disableOnlinePFKChange:1;
 818                 u32     supportPerfTuning:1;
 819                 u32     supportSSDPatrolRead:1;
 820                 u32     realTimeScheduler:1;
 821
 822                 u32     supportResetNow:1;
 823                 u32     supportEmulatedDrives:1;
 824                 u32     headlessMode:1;
 825                 u32     dedicatedHotSparesLimited:1;
 826
 827
 828                 u32     supportUnevenSpans:1;
 829                 u32     reserved:11;
 830         } adapterOperations2;
 831
 832         u8  driverVersion[32];                  /*7A8h */
 833         u8  maxDAPdCountSpinup60;               /*7C8h */
 834         u8  temperatureROC;                     /*7C9h */
 835         u8  temperatureCtrl;                    /*7CAh */
 836         u8  reserved4;                          /*7CBh */
 837         u16 maxConfigurablePds;                 /*7CCh */
 838
 839
 840         u8  reserved5[2];                       /*0x7CDh */
 841
 842         /*
 843         * HA cluster information
 844         */
 845         struct {
 846                 u32     peerIsPresent:1;
 847                 u32     peerIsIncompatible:1;
 848                 u32     hwIncompatible:1;
 849                 u32     fwVersionMismatch:1;
 850                 u32     ctrlPropIncompatible:1;
 851                 u32     premiumFeatureMismatch:1;
 852                 u32     reserved:26;
 853         } cluster;
 854
 855         char clusterId[16];                     /*7D4h */
 856
 857         u8          pad[0x800-0x7E4];           /*7E4 */
 858 } __packed;
 859
 860 /*
 861  * ===============================
 862  * MegaRAID SAS driver definitions
 863  * ===============================
 864  */
 865 #define MEGASAS_MAX_PD_CHANNELS                 2
 866 #define MEGASAS_MAX_LD_CHANNELS                 2
 867 #define MEGASAS_MAX_CHANNELS                    (MEGASAS_MAX_PD_CHANNELS + \
 868                                                 MEGASAS_MAX_LD_CHANNELS)
 869 #define MEGASAS_MAX_DEV_PER_CHANNEL             128
 870 #define MEGASAS_DEFAULT_INIT_ID                 -1
 871 #define MEGASAS_MAX_LUN                         8
 872 #define MEGASAS_MAX_LD                          64
 873 #define MEGASAS_DEFAULT_CMD_PER_LUN             256
 874 #define MEGASAS_MAX_PD                          (MEGASAS_MAX_PD_CHANNELS * \
 875                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
 876 #define MEGASAS_MAX_LD_IDS                      (MEGASAS_MAX_LD_CHANNELS * \
 877                                                 MEGASAS_MAX_DEV_PER_CHANNEL)
 878
 879 #define MEGASAS_MAX_SECTORS                    (2*1024)
 880 #define MEGASAS_MAX_SECTORS_IEEE                (2*128)
 881 #define MEGASAS_DBG_LVL                         1
 882
 883 #define MEGASAS_FW_BUSY                         1
 884
 885 /* Frame Type */
 886 #define IO_FRAME                                0
 887 #define PTHRU_FRAME                             1
 888
 889 /*
 890  * When SCSI mid-layer calls driver's reset routine, driver waits for
 891  * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
 892  * that the driver cannot _actually_ abort or reset pending commands. While
 893  * it is waiting for the commands to complete, it prints a diagnostic message
 894  * every MEGASAS_RESET_NOTICE_INTERVAL seconds
 895  */
 896 #define MEGASAS_RESET_WAIT_TIME                 180
 897 #define MEGASAS_INTERNAL_CMD_WAIT_TIME          180
 898 #define MEGASAS_RESET_NOTICE_INTERVAL           5
 899 #define MEGASAS_IOCTL_CMD                       0
 900 #define MEGASAS_DEFAULT_CMD_TIMEOUT             90
 901 #define MEGASAS_THROTTLE_QUEUE_DEPTH            16
 902
 903 /*
 904  * FW reports the maximum of number of commands that it can accept (maximum
 905  * commands that can be outstanding) at any time. The driver must report a
 906  * lower number to the mid layer because it can issue a few internal commands
 907  * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
 908  * is shown below
 909  */
 910 #define MEGASAS_INT_CMDS                        32
 911 #define MEGASAS_SKINNY_INT_CMDS                 5
 912
 913 #define MEGASAS_MAX_MSIX_QUEUES                 128
 914 /*
 915  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
 916  * SGLs based on the size of dma_addr_t
 917  */
 918 #define IS_DMA64                                (sizeof(dma_addr_t) == 8)
 919
 920 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT                0x00000001
 921
 922 #define MFI_INTR_FLAG_REPLY_MESSAGE                     0x00000001
 923 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE             0x00000002
 924 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT       0x00000004
 925
 926 #define MFI_OB_INTR_STATUS_MASK                 0x00000002
 927 #define MFI_POLL_TIMEOUT_SECS                   60
 928
 929 #define MFI_REPLY_1078_MESSAGE_INTERRUPT        0x80000000
 930 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT        0x00000001
 931 #define MFI_GEN2_ENABLE_INTERRUPT_MASK          (0x00000001 | 0x00000004)
 932 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT      0x40000000
 933 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK        (0x00000001)
 934
 935 #define MFI_1068_PCSR_OFFSET                    0x84
 936 #define MFI_1068_FW_HANDSHAKE_OFFSET            0x64
 937 #define MFI_1068_FW_READY                       0xDDDD0000
 938
 939 #define MR_MAX_REPLY_QUEUES_OFFSET              0X0000001F
 940 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET          0X003FC000
 941 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT    14
 942 #define MR_MAX_MSIX_REG_ARRAY                   16
 943 /*
 944 * register set for both 1068 and 1078 controllers
 945 * structure extended for 1078 registers
 946 */
 947
 948 struct megasas_register_set {
 949         u32     doorbell;                       /*0000h*/
 950         u32     fusion_seq_offset;              /*0004h*/
 951         u32     fusion_host_diag;               /*0008h*/
 952         u32     reserved_01;                    /*000Ch*/
 953
 954         u32     inbound_msg_0;                  /*0010h*/
 955         u32     inbound_msg_1;                  /*0014h*/
 956         u32     outbound_msg_0;                 /*0018h*/
 957         u32     outbound_msg_1;                 /*001Ch*/
 958
 959         u32     inbound_doorbell;               /*0020h*/
 960         u32     inbound_intr_status;            /*0024h*/
 961         u32     inbound_intr_mask;              /*0028h*/
 962
 963         u32     outbound_doorbell;              /*002Ch*/
 964         u32     outbound_intr_status;           /*0030h*/
 965         u32     outbound_intr_mask;             /*0034h*/
 966
 967         u32     reserved_1[2];                  /*0038h*/
 968
 969         u32     inbound_queue_port;             /*0040h*/
 970         u32     outbound_queue_port;            /*0044h*/
 971
 972         u32     reserved_2[9];                  /*0048h*/
 973         u32     reply_post_host_index;          /*006Ch*/
 974         u32     reserved_2_2[12];               /*0070h*/
 975
 976         u32     outbound_doorbell_clear;        /*00A0h*/
 977
 978         u32     reserved_3[3];                  /*00A4h*/
 979
 980         u32     outbound_scratch_pad ;          /*00B0h*/
 981         u32     outbound_scratch_pad_2;         /*00B4h*/
 982
 983         u32     reserved_4[2];                  /*00B8h*/
 984
 985         u32     inbound_low_queue_port ;        /*00C0h*/
 986
 987         u32     inbound_high_queue_port ;       /*00C4h*/
 988
 989         u32     reserved_5;                     /*00C8h*/
 990         u32     res_6[11];                      /*CCh*/
 991         u32     host_diag;
 992         u32     seq_offset;
 993         u32     index_registers[807];           /*00CCh*/
 994 } __attribute__ ((packed));
 995
 996 struct megasas_sge32 {
 997
 998         u32 phys_addr;
 999         u32 length;
1000
1001 } __attribute__ ((packed));
1002
1003 struct megasas_sge64 {
1004
1005         u64 phys_addr;
1006         u32 length;
1007
1008 } __attribute__ ((packed));
1009
1010 struct megasas_sge_skinny {
1011         u64 phys_addr;
1012         u32 length;
1013         u32 flag;
1014 } __packed;
1015
1016 union megasas_sgl {
1017
1018         struct megasas_sge32 sge32[1];
1019         struct megasas_sge64 sge64[1];
1020         struct megasas_sge_skinny sge_skinny[1];
1021
1022 } __attribute__ ((packed));
1023
1024 struct megasas_header {
1025
1026         u8 cmd;                 /*00h */
1027         u8 sense_len;           /*01h */
1028         u8 cmd_status;          /*02h */
1029         u8 scsi_status;         /*03h */
1030
1031         u8 target_id;           /*04h */
1032         u8 lun;                 /*05h */
1033         u8 cdb_len;             /*06h */
1034         u8 sge_count;           /*07h */
1035
1036         u32 context;            /*08h */
1037         u32 pad_0;              /*0Ch */
1038
1039         u16 flags;              /*10h */
1040         u16 timeout;            /*12h */
1041         u32 data_xferlen;       /*14h */
1042
1043 } __attribute__ ((packed));
1044
1045 union megasas_sgl_frame {
1046
1047         struct megasas_sge32 sge32[8];
1048         struct megasas_sge64 sge64[5];
1049
1050 } __attribute__ ((packed));
1051
1052 typedef union _MFI_CAPABILITIES {
1053         struct {
1054                 u32     support_fp_remote_lun:1;
1055                 u32     support_additional_msix:1;
1056                 u32     reserved:30;
1057         } mfi_capabilities;
1058         u32     reg;
1059 } MFI_CAPABILITIES;
1060
1061 struct megasas_init_frame {
1062
1063         u8 cmd;                 /*00h */
1064         u8 reserved_0;          /*01h */
1065         u8 cmd_status;          /*02h */
1066
1067         u8 reserved_1;          /*03h */
1068         MFI_CAPABILITIES driver_operations; /*04h*/
1069
1070         u32 context;            /*08h */
1071         u32 pad_0;              /*0Ch */
1072
1073         u16 flags;              /*10h */
1074         u16 reserved_3;         /*12h */
1075         u32 data_xfer_len;      /*14h */
1076
1077         u32 queue_info_new_phys_addr_lo;        /*18h */
1078         u32 queue_info_new_phys_addr_hi;        /*1Ch */
1079         u32 queue_info_old_phys_addr_lo;        /*20h */
1080         u32 queue_info_old_phys_addr_hi;        /*24h */
1081
1082         u32 reserved_4[6];      /*28h */
1083
1084 } __attribute__ ((packed));
1085
1086 struct megasas_init_queue_info {
1087
1088         u32 init_flags;         /*00h */
1089         u32 reply_queue_entries;        /*04h */
1090
1091         u32 reply_queue_start_phys_addr_lo;     /*08h */
1092         u32 reply_queue_start_phys_addr_hi;     /*0Ch */
1093         u32 producer_index_phys_addr_lo;        /*10h */
1094         u32 producer_index_phys_addr_hi;        /*14h */
1095         u32 consumer_index_phys_addr_lo;        /*18h */
1096         u32 consumer_index_phys_addr_hi;        /*1Ch */
1097
1098 } __attribute__ ((packed));
1099
1100 struct megasas_io_frame {
1101
1102         u8 cmd;                 /*00h */
1103         u8 sense_len;           /*01h */
1104         u8 cmd_status;          /*02h */
1105         u8 scsi_status;         /*03h */
1106
1107         u8 target_id;           /*04h */
1108         u8 access_byte;         /*05h */
1109         u8 reserved_0;          /*06h */
1110         u8 sge_count;           /*07h */
1111
1112         u32 context;            /*08h */
1113         u32 pad_0;              /*0Ch */
1114
1115         u16 flags;              /*10h */
1116         u16 timeout;            /*12h */
1117         u32 lba_count;          /*14h */
1118
1119         u32 sense_buf_phys_addr_lo;     /*18h */
1120         u32 sense_buf_phys_addr_hi;     /*1Ch */
1121
1122         u32 start_lba_lo;       /*20h */
1123         u32 start_lba_hi;       /*24h */
1124
1125         union megasas_sgl sgl;  /*28h */
1126
1127 } __attribute__ ((packed));
1128
1129 struct megasas_pthru_frame {
1130
1131         u8 cmd;                 /*00h */
1132         u8 sense_len;           /*01h */
1133         u8 cmd_status;          /*02h */
1134         u8 scsi_status;         /*03h */
1135
1136         u8 target_id;           /*04h */
1137         u8 lun;                 /*05h */
1138         u8 cdb_len;             /*06h */
1139         u8 sge_count;           /*07h */
1140
1141         u32 context;            /*08h */
1142         u32 pad_0;              /*0Ch */
1143
1144         u16 flags;              /*10h */
1145         u16 timeout;            /*12h */
1146         u32 data_xfer_len;      /*14h */
1147
1148         u32 sense_buf_phys_addr_lo;     /*18h */
1149         u32 sense_buf_phys_addr_hi;     /*1Ch */
1150
1151         u8 cdb[16];             /*20h */
1152         union megasas_sgl sgl;  /*30h */
1153
1154 } __attribute__ ((packed));
1155
1156 struct megasas_dcmd_frame {
1157
1158         u8 cmd;                 /*00h */
1159         u8 reserved_0;          /*01h */
1160         u8 cmd_status;          /*02h */
1161         u8 reserved_1[4];       /*03h */
1162         u8 sge_count;           /*07h */
1163
1164         u32 context;            /*08h */
1165         u32 pad_0;              /*0Ch */
1166
1167         u16 flags;              /*10h */
1168         u16 timeout;            /*12h */
1169
1170         u32 data_xfer_len;      /*14h */
1171         u32 opcode;             /*18h */
1172
1173         union {                 /*1Ch */
1174                 u8 b[12];
1175                 u16 s[6];
1176                 u32 w[3];
1177         } mbox;
1178
1179         union megasas_sgl sgl;  /*28h */
1180
1181 } __attribute__ ((packed));
1182
1183 struct megasas_abort_frame {
1184
1185         u8 cmd;                 /*00h */
1186         u8 reserved_0;          /*01h */
1187         u8 cmd_status;          /*02h */
1188
1189         u8 reserved_1;          /*03h */
1190         u32 reserved_2;         /*04h */
1191
1192         u32 context;            /*08h */
1193         u32 pad_0;              /*0Ch */
1194
1195         u16 flags;              /*10h */
1196         u16 reserved_3;         /*12h */
1197         u32 reserved_4;         /*14h */
1198
1199         u32 abort_context;      /*18h */
1200         u32 pad_1;              /*1Ch */
1201
1202         u32 abort_mfi_phys_addr_lo;     /*20h */
1203         u32 abort_mfi_phys_addr_hi;     /*24h */
1204
1205         u32 reserved_5[6];      /*28h */
1206
1207 } __attribute__ ((packed));
1208
1209 struct megasas_smp_frame {
1210
1211         u8 cmd;                 /*00h */
1212         u8 reserved_1;          /*01h */
1213         u8 cmd_status;          /*02h */
1214         u8 connection_status;   /*03h */
1215
1216         u8 reserved_2[3];       /*04h */
1217         u8 sge_count;           /*07h */
1218
1219         u32 context;            /*08h */
1220         u32 pad_0;              /*0Ch */
1221
1222         u16 flags;              /*10h */
1223         u16 timeout;            /*12h */
1224
1225         u32 data_xfer_len;      /*14h */
1226         u64 sas_addr;           /*18h */
1227
1228         union {
1229                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: req */
1230                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: req */
1231         } sgl;
1232
1233 } __attribute__ ((packed));
1234
1235 struct megasas_stp_frame {
1236
1237         u8 cmd;                 /*00h */
1238         u8 reserved_1;          /*01h */
1239         u8 cmd_status;          /*02h */
1240         u8 reserved_2;          /*03h */
1241
1242         u8 target_id;           /*04h */
1243         u8 reserved_3[2];       /*05h */
1244         u8 sge_count;           /*07h */
1245
1246         u32 context;            /*08h */
1247         u32 pad_0;              /*0Ch */
1248
1249         u16 flags;              /*10h */
1250         u16 timeout;            /*12h */
1251
1252         u32 data_xfer_len;      /*14h */
1253
1254         u16 fis[10];            /*18h */
1255         u32 stp_flags;
1256
1257         union {
1258                 struct megasas_sge32 sge32[2];  /* [0]: resp [1]: data */
1259                 struct megasas_sge64 sge64[2];  /* [0]: resp [1]: data */
1260         } sgl;
1261
1262 } __attribute__ ((packed));
1263
1264 union megasas_frame {
1265
1266         struct megasas_header hdr;
1267         struct megasas_init_frame init;
1268         struct megasas_io_frame io;
1269         struct megasas_pthru_frame pthru;
1270         struct megasas_dcmd_frame dcmd;
1271         struct megasas_abort_frame abort;
1272         struct megasas_smp_frame smp;
1273         struct megasas_stp_frame stp;
1274
1275         u8 raw_bytes[64];
1276 };
1277
1278 struct megasas_cmd;
1279
1280 union megasas_evt_class_locale {
1281
1282         struct {
1283                 u16 locale;
1284                 u8 reserved;
1285                 s8 class;
1286         } __attribute__ ((packed)) members;
1287
1288         u32 word;
1289
1290 } __attribute__ ((packed));
1291
1292 struct megasas_evt_log_info {
1293         u32 newest_seq_num;
1294         u32 oldest_seq_num;
1295         u32 clear_seq_num;
1296         u32 shutdown_seq_num;
1297         u32 boot_seq_num;
1298
1299 } __attribute__ ((packed));
1300
1301 struct megasas_progress {
1302
1303         u16 progress;
1304         u16 elapsed_seconds;
1305
1306 } __attribute__ ((packed));
1307
1308 struct megasas_evtarg_ld {
1309
1310         u16 target_id;
1311         u8 ld_index;
1312         u8 reserved;
1313
1314 } __attribute__ ((packed));
1315
1316 struct megasas_evtarg_pd {
1317         u16 device_id;
1318         u8 encl_index;
1319         u8 slot_number;
1320
1321 } __attribute__ ((packed));
1322
1323 struct megasas_evt_detail {
1324
1325         u32 seq_num;
1326         u32 time_stamp;
1327         u32 code;
1328         union megasas_evt_class_locale cl;
1329         u8 arg_type;
1330         u8 reserved1[15];
1331
1332         union {
1333                 struct {
1334                         struct megasas_evtarg_pd pd;
1335                         u8 cdb_length;
1336                         u8 sense_length;
1337                         u8 reserved[2];
1338                         u8 cdb[16];
1339                         u8 sense[64];
1340                 } __attribute__ ((packed)) cdbSense;
1341
1342                 struct megasas_evtarg_ld ld;
1343
1344                 struct {
1345                         struct megasas_evtarg_ld ld;
1346                         u64 count;
1347                 } __attribute__ ((packed)) ld_count;
1348
1349                 struct {
1350                         u64 lba;
1351                         struct megasas_evtarg_ld ld;
1352                 } __attribute__ ((packed)) ld_lba;
1353
1354                 struct {
1355                         struct megasas_evtarg_ld ld;
1356                         u32 prevOwner;
1357                         u32 newOwner;
1358                 } __attribute__ ((packed)) ld_owner;
1359
1360                 struct {
1361                         u64 ld_lba;
1362                         u64 pd_lba;
1363                         struct megasas_evtarg_ld ld;
1364                         struct megasas_evtarg_pd pd;
1365                 } __attribute__ ((packed)) ld_lba_pd_lba;
1366
1367                 struct {
1368                         struct megasas_evtarg_ld ld;
1369                         struct megasas_progress prog;
1370                 } __attribute__ ((packed)) ld_prog;
1371
1372                 struct {
1373                         struct megasas_evtarg_ld ld;
1374                         u32 prev_state;
1375                         u32 new_state;
1376                 } __attribute__ ((packed)) ld_state;
1377
1378                 struct {
1379                         u64 strip;
1380                         struct megasas_evtarg_ld ld;
1381                 } __attribute__ ((packed)) ld_strip;
1382
1383                 struct megasas_evtarg_pd pd;
1384
1385                 struct {
1386                         struct megasas_evtarg_pd pd;
1387                         u32 err;
1388                 } __attribute__ ((packed)) pd_err;
1389
1390                 struct {
1391                         u64 lba;
1392                         struct megasas_evtarg_pd pd;
1393                 } __attribute__ ((packed)) pd_lba;
1394
1395                 struct {
1396                         u64 lba;
1397                         struct megasas_evtarg_pd pd;
1398                         struct megasas_evtarg_ld ld;
1399                 } __attribute__ ((packed)) pd_lba_ld;
1400
1401                 struct {
1402                         struct megasas_evtarg_pd pd;
1403                         struct megasas_progress prog;
1404                 } __attribute__ ((packed)) pd_prog;
1405
1406                 struct {
1407                         struct megasas_evtarg_pd pd;
1408                         u32 prevState;
1409                         u32 newState;
1410                 } __attribute__ ((packed)) pd_state;
1411
1412                 struct {
1413                         u16 vendorId;
1414                         u16 deviceId;
1415                         u16 subVendorId;
1416                         u16 subDeviceId;
1417                 } __attribute__ ((packed)) pci;
1418
1419                 u32 rate;
1420                 char str[96];
1421
1422                 struct {
1423                         u32 rtc;
1424                         u32 elapsedSeconds;
1425                 } __attribute__ ((packed)) time;
1426
1427                 struct {
1428                         u32 ecar;
1429                         u32 elog;
1430                         char str[64];
1431                 } __attribute__ ((packed)) ecc;
1432
1433                 u8 b[96];
1434                 u16 s[48];
1435                 u32 w[24];
1436                 u64 d[12];
1437         } args;
1438
1439         char description[128];
1440
1441 } __attribute__ ((packed));
1442
1443 struct megasas_aen_event {
1444         struct delayed_work hotplug_work;
1445         struct megasas_instance *instance;
1446 };
1447
1448 struct megasas_irq_context {
1449         struct megasas_instance *instance;
1450         u32 MSIxIndex;
1451 };
1452
1453 struct megasas_instance {
1454
1455         u32 *producer;
1456         dma_addr_t producer_h;
1457         u32 *consumer;
1458         dma_addr_t consumer_h;
1459
1460         u32 *reply_queue;
1461         dma_addr_t reply_queue_h;
1462
1463         unsigned long base_addr;
1464         struct megasas_register_set __iomem *reg_set;
1465         u32 *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
1466         struct megasas_pd_list          pd_list[MEGASAS_MAX_PD];
1467         u8     ld_ids[MEGASAS_MAX_LD_IDS];
1468         s8 init_id;
1469
1470         u16 max_num_sge;
1471         u16 max_fw_cmds;
1472         /* For Fusion its num IOCTL cmds, for others MFI based its
1473            max_fw_cmds */
1474         u16 max_mfi_cmds;
1475         u32 max_sectors_per_req;
1476         struct megasas_aen_event *ev;
1477
1478         struct megasas_cmd **cmd_list;
1479         struct list_head cmd_pool;
1480         /* used to sync fire the cmd to fw */
1481         spinlock_t cmd_pool_lock;
1482         /* used to sync fire the cmd to fw */
1483         spinlock_t hba_lock;
1484         /* used to synch producer, consumer ptrs in dpc */
1485         spinlock_t completion_lock;
1486         struct dma_pool *frame_dma_pool;
1487         struct dma_pool *sense_dma_pool;
1488
1489         struct megasas_evt_detail *evt_detail;
1490         dma_addr_t evt_detail_h;
1491         struct megasas_cmd *aen_cmd;
1492         struct mutex aen_mutex;
1493         struct semaphore ioctl_sem;
1494
1495         struct Scsi_Host *host;
1496
1497         wait_queue_head_t int_cmd_wait_q;
1498         wait_queue_head_t abort_cmd_wait_q;
1499
1500         struct pci_dev *pdev;
1501         u32 unique_id;
1502         u32 fw_support_ieee;
1503
1504         atomic_t fw_outstanding;
1505         atomic_t fw_reset_no_pci_access;
1506
1507         struct megasas_instance_template *instancet;
1508         struct tasklet_struct isr_tasklet;
1509         struct work_struct work_init;
1510
1511         u8 flag;
1512         u8 unload;
1513         u8 flag_ieee;
1514         u8 issuepend_done;
1515         u8 disableOnlineCtrlReset;
1516         u8 UnevenSpanSupport;
1517         u8 adprecovery;
1518         unsigned long last_time;
1519         u32 mfiStatus;
1520         u32 last_seq_num;
1521
1522         struct list_head internal_reset_pending_q;
1523
1524         /* Ptr to hba specific information */
1525         void *ctrl_context;
1526         unsigned int msix_vectors;
1527         struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1528         struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
1529         u64 map_id;
1530         struct megasas_cmd *map_update_cmd;
1531         unsigned long bar;
1532         long reset_flags;
1533         struct mutex reset_mutex;
1534         int throttlequeuedepth;
1535         u8 mask_interrupts;
1536         u8 is_imr;
1537 };
1538
1539 enum {
1540         MEGASAS_HBA_OPERATIONAL                 = 0,
1541         MEGASAS_ADPRESET_SM_INFAULT             = 1,
1542         MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS    = 2,
1543         MEGASAS_ADPRESET_SM_OPERATIONAL         = 3,
1544         MEGASAS_HW_CRITICAL_ERROR               = 4,
1545         MEGASAS_ADPRESET_INPROG_SIGN            = 0xDEADDEAD,
1546 };
1547
1548 struct megasas_instance_template {
1549         void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1550                 u32, struct megasas_register_set __iomem *);
1551
1552         void (*enable_intr)(struct megasas_instance *);
1553         void (*disable_intr)(struct megasas_instance *);
1554
1555         int (*clear_intr)(struct megasas_register_set __iomem *);
1556
1557         u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1558         int (*adp_reset)(struct megasas_instance *, \
1559                 struct megasas_register_set __iomem *);
1560         int (*check_reset)(struct megasas_instance *, \
1561                 struct megasas_register_set __iomem *);
1562         irqreturn_t (*service_isr)(int irq, void *devp);
1563         void (*tasklet)(unsigned long);
1564         u32 (*init_adapter)(struct megasas_instance *);
1565         u32 (*build_and_issue_cmd) (struct megasas_instance *,
1566                                     struct scsi_cmnd *);
1567         void (*issue_dcmd) (struct megasas_instance *instance,
1568                             struct megasas_cmd *cmd);
1569 };
1570
1571 #define MEGASAS_IS_LOGICAL(scp)                                         \
1572         (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1573
1574 #define MEGASAS_DEV_INDEX(inst, scp)                                    \
1575         ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) +    \
1576         scp->device->id
1577
1578 struct megasas_cmd {
1579
1580         union megasas_frame *frame;
1581         dma_addr_t frame_phys_addr;
1582         u8 *sense;
1583         dma_addr_t sense_phys_addr;
1584
1585         u32 index;
1586         u8 sync_cmd;
1587         u8 cmd_status;
1588         u8 abort_aen;
1589         u8 retry_for_fw_reset;
1590
1591
1592         struct list_head list;
1593         struct scsi_cmnd *scmd;
1594         struct megasas_instance *instance;
1595         union {
1596                 struct {
1597                         u16 smid;
1598                         u16 resvd;
1599                 } context;
1600                 u32 frame_count;
1601         };
1602 };
1603
1604 #define MAX_MGMT_ADAPTERS               1024
1605 #define MAX_IOCTL_SGE                   16
1606
1607 struct megasas_iocpacket {
1608
1609         u16 host_no;
1610         u16 __pad1;
1611         u32 sgl_off;
1612         u32 sge_count;
1613         u32 sense_off;
1614         u32 sense_len;
1615         union {
1616                 u8 raw[128];
1617                 struct megasas_header hdr;
1618         } frame;
1619
1620         struct iovec sgl[MAX_IOCTL_SGE];
1621
1622 } __attribute__ ((packed));
1623
1624 struct megasas_aen {
1625         u16 host_no;
1626         u16 __pad1;
1627         u32 seq_num;
1628         u32 class_locale_word;
1629 } __attribute__ ((packed));
1630
1631 #ifdef CONFIG_COMPAT
1632 struct compat_megasas_iocpacket {
1633         u16 host_no;
1634         u16 __pad1;
1635         u32 sgl_off;
1636         u32 sge_count;
1637         u32 sense_off;
1638         u32 sense_len;
1639         union {
1640                 u8 raw[128];
1641                 struct megasas_header hdr;
1642         } frame;
1643         struct compat_iovec sgl[MAX_IOCTL_SGE];
1644 } __attribute__ ((packed));
1645
1646 #define MEGASAS_IOC_FIRMWARE32  _IOWR('M', 1, struct compat_megasas_iocpacket)
1647 #endif
1648
1649 #define MEGASAS_IOC_FIRMWARE    _IOWR('M', 1, struct megasas_iocpacket)
1650 #define MEGASAS_IOC_GET_AEN     _IOW('M', 3, struct megasas_aen)
1651
1652 struct megasas_mgmt_info {
1653
1654         u16 count;
1655         struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1656         int max_index;
1657 };
1658
1659 #endif                          /*LSI_MEGARAID_SAS_H */