2 * Linux MegaRAID driver for SAS based RAID controllers
4 * Copyright (c) 2003-2013 LSI Corporation
5 * Copyright (c) 2013-2014 Avago Technologies
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 * FILE: megaraid_sas.h
22 * Authors: Avago Technologies
23 * Kashyap Desai <kashyap.desai@avagotech.com>
24 * Sumit Saxena <sumit.saxena@avagotech.com>
26 * Send feedback to: megaraidlinux.pdl@avagotech.com
28 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
29 * San Jose, California 95131
32 #ifndef LSI_MEGARAID_SAS_H
33 #define LSI_MEGARAID_SAS_H
36 * MegaRAID SAS Driver meta data
38 #define MEGASAS_VERSION "06.807.10.00-rc1"
39 #define MEGASAS_RELDATE "March 6, 2015"
44 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
45 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
46 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
47 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
48 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
49 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
50 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
51 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
52 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
53 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
54 #define PCI_DEVICE_ID_LSI_FURY 0x005f
59 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
60 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
61 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
62 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
63 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
64 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
69 #define MEGARAID_INTEL_RS3DC080_BRANDING \
70 "Intel(R) RAID Controller RS3DC080"
71 #define MEGARAID_INTEL_RS3DC040_BRANDING \
72 "Intel(R) RAID Controller RS3DC040"
73 #define MEGARAID_INTEL_RS3SC008_BRANDING \
74 "Intel(R) RAID Controller RS3SC008"
75 #define MEGARAID_INTEL_RS3MC044_BRANDING \
76 "Intel(R) RAID Controller RS3MC044"
77 #define MEGARAID_INTEL_RS3WC080_BRANDING \
78 "Intel(R) RAID Controller RS3WC080"
79 #define MEGARAID_INTEL_RS3WC040_BRANDING \
80 "Intel(R) RAID Controller RS3WC040"
83 * =====================================
84 * MegaRAID SAS MFI firmware definitions
85 * =====================================
89 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
90 * protocol between the software and firmware. Commands are issued using
95 * FW posts its state in upper 4 bits of outbound_msg_0 register
97 #define MFI_STATE_MASK 0xF0000000
98 #define MFI_STATE_UNDEFINED 0x00000000
99 #define MFI_STATE_BB_INIT 0x10000000
100 #define MFI_STATE_FW_INIT 0x40000000
101 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
102 #define MFI_STATE_FW_INIT_2 0x70000000
103 #define MFI_STATE_DEVICE_SCAN 0x80000000
104 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
105 #define MFI_STATE_FLUSH_CACHE 0xA0000000
106 #define MFI_STATE_READY 0xB0000000
107 #define MFI_STATE_OPERATIONAL 0xC0000000
108 #define MFI_STATE_FAULT 0xF0000000
109 #define MFI_STATE_FORCE_OCR 0x00000080
110 #define MFI_STATE_DMADONE 0x00000008
111 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004
112 #define MFI_RESET_REQUIRED 0x00000001
113 #define MFI_RESET_ADAPTER 0x00000002
114 #define MEGAMFI_FRAME_SIZE 64
117 * During FW init, clear pending cmds & reset state using inbound_msg_0
119 * ABORT : Abort all pending cmds
120 * READY : Move from OPERATIONAL to READY state; discard queue info
121 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
122 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
123 * HOTPLUG : Resume from Hotplug
124 * MFI_STOP_ADP : Send signal to FW to stop processing
126 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
127 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
128 #define DIAG_WRITE_ENABLE (0x00000080)
129 #define DIAG_RESET_ADAPTER (0x00000004)
131 #define MFI_ADP_RESET 0x00000040
132 #define MFI_INIT_ABORT 0x00000001
133 #define MFI_INIT_READY 0x00000002
134 #define MFI_INIT_MFIMODE 0x00000004
135 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
136 #define MFI_INIT_HOTPLUG 0x00000010
137 #define MFI_STOP_ADP 0x00000020
138 #define MFI_RESET_FLAGS MFI_INIT_READY| \
145 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
146 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
147 #define MFI_FRAME_SGL32 0x0000
148 #define MFI_FRAME_SGL64 0x0002
149 #define MFI_FRAME_SENSE32 0x0000
150 #define MFI_FRAME_SENSE64 0x0004
151 #define MFI_FRAME_DIR_NONE 0x0000
152 #define MFI_FRAME_DIR_WRITE 0x0008
153 #define MFI_FRAME_DIR_READ 0x0010
154 #define MFI_FRAME_DIR_BOTH 0x0018
155 #define MFI_FRAME_IEEE 0x0020
157 /* Driver internal */
158 #define DRV_DCMD_POLLED_MODE 0x1
161 * Definition for cmd_status
163 #define MFI_CMD_STATUS_POLL_MODE 0xFF
166 * MFI command opcodes
168 #define MFI_CMD_INIT 0x00
169 #define MFI_CMD_LD_READ 0x01
170 #define MFI_CMD_LD_WRITE 0x02
171 #define MFI_CMD_LD_SCSI_IO 0x03
172 #define MFI_CMD_PD_SCSI_IO 0x04
173 #define MFI_CMD_DCMD 0x05
174 #define MFI_CMD_ABORT 0x06
175 #define MFI_CMD_SMP 0x07
176 #define MFI_CMD_STP 0x08
177 #define MFI_CMD_INVALID 0xff
179 #define MR_DCMD_CTRL_GET_INFO 0x01010000
180 #define MR_DCMD_LD_GET_LIST 0x03010000
181 #define MR_DCMD_LD_LIST_QUERY 0x03010100
183 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
184 #define MR_FLUSH_CTRL_CACHE 0x01
185 #define MR_FLUSH_DISK_CACHE 0x02
187 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
188 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
189 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
191 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
192 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
193 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
194 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
196 #define MR_DCMD_CLUSTER 0x08000000
197 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
198 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
199 #define MR_DCMD_PD_LIST_QUERY 0x02010100
201 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
202 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
207 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
211 * MFI command completion codes
215 MFI_STAT_INVALID_CMD = 0x01,
216 MFI_STAT_INVALID_DCMD = 0x02,
217 MFI_STAT_INVALID_PARAMETER = 0x03,
218 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
219 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
220 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
221 MFI_STAT_APP_IN_USE = 0x07,
222 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
223 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
224 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
225 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
226 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
227 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
228 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
229 MFI_STAT_FLASH_BUSY = 0x0f,
230 MFI_STAT_FLASH_ERROR = 0x10,
231 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
232 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
233 MFI_STAT_FLASH_NOT_OPEN = 0x13,
234 MFI_STAT_FLASH_NOT_STARTED = 0x14,
235 MFI_STAT_FLUSH_FAILED = 0x15,
236 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
237 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
238 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
239 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
240 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
241 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
242 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
243 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
244 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
245 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
246 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
247 MFI_STAT_MFC_HW_ERROR = 0x21,
248 MFI_STAT_NO_HW_PRESENT = 0x22,
249 MFI_STAT_NOT_FOUND = 0x23,
250 MFI_STAT_NOT_IN_ENCL = 0x24,
251 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
252 MFI_STAT_PD_TYPE_WRONG = 0x26,
253 MFI_STAT_PR_DISABLED = 0x27,
254 MFI_STAT_ROW_INDEX_INVALID = 0x28,
255 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
256 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
257 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
258 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
259 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
260 MFI_STAT_SCSI_IO_FAILED = 0x2e,
261 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
262 MFI_STAT_SHUTDOWN_FAILED = 0x30,
263 MFI_STAT_TIME_NOT_SET = 0x31,
264 MFI_STAT_WRONG_STATE = 0x32,
265 MFI_STAT_LD_OFFLINE = 0x33,
266 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
267 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
268 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
269 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
270 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
271 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
273 MFI_STAT_INVALID_STATUS = 0xFF
277 * Crash dump related defines
279 #define MAX_CRASH_DUMP_SIZE 512
280 #define CRASH_DMA_BUF_SIZE (1024 * 1024)
282 enum MR_FW_CRASH_DUMP_STATE {
290 enum _MR_CRASH_BUF_STATUS {
291 MR_CRASH_BUF_TURN_OFF = 0,
292 MR_CRASH_BUF_TURN_ON = 1,
296 * Number of mailbox bytes in DCMD message frame
298 #define MFI_MBOX_SIZE 12
302 MR_EVT_CLASS_DEBUG = -2,
303 MR_EVT_CLASS_PROGRESS = -1,
304 MR_EVT_CLASS_INFO = 0,
305 MR_EVT_CLASS_WARNING = 1,
306 MR_EVT_CLASS_CRITICAL = 2,
307 MR_EVT_CLASS_FATAL = 3,
308 MR_EVT_CLASS_DEAD = 4,
314 MR_EVT_LOCALE_LD = 0x0001,
315 MR_EVT_LOCALE_PD = 0x0002,
316 MR_EVT_LOCALE_ENCL = 0x0004,
317 MR_EVT_LOCALE_BBU = 0x0008,
318 MR_EVT_LOCALE_SAS = 0x0010,
319 MR_EVT_LOCALE_CTRL = 0x0020,
320 MR_EVT_LOCALE_CONFIG = 0x0040,
321 MR_EVT_LOCALE_CLUSTER = 0x0080,
322 MR_EVT_LOCALE_ALL = 0xffff,
329 MR_EVT_ARGS_CDB_SENSE,
331 MR_EVT_ARGS_LD_COUNT,
333 MR_EVT_ARGS_LD_OWNER,
334 MR_EVT_ARGS_LD_LBA_PD_LBA,
336 MR_EVT_ARGS_LD_STATE,
337 MR_EVT_ARGS_LD_STRIP,
341 MR_EVT_ARGS_PD_LBA_LD,
343 MR_EVT_ARGS_PD_STATE,
350 MR_EVT_ARGS_PD_SPARE,
351 MR_EVT_ARGS_PD_INDEX,
352 MR_EVT_ARGS_DIAG_PASS,
353 MR_EVT_ARGS_DIAG_FAIL,
354 MR_EVT_ARGS_PD_LBA_LBA,
355 MR_EVT_ARGS_PORT_PHY,
356 MR_EVT_ARGS_PD_MISSING,
357 MR_EVT_ARGS_PD_ADDRESS,
359 MR_EVT_ARGS_CONNECTOR,
362 MR_EVT_ARGS_PD_PATHINFO,
363 MR_EVT_ARGS_PD_POWER_STATE,
368 * define constants for device list query options
370 enum MR_PD_QUERY_TYPE {
371 MR_PD_QUERY_TYPE_ALL = 0,
372 MR_PD_QUERY_TYPE_STATE = 1,
373 MR_PD_QUERY_TYPE_POWER_STATE = 2,
374 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
375 MR_PD_QUERY_TYPE_SPEED = 4,
376 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
379 enum MR_LD_QUERY_TYPE {
380 MR_LD_QUERY_TYPE_ALL = 0,
381 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
382 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
383 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
384 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
388 #define MR_EVT_CFG_CLEARED 0x0004
389 #define MR_EVT_LD_STATE_CHANGE 0x0051
390 #define MR_EVT_PD_INSERTED 0x005b
391 #define MR_EVT_PD_REMOVED 0x0070
392 #define MR_EVT_LD_CREATED 0x008a
393 #define MR_EVT_LD_DELETED 0x008b
394 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
395 #define MR_EVT_LD_OFFLINE 0x00fc
396 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
399 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
400 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
401 MR_PD_STATE_HOT_SPARE = 0x02,
402 MR_PD_STATE_OFFLINE = 0x10,
403 MR_PD_STATE_FAILED = 0x11,
404 MR_PD_STATE_REBUILD = 0x14,
405 MR_PD_STATE_ONLINE = 0x18,
406 MR_PD_STATE_COPYBACK = 0x20,
407 MR_PD_STATE_SYSTEM = 0x40,
412 * defines the physical drive address structure
414 struct MR_PD_ADDRESS {
425 u8 enclConnectorIndex;
430 u8 connectedPortBitmap;
431 u8 connectedPortNumbers;
437 * defines the physical drive list structure
442 struct MR_PD_ADDRESS addr[1];
445 struct megasas_pd_list {
452 * defines the logical drive reference structure
464 * defines the logical drive list structure
474 } ldList[MAX_LOGICAL_DRIVES_EXT];
477 struct MR_LD_TARGETID_LIST {
481 u8 targetId[MAX_LOGICAL_DRIVES_EXT];
486 * SAS controller properties
488 struct megasas_ctrl_prop {
491 u16 pred_fail_poll_interval;
492 u16 intr_throttle_count;
493 u16 intr_throttle_timeouts;
499 u8 cache_flush_interval;
505 u8 disable_auto_rebuild;
506 u8 disable_battery_warn;
508 u16 ecc_bucket_leak_rate;
509 u8 restore_hotspare_on_insertion;
510 u8 expose_encl_devices;
511 u8 maintainPdFailHistory;
512 u8 disallowHostRequestReordering;
515 u8 disableAutoDetectBackplane;
520 * Add properties that can be controlled by
521 * a bit in the following structure.
524 #if defined(__BIG_ENDIAN_BITFIELD)
527 u32 disableSpinDownHS:1;
528 u32 allowBootWithPinnedCache:1;
529 u32 disableOnlineCtrlReset:1;
530 u32 enableSecretKeyControl:1;
531 u32 autoEnhancedImport:1;
532 u32 enableSpinDownUnconfigured:1;
533 u32 SSDPatrolReadEnabled:1;
534 u32 SSDSMARTerEnabled:1;
537 u32 prCorrectUnconfiguredAreas:1;
538 u32 SMARTerEnabled:1;
539 u32 copyBackDisabled:1;
541 u32 copyBackDisabled:1;
542 u32 SMARTerEnabled:1;
543 u32 prCorrectUnconfiguredAreas:1;
546 u32 SSDSMARTerEnabled:1;
547 u32 SSDPatrolReadEnabled:1;
548 u32 enableSpinDownUnconfigured:1;
549 u32 autoEnhancedImport:1;
550 u32 enableSecretKeyControl:1;
551 u32 disableOnlineCtrlReset:1;
552 u32 allowBootWithPinnedCache:1;
553 u32 disableSpinDownHS:1;
565 * SAS controller information
567 struct megasas_ctrl_info {
570 * PCI device information
576 __le16 sub_vendor_id;
577 __le16 sub_device_id;
580 } __attribute__ ((packed)) pci;
583 * Host interface information
597 } __attribute__ ((packed)) host_interface;
600 * Device (backend) interface information
613 } __attribute__ ((packed)) device_interface;
616 * List of components residing in flash. All str are null terminated
618 __le32 image_check_word;
619 __le32 image_component_count;
628 } __attribute__ ((packed)) image_component[8];
631 * List of flash components that have been flashed on the card, but
632 * are not in use, pending reset of the adapter. This list will be
633 * empty if a flash operation has not occurred. All stings are null
636 __le32 pending_image_component_count;
645 } __attribute__ ((packed)) pending_image_component[8];
652 char product_name[80];
656 * Other physical/controller/operation information. Indicates the
657 * presence of the hardware
667 } __attribute__ ((packed)) hw_present;
669 __le32 current_fw_time;
672 * Maximum data transfer sizes
674 __le16 max_concurrent_cmds;
675 __le16 max_sge_count;
676 __le32 max_request_size;
679 * Logical and physical device counts
681 __le16 ld_present_count;
682 __le16 ld_degraded_count;
683 __le16 ld_offline_count;
685 __le16 pd_present_count;
686 __le16 pd_disk_present_count;
687 __le16 pd_disk_pred_failure_count;
688 __le16 pd_disk_failed_count;
691 * Memory size information
700 __le16 mem_correctable_error_count;
701 __le16 mem_uncorrectable_error_count;
704 * Cluster information
706 u8 cluster_permitted;
710 * Additional max data transfer sizes
712 __le16 max_strips_per_io;
715 * Controller capabilities structures
726 } __attribute__ ((packed)) raid_levels;
736 u32 cluster_supported:1;
738 u32 spanning_allowed:1;
739 u32 dedicated_hotspares:1;
740 u32 revertible_hotspares:1;
741 u32 foreign_config_import:1;
742 u32 self_diagnostic:1;
743 u32 mixed_redundancy_arr:1;
744 u32 global_hot_spares:1;
747 } __attribute__ ((packed)) adapter_operations;
755 u32 disk_cache_policy:1;
758 } __attribute__ ((packed)) ld_operations;
766 } __attribute__ ((packed)) stripe_sz_ops;
775 } __attribute__ ((packed)) pd_operations;
779 u32 ctrl_supports_sas:1;
780 u32 ctrl_supports_sata:1;
781 u32 allow_mix_in_encl:1;
782 u32 allow_mix_in_ld:1;
783 u32 allow_sata_in_cluster:1;
786 } __attribute__ ((packed)) pd_mix_support;
789 * Define ECC single-bit-error bucket information
795 * Include the controller properties (changeable items)
797 struct megasas_ctrl_prop properties;
800 * Define FW pkg version (set in envt v'bles on OEM basis)
802 char package_version[0x60];
806 * If adapterOperations.supportMoreThan8Phys is set,
807 * and deviceInterface.portCount is greater than 8,
808 * SAS Addrs for first 8 ports shall be populated in
809 * deviceInterface.portAddr, and the rest shall be
810 * populated in deviceInterfacePortAddr2.
812 __le64 deviceInterfacePortAddr2[8]; /*6a0h */
813 u8 reserved3[128]; /*6e0h */
816 u16 minPdRaidLevel_0:4;
817 u16 maxPdRaidLevel_0:12;
819 u16 minPdRaidLevel_1:4;
820 u16 maxPdRaidLevel_1:12;
822 u16 minPdRaidLevel_5:4;
823 u16 maxPdRaidLevel_5:12;
825 u16 minPdRaidLevel_1E:4;
826 u16 maxPdRaidLevel_1E:12;
828 u16 minPdRaidLevel_6:4;
829 u16 maxPdRaidLevel_6:12;
831 u16 minPdRaidLevel_10:4;
832 u16 maxPdRaidLevel_10:12;
834 u16 minPdRaidLevel_50:4;
835 u16 maxPdRaidLevel_50:12;
837 u16 minPdRaidLevel_60:4;
838 u16 maxPdRaidLevel_60:12;
840 u16 minPdRaidLevel_1E_RLQ0:4;
841 u16 maxPdRaidLevel_1E_RLQ0:12;
843 u16 minPdRaidLevel_1E0_RLQ0:4;
844 u16 maxPdRaidLevel_1E0_RLQ0:12;
849 __le16 maxPds; /*780h */
850 __le16 maxDedHSPs; /*782h */
851 __le16 maxGlobalHSP; /*784h */
852 __le16 ddfSize; /*786h */
853 u8 maxLdsPerArray; /*788h */
854 u8 partitionsInDDF; /*789h */
855 u8 lockKeyBinding; /*78ah */
856 u8 maxPITsPerLd; /*78bh */
857 u8 maxViewsPerLd; /*78ch */
858 u8 maxTargetId; /*78dh */
859 __le16 maxBvlVdSize; /*78eh */
861 __le16 maxConfigurableSSCSize; /*790h */
862 __le16 currentSSCsize; /*792h */
864 char expanderFwVersion[12]; /*794h */
866 __le16 PFKTrialTimeRemaining; /*7A0h */
868 __le16 cacheMemorySize; /*7A2h */
871 #if defined(__BIG_ENDIAN_BITFIELD)
874 u32 supportConfigAutoBalance:1;
876 u32 supportDataLDonSSCArray:1;
877 u32 supportPointInTimeProgress:1;
878 u32 supportUnevenSpans:1;
879 u32 dedicatedHotSparesLimited:1;
881 u32 supportEmulatedDrives:1;
882 u32 supportResetNow:1;
883 u32 realTimeScheduler:1;
884 u32 supportSSDPatrolRead:1;
885 u32 supportPerfTuning:1;
886 u32 disableOnlinePFKChange:1;
888 u32 supportBootTimePFKChange:1;
889 u32 supportSetLinkSpeed:1;
890 u32 supportEmergencySpares:1;
891 u32 supportSuspendResumeBGops:1;
892 u32 blockSSDWriteCacheChange:1;
893 u32 supportShieldState:1;
894 u32 supportLdBBMInfo:1;
895 u32 supportLdPIType3:1;
896 u32 supportLdPIType2:1;
897 u32 supportLdPIType1:1;
898 u32 supportPIcontroller:1;
900 u32 supportPIcontroller:1;
901 u32 supportLdPIType1:1;
902 u32 supportLdPIType2:1;
903 u32 supportLdPIType3:1;
904 u32 supportLdBBMInfo:1;
905 u32 supportShieldState:1;
906 u32 blockSSDWriteCacheChange:1;
907 u32 supportSuspendResumeBGops:1;
908 u32 supportEmergencySpares:1;
909 u32 supportSetLinkSpeed:1;
910 u32 supportBootTimePFKChange:1;
912 u32 disableOnlinePFKChange:1;
913 u32 supportPerfTuning:1;
914 u32 supportSSDPatrolRead:1;
915 u32 realTimeScheduler:1;
917 u32 supportResetNow:1;
918 u32 supportEmulatedDrives:1;
920 u32 dedicatedHotSparesLimited:1;
923 u32 supportUnevenSpans:1;
924 u32 supportPointInTimeProgress:1;
925 u32 supportDataLDonSSCArray:1;
927 u32 supportConfigAutoBalance:1;
931 } adapterOperations2;
933 u8 driverVersion[32]; /*7A8h */
934 u8 maxDAPdCountSpinup60; /*7C8h */
935 u8 temperatureROC; /*7C9h */
936 u8 temperatureCtrl; /*7CAh */
937 u8 reserved4; /*7CBh */
938 __le16 maxConfigurablePds; /*7CCh */
941 u8 reserved5[2]; /*0x7CDh */
944 * HA cluster information
947 #if defined(__BIG_ENDIAN_BITFIELD)
949 u32 premiumFeatureMismatch:1;
950 u32 ctrlPropIncompatible:1;
951 u32 fwVersionMismatch:1;
952 u32 hwIncompatible:1;
953 u32 peerIsIncompatible:1;
957 u32 peerIsIncompatible:1;
958 u32 hwIncompatible:1;
959 u32 fwVersionMismatch:1;
960 u32 ctrlPropIncompatible:1;
961 u32 premiumFeatureMismatch:1;
966 char clusterId[16]; /*7D4h */
968 u8 maxVFsSupported; /*0x7E4*/
969 u8 numVFsEnabled; /*0x7E5*/
970 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
971 u8 reserved; /*0x7E7*/
975 #if defined(__BIG_ENDIAN_BITFIELD)
977 u32 discardCacheDuringLDDelete:1;
978 u32 supportSecurityonJBOD:1;
979 u32 supportCacheBypassModes:1;
980 u32 supportDisableSESMonitoring:1;
981 u32 supportForceFlash:1;
983 u32 supportDrvActivityLEDSetting:1;
984 u32 supportAllowedOpsforDrvRemoval:1;
985 u32 supportHOQRebuild:1;
986 u32 supportForceTo512e:1;
987 u32 supportNVCacheErase:1;
988 u32 supportDebugQueue:1;
990 u32 supportCrashDump:1;
991 u32 supportMaxExtLDs:1;
992 u32 supportT10RebuildAssist:1;
993 u32 supportDisableImmediateIO:1;
994 u32 supportThermalPollInterval:1;
995 u32 supportPersonalityChange:2;
997 u32 supportPersonalityChange:2;
998 u32 supportThermalPollInterval:1;
999 u32 supportDisableImmediateIO:1;
1000 u32 supportT10RebuildAssist:1;
1001 u32 supportMaxExtLDs:1;
1002 u32 supportCrashDump:1;
1003 u32 supportSwZone:1;
1004 u32 supportDebugQueue:1;
1005 u32 supportNVCacheErase:1;
1006 u32 supportForceTo512e:1;
1007 u32 supportHOQRebuild:1;
1008 u32 supportAllowedOpsforDrvRemoval:1;
1009 u32 supportDrvActivityLEDSetting:1;
1010 u32 supportNVDRAM:1;
1011 u32 supportForceFlash:1;
1012 u32 supportDisableSESMonitoring:1;
1013 u32 supportCacheBypassModes:1;
1014 u32 supportSecurityonJBOD:1;
1015 u32 discardCacheDuringLDDelete:1;
1018 } adapterOperations3;
1020 u8 pad[0x800-0x7EC];
1024 * ===============================
1025 * MegaRAID SAS driver definitions
1026 * ===============================
1028 #define MEGASAS_MAX_PD_CHANNELS 2
1029 #define MEGASAS_MAX_LD_CHANNELS 2
1030 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
1031 MEGASAS_MAX_LD_CHANNELS)
1032 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
1033 #define MEGASAS_DEFAULT_INIT_ID -1
1034 #define MEGASAS_MAX_LUN 8
1035 #define MEGASAS_DEFAULT_CMD_PER_LUN 256
1036 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
1037 MEGASAS_MAX_DEV_PER_CHANNEL)
1038 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1039 MEGASAS_MAX_DEV_PER_CHANNEL)
1041 #define MEGASAS_MAX_SECTORS (2*1024)
1042 #define MEGASAS_MAX_SECTORS_IEEE (2*128)
1043 #define MEGASAS_DBG_LVL 1
1045 #define MEGASAS_FW_BUSY 1
1047 #define VD_EXT_DEBUG 0
1050 enum MR_SCSI_CMD_TYPE {
1051 READ_WRITE_LDIO = 0,
1052 NON_READ_WRITE_LDIO = 1,
1053 READ_WRITE_SYSPDIO = 2,
1054 NON_READ_WRITE_SYSPDIO = 3,
1059 #define PTHRU_FRAME 1
1062 * When SCSI mid-layer calls driver's reset routine, driver waits for
1063 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1064 * that the driver cannot _actually_ abort or reset pending commands. While
1065 * it is waiting for the commands to complete, it prints a diagnostic message
1066 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1068 #define MEGASAS_RESET_WAIT_TIME 180
1069 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
1070 #define MEGASAS_RESET_NOTICE_INTERVAL 5
1071 #define MEGASAS_IOCTL_CMD 0
1072 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
1073 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16
1074 #define MEGASAS_BLOCKED_CMD_TIMEOUT 60
1076 * FW reports the maximum of number of commands that it can accept (maximum
1077 * commands that can be outstanding) at any time. The driver must report a
1078 * lower number to the mid layer because it can issue a few internal commands
1079 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1082 #define MEGASAS_INT_CMDS 32
1083 #define MEGASAS_SKINNY_INT_CMDS 5
1084 #define MEGASAS_FUSION_INTERNAL_CMDS 5
1085 #define MEGASAS_FUSION_IOCTL_CMDS 3
1086 #define MEGASAS_MFI_IOCTL_CMDS 27
1088 #define MEGASAS_MAX_MSIX_QUEUES 128
1090 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1091 * SGLs based on the size of dma_addr_t
1093 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
1095 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1097 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1098 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1099 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1101 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1102 #define MFI_POLL_TIMEOUT_SECS 60
1103 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1104 #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
1105 #define MEGASAS_ROUTINE_WAIT_TIME_VF 300
1106 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
1107 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1108 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
1109 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1110 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
1112 #define MFI_1068_PCSR_OFFSET 0x84
1113 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1114 #define MFI_1068_FW_READY 0xDDDD0000
1116 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1117 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1118 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1119 #define MR_MAX_MSIX_REG_ARRAY 16
1121 * register set for both 1068 and 1078 controllers
1122 * structure extended for 1078 registers
1125 struct megasas_register_set {
1126 u32 doorbell; /*0000h*/
1127 u32 fusion_seq_offset; /*0004h*/
1128 u32 fusion_host_diag; /*0008h*/
1129 u32 reserved_01; /*000Ch*/
1131 u32 inbound_msg_0; /*0010h*/
1132 u32 inbound_msg_1; /*0014h*/
1133 u32 outbound_msg_0; /*0018h*/
1134 u32 outbound_msg_1; /*001Ch*/
1136 u32 inbound_doorbell; /*0020h*/
1137 u32 inbound_intr_status; /*0024h*/
1138 u32 inbound_intr_mask; /*0028h*/
1140 u32 outbound_doorbell; /*002Ch*/
1141 u32 outbound_intr_status; /*0030h*/
1142 u32 outbound_intr_mask; /*0034h*/
1144 u32 reserved_1[2]; /*0038h*/
1146 u32 inbound_queue_port; /*0040h*/
1147 u32 outbound_queue_port; /*0044h*/
1149 u32 reserved_2[9]; /*0048h*/
1150 u32 reply_post_host_index; /*006Ch*/
1151 u32 reserved_2_2[12]; /*0070h*/
1153 u32 outbound_doorbell_clear; /*00A0h*/
1155 u32 reserved_3[3]; /*00A4h*/
1157 u32 outbound_scratch_pad ; /*00B0h*/
1158 u32 outbound_scratch_pad_2; /*00B4h*/
1160 u32 reserved_4[2]; /*00B8h*/
1162 u32 inbound_low_queue_port ; /*00C0h*/
1164 u32 inbound_high_queue_port ; /*00C4h*/
1166 u32 reserved_5; /*00C8h*/
1167 u32 res_6[11]; /*CCh*/
1170 u32 index_registers[807]; /*00CCh*/
1171 } __attribute__ ((packed));
1173 struct megasas_sge32 {
1178 } __attribute__ ((packed));
1180 struct megasas_sge64 {
1185 } __attribute__ ((packed));
1187 struct megasas_sge_skinny {
1195 struct megasas_sge32 sge32[1];
1196 struct megasas_sge64 sge64[1];
1197 struct megasas_sge_skinny sge_skinny[1];
1199 } __attribute__ ((packed));
1201 struct megasas_header {
1204 u8 sense_len; /*01h */
1205 u8 cmd_status; /*02h */
1206 u8 scsi_status; /*03h */
1208 u8 target_id; /*04h */
1210 u8 cdb_len; /*06h */
1211 u8 sge_count; /*07h */
1213 __le32 context; /*08h */
1214 __le32 pad_0; /*0Ch */
1216 __le16 flags; /*10h */
1217 __le16 timeout; /*12h */
1218 __le32 data_xferlen; /*14h */
1220 } __attribute__ ((packed));
1222 union megasas_sgl_frame {
1224 struct megasas_sge32 sge32[8];
1225 struct megasas_sge64 sge64[5];
1227 } __attribute__ ((packed));
1229 typedef union _MFI_CAPABILITIES {
1231 #if defined(__BIG_ENDIAN_BITFIELD)
1233 u32 security_protocol_cmds_fw:1;
1234 u32 support_core_affinity:1;
1235 u32 support_ndrive_r1_lb:1;
1236 u32 support_max_255lds:1;
1237 u32 support_fastpath_wb:1;
1238 u32 support_additional_msix:1;
1239 u32 support_fp_remote_lun:1;
1241 u32 support_fp_remote_lun:1;
1242 u32 support_additional_msix:1;
1243 u32 support_fastpath_wb:1;
1244 u32 support_max_255lds:1;
1245 u32 support_ndrive_r1_lb:1;
1246 u32 support_core_affinity:1;
1247 u32 security_protocol_cmds_fw:1;
1254 struct megasas_init_frame {
1257 u8 reserved_0; /*01h */
1258 u8 cmd_status; /*02h */
1260 u8 reserved_1; /*03h */
1261 MFI_CAPABILITIES driver_operations; /*04h*/
1263 __le32 context; /*08h */
1264 __le32 pad_0; /*0Ch */
1266 __le16 flags; /*10h */
1267 __le16 reserved_3; /*12h */
1268 __le32 data_xfer_len; /*14h */
1270 __le32 queue_info_new_phys_addr_lo; /*18h */
1271 __le32 queue_info_new_phys_addr_hi; /*1Ch */
1272 __le32 queue_info_old_phys_addr_lo; /*20h */
1273 __le32 queue_info_old_phys_addr_hi; /*24h */
1274 __le32 reserved_4[2]; /*28h */
1275 __le32 system_info_lo; /*30h */
1276 __le32 system_info_hi; /*34h */
1277 __le32 reserved_5[2]; /*38h */
1279 } __attribute__ ((packed));
1281 struct megasas_init_queue_info {
1283 __le32 init_flags; /*00h */
1284 __le32 reply_queue_entries; /*04h */
1286 __le32 reply_queue_start_phys_addr_lo; /*08h */
1287 __le32 reply_queue_start_phys_addr_hi; /*0Ch */
1288 __le32 producer_index_phys_addr_lo; /*10h */
1289 __le32 producer_index_phys_addr_hi; /*14h */
1290 __le32 consumer_index_phys_addr_lo; /*18h */
1291 __le32 consumer_index_phys_addr_hi; /*1Ch */
1293 } __attribute__ ((packed));
1295 struct megasas_io_frame {
1298 u8 sense_len; /*01h */
1299 u8 cmd_status; /*02h */
1300 u8 scsi_status; /*03h */
1302 u8 target_id; /*04h */
1303 u8 access_byte; /*05h */
1304 u8 reserved_0; /*06h */
1305 u8 sge_count; /*07h */
1307 __le32 context; /*08h */
1308 __le32 pad_0; /*0Ch */
1310 __le16 flags; /*10h */
1311 __le16 timeout; /*12h */
1312 __le32 lba_count; /*14h */
1314 __le32 sense_buf_phys_addr_lo; /*18h */
1315 __le32 sense_buf_phys_addr_hi; /*1Ch */
1317 __le32 start_lba_lo; /*20h */
1318 __le32 start_lba_hi; /*24h */
1320 union megasas_sgl sgl; /*28h */
1322 } __attribute__ ((packed));
1324 struct megasas_pthru_frame {
1327 u8 sense_len; /*01h */
1328 u8 cmd_status; /*02h */
1329 u8 scsi_status; /*03h */
1331 u8 target_id; /*04h */
1333 u8 cdb_len; /*06h */
1334 u8 sge_count; /*07h */
1336 __le32 context; /*08h */
1337 __le32 pad_0; /*0Ch */
1339 __le16 flags; /*10h */
1340 __le16 timeout; /*12h */
1341 __le32 data_xfer_len; /*14h */
1343 __le32 sense_buf_phys_addr_lo; /*18h */
1344 __le32 sense_buf_phys_addr_hi; /*1Ch */
1346 u8 cdb[16]; /*20h */
1347 union megasas_sgl sgl; /*30h */
1349 } __attribute__ ((packed));
1351 struct megasas_dcmd_frame {
1354 u8 reserved_0; /*01h */
1355 u8 cmd_status; /*02h */
1356 u8 reserved_1[4]; /*03h */
1357 u8 sge_count; /*07h */
1359 __le32 context; /*08h */
1360 __le32 pad_0; /*0Ch */
1362 __le16 flags; /*10h */
1363 __le16 timeout; /*12h */
1365 __le32 data_xfer_len; /*14h */
1366 __le32 opcode; /*18h */
1374 union megasas_sgl sgl; /*28h */
1376 } __attribute__ ((packed));
1378 struct megasas_abort_frame {
1381 u8 reserved_0; /*01h */
1382 u8 cmd_status; /*02h */
1384 u8 reserved_1; /*03h */
1385 __le32 reserved_2; /*04h */
1387 __le32 context; /*08h */
1388 __le32 pad_0; /*0Ch */
1390 __le16 flags; /*10h */
1391 __le16 reserved_3; /*12h */
1392 __le32 reserved_4; /*14h */
1394 __le32 abort_context; /*18h */
1395 __le32 pad_1; /*1Ch */
1397 __le32 abort_mfi_phys_addr_lo; /*20h */
1398 __le32 abort_mfi_phys_addr_hi; /*24h */
1400 __le32 reserved_5[6]; /*28h */
1402 } __attribute__ ((packed));
1404 struct megasas_smp_frame {
1407 u8 reserved_1; /*01h */
1408 u8 cmd_status; /*02h */
1409 u8 connection_status; /*03h */
1411 u8 reserved_2[3]; /*04h */
1412 u8 sge_count; /*07h */
1414 __le32 context; /*08h */
1415 __le32 pad_0; /*0Ch */
1417 __le16 flags; /*10h */
1418 __le16 timeout; /*12h */
1420 __le32 data_xfer_len; /*14h */
1421 __le64 sas_addr; /*18h */
1424 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1425 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1428 } __attribute__ ((packed));
1430 struct megasas_stp_frame {
1433 u8 reserved_1; /*01h */
1434 u8 cmd_status; /*02h */
1435 u8 reserved_2; /*03h */
1437 u8 target_id; /*04h */
1438 u8 reserved_3[2]; /*05h */
1439 u8 sge_count; /*07h */
1441 __le32 context; /*08h */
1442 __le32 pad_0; /*0Ch */
1444 __le16 flags; /*10h */
1445 __le16 timeout; /*12h */
1447 __le32 data_xfer_len; /*14h */
1449 __le16 fis[10]; /*18h */
1453 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1454 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1457 } __attribute__ ((packed));
1459 union megasas_frame {
1461 struct megasas_header hdr;
1462 struct megasas_init_frame init;
1463 struct megasas_io_frame io;
1464 struct megasas_pthru_frame pthru;
1465 struct megasas_dcmd_frame dcmd;
1466 struct megasas_abort_frame abort;
1467 struct megasas_smp_frame smp;
1468 struct megasas_stp_frame stp;
1475 union megasas_evt_class_locale {
1478 #ifndef __BIG_ENDIAN_BITFIELD
1487 } __attribute__ ((packed)) members;
1491 } __attribute__ ((packed));
1493 struct megasas_evt_log_info {
1494 __le32 newest_seq_num;
1495 __le32 oldest_seq_num;
1496 __le32 clear_seq_num;
1497 __le32 shutdown_seq_num;
1498 __le32 boot_seq_num;
1500 } __attribute__ ((packed));
1502 struct megasas_progress {
1505 __le16 elapsed_seconds;
1507 } __attribute__ ((packed));
1509 struct megasas_evtarg_ld {
1515 } __attribute__ ((packed));
1517 struct megasas_evtarg_pd {
1522 } __attribute__ ((packed));
1524 struct megasas_evt_detail {
1529 union megasas_evt_class_locale cl;
1535 struct megasas_evtarg_pd pd;
1541 } __attribute__ ((packed)) cdbSense;
1543 struct megasas_evtarg_ld ld;
1546 struct megasas_evtarg_ld ld;
1548 } __attribute__ ((packed)) ld_count;
1552 struct megasas_evtarg_ld ld;
1553 } __attribute__ ((packed)) ld_lba;
1556 struct megasas_evtarg_ld ld;
1559 } __attribute__ ((packed)) ld_owner;
1564 struct megasas_evtarg_ld ld;
1565 struct megasas_evtarg_pd pd;
1566 } __attribute__ ((packed)) ld_lba_pd_lba;
1569 struct megasas_evtarg_ld ld;
1570 struct megasas_progress prog;
1571 } __attribute__ ((packed)) ld_prog;
1574 struct megasas_evtarg_ld ld;
1577 } __attribute__ ((packed)) ld_state;
1581 struct megasas_evtarg_ld ld;
1582 } __attribute__ ((packed)) ld_strip;
1584 struct megasas_evtarg_pd pd;
1587 struct megasas_evtarg_pd pd;
1589 } __attribute__ ((packed)) pd_err;
1593 struct megasas_evtarg_pd pd;
1594 } __attribute__ ((packed)) pd_lba;
1598 struct megasas_evtarg_pd pd;
1599 struct megasas_evtarg_ld ld;
1600 } __attribute__ ((packed)) pd_lba_ld;
1603 struct megasas_evtarg_pd pd;
1604 struct megasas_progress prog;
1605 } __attribute__ ((packed)) pd_prog;
1608 struct megasas_evtarg_pd pd;
1611 } __attribute__ ((packed)) pd_state;
1618 } __attribute__ ((packed)) pci;
1626 } __attribute__ ((packed)) time;
1632 } __attribute__ ((packed)) ecc;
1640 char description[128];
1642 } __attribute__ ((packed));
1644 struct megasas_aen_event {
1645 struct delayed_work hotplug_work;
1646 struct megasas_instance *instance;
1649 struct megasas_irq_context {
1650 struct megasas_instance *instance;
1654 struct MR_DRV_SYSTEM_INFO {
1662 struct megasas_instance {
1665 dma_addr_t producer_h;
1667 dma_addr_t consumer_h;
1668 struct MR_DRV_SYSTEM_INFO *system_info_buf;
1669 dma_addr_t system_info_h;
1670 struct MR_LD_VF_AFFILIATION *vf_affiliation;
1671 dma_addr_t vf_affiliation_h;
1672 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
1673 dma_addr_t vf_affiliation_111_h;
1674 struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
1675 dma_addr_t hb_host_mem_h;
1677 __le32 *reply_queue;
1678 dma_addr_t reply_queue_h;
1680 u32 *crash_dump_buf;
1681 dma_addr_t crash_dump_h;
1682 void *crash_buf[MAX_CRASH_DUMP_SIZE];
1683 u32 crash_buf_pages;
1684 unsigned int fw_crash_buffer_size;
1685 unsigned int fw_crash_state;
1686 unsigned int fw_crash_buffer_offset;
1689 u32 crash_dump_fw_support;
1690 u32 crash_dump_drv_support;
1691 u32 crash_dump_app_support;
1692 u32 secure_jbod_support;
1693 spinlock_t crashdump_lock;
1695 struct megasas_register_set __iomem *reg_set;
1696 u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
1697 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
1698 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD];
1699 u8 ld_ids[MEGASAS_MAX_LD_IDS];
1706 u32 max_sectors_per_req;
1707 struct megasas_aen_event *ev;
1709 struct megasas_cmd **cmd_list;
1710 struct list_head cmd_pool;
1711 /* used to sync fire the cmd to fw */
1712 spinlock_t mfi_pool_lock;
1713 /* used to sync fire the cmd to fw */
1714 spinlock_t hba_lock;
1715 /* used to synch producer, consumer ptrs in dpc */
1716 spinlock_t completion_lock;
1717 struct dma_pool *frame_dma_pool;
1718 struct dma_pool *sense_dma_pool;
1720 struct megasas_evt_detail *evt_detail;
1721 dma_addr_t evt_detail_h;
1722 struct megasas_cmd *aen_cmd;
1723 struct mutex aen_mutex;
1724 struct semaphore ioctl_sem;
1726 struct Scsi_Host *host;
1728 wait_queue_head_t int_cmd_wait_q;
1729 wait_queue_head_t abort_cmd_wait_q;
1731 struct pci_dev *pdev;
1733 u32 fw_support_ieee;
1735 atomic_t fw_outstanding;
1736 atomic_t fw_reset_no_pci_access;
1738 struct megasas_instance_template *instancet;
1739 struct tasklet_struct isr_tasklet;
1740 struct work_struct work_init;
1741 struct work_struct crash_init;
1747 u8 disableOnlineCtrlReset;
1748 u8 UnevenSpanSupport;
1751 u16 fw_supported_vd_count;
1752 u16 fw_supported_pd_count;
1754 u16 drv_supported_vd_count;
1755 u16 drv_supported_pd_count;
1758 unsigned long last_time;
1762 struct list_head internal_reset_pending_q;
1764 /* Ptr to hba specific information */
1766 u32 ctrl_context_pages;
1767 struct megasas_ctrl_info *ctrl_info;
1768 unsigned int msix_vectors;
1769 struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1770 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
1772 struct megasas_cmd *map_update_cmd;
1775 struct mutex reset_mutex;
1776 struct timer_list sriov_heartbeat_timer;
1777 char skip_heartbeat_timer_del;
1781 u16 throttlequeuedepth;
1786 struct MR_LD_VF_MAP {
1788 union MR_LD_REF ref;
1794 struct MR_LD_VF_AFFILIATION {
1800 struct MR_LD_VF_MAP map[1];
1803 /* Plasma 1.11 FW backward compatibility structures */
1804 #define IOV_111_OFFSET 0x7CE
1805 #define MAX_VIRTUAL_FUNCTIONS 8
1806 #define MR_LD_ACCESS_HIDDEN 15
1815 struct MR_LD_VF_MAP_111 {
1818 u8 policy[MAX_VIRTUAL_FUNCTIONS];
1821 struct MR_LD_VF_AFFILIATION_111 {
1826 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
1829 struct MR_CTRL_HB_HOST_MEM {
1831 u32 fwCounter; /* Firmware heart beat counter */
1833 u32 debugmode:1; /* 1=Firmware is in debug mode.
1834 Heart beat will not be updated. */
1838 u32 driverCounter; /* Driver heart beat counter. 0x20 */
1839 u32 reserved_driver[7];
1845 MEGASAS_HBA_OPERATIONAL = 0,
1846 MEGASAS_ADPRESET_SM_INFAULT = 1,
1847 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1848 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1849 MEGASAS_HW_CRITICAL_ERROR = 4,
1850 MEGASAS_ADPRESET_SM_POLLING = 5,
1851 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1854 struct megasas_instance_template {
1855 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1856 u32, struct megasas_register_set __iomem *);
1858 void (*enable_intr)(struct megasas_instance *);
1859 void (*disable_intr)(struct megasas_instance *);
1861 int (*clear_intr)(struct megasas_register_set __iomem *);
1863 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1864 int (*adp_reset)(struct megasas_instance *, \
1865 struct megasas_register_set __iomem *);
1866 int (*check_reset)(struct megasas_instance *, \
1867 struct megasas_register_set __iomem *);
1868 irqreturn_t (*service_isr)(int irq, void *devp);
1869 void (*tasklet)(unsigned long);
1870 u32 (*init_adapter)(struct megasas_instance *);
1871 u32 (*build_and_issue_cmd) (struct megasas_instance *,
1872 struct scsi_cmnd *);
1873 void (*issue_dcmd) (struct megasas_instance *instance,
1874 struct megasas_cmd *cmd);
1877 #define MEGASAS_IS_LOGICAL(scp) \
1878 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1880 #define MEGASAS_DEV_INDEX(scp) \
1881 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1884 #define MEGASAS_PD_INDEX(scp) \
1885 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1888 struct megasas_cmd {
1890 union megasas_frame *frame;
1891 dma_addr_t frame_phys_addr;
1893 dma_addr_t sense_phys_addr;
1899 u8 retry_for_fw_reset;
1902 struct list_head list;
1903 struct scsi_cmnd *scmd;
1906 struct megasas_instance *instance;
1916 #define MAX_MGMT_ADAPTERS 1024
1917 #define MAX_IOCTL_SGE 16
1919 struct megasas_iocpacket {
1929 struct megasas_header hdr;
1932 struct iovec sgl[MAX_IOCTL_SGE];
1934 } __attribute__ ((packed));
1936 struct megasas_aen {
1940 u32 class_locale_word;
1941 } __attribute__ ((packed));
1943 #ifdef CONFIG_COMPAT
1944 struct compat_megasas_iocpacket {
1953 struct megasas_header hdr;
1955 struct compat_iovec sgl[MAX_IOCTL_SGE];
1956 } __attribute__ ((packed));
1958 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
1961 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
1962 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1964 struct megasas_mgmt_info {
1967 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1972 MR_BuildRaidContext(struct megasas_instance *instance,
1973 struct IO_REQUEST_INFO *io_info,
1974 struct RAID_CONTEXT *pRAID_Context,
1975 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
1976 u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
1977 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
1978 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
1979 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
1980 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
1981 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
1983 __le16 get_updated_dev_handle(struct megasas_instance *instance,
1984 struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info);
1985 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
1986 struct LD_LOAD_BALANCE_INFO *lbInfo);
1987 int megasas_get_ctrl_info(struct megasas_instance *instance);
1988 int megasas_set_crash_dump_params(struct megasas_instance *instance,
1989 u8 crash_buf_state);
1990 void megasas_free_host_crash_buffer(struct megasas_instance *instance);
1991 void megasas_fusion_crash_dump_wq(struct work_struct *work);
1993 void megasas_return_cmd_fusion(struct megasas_instance *instance,
1994 struct megasas_cmd_fusion *cmd);
1995 int megasas_issue_blocked_cmd(struct megasas_instance *instance,
1996 struct megasas_cmd *cmd, int timeout);
1997 void __megasas_return_cmd(struct megasas_instance *instance,
1998 struct megasas_cmd *cmd);
2000 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2001 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
2002 int megasas_cmd_type(struct scsi_cmnd *cmd);
2004 #endif /*LSI_MEGARAID_SAS_H */