2 * Linux MegaRAID driver for SAS based RAID controllers
4 * Copyright (c) 2003-2013 LSI Corporation
5 * Copyright (c) 2013-2014 Avago Technologies
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 * FILE: megaraid_sas.h
22 * Authors: Avago Technologies
23 * Kashyap Desai <kashyap.desai@avagotech.com>
24 * Sumit Saxena <sumit.saxena@avagotech.com>
26 * Send feedback to: megaraidlinux.pdl@avagotech.com
28 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
29 * San Jose, California 95131
32 #ifndef LSI_MEGARAID_SAS_H
33 #define LSI_MEGARAID_SAS_H
36 * MegaRAID SAS Driver meta data
38 #define MEGASAS_VERSION "06.808.14.00-rc1"
39 #define MEGASAS_RELDATE "Jul 31, 2015"
44 #define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
45 #define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
46 #define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
47 #define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
48 #define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
49 #define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
50 #define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
51 #define PCI_DEVICE_ID_LSI_FUSION 0x005b
52 #define PCI_DEVICE_ID_LSI_PLASMA 0x002f
53 #define PCI_DEVICE_ID_LSI_INVADER 0x005d
54 #define PCI_DEVICE_ID_LSI_FURY 0x005f
55 #define PCI_DEVICE_ID_LSI_INTRUDER 0x00ce
56 #define PCI_DEVICE_ID_LSI_INTRUDER_24 0x00cf
57 #define PCI_DEVICE_ID_LSI_CUTLASS_52 0x0052
58 #define PCI_DEVICE_ID_LSI_CUTLASS_53 0x0053
63 #define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
64 #define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
65 #define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
66 #define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
67 #define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
68 #define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
69 #define MEGARAID_INTEL_RMS3BC160_SSDID 0x352B
74 #define MEGARAID_INTRUDER_SSDID1 0x9371
75 #define MEGARAID_INTRUDER_SSDID2 0x9390
76 #define MEGARAID_INTRUDER_SSDID3 0x9370
81 #define MEGARAID_INTEL_RS3DC080_BRANDING \
82 "Intel(R) RAID Controller RS3DC080"
83 #define MEGARAID_INTEL_RS3DC040_BRANDING \
84 "Intel(R) RAID Controller RS3DC040"
85 #define MEGARAID_INTEL_RS3SC008_BRANDING \
86 "Intel(R) RAID Controller RS3SC008"
87 #define MEGARAID_INTEL_RS3MC044_BRANDING \
88 "Intel(R) RAID Controller RS3MC044"
89 #define MEGARAID_INTEL_RS3WC080_BRANDING \
90 "Intel(R) RAID Controller RS3WC080"
91 #define MEGARAID_INTEL_RS3WC040_BRANDING \
92 "Intel(R) RAID Controller RS3WC040"
93 #define MEGARAID_INTEL_RMS3BC160_BRANDING \
94 "Intel(R) Integrated RAID Module RMS3BC160"
97 * =====================================
98 * MegaRAID SAS MFI firmware definitions
99 * =====================================
103 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
104 * protocol between the software and firmware. Commands are issued using
109 * FW posts its state in upper 4 bits of outbound_msg_0 register
111 #define MFI_STATE_MASK 0xF0000000
112 #define MFI_STATE_UNDEFINED 0x00000000
113 #define MFI_STATE_BB_INIT 0x10000000
114 #define MFI_STATE_FW_INIT 0x40000000
115 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000
116 #define MFI_STATE_FW_INIT_2 0x70000000
117 #define MFI_STATE_DEVICE_SCAN 0x80000000
118 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
119 #define MFI_STATE_FLUSH_CACHE 0xA0000000
120 #define MFI_STATE_READY 0xB0000000
121 #define MFI_STATE_OPERATIONAL 0xC0000000
122 #define MFI_STATE_FAULT 0xF0000000
123 #define MFI_STATE_FORCE_OCR 0x00000080
124 #define MFI_STATE_DMADONE 0x00000008
125 #define MFI_STATE_CRASH_DUMP_DONE 0x00000004
126 #define MFI_RESET_REQUIRED 0x00000001
127 #define MFI_RESET_ADAPTER 0x00000002
128 #define MEGAMFI_FRAME_SIZE 64
131 * During FW init, clear pending cmds & reset state using inbound_msg_0
133 * ABORT : Abort all pending cmds
134 * READY : Move from OPERATIONAL to READY state; discard queue info
135 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
136 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
137 * HOTPLUG : Resume from Hotplug
138 * MFI_STOP_ADP : Send signal to FW to stop processing
140 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
141 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
142 #define DIAG_WRITE_ENABLE (0x00000080)
143 #define DIAG_RESET_ADAPTER (0x00000004)
145 #define MFI_ADP_RESET 0x00000040
146 #define MFI_INIT_ABORT 0x00000001
147 #define MFI_INIT_READY 0x00000002
148 #define MFI_INIT_MFIMODE 0x00000004
149 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
150 #define MFI_INIT_HOTPLUG 0x00000010
151 #define MFI_STOP_ADP 0x00000020
152 #define MFI_RESET_FLAGS MFI_INIT_READY| \
159 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
160 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
161 #define MFI_FRAME_SGL32 0x0000
162 #define MFI_FRAME_SGL64 0x0002
163 #define MFI_FRAME_SENSE32 0x0000
164 #define MFI_FRAME_SENSE64 0x0004
165 #define MFI_FRAME_DIR_NONE 0x0000
166 #define MFI_FRAME_DIR_WRITE 0x0008
167 #define MFI_FRAME_DIR_READ 0x0010
168 #define MFI_FRAME_DIR_BOTH 0x0018
169 #define MFI_FRAME_IEEE 0x0020
171 /* Driver internal */
172 #define DRV_DCMD_POLLED_MODE 0x1
175 * Definition for cmd_status
177 #define MFI_CMD_STATUS_POLL_MODE 0xFF
180 * MFI command opcodes
182 #define MFI_CMD_INIT 0x00
183 #define MFI_CMD_LD_READ 0x01
184 #define MFI_CMD_LD_WRITE 0x02
185 #define MFI_CMD_LD_SCSI_IO 0x03
186 #define MFI_CMD_PD_SCSI_IO 0x04
187 #define MFI_CMD_DCMD 0x05
188 #define MFI_CMD_ABORT 0x06
189 #define MFI_CMD_SMP 0x07
190 #define MFI_CMD_STP 0x08
191 #define MFI_CMD_INVALID 0xff
193 #define MR_DCMD_CTRL_GET_INFO 0x01010000
194 #define MR_DCMD_LD_GET_LIST 0x03010000
195 #define MR_DCMD_LD_LIST_QUERY 0x03010100
197 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
198 #define MR_FLUSH_CTRL_CACHE 0x01
199 #define MR_FLUSH_DISK_CACHE 0x02
201 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000
202 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
203 #define MR_ENABLE_DRIVE_SPINDOWN 0x01
205 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
206 #define MR_DCMD_CTRL_EVENT_GET 0x01040300
207 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
208 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000
210 #define MR_DCMD_CLUSTER 0x08000000
211 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
212 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200
213 #define MR_DCMD_PD_LIST_QUERY 0x02010100
215 #define MR_DCMD_CTRL_SET_CRASH_DUMP_PARAMS 0x01190100
216 #define MR_DRIVER_SET_APP_CRASHDUMP_MODE (0xF0010000 | 0x0600)
221 extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
225 * MFI command completion codes
229 MFI_STAT_INVALID_CMD = 0x01,
230 MFI_STAT_INVALID_DCMD = 0x02,
231 MFI_STAT_INVALID_PARAMETER = 0x03,
232 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
233 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
234 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
235 MFI_STAT_APP_IN_USE = 0x07,
236 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
237 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
238 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
239 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
240 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
241 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
242 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
243 MFI_STAT_FLASH_BUSY = 0x0f,
244 MFI_STAT_FLASH_ERROR = 0x10,
245 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
246 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
247 MFI_STAT_FLASH_NOT_OPEN = 0x13,
248 MFI_STAT_FLASH_NOT_STARTED = 0x14,
249 MFI_STAT_FLUSH_FAILED = 0x15,
250 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
251 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
252 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
253 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
254 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
255 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
256 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
257 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
258 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
259 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
260 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
261 MFI_STAT_MFC_HW_ERROR = 0x21,
262 MFI_STAT_NO_HW_PRESENT = 0x22,
263 MFI_STAT_NOT_FOUND = 0x23,
264 MFI_STAT_NOT_IN_ENCL = 0x24,
265 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
266 MFI_STAT_PD_TYPE_WRONG = 0x26,
267 MFI_STAT_PR_DISABLED = 0x27,
268 MFI_STAT_ROW_INDEX_INVALID = 0x28,
269 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
270 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
271 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
272 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
273 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
274 MFI_STAT_SCSI_IO_FAILED = 0x2e,
275 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
276 MFI_STAT_SHUTDOWN_FAILED = 0x30,
277 MFI_STAT_TIME_NOT_SET = 0x31,
278 MFI_STAT_WRONG_STATE = 0x32,
279 MFI_STAT_LD_OFFLINE = 0x33,
280 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
281 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
282 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
283 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
284 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
285 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
287 MFI_STAT_INVALID_STATUS = 0xFF
291 MFI_EVT_CLASS_DEBUG = -2,
292 MFI_EVT_CLASS_PROGRESS = -1,
293 MFI_EVT_CLASS_INFO = 0,
294 MFI_EVT_CLASS_WARNING = 1,
295 MFI_EVT_CLASS_CRITICAL = 2,
296 MFI_EVT_CLASS_FATAL = 3,
297 MFI_EVT_CLASS_DEAD = 4
301 * Crash dump related defines
303 #define MAX_CRASH_DUMP_SIZE 512
304 #define CRASH_DMA_BUF_SIZE (1024 * 1024)
306 enum MR_FW_CRASH_DUMP_STATE {
314 enum _MR_CRASH_BUF_STATUS {
315 MR_CRASH_BUF_TURN_OFF = 0,
316 MR_CRASH_BUF_TURN_ON = 1,
320 * Number of mailbox bytes in DCMD message frame
322 #define MFI_MBOX_SIZE 12
326 MR_EVT_CLASS_DEBUG = -2,
327 MR_EVT_CLASS_PROGRESS = -1,
328 MR_EVT_CLASS_INFO = 0,
329 MR_EVT_CLASS_WARNING = 1,
330 MR_EVT_CLASS_CRITICAL = 2,
331 MR_EVT_CLASS_FATAL = 3,
332 MR_EVT_CLASS_DEAD = 4,
338 MR_EVT_LOCALE_LD = 0x0001,
339 MR_EVT_LOCALE_PD = 0x0002,
340 MR_EVT_LOCALE_ENCL = 0x0004,
341 MR_EVT_LOCALE_BBU = 0x0008,
342 MR_EVT_LOCALE_SAS = 0x0010,
343 MR_EVT_LOCALE_CTRL = 0x0020,
344 MR_EVT_LOCALE_CONFIG = 0x0040,
345 MR_EVT_LOCALE_CLUSTER = 0x0080,
346 MR_EVT_LOCALE_ALL = 0xffff,
353 MR_EVT_ARGS_CDB_SENSE,
355 MR_EVT_ARGS_LD_COUNT,
357 MR_EVT_ARGS_LD_OWNER,
358 MR_EVT_ARGS_LD_LBA_PD_LBA,
360 MR_EVT_ARGS_LD_STATE,
361 MR_EVT_ARGS_LD_STRIP,
365 MR_EVT_ARGS_PD_LBA_LD,
367 MR_EVT_ARGS_PD_STATE,
374 MR_EVT_ARGS_PD_SPARE,
375 MR_EVT_ARGS_PD_INDEX,
376 MR_EVT_ARGS_DIAG_PASS,
377 MR_EVT_ARGS_DIAG_FAIL,
378 MR_EVT_ARGS_PD_LBA_LBA,
379 MR_EVT_ARGS_PORT_PHY,
380 MR_EVT_ARGS_PD_MISSING,
381 MR_EVT_ARGS_PD_ADDRESS,
383 MR_EVT_ARGS_CONNECTOR,
386 MR_EVT_ARGS_PD_PATHINFO,
387 MR_EVT_ARGS_PD_POWER_STATE,
392 * define constants for device list query options
394 enum MR_PD_QUERY_TYPE {
395 MR_PD_QUERY_TYPE_ALL = 0,
396 MR_PD_QUERY_TYPE_STATE = 1,
397 MR_PD_QUERY_TYPE_POWER_STATE = 2,
398 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
399 MR_PD_QUERY_TYPE_SPEED = 4,
400 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
403 enum MR_LD_QUERY_TYPE {
404 MR_LD_QUERY_TYPE_ALL = 0,
405 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
406 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
407 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
408 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
412 #define MR_EVT_CFG_CLEARED 0x0004
413 #define MR_EVT_LD_STATE_CHANGE 0x0051
414 #define MR_EVT_PD_INSERTED 0x005b
415 #define MR_EVT_PD_REMOVED 0x0070
416 #define MR_EVT_LD_CREATED 0x008a
417 #define MR_EVT_LD_DELETED 0x008b
418 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
419 #define MR_EVT_LD_OFFLINE 0x00fc
420 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
423 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
424 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
425 MR_PD_STATE_HOT_SPARE = 0x02,
426 MR_PD_STATE_OFFLINE = 0x10,
427 MR_PD_STATE_FAILED = 0x11,
428 MR_PD_STATE_REBUILD = 0x14,
429 MR_PD_STATE_ONLINE = 0x18,
430 MR_PD_STATE_COPYBACK = 0x20,
431 MR_PD_STATE_SYSTEM = 0x40,
436 * defines the physical drive address structure
438 struct MR_PD_ADDRESS {
449 u8 enclConnectorIndex;
454 u8 connectedPortBitmap;
455 u8 connectedPortNumbers;
461 * defines the physical drive list structure
466 struct MR_PD_ADDRESS addr[1];
469 struct megasas_pd_list {
476 * defines the logical drive reference structure
488 * defines the logical drive list structure
498 } ldList[MAX_LOGICAL_DRIVES_EXT];
501 struct MR_LD_TARGETID_LIST {
505 u8 targetId[MAX_LOGICAL_DRIVES_EXT];
510 * SAS controller properties
512 struct megasas_ctrl_prop {
515 u16 pred_fail_poll_interval;
516 u16 intr_throttle_count;
517 u16 intr_throttle_timeouts;
523 u8 cache_flush_interval;
529 u8 disable_auto_rebuild;
530 u8 disable_battery_warn;
532 u16 ecc_bucket_leak_rate;
533 u8 restore_hotspare_on_insertion;
534 u8 expose_encl_devices;
535 u8 maintainPdFailHistory;
536 u8 disallowHostRequestReordering;
539 u8 disableAutoDetectBackplane;
544 * Add properties that can be controlled by
545 * a bit in the following structure.
548 #if defined(__BIG_ENDIAN_BITFIELD)
551 u32 disableSpinDownHS:1;
552 u32 allowBootWithPinnedCache:1;
553 u32 disableOnlineCtrlReset:1;
554 u32 enableSecretKeyControl:1;
555 u32 autoEnhancedImport:1;
556 u32 enableSpinDownUnconfigured:1;
557 u32 SSDPatrolReadEnabled:1;
558 u32 SSDSMARTerEnabled:1;
561 u32 prCorrectUnconfiguredAreas:1;
562 u32 SMARTerEnabled:1;
563 u32 copyBackDisabled:1;
565 u32 copyBackDisabled:1;
566 u32 SMARTerEnabled:1;
567 u32 prCorrectUnconfiguredAreas:1;
570 u32 SSDSMARTerEnabled:1;
571 u32 SSDPatrolReadEnabled:1;
572 u32 enableSpinDownUnconfigured:1;
573 u32 autoEnhancedImport:1;
574 u32 enableSecretKeyControl:1;
575 u32 disableOnlineCtrlReset:1;
576 u32 allowBootWithPinnedCache:1;
577 u32 disableSpinDownHS:1;
589 * SAS controller information
591 struct megasas_ctrl_info {
594 * PCI device information
600 __le16 sub_vendor_id;
601 __le16 sub_device_id;
604 } __attribute__ ((packed)) pci;
607 * Host interface information
621 } __attribute__ ((packed)) host_interface;
624 * Device (backend) interface information
637 } __attribute__ ((packed)) device_interface;
640 * List of components residing in flash. All str are null terminated
642 __le32 image_check_word;
643 __le32 image_component_count;
652 } __attribute__ ((packed)) image_component[8];
655 * List of flash components that have been flashed on the card, but
656 * are not in use, pending reset of the adapter. This list will be
657 * empty if a flash operation has not occurred. All stings are null
660 __le32 pending_image_component_count;
669 } __attribute__ ((packed)) pending_image_component[8];
676 char product_name[80];
680 * Other physical/controller/operation information. Indicates the
681 * presence of the hardware
691 } __attribute__ ((packed)) hw_present;
693 __le32 current_fw_time;
696 * Maximum data transfer sizes
698 __le16 max_concurrent_cmds;
699 __le16 max_sge_count;
700 __le32 max_request_size;
703 * Logical and physical device counts
705 __le16 ld_present_count;
706 __le16 ld_degraded_count;
707 __le16 ld_offline_count;
709 __le16 pd_present_count;
710 __le16 pd_disk_present_count;
711 __le16 pd_disk_pred_failure_count;
712 __le16 pd_disk_failed_count;
715 * Memory size information
724 __le16 mem_correctable_error_count;
725 __le16 mem_uncorrectable_error_count;
728 * Cluster information
730 u8 cluster_permitted;
734 * Additional max data transfer sizes
736 __le16 max_strips_per_io;
739 * Controller capabilities structures
750 } __attribute__ ((packed)) raid_levels;
760 u32 cluster_supported:1;
762 u32 spanning_allowed:1;
763 u32 dedicated_hotspares:1;
764 u32 revertible_hotspares:1;
765 u32 foreign_config_import:1;
766 u32 self_diagnostic:1;
767 u32 mixed_redundancy_arr:1;
768 u32 global_hot_spares:1;
771 } __attribute__ ((packed)) adapter_operations;
779 u32 disk_cache_policy:1;
782 } __attribute__ ((packed)) ld_operations;
790 } __attribute__ ((packed)) stripe_sz_ops;
799 } __attribute__ ((packed)) pd_operations;
803 u32 ctrl_supports_sas:1;
804 u32 ctrl_supports_sata:1;
805 u32 allow_mix_in_encl:1;
806 u32 allow_mix_in_ld:1;
807 u32 allow_sata_in_cluster:1;
810 } __attribute__ ((packed)) pd_mix_support;
813 * Define ECC single-bit-error bucket information
819 * Include the controller properties (changeable items)
821 struct megasas_ctrl_prop properties;
824 * Define FW pkg version (set in envt v'bles on OEM basis)
826 char package_version[0x60];
830 * If adapterOperations.supportMoreThan8Phys is set,
831 * and deviceInterface.portCount is greater than 8,
832 * SAS Addrs for first 8 ports shall be populated in
833 * deviceInterface.portAddr, and the rest shall be
834 * populated in deviceInterfacePortAddr2.
836 __le64 deviceInterfacePortAddr2[8]; /*6a0h */
837 u8 reserved3[128]; /*6e0h */
840 u16 minPdRaidLevel_0:4;
841 u16 maxPdRaidLevel_0:12;
843 u16 minPdRaidLevel_1:4;
844 u16 maxPdRaidLevel_1:12;
846 u16 minPdRaidLevel_5:4;
847 u16 maxPdRaidLevel_5:12;
849 u16 minPdRaidLevel_1E:4;
850 u16 maxPdRaidLevel_1E:12;
852 u16 minPdRaidLevel_6:4;
853 u16 maxPdRaidLevel_6:12;
855 u16 minPdRaidLevel_10:4;
856 u16 maxPdRaidLevel_10:12;
858 u16 minPdRaidLevel_50:4;
859 u16 maxPdRaidLevel_50:12;
861 u16 minPdRaidLevel_60:4;
862 u16 maxPdRaidLevel_60:12;
864 u16 minPdRaidLevel_1E_RLQ0:4;
865 u16 maxPdRaidLevel_1E_RLQ0:12;
867 u16 minPdRaidLevel_1E0_RLQ0:4;
868 u16 maxPdRaidLevel_1E0_RLQ0:12;
873 __le16 maxPds; /*780h */
874 __le16 maxDedHSPs; /*782h */
875 __le16 maxGlobalHSP; /*784h */
876 __le16 ddfSize; /*786h */
877 u8 maxLdsPerArray; /*788h */
878 u8 partitionsInDDF; /*789h */
879 u8 lockKeyBinding; /*78ah */
880 u8 maxPITsPerLd; /*78bh */
881 u8 maxViewsPerLd; /*78ch */
882 u8 maxTargetId; /*78dh */
883 __le16 maxBvlVdSize; /*78eh */
885 __le16 maxConfigurableSSCSize; /*790h */
886 __le16 currentSSCsize; /*792h */
888 char expanderFwVersion[12]; /*794h */
890 __le16 PFKTrialTimeRemaining; /*7A0h */
892 __le16 cacheMemorySize; /*7A2h */
895 #if defined(__BIG_ENDIAN_BITFIELD)
898 u32 supportConfigAutoBalance:1;
900 u32 supportDataLDonSSCArray:1;
901 u32 supportPointInTimeProgress:1;
902 u32 supportUnevenSpans:1;
903 u32 dedicatedHotSparesLimited:1;
905 u32 supportEmulatedDrives:1;
906 u32 supportResetNow:1;
907 u32 realTimeScheduler:1;
908 u32 supportSSDPatrolRead:1;
909 u32 supportPerfTuning:1;
910 u32 disableOnlinePFKChange:1;
912 u32 supportBootTimePFKChange:1;
913 u32 supportSetLinkSpeed:1;
914 u32 supportEmergencySpares:1;
915 u32 supportSuspendResumeBGops:1;
916 u32 blockSSDWriteCacheChange:1;
917 u32 supportShieldState:1;
918 u32 supportLdBBMInfo:1;
919 u32 supportLdPIType3:1;
920 u32 supportLdPIType2:1;
921 u32 supportLdPIType1:1;
922 u32 supportPIcontroller:1;
924 u32 supportPIcontroller:1;
925 u32 supportLdPIType1:1;
926 u32 supportLdPIType2:1;
927 u32 supportLdPIType3:1;
928 u32 supportLdBBMInfo:1;
929 u32 supportShieldState:1;
930 u32 blockSSDWriteCacheChange:1;
931 u32 supportSuspendResumeBGops:1;
932 u32 supportEmergencySpares:1;
933 u32 supportSetLinkSpeed:1;
934 u32 supportBootTimePFKChange:1;
936 u32 disableOnlinePFKChange:1;
937 u32 supportPerfTuning:1;
938 u32 supportSSDPatrolRead:1;
939 u32 realTimeScheduler:1;
941 u32 supportResetNow:1;
942 u32 supportEmulatedDrives:1;
944 u32 dedicatedHotSparesLimited:1;
947 u32 supportUnevenSpans:1;
948 u32 supportPointInTimeProgress:1;
949 u32 supportDataLDonSSCArray:1;
951 u32 supportConfigAutoBalance:1;
955 } adapterOperations2;
957 u8 driverVersion[32]; /*7A8h */
958 u8 maxDAPdCountSpinup60; /*7C8h */
959 u8 temperatureROC; /*7C9h */
960 u8 temperatureCtrl; /*7CAh */
961 u8 reserved4; /*7CBh */
962 __le16 maxConfigurablePds; /*7CCh */
965 u8 reserved5[2]; /*0x7CDh */
968 * HA cluster information
971 #if defined(__BIG_ENDIAN_BITFIELD)
973 u32 premiumFeatureMismatch:1;
974 u32 ctrlPropIncompatible:1;
975 u32 fwVersionMismatch:1;
976 u32 hwIncompatible:1;
977 u32 peerIsIncompatible:1;
981 u32 peerIsIncompatible:1;
982 u32 hwIncompatible:1;
983 u32 fwVersionMismatch:1;
984 u32 ctrlPropIncompatible:1;
985 u32 premiumFeatureMismatch:1;
990 char clusterId[16]; /*7D4h */
992 u8 maxVFsSupported; /*0x7E4*/
993 u8 numVFsEnabled; /*0x7E5*/
994 u8 requestorId; /*0x7E6 0:PF, 1:VF1, 2:VF2*/
995 u8 reserved; /*0x7E7*/
999 #if defined(__BIG_ENDIAN_BITFIELD)
1001 u32 useSeqNumJbodFP:1;
1002 u32 supportExtendedSSCSize:1;
1003 u32 supportDiskCacheSettingForSysPDs:1;
1004 u32 supportCPLDUpdate:1;
1005 u32 supportTTYLogCompression:1;
1006 u32 discardCacheDuringLDDelete:1;
1007 u32 supportSecurityonJBOD:1;
1008 u32 supportCacheBypassModes:1;
1009 u32 supportDisableSESMonitoring:1;
1010 u32 supportForceFlash:1;
1011 u32 supportNVDRAM:1;
1012 u32 supportDrvActivityLEDSetting:1;
1013 u32 supportAllowedOpsforDrvRemoval:1;
1014 u32 supportHOQRebuild:1;
1015 u32 supportForceTo512e:1;
1016 u32 supportNVCacheErase:1;
1017 u32 supportDebugQueue:1;
1018 u32 supportSwZone:1;
1019 u32 supportCrashDump:1;
1020 u32 supportMaxExtLDs:1;
1021 u32 supportT10RebuildAssist:1;
1022 u32 supportDisableImmediateIO:1;
1023 u32 supportThermalPollInterval:1;
1024 u32 supportPersonalityChange:2;
1026 u32 supportPersonalityChange:2;
1027 u32 supportThermalPollInterval:1;
1028 u32 supportDisableImmediateIO:1;
1029 u32 supportT10RebuildAssist:1;
1030 u32 supportMaxExtLDs:1;
1031 u32 supportCrashDump:1;
1032 u32 supportSwZone:1;
1033 u32 supportDebugQueue:1;
1034 u32 supportNVCacheErase:1;
1035 u32 supportForceTo512e:1;
1036 u32 supportHOQRebuild:1;
1037 u32 supportAllowedOpsforDrvRemoval:1;
1038 u32 supportDrvActivityLEDSetting:1;
1039 u32 supportNVDRAM:1;
1040 u32 supportForceFlash:1;
1041 u32 supportDisableSESMonitoring:1;
1042 u32 supportCacheBypassModes:1;
1043 u32 supportSecurityonJBOD:1;
1044 u32 discardCacheDuringLDDelete:1;
1045 u32 supportTTYLogCompression:1;
1046 u32 supportCPLDUpdate:1;
1047 u32 supportDiskCacheSettingForSysPDs:1;
1048 u32 supportExtendedSSCSize:1;
1049 u32 useSeqNumJbodFP:1;
1052 } adapterOperations3;
1054 u8 pad[0x800-0x7EC];
1058 * ===============================
1059 * MegaRAID SAS driver definitions
1060 * ===============================
1062 #define MEGASAS_MAX_PD_CHANNELS 2
1063 #define MEGASAS_MAX_LD_CHANNELS 2
1064 #define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
1065 MEGASAS_MAX_LD_CHANNELS)
1066 #define MEGASAS_MAX_DEV_PER_CHANNEL 128
1067 #define MEGASAS_DEFAULT_INIT_ID -1
1068 #define MEGASAS_MAX_LUN 8
1069 #define MEGASAS_DEFAULT_CMD_PER_LUN 256
1070 #define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
1071 MEGASAS_MAX_DEV_PER_CHANNEL)
1072 #define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
1073 MEGASAS_MAX_DEV_PER_CHANNEL)
1075 #define MEGASAS_MAX_SECTORS (2*1024)
1076 #define MEGASAS_MAX_SECTORS_IEEE (2*128)
1077 #define MEGASAS_DBG_LVL 1
1079 #define MEGASAS_FW_BUSY 1
1081 #define VD_EXT_DEBUG 0
1084 enum MR_SCSI_CMD_TYPE {
1085 READ_WRITE_LDIO = 0,
1086 NON_READ_WRITE_LDIO = 1,
1087 READ_WRITE_SYSPDIO = 2,
1088 NON_READ_WRITE_SYSPDIO = 3,
1093 #define PTHRU_FRAME 1
1096 * When SCSI mid-layer calls driver's reset routine, driver waits for
1097 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
1098 * that the driver cannot _actually_ abort or reset pending commands. While
1099 * it is waiting for the commands to complete, it prints a diagnostic message
1100 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
1102 #define MEGASAS_RESET_WAIT_TIME 180
1103 #define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
1104 #define MEGASAS_RESET_NOTICE_INTERVAL 5
1105 #define MEGASAS_IOCTL_CMD 0
1106 #define MEGASAS_DEFAULT_CMD_TIMEOUT 90
1107 #define MEGASAS_THROTTLE_QUEUE_DEPTH 16
1108 #define MEGASAS_BLOCKED_CMD_TIMEOUT 60
1110 * FW reports the maximum of number of commands that it can accept (maximum
1111 * commands that can be outstanding) at any time. The driver must report a
1112 * lower number to the mid layer because it can issue a few internal commands
1113 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
1116 #define MEGASAS_INT_CMDS 32
1117 #define MEGASAS_SKINNY_INT_CMDS 5
1118 #define MEGASAS_FUSION_INTERNAL_CMDS 5
1119 #define MEGASAS_FUSION_IOCTL_CMDS 3
1120 #define MEGASAS_MFI_IOCTL_CMDS 27
1122 #define MEGASAS_MAX_MSIX_QUEUES 128
1124 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1125 * SGLs based on the size of dma_addr_t
1127 #define IS_DMA64 (sizeof(dma_addr_t) == 8)
1129 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
1131 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
1132 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
1133 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
1135 #define MFI_OB_INTR_STATUS_MASK 0x00000002
1136 #define MFI_POLL_TIMEOUT_SECS 60
1137 #define MEGASAS_SRIOV_HEARTBEAT_INTERVAL_VF (5 * HZ)
1138 #define MEGASAS_OCR_SETTLE_TIME_VF (1000 * 30)
1139 #define MEGASAS_ROUTINE_WAIT_TIME_VF 300
1140 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
1141 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
1142 #define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
1143 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
1144 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
1146 #define MFI_1068_PCSR_OFFSET 0x84
1147 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
1148 #define MFI_1068_FW_READY 0xDDDD0000
1150 #define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
1151 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
1152 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
1153 #define MR_MAX_MSIX_REG_ARRAY 16
1155 * register set for both 1068 and 1078 controllers
1156 * structure extended for 1078 registers
1159 struct megasas_register_set {
1160 u32 doorbell; /*0000h*/
1161 u32 fusion_seq_offset; /*0004h*/
1162 u32 fusion_host_diag; /*0008h*/
1163 u32 reserved_01; /*000Ch*/
1165 u32 inbound_msg_0; /*0010h*/
1166 u32 inbound_msg_1; /*0014h*/
1167 u32 outbound_msg_0; /*0018h*/
1168 u32 outbound_msg_1; /*001Ch*/
1170 u32 inbound_doorbell; /*0020h*/
1171 u32 inbound_intr_status; /*0024h*/
1172 u32 inbound_intr_mask; /*0028h*/
1174 u32 outbound_doorbell; /*002Ch*/
1175 u32 outbound_intr_status; /*0030h*/
1176 u32 outbound_intr_mask; /*0034h*/
1178 u32 reserved_1[2]; /*0038h*/
1180 u32 inbound_queue_port; /*0040h*/
1181 u32 outbound_queue_port; /*0044h*/
1183 u32 reserved_2[9]; /*0048h*/
1184 u32 reply_post_host_index; /*006Ch*/
1185 u32 reserved_2_2[12]; /*0070h*/
1187 u32 outbound_doorbell_clear; /*00A0h*/
1189 u32 reserved_3[3]; /*00A4h*/
1191 u32 outbound_scratch_pad ; /*00B0h*/
1192 u32 outbound_scratch_pad_2; /*00B4h*/
1194 u32 reserved_4[2]; /*00B8h*/
1196 u32 inbound_low_queue_port ; /*00C0h*/
1198 u32 inbound_high_queue_port ; /*00C4h*/
1200 u32 reserved_5; /*00C8h*/
1201 u32 res_6[11]; /*CCh*/
1204 u32 index_registers[807]; /*00CCh*/
1205 } __attribute__ ((packed));
1207 struct megasas_sge32 {
1212 } __attribute__ ((packed));
1214 struct megasas_sge64 {
1219 } __attribute__ ((packed));
1221 struct megasas_sge_skinny {
1229 struct megasas_sge32 sge32[1];
1230 struct megasas_sge64 sge64[1];
1231 struct megasas_sge_skinny sge_skinny[1];
1233 } __attribute__ ((packed));
1235 struct megasas_header {
1238 u8 sense_len; /*01h */
1239 u8 cmd_status; /*02h */
1240 u8 scsi_status; /*03h */
1242 u8 target_id; /*04h */
1244 u8 cdb_len; /*06h */
1245 u8 sge_count; /*07h */
1247 __le32 context; /*08h */
1248 __le32 pad_0; /*0Ch */
1250 __le16 flags; /*10h */
1251 __le16 timeout; /*12h */
1252 __le32 data_xferlen; /*14h */
1254 } __attribute__ ((packed));
1256 union megasas_sgl_frame {
1258 struct megasas_sge32 sge32[8];
1259 struct megasas_sge64 sge64[5];
1261 } __attribute__ ((packed));
1263 typedef union _MFI_CAPABILITIES {
1265 #if defined(__BIG_ENDIAN_BITFIELD)
1267 u32 support_ext_io_size:1;
1268 u32 support_ext_queue_depth:1;
1269 u32 security_protocol_cmds_fw:1;
1270 u32 support_core_affinity:1;
1271 u32 support_ndrive_r1_lb:1;
1272 u32 support_max_255lds:1;
1273 u32 support_fastpath_wb:1;
1274 u32 support_additional_msix:1;
1275 u32 support_fp_remote_lun:1;
1277 u32 support_fp_remote_lun:1;
1278 u32 support_additional_msix:1;
1279 u32 support_fastpath_wb:1;
1280 u32 support_max_255lds:1;
1281 u32 support_ndrive_r1_lb:1;
1282 u32 support_core_affinity:1;
1283 u32 security_protocol_cmds_fw:1;
1284 u32 support_ext_queue_depth:1;
1285 u32 support_ext_io_size:1;
1292 struct megasas_init_frame {
1295 u8 reserved_0; /*01h */
1296 u8 cmd_status; /*02h */
1298 u8 reserved_1; /*03h */
1299 MFI_CAPABILITIES driver_operations; /*04h*/
1301 __le32 context; /*08h */
1302 __le32 pad_0; /*0Ch */
1304 __le16 flags; /*10h */
1305 __le16 reserved_3; /*12h */
1306 __le32 data_xfer_len; /*14h */
1308 __le32 queue_info_new_phys_addr_lo; /*18h */
1309 __le32 queue_info_new_phys_addr_hi; /*1Ch */
1310 __le32 queue_info_old_phys_addr_lo; /*20h */
1311 __le32 queue_info_old_phys_addr_hi; /*24h */
1312 __le32 reserved_4[2]; /*28h */
1313 __le32 system_info_lo; /*30h */
1314 __le32 system_info_hi; /*34h */
1315 __le32 reserved_5[2]; /*38h */
1317 } __attribute__ ((packed));
1319 struct megasas_init_queue_info {
1321 __le32 init_flags; /*00h */
1322 __le32 reply_queue_entries; /*04h */
1324 __le32 reply_queue_start_phys_addr_lo; /*08h */
1325 __le32 reply_queue_start_phys_addr_hi; /*0Ch */
1326 __le32 producer_index_phys_addr_lo; /*10h */
1327 __le32 producer_index_phys_addr_hi; /*14h */
1328 __le32 consumer_index_phys_addr_lo; /*18h */
1329 __le32 consumer_index_phys_addr_hi; /*1Ch */
1331 } __attribute__ ((packed));
1333 struct megasas_io_frame {
1336 u8 sense_len; /*01h */
1337 u8 cmd_status; /*02h */
1338 u8 scsi_status; /*03h */
1340 u8 target_id; /*04h */
1341 u8 access_byte; /*05h */
1342 u8 reserved_0; /*06h */
1343 u8 sge_count; /*07h */
1345 __le32 context; /*08h */
1346 __le32 pad_0; /*0Ch */
1348 __le16 flags; /*10h */
1349 __le16 timeout; /*12h */
1350 __le32 lba_count; /*14h */
1352 __le32 sense_buf_phys_addr_lo; /*18h */
1353 __le32 sense_buf_phys_addr_hi; /*1Ch */
1355 __le32 start_lba_lo; /*20h */
1356 __le32 start_lba_hi; /*24h */
1358 union megasas_sgl sgl; /*28h */
1360 } __attribute__ ((packed));
1362 struct megasas_pthru_frame {
1365 u8 sense_len; /*01h */
1366 u8 cmd_status; /*02h */
1367 u8 scsi_status; /*03h */
1369 u8 target_id; /*04h */
1371 u8 cdb_len; /*06h */
1372 u8 sge_count; /*07h */
1374 __le32 context; /*08h */
1375 __le32 pad_0; /*0Ch */
1377 __le16 flags; /*10h */
1378 __le16 timeout; /*12h */
1379 __le32 data_xfer_len; /*14h */
1381 __le32 sense_buf_phys_addr_lo; /*18h */
1382 __le32 sense_buf_phys_addr_hi; /*1Ch */
1384 u8 cdb[16]; /*20h */
1385 union megasas_sgl sgl; /*30h */
1387 } __attribute__ ((packed));
1389 struct megasas_dcmd_frame {
1392 u8 reserved_0; /*01h */
1393 u8 cmd_status; /*02h */
1394 u8 reserved_1[4]; /*03h */
1395 u8 sge_count; /*07h */
1397 __le32 context; /*08h */
1398 __le32 pad_0; /*0Ch */
1400 __le16 flags; /*10h */
1401 __le16 timeout; /*12h */
1403 __le32 data_xfer_len; /*14h */
1404 __le32 opcode; /*18h */
1412 union megasas_sgl sgl; /*28h */
1414 } __attribute__ ((packed));
1416 struct megasas_abort_frame {
1419 u8 reserved_0; /*01h */
1420 u8 cmd_status; /*02h */
1422 u8 reserved_1; /*03h */
1423 __le32 reserved_2; /*04h */
1425 __le32 context; /*08h */
1426 __le32 pad_0; /*0Ch */
1428 __le16 flags; /*10h */
1429 __le16 reserved_3; /*12h */
1430 __le32 reserved_4; /*14h */
1432 __le32 abort_context; /*18h */
1433 __le32 pad_1; /*1Ch */
1435 __le32 abort_mfi_phys_addr_lo; /*20h */
1436 __le32 abort_mfi_phys_addr_hi; /*24h */
1438 __le32 reserved_5[6]; /*28h */
1440 } __attribute__ ((packed));
1442 struct megasas_smp_frame {
1445 u8 reserved_1; /*01h */
1446 u8 cmd_status; /*02h */
1447 u8 connection_status; /*03h */
1449 u8 reserved_2[3]; /*04h */
1450 u8 sge_count; /*07h */
1452 __le32 context; /*08h */
1453 __le32 pad_0; /*0Ch */
1455 __le16 flags; /*10h */
1456 __le16 timeout; /*12h */
1458 __le32 data_xfer_len; /*14h */
1459 __le64 sas_addr; /*18h */
1462 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1463 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1466 } __attribute__ ((packed));
1468 struct megasas_stp_frame {
1471 u8 reserved_1; /*01h */
1472 u8 cmd_status; /*02h */
1473 u8 reserved_2; /*03h */
1475 u8 target_id; /*04h */
1476 u8 reserved_3[2]; /*05h */
1477 u8 sge_count; /*07h */
1479 __le32 context; /*08h */
1480 __le32 pad_0; /*0Ch */
1482 __le16 flags; /*10h */
1483 __le16 timeout; /*12h */
1485 __le32 data_xfer_len; /*14h */
1487 __le16 fis[10]; /*18h */
1491 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1492 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1495 } __attribute__ ((packed));
1497 union megasas_frame {
1499 struct megasas_header hdr;
1500 struct megasas_init_frame init;
1501 struct megasas_io_frame io;
1502 struct megasas_pthru_frame pthru;
1503 struct megasas_dcmd_frame dcmd;
1504 struct megasas_abort_frame abort;
1505 struct megasas_smp_frame smp;
1506 struct megasas_stp_frame stp;
1513 union megasas_evt_class_locale {
1516 #ifndef __BIG_ENDIAN_BITFIELD
1525 } __attribute__ ((packed)) members;
1529 } __attribute__ ((packed));
1531 struct megasas_evt_log_info {
1532 __le32 newest_seq_num;
1533 __le32 oldest_seq_num;
1534 __le32 clear_seq_num;
1535 __le32 shutdown_seq_num;
1536 __le32 boot_seq_num;
1538 } __attribute__ ((packed));
1540 struct megasas_progress {
1543 __le16 elapsed_seconds;
1545 } __attribute__ ((packed));
1547 struct megasas_evtarg_ld {
1553 } __attribute__ ((packed));
1555 struct megasas_evtarg_pd {
1560 } __attribute__ ((packed));
1562 struct megasas_evt_detail {
1567 union megasas_evt_class_locale cl;
1573 struct megasas_evtarg_pd pd;
1579 } __attribute__ ((packed)) cdbSense;
1581 struct megasas_evtarg_ld ld;
1584 struct megasas_evtarg_ld ld;
1586 } __attribute__ ((packed)) ld_count;
1590 struct megasas_evtarg_ld ld;
1591 } __attribute__ ((packed)) ld_lba;
1594 struct megasas_evtarg_ld ld;
1597 } __attribute__ ((packed)) ld_owner;
1602 struct megasas_evtarg_ld ld;
1603 struct megasas_evtarg_pd pd;
1604 } __attribute__ ((packed)) ld_lba_pd_lba;
1607 struct megasas_evtarg_ld ld;
1608 struct megasas_progress prog;
1609 } __attribute__ ((packed)) ld_prog;
1612 struct megasas_evtarg_ld ld;
1615 } __attribute__ ((packed)) ld_state;
1619 struct megasas_evtarg_ld ld;
1620 } __attribute__ ((packed)) ld_strip;
1622 struct megasas_evtarg_pd pd;
1625 struct megasas_evtarg_pd pd;
1627 } __attribute__ ((packed)) pd_err;
1631 struct megasas_evtarg_pd pd;
1632 } __attribute__ ((packed)) pd_lba;
1636 struct megasas_evtarg_pd pd;
1637 struct megasas_evtarg_ld ld;
1638 } __attribute__ ((packed)) pd_lba_ld;
1641 struct megasas_evtarg_pd pd;
1642 struct megasas_progress prog;
1643 } __attribute__ ((packed)) pd_prog;
1646 struct megasas_evtarg_pd pd;
1649 } __attribute__ ((packed)) pd_state;
1656 } __attribute__ ((packed)) pci;
1664 } __attribute__ ((packed)) time;
1670 } __attribute__ ((packed)) ecc;
1678 char description[128];
1680 } __attribute__ ((packed));
1682 struct megasas_aen_event {
1683 struct delayed_work hotplug_work;
1684 struct megasas_instance *instance;
1687 struct megasas_irq_context {
1688 struct megasas_instance *instance;
1692 struct MR_DRV_SYSTEM_INFO {
1700 struct megasas_instance {
1703 dma_addr_t producer_h;
1705 dma_addr_t consumer_h;
1706 struct MR_DRV_SYSTEM_INFO *system_info_buf;
1707 dma_addr_t system_info_h;
1708 struct MR_LD_VF_AFFILIATION *vf_affiliation;
1709 dma_addr_t vf_affiliation_h;
1710 struct MR_LD_VF_AFFILIATION_111 *vf_affiliation_111;
1711 dma_addr_t vf_affiliation_111_h;
1712 struct MR_CTRL_HB_HOST_MEM *hb_host_mem;
1713 dma_addr_t hb_host_mem_h;
1715 __le32 *reply_queue;
1716 dma_addr_t reply_queue_h;
1718 u32 *crash_dump_buf;
1719 dma_addr_t crash_dump_h;
1720 void *crash_buf[MAX_CRASH_DUMP_SIZE];
1721 u32 crash_buf_pages;
1722 unsigned int fw_crash_buffer_size;
1723 unsigned int fw_crash_state;
1724 unsigned int fw_crash_buffer_offset;
1727 u32 crash_dump_fw_support;
1728 u32 crash_dump_drv_support;
1729 u32 crash_dump_app_support;
1730 u32 secure_jbod_support;
1731 bool use_seqnum_jbod_fp; /* Added for PD sequence */
1732 spinlock_t crashdump_lock;
1734 struct megasas_register_set __iomem *reg_set;
1735 u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
1736 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
1737 struct megasas_pd_list local_pd_list[MEGASAS_MAX_PD];
1738 u8 ld_ids[MEGASAS_MAX_LD_IDS];
1745 u32 max_sectors_per_req;
1746 struct megasas_aen_event *ev;
1748 struct megasas_cmd **cmd_list;
1749 struct list_head cmd_pool;
1750 /* used to sync fire the cmd to fw */
1751 spinlock_t mfi_pool_lock;
1752 /* used to sync fire the cmd to fw */
1753 spinlock_t hba_lock;
1754 /* used to synch producer, consumer ptrs in dpc */
1755 spinlock_t completion_lock;
1756 struct dma_pool *frame_dma_pool;
1757 struct dma_pool *sense_dma_pool;
1759 struct megasas_evt_detail *evt_detail;
1760 dma_addr_t evt_detail_h;
1761 struct megasas_cmd *aen_cmd;
1762 struct mutex aen_mutex;
1763 struct semaphore ioctl_sem;
1765 struct Scsi_Host *host;
1767 wait_queue_head_t int_cmd_wait_q;
1768 wait_queue_head_t abort_cmd_wait_q;
1770 struct pci_dev *pdev;
1772 u32 fw_support_ieee;
1774 atomic_t fw_outstanding;
1775 atomic_t fw_reset_no_pci_access;
1777 struct megasas_instance_template *instancet;
1778 struct tasklet_struct isr_tasklet;
1779 struct work_struct work_init;
1780 struct work_struct crash_init;
1786 u8 disableOnlineCtrlReset;
1787 u8 UnevenSpanSupport;
1790 u16 fw_supported_vd_count;
1791 u16 fw_supported_pd_count;
1793 u16 drv_supported_vd_count;
1794 u16 drv_supported_pd_count;
1797 unsigned long last_time;
1801 struct list_head internal_reset_pending_q;
1803 /* Ptr to hba specific information */
1805 u32 ctrl_context_pages;
1806 struct megasas_ctrl_info *ctrl_info;
1807 unsigned int msix_vectors;
1808 struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1809 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
1812 struct megasas_cmd *map_update_cmd;
1813 struct megasas_cmd *jbod_seq_cmd;
1816 struct mutex reset_mutex;
1817 struct timer_list sriov_heartbeat_timer;
1818 char skip_heartbeat_timer_del;
1822 u16 throttlequeuedepth;
1824 u16 max_chain_frame_sz;
1828 struct MR_LD_VF_MAP {
1830 union MR_LD_REF ref;
1836 struct MR_LD_VF_AFFILIATION {
1842 struct MR_LD_VF_MAP map[1];
1845 /* Plasma 1.11 FW backward compatibility structures */
1846 #define IOV_111_OFFSET 0x7CE
1847 #define MAX_VIRTUAL_FUNCTIONS 8
1848 #define MR_LD_ACCESS_HIDDEN 15
1857 struct MR_LD_VF_MAP_111 {
1860 u8 policy[MAX_VIRTUAL_FUNCTIONS];
1863 struct MR_LD_VF_AFFILIATION_111 {
1868 struct MR_LD_VF_MAP_111 map[MAX_LOGICAL_DRIVES];
1871 struct MR_CTRL_HB_HOST_MEM {
1873 u32 fwCounter; /* Firmware heart beat counter */
1875 u32 debugmode:1; /* 1=Firmware is in debug mode.
1876 Heart beat will not be updated. */
1880 u32 driverCounter; /* Driver heart beat counter. 0x20 */
1881 u32 reserved_driver[7];
1887 MEGASAS_HBA_OPERATIONAL = 0,
1888 MEGASAS_ADPRESET_SM_INFAULT = 1,
1889 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1890 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1891 MEGASAS_HW_CRITICAL_ERROR = 4,
1892 MEGASAS_ADPRESET_SM_POLLING = 5,
1893 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
1896 struct megasas_instance_template {
1897 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1898 u32, struct megasas_register_set __iomem *);
1900 void (*enable_intr)(struct megasas_instance *);
1901 void (*disable_intr)(struct megasas_instance *);
1903 int (*clear_intr)(struct megasas_register_set __iomem *);
1905 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
1906 int (*adp_reset)(struct megasas_instance *, \
1907 struct megasas_register_set __iomem *);
1908 int (*check_reset)(struct megasas_instance *, \
1909 struct megasas_register_set __iomem *);
1910 irqreturn_t (*service_isr)(int irq, void *devp);
1911 void (*tasklet)(unsigned long);
1912 u32 (*init_adapter)(struct megasas_instance *);
1913 u32 (*build_and_issue_cmd) (struct megasas_instance *,
1914 struct scsi_cmnd *);
1915 void (*issue_dcmd) (struct megasas_instance *instance,
1916 struct megasas_cmd *cmd);
1919 #define MEGASAS_IS_LOGICAL(scp) \
1920 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1922 #define MEGASAS_DEV_INDEX(scp) \
1923 (((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1926 #define MEGASAS_PD_INDEX(scp) \
1927 ((scp->device->channel * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1930 struct megasas_cmd {
1932 union megasas_frame *frame;
1933 dma_addr_t frame_phys_addr;
1935 dma_addr_t sense_phys_addr;
1941 u8 retry_for_fw_reset;
1944 struct list_head list;
1945 struct scsi_cmnd *scmd;
1948 struct megasas_instance *instance;
1958 #define MAX_MGMT_ADAPTERS 1024
1959 #define MAX_IOCTL_SGE 16
1961 struct megasas_iocpacket {
1971 struct megasas_header hdr;
1974 struct iovec sgl[MAX_IOCTL_SGE];
1976 } __attribute__ ((packed));
1978 struct megasas_aen {
1982 u32 class_locale_word;
1983 } __attribute__ ((packed));
1985 #ifdef CONFIG_COMPAT
1986 struct compat_megasas_iocpacket {
1995 struct megasas_header hdr;
1997 struct compat_iovec sgl[MAX_IOCTL_SGE];
1998 } __attribute__ ((packed));
2000 #define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
2003 #define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
2004 #define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
2006 struct megasas_mgmt_info {
2009 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
2014 MR_BuildRaidContext(struct megasas_instance *instance,
2015 struct IO_REQUEST_INFO *io_info,
2016 struct RAID_CONTEXT *pRAID_Context,
2017 struct MR_DRV_RAID_MAP_ALL *map, u8 **raidLUN);
2018 u8 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_DRV_RAID_MAP_ALL *map);
2019 struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2020 u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_DRV_RAID_MAP_ALL *map);
2021 u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_DRV_RAID_MAP_ALL *map);
2022 __le16 MR_PdDevHandleGet(u32 pd, struct MR_DRV_RAID_MAP_ALL *map);
2023 u16 MR_GetLDTgtId(u32 ld, struct MR_DRV_RAID_MAP_ALL *map);
2025 __le16 get_updated_dev_handle(struct megasas_instance *instance,
2026 struct LD_LOAD_BALANCE_INFO *lbInfo, struct IO_REQUEST_INFO *in_info);
2027 void mr_update_load_balance_params(struct MR_DRV_RAID_MAP_ALL *map,
2028 struct LD_LOAD_BALANCE_INFO *lbInfo);
2029 int megasas_get_ctrl_info(struct megasas_instance *instance);
2032 megasas_sync_pd_seq_num(struct megasas_instance *instance, bool pend);
2033 int megasas_set_crash_dump_params(struct megasas_instance *instance,
2034 u8 crash_buf_state);
2035 void megasas_free_host_crash_buffer(struct megasas_instance *instance);
2036 void megasas_fusion_crash_dump_wq(struct work_struct *work);
2038 void megasas_return_cmd_fusion(struct megasas_instance *instance,
2039 struct megasas_cmd_fusion *cmd);
2040 int megasas_issue_blocked_cmd(struct megasas_instance *instance,
2041 struct megasas_cmd *cmd, int timeout);
2042 void __megasas_return_cmd(struct megasas_instance *instance,
2043 struct megasas_cmd *cmd);
2045 void megasas_return_mfi_mpt_pthr(struct megasas_instance *instance,
2046 struct megasas_cmd *cmd_mfi, struct megasas_cmd_fusion *cmd_fusion);
2047 int megasas_cmd_type(struct scsi_cmnd *cmd);
2048 void megasas_setup_jbod_map(struct megasas_instance *instance);
2050 #endif /*LSI_MEGARAID_SAS_H */