2 * Copyright (c) 2000-2011 LSI Corporation.
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
11 * mpi2.h Version: 02.00.21
16 * Date Version Description
17 * -------- -------- ------------------------------------------------------
18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
22 * Moved ReplyPostHostIndex register to offset 0x6C of the
23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
25 * Added union of request descriptors.
26 * Added union of reply descriptors.
27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Added define for MPI2_VERSION_02_00.
29 * Fixed the size of the FunctionDependent5 field in the
30 * MPI2_DEFAULT_REPLY structure.
31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
32 * Removed the MPI-defined Fault Codes and extended the
33 * product specific codes up to 0xEFFF.
34 * Added a sixth key value for the WriteSequence register
35 * and changed the flush value to 0x0.
36 * Added message function codes for Diagnostic Buffer Post
37 * and Diagnsotic Release.
38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
43 * Added #defines for marking a reply descriptor as unused.
44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
46 * Moved LUN field defines from mpi2_init.h.
47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
49 * In all request and reply descriptors, replaced VF_ID
50 * field with MSIxIndex field.
51 * Removed DevHandle field from
52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
54 * Added RAID Accelerator functionality.
55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
56 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
57 * Added MSI-x index mask and shift for Reply Post Host
59 * Added function code for Host Based Discovery Action.
60 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
61 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
62 * Added defines for product-specific range of message
63 * function codes, 0xF0 to 0xFF.
64 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
65 * Added alternative defines for the SGE Direction bit.
66 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
67 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
68 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
69 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
70 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
71 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
72 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
73 * --------------------------------------------------------------------------
80 /*****************************************************************************
82 * MPI Version Definitions
84 *****************************************************************************/
86 #define MPI2_VERSION_MAJOR (0x02)
87 #define MPI2_VERSION_MINOR (0x00)
88 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
89 #define MPI2_VERSION_MAJOR_SHIFT (8)
90 #define MPI2_VERSION_MINOR_MASK (0x00FF)
91 #define MPI2_VERSION_MINOR_SHIFT (0)
92 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
95 #define MPI2_VERSION_02_00 (0x0200)
97 /* versioning for this MPI header set */
98 #define MPI2_HEADER_VERSION_UNIT (0x15)
99 #define MPI2_HEADER_VERSION_DEV (0x00)
100 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
101 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
102 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
103 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
104 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
107 /*****************************************************************************
109 * IOC State Definitions
111 *****************************************************************************/
113 #define MPI2_IOC_STATE_RESET (0x00000000)
114 #define MPI2_IOC_STATE_READY (0x10000000)
115 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
116 #define MPI2_IOC_STATE_FAULT (0x40000000)
118 #define MPI2_IOC_STATE_MASK (0xF0000000)
119 #define MPI2_IOC_STATE_SHIFT (28)
121 /* Fault state range for prodcut specific codes */
122 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
123 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
126 /*****************************************************************************
128 * System Interface Register Definitions
130 *****************************************************************************/
132 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
134 U32 Doorbell; /* 0x00 */
135 U32 WriteSequence; /* 0x04 */
136 U32 HostDiagnostic; /* 0x08 */
137 U32 Reserved1; /* 0x0C */
138 U32 DiagRWData; /* 0x10 */
139 U32 DiagRWAddressLow; /* 0x14 */
140 U32 DiagRWAddressHigh; /* 0x18 */
141 U32 Reserved2[5]; /* 0x1C */
142 U32 HostInterruptStatus; /* 0x30 */
143 U32 HostInterruptMask; /* 0x34 */
144 U32 DCRData; /* 0x38 */
145 U32 DCRAddress; /* 0x3C */
146 U32 Reserved3[2]; /* 0x40 */
147 U32 ReplyFreeHostIndex; /* 0x48 */
148 U32 Reserved4[8]; /* 0x4C */
149 U32 ReplyPostHostIndex; /* 0x6C */
150 U32 Reserved5; /* 0x70 */
151 U32 HCBSize; /* 0x74 */
152 U32 HCBAddressLow; /* 0x78 */
153 U32 HCBAddressHigh; /* 0x7C */
154 U32 Reserved6[16]; /* 0x80 */
155 U32 RequestDescriptorPostLow; /* 0xC0 */
156 U32 RequestDescriptorPostHigh; /* 0xC4 */
157 U32 Reserved7[14]; /* 0xC8 */
158 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
159 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
162 * Defines for working with the Doorbell register.
164 #define MPI2_DOORBELL_OFFSET (0x00000000)
166 /* IOC --> System values */
167 #define MPI2_DOORBELL_USED (0x08000000)
168 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
169 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
170 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
171 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
173 /* System --> IOC values */
174 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
175 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
176 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
177 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
181 * Defines for the WriteSequence register
183 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
184 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
185 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
186 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
187 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
188 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
189 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
190 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
191 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
194 * Defines for the HostDiagnostic register
196 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
198 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
199 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
200 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
202 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
203 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
204 #define MPI2_DIAG_HCB_MODE (0x00000100)
205 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
206 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
207 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
208 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
209 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
210 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
213 * Offsets for DiagRWData and address
215 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
216 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
217 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
220 * Defines for the HostInterruptStatus register
222 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
223 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
224 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
225 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
226 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
227 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
228 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
231 * Defines for the HostInterruptMask register
233 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
234 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
235 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
236 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
237 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
238 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
241 * Offsets for DCRData and address
243 #define MPI2_DCR_DATA_OFFSET (0x00000038)
244 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
247 * Offset for the Reply Free Queue
249 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
252 * Defines for the Reply Descriptor Post Queue
254 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
255 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
256 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
257 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
260 * Defines for the HCBSize and address
262 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
263 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
264 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
266 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
267 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
270 * Offsets for the Request Queue
272 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
273 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
276 /*****************************************************************************
278 * Message Descriptors
280 *****************************************************************************/
282 /* Request Descriptors */
284 /* Default Request Descriptor */
285 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
287 U8 RequestFlags; /* 0x00 */
288 U8 MSIxIndex; /* 0x01 */
291 U16 DescriptorTypeDependent; /* 0x06 */
292 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
293 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
294 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
296 /* defines for the RequestFlags field */
297 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
298 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
299 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
300 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
301 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
302 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
304 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
307 /* High Priority Request Descriptor */
308 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
310 U8 RequestFlags; /* 0x00 */
311 U8 MSIxIndex; /* 0x01 */
314 U16 Reserved1; /* 0x06 */
315 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
316 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
317 Mpi2HighPriorityRequestDescriptor_t,
318 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
321 /* SCSI IO Request Descriptor */
322 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
324 U8 RequestFlags; /* 0x00 */
325 U8 MSIxIndex; /* 0x01 */
328 U16 DevHandle; /* 0x06 */
329 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
330 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
331 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
334 /* SCSI Target Request Descriptor */
335 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
337 U8 RequestFlags; /* 0x00 */
338 U8 MSIxIndex; /* 0x01 */
341 U16 IoIndex; /* 0x06 */
342 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
343 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
344 Mpi2SCSITargetRequestDescriptor_t,
345 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
348 /* RAID Accelerator Request Descriptor */
349 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
350 U8 RequestFlags; /* 0x00 */
351 U8 MSIxIndex; /* 0x01 */
354 U16 Reserved; /* 0x06 */
355 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
356 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
357 Mpi2RAIDAcceleratorRequestDescriptor_t,
358 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
361 /* union of Request Descriptors */
362 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
364 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
365 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
366 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
367 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
368 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
370 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
371 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
374 /* Reply Descriptors */
376 /* Default Reply Descriptor */
377 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
379 U8 ReplyFlags; /* 0x00 */
380 U8 MSIxIndex; /* 0x01 */
381 U16 DescriptorTypeDependent1; /* 0x02 */
382 U32 DescriptorTypeDependent2; /* 0x04 */
383 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
384 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
386 /* defines for the ReplyFlags field */
387 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
388 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
389 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
390 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
391 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
392 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
393 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
395 /* values for marking a reply descriptor as unused */
396 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
397 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
399 /* Address Reply Descriptor */
400 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
402 U8 ReplyFlags; /* 0x00 */
403 U8 MSIxIndex; /* 0x01 */
405 U32 ReplyFrameAddress; /* 0x04 */
406 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
407 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
409 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
412 /* SCSI IO Success Reply Descriptor */
413 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
415 U8 ReplyFlags; /* 0x00 */
416 U8 MSIxIndex; /* 0x01 */
418 U16 TaskTag; /* 0x04 */
419 U16 Reserved1; /* 0x06 */
420 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
421 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
422 Mpi2SCSIIOSuccessReplyDescriptor_t,
423 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
426 /* TargetAssist Success Reply Descriptor */
427 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
429 U8 ReplyFlags; /* 0x00 */
430 U8 MSIxIndex; /* 0x01 */
432 U8 SequenceNumber; /* 0x04 */
433 U8 Reserved1; /* 0x05 */
434 U16 IoIndex; /* 0x06 */
435 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
436 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
437 Mpi2TargetAssistSuccessReplyDescriptor_t,
438 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
441 /* Target Command Buffer Reply Descriptor */
442 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
444 U8 ReplyFlags; /* 0x00 */
445 U8 MSIxIndex; /* 0x01 */
448 U16 InitiatorDevHandle; /* 0x04 */
449 U16 IoIndex; /* 0x06 */
450 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
451 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
452 Mpi2TargetCommandBufferReplyDescriptor_t,
453 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
455 /* defines for Flags field */
456 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
459 /* RAID Accelerator Success Reply Descriptor */
460 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
461 U8 ReplyFlags; /* 0x00 */
462 U8 MSIxIndex; /* 0x01 */
464 U32 Reserved; /* 0x04 */
465 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
466 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
467 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
468 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
471 /* union of Reply Descriptors */
472 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
474 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
475 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
476 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
477 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
478 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
479 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
481 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
482 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
486 /*****************************************************************************
490 *****************************************************************************/
492 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
493 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
494 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
495 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
496 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
497 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
498 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
499 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
500 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
501 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
502 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
503 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
504 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
505 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
506 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
507 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
508 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
509 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
510 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
511 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
512 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
513 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
514 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
515 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
516 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
517 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/
518 /* Host Based Discovery Action */
519 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
520 /* Power Management Control */
521 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
522 /* Send Host Message */
523 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
524 /* beginning of product-specific range */
525 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
526 /* end of product-specific range */
527 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
532 /* Doorbell functions */
533 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
534 #define MPI2_FUNCTION_HANDSHAKE (0x42)
537 /*****************************************************************************
541 *****************************************************************************/
543 /* mask for IOCStatus status value */
544 #define MPI2_IOCSTATUS_MASK (0x7FFF)
546 /****************************************************************************
547 * Common IOCStatus values for all replies
548 ****************************************************************************/
550 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
551 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
552 #define MPI2_IOCSTATUS_BUSY (0x0002)
553 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
554 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
555 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
556 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
557 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
558 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
559 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
561 /****************************************************************************
562 * Config IOCStatus values
563 ****************************************************************************/
565 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
566 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
567 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
568 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
569 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
570 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
572 /****************************************************************************
574 ****************************************************************************/
576 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
577 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
578 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
579 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
580 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
581 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
582 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
583 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
584 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
585 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
586 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
587 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
589 /****************************************************************************
590 * For use by SCSI Initiator and SCSI Target end-to-end data protection
591 ****************************************************************************/
593 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
594 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
595 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
597 /****************************************************************************
599 ****************************************************************************/
601 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
602 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
603 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
604 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
605 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
606 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
607 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
608 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
609 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
610 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
612 /****************************************************************************
613 * Serial Attached SCSI values
614 ****************************************************************************/
616 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
617 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
619 /****************************************************************************
620 * Diagnostic Buffer Post / Diagnostic Release values
621 ****************************************************************************/
623 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
625 /****************************************************************************
626 * RAID Accelerator values
627 ****************************************************************************/
629 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
631 /****************************************************************************
632 * IOCStatus flag to indicate that log info is available
633 ****************************************************************************/
635 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
637 /****************************************************************************
639 ****************************************************************************/
641 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
642 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
643 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
644 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
645 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
646 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
647 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
648 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
651 /*****************************************************************************
653 * Standard Message Structures
655 *****************************************************************************/
657 /****************************************************************************
658 * Request Message Header for all request messages
659 ****************************************************************************/
661 typedef struct _MPI2_REQUEST_HEADER
663 U16 FunctionDependent1; /* 0x00 */
664 U8 ChainOffset; /* 0x02 */
665 U8 Function; /* 0x03 */
666 U16 FunctionDependent2; /* 0x04 */
667 U8 FunctionDependent3; /* 0x06 */
668 U8 MsgFlags; /* 0x07 */
671 U16 Reserved1; /* 0x0A */
672 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
673 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
676 /****************************************************************************
678 ****************************************************************************/
680 typedef struct _MPI2_DEFAULT_REPLY
682 U16 FunctionDependent1; /* 0x00 */
683 U8 MsgLength; /* 0x02 */
684 U8 Function; /* 0x03 */
685 U16 FunctionDependent2; /* 0x04 */
686 U8 FunctionDependent3; /* 0x06 */
687 U8 MsgFlags; /* 0x07 */
690 U16 Reserved1; /* 0x0A */
691 U16 FunctionDependent5; /* 0x0C */
692 U16 IOCStatus; /* 0x0E */
693 U32 IOCLogInfo; /* 0x10 */
694 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
695 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
698 /* common version structure/union used in messages and configuration pages */
700 typedef struct _MPI2_VERSION_STRUCT
706 } MPI2_VERSION_STRUCT;
708 typedef union _MPI2_VERSION_UNION
710 MPI2_VERSION_STRUCT Struct;
712 } MPI2_VERSION_UNION;
715 /* LUN field defines, common to many structures */
716 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
717 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
718 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
719 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
720 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
721 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
724 /*****************************************************************************
726 * Fusion-MPT MPI Scatter Gather Elements
728 *****************************************************************************/
730 /****************************************************************************
731 * MPI Simple Element structures
732 ****************************************************************************/
734 typedef struct _MPI2_SGE_SIMPLE32
738 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
739 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
741 typedef struct _MPI2_SGE_SIMPLE64
745 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
746 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
748 typedef struct _MPI2_SGE_SIMPLE_UNION
756 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
757 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
760 /****************************************************************************
761 * MPI Chain Element structures
762 ****************************************************************************/
764 typedef struct _MPI2_SGE_CHAIN32
770 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
771 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
773 typedef struct _MPI2_SGE_CHAIN64
779 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
780 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
782 typedef struct _MPI2_SGE_CHAIN_UNION
792 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
793 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
796 /****************************************************************************
797 * MPI Transaction Context Element structures
798 ****************************************************************************/
800 typedef struct _MPI2_SGE_TRANSACTION32
806 U32 TransactionContext[1];
807 U32 TransactionDetails[1];
808 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
809 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
811 typedef struct _MPI2_SGE_TRANSACTION64
817 U32 TransactionContext[2];
818 U32 TransactionDetails[1];
819 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
820 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
822 typedef struct _MPI2_SGE_TRANSACTION96
828 U32 TransactionContext[3];
829 U32 TransactionDetails[1];
830 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
831 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
833 typedef struct _MPI2_SGE_TRANSACTION128
839 U32 TransactionContext[4];
840 U32 TransactionDetails[1];
841 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
842 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
844 typedef struct _MPI2_SGE_TRANSACTION_UNION
852 U32 TransactionContext32[1];
853 U32 TransactionContext64[2];
854 U32 TransactionContext96[3];
855 U32 TransactionContext128[4];
857 U32 TransactionDetails[1];
858 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
859 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
862 /****************************************************************************
863 * MPI SGE union for IO SGL's
864 ****************************************************************************/
866 typedef struct _MPI2_MPI_SGE_IO_UNION
870 MPI2_SGE_SIMPLE_UNION Simple;
871 MPI2_SGE_CHAIN_UNION Chain;
873 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
874 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
877 /****************************************************************************
878 * MPI SGE union for SGL's with Simple and Transaction elements
879 ****************************************************************************/
881 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
885 MPI2_SGE_SIMPLE_UNION Simple;
886 MPI2_SGE_TRANSACTION_UNION Transaction;
888 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
889 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
892 /****************************************************************************
893 * All MPI SGE types union
894 ****************************************************************************/
896 typedef struct _MPI2_MPI_SGE_UNION
900 MPI2_SGE_SIMPLE_UNION Simple;
901 MPI2_SGE_CHAIN_UNION Chain;
902 MPI2_SGE_TRANSACTION_UNION Transaction;
904 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
905 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
908 /****************************************************************************
909 * MPI SGE field definition and masks
910 ****************************************************************************/
912 /* Flags field bit definitions */
914 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
915 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
916 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
917 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
918 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
919 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
920 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
922 #define MPI2_SGE_FLAGS_SHIFT (24)
924 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
925 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
929 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
930 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
931 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
932 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
934 /* Address location */
936 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
940 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
941 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
943 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
944 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
948 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
949 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
953 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
954 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
955 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
956 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
958 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
959 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
961 /****************************************************************************
962 * MPI SGE operation Macros
963 ****************************************************************************/
965 /* SIMPLE FlagsLength manipulations... */
966 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
967 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
968 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
969 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
971 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
973 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
974 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
975 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
977 /* CAUTION - The following are READ-MODIFY-WRITE! */
978 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
979 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
981 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
984 /*****************************************************************************
986 * Fusion-MPT IEEE Scatter Gather Elements
988 *****************************************************************************/
990 /****************************************************************************
991 * IEEE Simple Element structures
992 ****************************************************************************/
994 typedef struct _MPI2_IEEE_SGE_SIMPLE32
998 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
999 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1001 typedef struct _MPI2_IEEE_SGE_SIMPLE64
1008 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1009 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1011 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1013 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1014 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1015 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1016 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1019 /****************************************************************************
1020 * IEEE Chain Element structures
1021 ****************************************************************************/
1023 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1025 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1027 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1029 MPI2_IEEE_SGE_CHAIN32 Chain32;
1030 MPI2_IEEE_SGE_CHAIN64 Chain64;
1031 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1032 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1035 /****************************************************************************
1036 * All IEEE SGE types union
1037 ****************************************************************************/
1039 typedef struct _MPI2_IEEE_SGE_UNION
1043 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1044 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1046 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1047 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1050 /****************************************************************************
1051 * IEEE SGE field definitions and masks
1052 ****************************************************************************/
1054 /* Flags field bit definitions */
1056 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1058 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1060 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1064 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1065 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1067 /* Data Location Address Space */
1069 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1070 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1071 /* IEEE Simple Element only */
1072 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1073 /* IEEE Simple Element only */
1074 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1075 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1076 /* IEEE Simple Element only */
1077 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1078 /* IEEE Chain Element only */
1079 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1080 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */
1082 /****************************************************************************
1083 * IEEE SGE operation Macros
1084 ****************************************************************************/
1086 /* SIMPLE FlagsLength manipulations... */
1087 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1088 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1089 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1091 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1093 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1094 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1095 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1097 /* CAUTION - The following are READ-MODIFY-WRITE! */
1098 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1099 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1104 /*****************************************************************************
1106 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1108 *****************************************************************************/
1110 typedef union _MPI2_SIMPLE_SGE_UNION
1112 MPI2_SGE_SIMPLE_UNION MpiSimple;
1113 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1114 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1115 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1118 typedef union _MPI2_SGE_IO_UNION
1120 MPI2_SGE_SIMPLE_UNION MpiSimple;
1121 MPI2_SGE_CHAIN_UNION MpiChain;
1122 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1123 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1124 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1125 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1128 /****************************************************************************
1130 * Values for SGLFlags field, used in many request messages with an SGL
1132 ****************************************************************************/
1134 /* values for MPI SGL Data Location Address Space subfield */
1135 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1136 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1137 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1138 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1139 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1140 /* values for SGL Type subfield */
1141 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1142 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1143 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1144 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)