2 * Copyright (c) 2000-2012 LSI Corporation.
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
11 * mpi2.h Version: 02.00.27
16 * Date Version Description
17 * -------- -------- ------------------------------------------------------
18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
22 * Moved ReplyPostHostIndex register to offset 0x6C of the
23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
25 * Added union of request descriptors.
26 * Added union of reply descriptors.
27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Added define for MPI2_VERSION_02_00.
29 * Fixed the size of the FunctionDependent5 field in the
30 * MPI2_DEFAULT_REPLY structure.
31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
32 * Removed the MPI-defined Fault Codes and extended the
33 * product specific codes up to 0xEFFF.
34 * Added a sixth key value for the WriteSequence register
35 * and changed the flush value to 0x0.
36 * Added message function codes for Diagnostic Buffer Post
37 * and Diagnsotic Release.
38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
43 * Added #defines for marking a reply descriptor as unused.
44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
46 * Moved LUN field defines from mpi2_init.h.
47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
49 * In all request and reply descriptors, replaced VF_ID
50 * field with MSIxIndex field.
51 * Removed DevHandle field from
52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
54 * Added RAID Accelerator functionality.
55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
56 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
57 * Added MSI-x index mask and shift for Reply Post Host
59 * Added function code for Host Based Discovery Action.
60 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
61 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
62 * Added defines for product-specific range of message
63 * function codes, 0xF0 to 0xFF.
64 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
65 * Added alternative defines for the SGE Direction bit.
66 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
67 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
68 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
69 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
70 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
71 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
72 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
73 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
74 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
75 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
76 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
77 * Added Hard Reset delay timings.
78 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
80 * --------------------------------------------------------------------------
87 /*****************************************************************************
89 * MPI Version Definitions
91 *****************************************************************************/
93 #define MPI2_VERSION_MAJOR (0x02)
94 #define MPI2_VERSION_MINOR (0x00)
95 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
96 #define MPI2_VERSION_MAJOR_SHIFT (8)
97 #define MPI2_VERSION_MINOR_MASK (0x00FF)
98 #define MPI2_VERSION_MINOR_SHIFT (0)
99 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
102 #define MPI2_VERSION_02_00 (0x0200)
104 /* versioning for this MPI header set */
105 #define MPI2_HEADER_VERSION_UNIT (0x1B)
106 #define MPI2_HEADER_VERSION_DEV (0x00)
107 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
108 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
109 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
110 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
111 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
114 /*****************************************************************************
116 * IOC State Definitions
118 *****************************************************************************/
120 #define MPI2_IOC_STATE_RESET (0x00000000)
121 #define MPI2_IOC_STATE_READY (0x10000000)
122 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
123 #define MPI2_IOC_STATE_FAULT (0x40000000)
125 #define MPI2_IOC_STATE_MASK (0xF0000000)
126 #define MPI2_IOC_STATE_SHIFT (28)
128 /* Fault state range for prodcut specific codes */
129 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
130 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
133 /*****************************************************************************
135 * System Interface Register Definitions
137 *****************************************************************************/
139 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
141 U32 Doorbell; /* 0x00 */
142 U32 WriteSequence; /* 0x04 */
143 U32 HostDiagnostic; /* 0x08 */
144 U32 Reserved1; /* 0x0C */
145 U32 DiagRWData; /* 0x10 */
146 U32 DiagRWAddressLow; /* 0x14 */
147 U32 DiagRWAddressHigh; /* 0x18 */
148 U32 Reserved2[5]; /* 0x1C */
149 U32 HostInterruptStatus; /* 0x30 */
150 U32 HostInterruptMask; /* 0x34 */
151 U32 DCRData; /* 0x38 */
152 U32 DCRAddress; /* 0x3C */
153 U32 Reserved3[2]; /* 0x40 */
154 U32 ReplyFreeHostIndex; /* 0x48 */
155 U32 Reserved4[8]; /* 0x4C */
156 U32 ReplyPostHostIndex; /* 0x6C */
157 U32 Reserved5; /* 0x70 */
158 U32 HCBSize; /* 0x74 */
159 U32 HCBAddressLow; /* 0x78 */
160 U32 HCBAddressHigh; /* 0x7C */
161 U32 Reserved6[16]; /* 0x80 */
162 U32 RequestDescriptorPostLow; /* 0xC0 */
163 U32 RequestDescriptorPostHigh; /* 0xC4 */
164 U32 Reserved7[14]; /* 0xC8 */
165 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
166 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
169 * Defines for working with the Doorbell register.
171 #define MPI2_DOORBELL_OFFSET (0x00000000)
173 /* IOC --> System values */
174 #define MPI2_DOORBELL_USED (0x08000000)
175 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
176 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
177 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
178 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
180 /* System --> IOC values */
181 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
182 #define MPI2_DOORBELL_FUNCTION_SHIFT (24)
183 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
184 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
188 * Defines for the WriteSequence register
190 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
191 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
192 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
193 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
194 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
195 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
196 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
197 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
198 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
201 * Defines for the HostDiagnostic register
203 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
205 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
206 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
207 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
209 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
210 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
211 #define MPI2_DIAG_HCB_MODE (0x00000100)
212 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
213 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
214 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
215 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
216 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
217 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
220 * Offsets for DiagRWData and address
222 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
223 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
224 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
227 * Defines for the HostInterruptStatus register
229 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
230 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
231 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
232 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
233 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
234 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
235 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
238 * Defines for the HostInterruptMask register
240 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
241 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
242 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
243 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
244 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
245 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
248 * Offsets for DCRData and address
250 #define MPI2_DCR_DATA_OFFSET (0x00000038)
251 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
254 * Offset for the Reply Free Queue
256 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
259 * Defines for the Reply Descriptor Post Queue
261 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
262 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
263 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
264 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
267 * Defines for the HCBSize and address
269 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
270 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
271 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
273 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
274 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
277 * Offsets for the Request Queue
279 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
280 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
283 /* Hard Reset delay timings */
284 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
285 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
286 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
288 /*****************************************************************************
290 * Message Descriptors
292 *****************************************************************************/
294 /* Request Descriptors */
296 /* Default Request Descriptor */
297 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
299 U8 RequestFlags; /* 0x00 */
300 U8 MSIxIndex; /* 0x01 */
303 U16 DescriptorTypeDependent; /* 0x06 */
304 } MPI2_DEFAULT_REQUEST_DESCRIPTOR,
305 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
306 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
308 /* defines for the RequestFlags field */
309 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
310 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
311 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
312 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
313 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
314 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
316 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
319 /* High Priority Request Descriptor */
320 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
322 U8 RequestFlags; /* 0x00 */
323 U8 MSIxIndex; /* 0x01 */
326 U16 Reserved1; /* 0x06 */
327 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
328 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
329 Mpi2HighPriorityRequestDescriptor_t,
330 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
333 /* SCSI IO Request Descriptor */
334 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
336 U8 RequestFlags; /* 0x00 */
337 U8 MSIxIndex; /* 0x01 */
340 U16 DevHandle; /* 0x06 */
341 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
342 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
343 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
346 /* SCSI Target Request Descriptor */
347 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
349 U8 RequestFlags; /* 0x00 */
350 U8 MSIxIndex; /* 0x01 */
353 U16 IoIndex; /* 0x06 */
354 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
355 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
356 Mpi2SCSITargetRequestDescriptor_t,
357 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
360 /* RAID Accelerator Request Descriptor */
361 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
362 U8 RequestFlags; /* 0x00 */
363 U8 MSIxIndex; /* 0x01 */
366 U16 Reserved; /* 0x06 */
367 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
368 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
369 Mpi2RAIDAcceleratorRequestDescriptor_t,
370 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
373 /* union of Request Descriptors */
374 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
376 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
377 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
378 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
379 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
380 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
382 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
383 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
386 /* Reply Descriptors */
388 /* Default Reply Descriptor */
389 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
391 U8 ReplyFlags; /* 0x00 */
392 U8 MSIxIndex; /* 0x01 */
393 U16 DescriptorTypeDependent1; /* 0x02 */
394 U32 DescriptorTypeDependent2; /* 0x04 */
395 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
396 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
398 /* defines for the ReplyFlags field */
399 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
400 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
401 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
402 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
403 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
404 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
405 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
407 /* values for marking a reply descriptor as unused */
408 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
409 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
411 /* Address Reply Descriptor */
412 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
414 U8 ReplyFlags; /* 0x00 */
415 U8 MSIxIndex; /* 0x01 */
417 U32 ReplyFrameAddress; /* 0x04 */
418 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
419 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
421 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
424 /* SCSI IO Success Reply Descriptor */
425 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
427 U8 ReplyFlags; /* 0x00 */
428 U8 MSIxIndex; /* 0x01 */
430 U16 TaskTag; /* 0x04 */
431 U16 Reserved1; /* 0x06 */
432 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
433 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
434 Mpi2SCSIIOSuccessReplyDescriptor_t,
435 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
438 /* TargetAssist Success Reply Descriptor */
439 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
441 U8 ReplyFlags; /* 0x00 */
442 U8 MSIxIndex; /* 0x01 */
444 U8 SequenceNumber; /* 0x04 */
445 U8 Reserved1; /* 0x05 */
446 U16 IoIndex; /* 0x06 */
447 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
448 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
449 Mpi2TargetAssistSuccessReplyDescriptor_t,
450 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
453 /* Target Command Buffer Reply Descriptor */
454 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
456 U8 ReplyFlags; /* 0x00 */
457 U8 MSIxIndex; /* 0x01 */
460 U16 InitiatorDevHandle; /* 0x04 */
461 U16 IoIndex; /* 0x06 */
462 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
463 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
464 Mpi2TargetCommandBufferReplyDescriptor_t,
465 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
467 /* defines for Flags field */
468 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
471 /* RAID Accelerator Success Reply Descriptor */
472 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
473 U8 ReplyFlags; /* 0x00 */
474 U8 MSIxIndex; /* 0x01 */
476 U32 Reserved; /* 0x04 */
477 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
478 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
479 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
480 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
483 /* union of Reply Descriptors */
484 typedef union _MPI2_REPLY_DESCRIPTORS_UNION
486 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
487 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
488 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
489 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
490 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
491 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
493 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
494 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
498 /*****************************************************************************
502 *****************************************************************************/
504 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
505 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
506 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
507 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
508 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
509 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
510 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
511 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
512 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
513 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
514 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
515 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
516 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
517 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
518 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
519 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
520 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
521 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
522 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
523 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
524 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
525 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
526 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
527 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
528 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
529 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/
530 /* Host Based Discovery Action */
531 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
532 /* Power Management Control */
533 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
534 /* Send Host Message */
535 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
536 /* beginning of product-specific range */
537 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
538 /* end of product-specific range */
539 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
544 /* Doorbell functions */
545 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
546 #define MPI2_FUNCTION_HANDSHAKE (0x42)
549 /*****************************************************************************
553 *****************************************************************************/
555 /* mask for IOCStatus status value */
556 #define MPI2_IOCSTATUS_MASK (0x7FFF)
558 /****************************************************************************
559 * Common IOCStatus values for all replies
560 ****************************************************************************/
562 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
563 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
564 #define MPI2_IOCSTATUS_BUSY (0x0002)
565 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
566 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
567 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
568 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
569 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
570 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
571 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
573 /****************************************************************************
574 * Config IOCStatus values
575 ****************************************************************************/
577 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
578 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
579 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
580 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
581 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
582 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
584 /****************************************************************************
586 ****************************************************************************/
588 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
589 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
590 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
591 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
592 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
593 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
594 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
595 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
596 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
597 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
598 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
599 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
601 /****************************************************************************
602 * For use by SCSI Initiator and SCSI Target end-to-end data protection
603 ****************************************************************************/
605 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
606 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
607 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
609 /****************************************************************************
611 ****************************************************************************/
613 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
614 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
615 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
616 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
617 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
618 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
619 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
620 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
621 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
622 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
624 /****************************************************************************
625 * Serial Attached SCSI values
626 ****************************************************************************/
628 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
629 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
631 /****************************************************************************
632 * Diagnostic Buffer Post / Diagnostic Release values
633 ****************************************************************************/
635 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
637 /****************************************************************************
638 * RAID Accelerator values
639 ****************************************************************************/
641 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
643 /****************************************************************************
644 * IOCStatus flag to indicate that log info is available
645 ****************************************************************************/
647 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
649 /****************************************************************************
651 ****************************************************************************/
653 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
654 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
655 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
656 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
657 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
658 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
659 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
660 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
663 /*****************************************************************************
665 * Standard Message Structures
667 *****************************************************************************/
669 /****************************************************************************
670 * Request Message Header for all request messages
671 ****************************************************************************/
673 typedef struct _MPI2_REQUEST_HEADER
675 U16 FunctionDependent1; /* 0x00 */
676 U8 ChainOffset; /* 0x02 */
677 U8 Function; /* 0x03 */
678 U16 FunctionDependent2; /* 0x04 */
679 U8 FunctionDependent3; /* 0x06 */
680 U8 MsgFlags; /* 0x07 */
683 U16 Reserved1; /* 0x0A */
684 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
685 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
688 /****************************************************************************
690 ****************************************************************************/
692 typedef struct _MPI2_DEFAULT_REPLY
694 U16 FunctionDependent1; /* 0x00 */
695 U8 MsgLength; /* 0x02 */
696 U8 Function; /* 0x03 */
697 U16 FunctionDependent2; /* 0x04 */
698 U8 FunctionDependent3; /* 0x06 */
699 U8 MsgFlags; /* 0x07 */
702 U16 Reserved1; /* 0x0A */
703 U16 FunctionDependent5; /* 0x0C */
704 U16 IOCStatus; /* 0x0E */
705 U32 IOCLogInfo; /* 0x10 */
706 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
707 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
710 /* common version structure/union used in messages and configuration pages */
712 typedef struct _MPI2_VERSION_STRUCT
718 } MPI2_VERSION_STRUCT;
720 typedef union _MPI2_VERSION_UNION
722 MPI2_VERSION_STRUCT Struct;
724 } MPI2_VERSION_UNION;
727 /* LUN field defines, common to many structures */
728 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
729 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
730 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
731 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
732 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
733 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
736 /*****************************************************************************
738 * Fusion-MPT MPI Scatter Gather Elements
740 *****************************************************************************/
742 /****************************************************************************
743 * MPI Simple Element structures
744 ****************************************************************************/
746 typedef struct _MPI2_SGE_SIMPLE32
750 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
751 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
753 typedef struct _MPI2_SGE_SIMPLE64
757 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
758 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
760 typedef struct _MPI2_SGE_SIMPLE_UNION
768 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
769 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
772 /****************************************************************************
773 * MPI Chain Element structures
774 ****************************************************************************/
776 typedef struct _MPI2_SGE_CHAIN32
782 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
783 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
785 typedef struct _MPI2_SGE_CHAIN64
791 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
792 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
794 typedef struct _MPI2_SGE_CHAIN_UNION
804 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
805 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
808 /****************************************************************************
809 * MPI Transaction Context Element structures
810 ****************************************************************************/
812 typedef struct _MPI2_SGE_TRANSACTION32
818 U32 TransactionContext[1];
819 U32 TransactionDetails[1];
820 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
821 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
823 typedef struct _MPI2_SGE_TRANSACTION64
829 U32 TransactionContext[2];
830 U32 TransactionDetails[1];
831 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
832 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
834 typedef struct _MPI2_SGE_TRANSACTION96
840 U32 TransactionContext[3];
841 U32 TransactionDetails[1];
842 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
843 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
845 typedef struct _MPI2_SGE_TRANSACTION128
851 U32 TransactionContext[4];
852 U32 TransactionDetails[1];
853 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
854 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
856 typedef struct _MPI2_SGE_TRANSACTION_UNION
864 U32 TransactionContext32[1];
865 U32 TransactionContext64[2];
866 U32 TransactionContext96[3];
867 U32 TransactionContext128[4];
869 U32 TransactionDetails[1];
870 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
871 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
874 /****************************************************************************
875 * MPI SGE union for IO SGL's
876 ****************************************************************************/
878 typedef struct _MPI2_MPI_SGE_IO_UNION
882 MPI2_SGE_SIMPLE_UNION Simple;
883 MPI2_SGE_CHAIN_UNION Chain;
885 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
886 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
889 /****************************************************************************
890 * MPI SGE union for SGL's with Simple and Transaction elements
891 ****************************************************************************/
893 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
897 MPI2_SGE_SIMPLE_UNION Simple;
898 MPI2_SGE_TRANSACTION_UNION Transaction;
900 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
901 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
904 /****************************************************************************
905 * All MPI SGE types union
906 ****************************************************************************/
908 typedef struct _MPI2_MPI_SGE_UNION
912 MPI2_SGE_SIMPLE_UNION Simple;
913 MPI2_SGE_CHAIN_UNION Chain;
914 MPI2_SGE_TRANSACTION_UNION Transaction;
916 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
917 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
920 /****************************************************************************
921 * MPI SGE field definition and masks
922 ****************************************************************************/
924 /* Flags field bit definitions */
926 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
927 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
928 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
929 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
930 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
931 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
932 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
934 #define MPI2_SGE_FLAGS_SHIFT (24)
936 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
937 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
941 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
942 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
943 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
944 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
946 /* Address location */
948 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
952 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
953 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
955 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
956 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
960 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
961 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
965 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
966 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
967 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
968 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
970 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
971 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
973 /****************************************************************************
974 * MPI SGE operation Macros
975 ****************************************************************************/
977 /* SIMPLE FlagsLength manipulations... */
978 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
979 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
980 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
981 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
983 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
985 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
986 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
987 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
989 /* CAUTION - The following are READ-MODIFY-WRITE! */
990 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
991 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
993 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
996 /*****************************************************************************
998 * Fusion-MPT IEEE Scatter Gather Elements
1000 *****************************************************************************/
1002 /****************************************************************************
1003 * IEEE Simple Element structures
1004 ****************************************************************************/
1006 typedef struct _MPI2_IEEE_SGE_SIMPLE32
1010 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
1011 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1013 typedef struct _MPI2_IEEE_SGE_SIMPLE64
1020 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1021 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1023 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1025 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1026 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1027 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1028 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1031 /****************************************************************************
1032 * IEEE Chain Element structures
1033 ****************************************************************************/
1035 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1037 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1039 typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1041 MPI2_IEEE_SGE_CHAIN32 Chain32;
1042 MPI2_IEEE_SGE_CHAIN64 Chain64;
1043 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1044 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1047 /****************************************************************************
1048 * All IEEE SGE types union
1049 ****************************************************************************/
1051 typedef struct _MPI2_IEEE_SGE_UNION
1055 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1056 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1058 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1059 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1062 /****************************************************************************
1063 * IEEE SGE field definitions and masks
1064 ****************************************************************************/
1066 /* Flags field bit definitions */
1068 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1070 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1072 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1076 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1077 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1079 /* Data Location Address Space */
1081 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1082 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1083 /* IEEE Simple Element only */
1084 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1085 /* IEEE Simple Element only */
1086 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1087 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1088 /* IEEE Simple Element only */
1089 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1090 /* IEEE Chain Element only */
1091 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1092 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */
1094 /****************************************************************************
1095 * IEEE SGE operation Macros
1096 ****************************************************************************/
1098 /* SIMPLE FlagsLength manipulations... */
1099 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1100 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1101 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1103 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1105 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1106 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1107 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1109 /* CAUTION - The following are READ-MODIFY-WRITE! */
1110 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1111 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1116 /*****************************************************************************
1118 * Fusion-MPT MPI/IEEE Scatter Gather Unions
1120 *****************************************************************************/
1122 typedef union _MPI2_SIMPLE_SGE_UNION
1124 MPI2_SGE_SIMPLE_UNION MpiSimple;
1125 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1126 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1127 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1130 typedef union _MPI2_SGE_IO_UNION
1132 MPI2_SGE_SIMPLE_UNION MpiSimple;
1133 MPI2_SGE_CHAIN_UNION MpiChain;
1134 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1135 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1136 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1137 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1140 /****************************************************************************
1142 * Values for SGLFlags field, used in many request messages with an SGL
1144 ****************************************************************************/
1146 /* values for MPI SGL Data Location Address Space subfield */
1147 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1148 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1149 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1150 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1151 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1152 /* values for SGL Type subfield */
1153 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1154 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1155 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1156 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)