2 * This is the Fusion MPT base driver providing common API layer interface
3 * for access to MPT (Message Passing Technology) firmware.
5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
6 * Copyright (C) 2012-2014 LSI Corporation
7 * Copyright (C) 2013-2014 Avago Technologies
8 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/init.h>
50 #include <linux/slab.h>
51 #include <linux/types.h>
52 #include <linux/pci.h>
53 #include <linux/kdev_t.h>
54 #include <linux/blkdev.h>
55 #include <linux/delay.h>
56 #include <linux/interrupt.h>
57 #include <linux/dma-mapping.h>
59 #include <linux/time.h>
60 #include <linux/kthread.h>
61 #include <linux/aer.h>
64 #include "mpt3sas_base.h"
66 static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
69 #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
71 /* maximum controller queue depth */
72 #define MAX_HBA_QUEUE_DEPTH 30000
73 #define MAX_CHAIN_DEPTH 100000
74 static int max_queue_depth = -1;
75 module_param(max_queue_depth, int, 0);
76 MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
78 static int max_sgl_entries = -1;
79 module_param(max_sgl_entries, int, 0);
80 MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
82 static int msix_disable = -1;
83 module_param(msix_disable, int, 0);
84 MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
86 static int max_msix_vectors = -1;
87 module_param(max_msix_vectors, int, 0);
88 MODULE_PARM_DESC(max_msix_vectors,
91 static int mpt3sas_fwfault_debug;
92 MODULE_PARM_DESC(mpt3sas_fwfault_debug,
93 " enable detection of firmware fault and halt firmware - (default=0)");
96 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
99 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
103 _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
105 int ret = param_set_int(val, kp);
106 struct MPT3SAS_ADAPTER *ioc;
111 pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
112 list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
113 ioc->fwfault_debug = mpt3sas_fwfault_debug;
116 module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
117 param_get_int, &mpt3sas_fwfault_debug, 0644);
120 * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
121 * @arg: input argument, used to derive ioc
123 * Return 0 if controller is removed from pci subsystem.
124 * Return -1 for other case.
126 static int mpt3sas_remove_dead_ioc_func(void *arg)
128 struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
129 struct pci_dev *pdev;
137 pci_stop_and_remove_bus_device_locked(pdev);
142 * _base_fault_reset_work - workq handling ioc fault conditions
143 * @work: input argument, used to derive ioc
149 _base_fault_reset_work(struct work_struct *work)
151 struct MPT3SAS_ADAPTER *ioc =
152 container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
156 struct task_struct *p;
159 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
160 if (ioc->shost_recovery)
162 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
164 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
165 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
166 pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
170 * Call _scsih_flush_pending_cmds callback so that we flush all
171 * pending commands back to OS. This call is required to aovid
172 * deadlock at block layer. Dead IOC will fail to do diag reset,
173 * and this call is safe since dead ioc will never return any
174 * command back from HW.
176 ioc->schedule_dead_ioc_flush_running_cmds(ioc);
178 * Set remove_host flag early since kernel thread will
179 * take some time to execute.
181 ioc->remove_host = 1;
182 /*Remove the Dead Host */
183 p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
184 "mpt3sas_dead_ioc_%d", ioc->id);
187 "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
188 ioc->name, __func__);
191 "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
192 ioc->name, __func__);
193 return; /* don't rearm timer */
196 if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
197 rc = mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
199 pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
200 __func__, (rc == 0) ? "success" : "failed");
201 doorbell = mpt3sas_base_get_iocstate(ioc, 0);
202 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
203 mpt3sas_base_fault_info(ioc, doorbell &
204 MPI2_DOORBELL_DATA_MASK);
205 if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
206 MPI2_IOC_STATE_OPERATIONAL)
207 return; /* don't rearm timer */
210 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
212 if (ioc->fault_reset_work_q)
213 queue_delayed_work(ioc->fault_reset_work_q,
214 &ioc->fault_reset_work,
215 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
216 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
220 * mpt3sas_base_start_watchdog - start the fault_reset_work_q
221 * @ioc: per adapter object
227 mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
231 if (ioc->fault_reset_work_q)
234 /* initialize fault polling */
236 INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
237 snprintf(ioc->fault_reset_work_q_name,
238 sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
239 ioc->fault_reset_work_q =
240 create_singlethread_workqueue(ioc->fault_reset_work_q_name);
241 if (!ioc->fault_reset_work_q) {
242 pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
243 ioc->name, __func__, __LINE__);
246 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
247 if (ioc->fault_reset_work_q)
248 queue_delayed_work(ioc->fault_reset_work_q,
249 &ioc->fault_reset_work,
250 msecs_to_jiffies(FAULT_POLLING_INTERVAL));
251 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
255 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
256 * @ioc: per adapter object
262 mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
265 struct workqueue_struct *wq;
267 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
268 wq = ioc->fault_reset_work_q;
269 ioc->fault_reset_work_q = NULL;
270 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
272 if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
274 destroy_workqueue(wq);
279 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
280 * @ioc: per adapter object
281 * @fault_code: fault code
286 mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
288 pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
289 ioc->name, fault_code);
293 * mpt3sas_halt_firmware - halt's mpt controller firmware
294 * @ioc: per adapter object
296 * For debugging timeout related issues. Writing 0xCOFFEE00
297 * to the doorbell register will halt controller firmware. With
298 * the purpose to stop both driver and firmware, the enduser can
299 * obtain a ring buffer from controller UART.
302 mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
306 if (!ioc->fwfault_debug)
311 doorbell = readl(&ioc->chip->Doorbell);
312 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
313 mpt3sas_base_fault_info(ioc , doorbell);
315 writel(0xC0FFEE00, &ioc->chip->Doorbell);
316 pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
320 if (ioc->fwfault_debug == 2)
324 panic("panic in %s\n", __func__);
327 #ifdef CONFIG_SCSI_MPT3SAS_LOGGING
329 * _base_sas_ioc_info - verbose translation of the ioc status
330 * @ioc: per adapter object
331 * @mpi_reply: reply mf payload returned from firmware
332 * @request_hdr: request mf
337 _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
338 MPI2RequestHeader_t *request_hdr)
340 u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
344 char *func_str = NULL;
346 /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
347 if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
348 request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
349 request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
352 if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
355 switch (ioc_status) {
357 /****************************************************************************
358 * Common IOCStatus values for all replies
359 ****************************************************************************/
361 case MPI2_IOCSTATUS_INVALID_FUNCTION:
362 desc = "invalid function";
364 case MPI2_IOCSTATUS_BUSY:
367 case MPI2_IOCSTATUS_INVALID_SGL:
368 desc = "invalid sgl";
370 case MPI2_IOCSTATUS_INTERNAL_ERROR:
371 desc = "internal error";
373 case MPI2_IOCSTATUS_INVALID_VPID:
374 desc = "invalid vpid";
376 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
377 desc = "insufficient resources";
379 case MPI2_IOCSTATUS_INVALID_FIELD:
380 desc = "invalid field";
382 case MPI2_IOCSTATUS_INVALID_STATE:
383 desc = "invalid state";
385 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
386 desc = "op state not supported";
389 /****************************************************************************
390 * Config IOCStatus values
391 ****************************************************************************/
393 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
394 desc = "config invalid action";
396 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
397 desc = "config invalid type";
399 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
400 desc = "config invalid page";
402 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
403 desc = "config invalid data";
405 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
406 desc = "config no defaults";
408 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
409 desc = "config cant commit";
412 /****************************************************************************
414 ****************************************************************************/
416 case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
417 case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
418 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
419 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
420 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
421 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
422 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
423 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
424 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
425 case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
426 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
427 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
430 /****************************************************************************
431 * For use by SCSI Initiator and SCSI Target end-to-end data protection
432 ****************************************************************************/
434 case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
435 desc = "eedp guard error";
437 case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
438 desc = "eedp ref tag error";
440 case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
441 desc = "eedp app tag error";
444 /****************************************************************************
446 ****************************************************************************/
448 case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
449 desc = "target invalid io index";
451 case MPI2_IOCSTATUS_TARGET_ABORTED:
452 desc = "target aborted";
454 case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
455 desc = "target no conn retryable";
457 case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
458 desc = "target no connection";
460 case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
461 desc = "target xfer count mismatch";
463 case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
464 desc = "target data offset error";
466 case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
467 desc = "target too much write data";
469 case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
470 desc = "target iu too short";
472 case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
473 desc = "target ack nak timeout";
475 case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
476 desc = "target nak received";
479 /****************************************************************************
480 * Serial Attached SCSI values
481 ****************************************************************************/
483 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
484 desc = "smp request failed";
486 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
487 desc = "smp data overrun";
490 /****************************************************************************
491 * Diagnostic Buffer Post / Diagnostic Release values
492 ****************************************************************************/
494 case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
495 desc = "diagnostic released";
504 switch (request_hdr->Function) {
505 case MPI2_FUNCTION_CONFIG:
506 frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
507 func_str = "config_page";
509 case MPI2_FUNCTION_SCSI_TASK_MGMT:
510 frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
511 func_str = "task_mgmt";
513 case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
514 frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
515 func_str = "sas_iounit_ctl";
517 case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
518 frame_sz = sizeof(Mpi2SepRequest_t);
519 func_str = "enclosure";
521 case MPI2_FUNCTION_IOC_INIT:
522 frame_sz = sizeof(Mpi2IOCInitRequest_t);
523 func_str = "ioc_init";
525 case MPI2_FUNCTION_PORT_ENABLE:
526 frame_sz = sizeof(Mpi2PortEnableRequest_t);
527 func_str = "port_enable";
529 case MPI2_FUNCTION_SMP_PASSTHROUGH:
530 frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
531 func_str = "smp_passthru";
535 func_str = "unknown";
539 pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
540 ioc->name, desc, ioc_status, request_hdr, func_str);
542 _debug_dump_mf(request_hdr, frame_sz/4);
546 * _base_display_event_data - verbose translation of firmware asyn events
547 * @ioc: per adapter object
548 * @mpi_reply: reply mf payload returned from firmware
553 _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
554 Mpi2EventNotificationReply_t *mpi_reply)
559 if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
562 event = le16_to_cpu(mpi_reply->Event);
565 case MPI2_EVENT_LOG_DATA:
568 case MPI2_EVENT_STATE_CHANGE:
569 desc = "Status Change";
571 case MPI2_EVENT_HARD_RESET_RECEIVED:
572 desc = "Hard Reset Received";
574 case MPI2_EVENT_EVENT_CHANGE:
575 desc = "Event Change";
577 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
578 desc = "Device Status Change";
580 case MPI2_EVENT_IR_OPERATION_STATUS:
581 desc = "IR Operation Status";
583 case MPI2_EVENT_SAS_DISCOVERY:
585 Mpi2EventDataSasDiscovery_t *event_data =
586 (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
587 pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
588 (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
590 if (event_data->DiscoveryStatus)
591 pr_info("discovery_status(0x%08x)",
592 le32_to_cpu(event_data->DiscoveryStatus));
596 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
597 desc = "SAS Broadcast Primitive";
599 case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
600 desc = "SAS Init Device Status Change";
602 case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
603 desc = "SAS Init Table Overflow";
605 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
606 desc = "SAS Topology Change List";
608 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
609 desc = "SAS Enclosure Device Status Change";
611 case MPI2_EVENT_IR_VOLUME:
614 case MPI2_EVENT_IR_PHYSICAL_DISK:
615 desc = "IR Physical Disk";
617 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
618 desc = "IR Configuration Change List";
620 case MPI2_EVENT_LOG_ENTRY_ADDED:
621 desc = "Log Entry Added";
623 case MPI2_EVENT_TEMP_THRESHOLD:
624 desc = "Temperature Threshold";
631 pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
636 * _base_sas_log_info - verbose translation of firmware log info
637 * @ioc: per adapter object
638 * @log_info: log info
643 _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
654 union loginfo_type sas_loginfo;
655 char *originator_str = NULL;
657 sas_loginfo.loginfo = log_info;
658 if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
661 /* each nexus loss loginfo */
662 if (log_info == 0x31170000)
665 /* eat the loginfos associated with task aborts */
666 if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
667 0x31140000 || log_info == 0x31130000))
670 switch (sas_loginfo.dw.originator) {
672 originator_str = "IOP";
675 originator_str = "PL";
678 originator_str = "IR";
683 "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
685 originator_str, sas_loginfo.dw.code,
686 sas_loginfo.dw.subcode);
690 * _base_display_reply_info -
691 * @ioc: per adapter object
692 * @smid: system request message index
693 * @msix_index: MSIX table index supplied by the OS
694 * @reply: reply message frame(lower 32bit addr)
699 _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
702 MPI2DefaultReply_t *mpi_reply;
706 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
707 if (unlikely(!mpi_reply)) {
708 pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
709 ioc->name, __FILE__, __LINE__, __func__);
712 ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
713 #ifdef CONFIG_SCSI_MPT3SAS_LOGGING
714 if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
715 (ioc->logging_level & MPT_DEBUG_REPLY)) {
716 _base_sas_ioc_info(ioc , mpi_reply,
717 mpt3sas_base_get_msg_frame(ioc, smid));
720 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
721 loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
722 _base_sas_log_info(ioc, loginfo);
725 if (ioc_status || loginfo) {
726 ioc_status &= MPI2_IOCSTATUS_MASK;
727 mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
732 * mpt3sas_base_done - base internal command completion routine
733 * @ioc: per adapter object
734 * @smid: system request message index
735 * @msix_index: MSIX table index supplied by the OS
736 * @reply: reply message frame(lower 32bit addr)
738 * Return 1 meaning mf should be freed from _base_interrupt
739 * 0 means the mf is freed from this function.
742 mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
745 MPI2DefaultReply_t *mpi_reply;
747 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
748 if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
751 if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
754 ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
756 ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
757 memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
759 ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
761 complete(&ioc->base_cmds.done);
766 * _base_async_event - main callback handler for firmware asyn events
767 * @ioc: per adapter object
768 * @msix_index: MSIX table index supplied by the OS
769 * @reply: reply message frame(lower 32bit addr)
771 * Return 1 meaning mf should be freed from _base_interrupt
772 * 0 means the mf is freed from this function.
775 _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
777 Mpi2EventNotificationReply_t *mpi_reply;
778 Mpi2EventAckRequest_t *ack_request;
781 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
784 if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
786 #ifdef CONFIG_SCSI_MPT3SAS_LOGGING
787 _base_display_event_data(ioc, mpi_reply);
789 if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
791 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
793 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
794 ioc->name, __func__);
798 ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
799 memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
800 ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
801 ack_request->Event = mpi_reply->Event;
802 ack_request->EventContext = mpi_reply->EventContext;
803 ack_request->VF_ID = 0; /* TODO */
804 ack_request->VP_ID = 0;
805 mpt3sas_base_put_smid_default(ioc, smid);
809 /* scsih callback handler */
810 mpt3sas_scsih_event_callback(ioc, msix_index, reply);
812 /* ctl callback handler */
813 mpt3sas_ctl_event_callback(ioc, msix_index, reply);
819 * _base_get_cb_idx - obtain the callback index
820 * @ioc: per adapter object
821 * @smid: system request message index
823 * Return callback index.
826 _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
831 if (smid < ioc->hi_priority_smid) {
833 cb_idx = ioc->scsi_lookup[i].cb_idx;
834 } else if (smid < ioc->internal_smid) {
835 i = smid - ioc->hi_priority_smid;
836 cb_idx = ioc->hpr_lookup[i].cb_idx;
837 } else if (smid <= ioc->hba_queue_depth) {
838 i = smid - ioc->internal_smid;
839 cb_idx = ioc->internal_lookup[i].cb_idx;
846 * _base_mask_interrupts - disable interrupts
847 * @ioc: per adapter object
849 * Disabling ResetIRQ, Reply and Doorbell Interrupts
854 _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
858 ioc->mask_interrupts = 1;
859 him_register = readl(&ioc->chip->HostInterruptMask);
860 him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
861 writel(him_register, &ioc->chip->HostInterruptMask);
862 readl(&ioc->chip->HostInterruptMask);
866 * _base_unmask_interrupts - enable interrupts
867 * @ioc: per adapter object
869 * Enabling only Reply Interrupts
874 _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
878 him_register = readl(&ioc->chip->HostInterruptMask);
879 him_register &= ~MPI2_HIM_RIM;
880 writel(him_register, &ioc->chip->HostInterruptMask);
881 ioc->mask_interrupts = 0;
884 union reply_descriptor {
893 * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
894 * @irq: irq number (not used)
895 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
896 * @r: pt_regs pointer (not used)
898 * Return IRQ_HANDLE if processed, else IRQ_NONE.
901 _base_interrupt(int irq, void *bus_id)
903 struct adapter_reply_queue *reply_q = bus_id;
904 union reply_descriptor rd;
906 u8 request_desript_type;
910 u8 msix_index = reply_q->msix_index;
911 struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
912 Mpi2ReplyDescriptorsUnion_t *rpf;
915 if (ioc->mask_interrupts)
918 if (!atomic_add_unless(&reply_q->busy, 1, 1))
921 rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
922 request_desript_type = rpf->Default.ReplyFlags
923 & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
924 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
925 atomic_dec(&reply_q->busy);
932 rd.word = le64_to_cpu(rpf->Words);
933 if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
936 smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
937 if (request_desript_type ==
938 MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
939 request_desript_type ==
940 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
941 cb_idx = _base_get_cb_idx(ioc, smid);
942 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
943 (likely(mpt_callbacks[cb_idx] != NULL))) {
944 rc = mpt_callbacks[cb_idx](ioc, smid,
947 mpt3sas_base_free_smid(ioc, smid);
949 } else if (request_desript_type ==
950 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
952 rpf->AddressReply.ReplyFrameAddress);
953 if (reply > ioc->reply_dma_max_address ||
954 reply < ioc->reply_dma_min_address)
957 cb_idx = _base_get_cb_idx(ioc, smid);
958 if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
959 (likely(mpt_callbacks[cb_idx] != NULL))) {
960 rc = mpt_callbacks[cb_idx](ioc, smid,
963 _base_display_reply_info(ioc,
964 smid, msix_index, reply);
966 mpt3sas_base_free_smid(ioc,
970 _base_async_event(ioc, msix_index, reply);
973 /* reply free queue handling */
975 ioc->reply_free_host_index =
976 (ioc->reply_free_host_index ==
977 (ioc->reply_free_queue_depth - 1)) ?
978 0 : ioc->reply_free_host_index + 1;
979 ioc->reply_free[ioc->reply_free_host_index] =
982 writel(ioc->reply_free_host_index,
983 &ioc->chip->ReplyFreeHostIndex);
987 rpf->Words = cpu_to_le64(ULLONG_MAX);
988 reply_q->reply_post_host_index =
989 (reply_q->reply_post_host_index ==
990 (ioc->reply_post_queue_depth - 1)) ? 0 :
991 reply_q->reply_post_host_index + 1;
992 request_desript_type =
993 reply_q->reply_post_free[reply_q->reply_post_host_index].
994 Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
996 if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
998 if (!reply_q->reply_post_host_index)
999 rpf = reply_q->reply_post_free;
1006 if (!completed_cmds) {
1007 atomic_dec(&reply_q->busy);
1013 /* Update Reply Post Host Index.
1014 * For those HBA's which support combined reply queue feature
1015 * 1. Get the correct Supplemental Reply Post Host Index Register.
1016 * i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1017 * Index Register address bank i.e replyPostRegisterIndex[],
1018 * 2. Then update this register with new reply host index value
1019 * in ReplyPostIndex field and the MSIxIndex field with
1020 * msix_index value reduced to a value between 0 and 7,
1021 * using a modulo 8 operation. Since each Supplemental Reply Post
1022 * Host Index Register supports 8 MSI-X vectors.
1024 * For other HBA's just update the Reply Post Host Index register with
1025 * new reply host index value in ReplyPostIndex Field and msix_index
1026 * value in MSIxIndex field.
1028 if (ioc->msix96_vector)
1029 writel(reply_q->reply_post_host_index | ((msix_index & 7) <<
1030 MPI2_RPHI_MSIX_INDEX_SHIFT),
1031 ioc->replyPostRegisterIndex[msix_index/8]);
1033 writel(reply_q->reply_post_host_index | (msix_index <<
1034 MPI2_RPHI_MSIX_INDEX_SHIFT),
1035 &ioc->chip->ReplyPostHostIndex);
1036 atomic_dec(&reply_q->busy);
1041 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1042 * @ioc: per adapter object
1046 _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1048 return (ioc->facts.IOCCapabilities &
1049 MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1053 * mpt3sas_base_flush_reply_queues - flushing the MSIX reply queues
1054 * @ioc: per adapter object
1055 * Context: ISR conext
1057 * Called when a Task Management request has completed. We want
1058 * to flush the other reply queues so all the outstanding IO has been
1059 * completed back to OS before we process the TM completetion.
1064 mpt3sas_base_flush_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1066 struct adapter_reply_queue *reply_q;
1068 /* If MSIX capability is turned off
1069 * then multi-queues are not enabled
1071 if (!_base_is_controller_msix_enabled(ioc))
1074 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1075 if (ioc->shost_recovery)
1077 /* TMs are on msix_index == 0 */
1078 if (reply_q->msix_index == 0)
1080 _base_interrupt(reply_q->vector, (void *)reply_q);
1085 * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1086 * @cb_idx: callback index
1091 mpt3sas_base_release_callback_handler(u8 cb_idx)
1093 mpt_callbacks[cb_idx] = NULL;
1097 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1098 * @cb_func: callback function
1103 mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1107 for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1108 if (mpt_callbacks[cb_idx] == NULL)
1111 mpt_callbacks[cb_idx] = cb_func;
1116 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1121 mpt3sas_base_initialize_callback_handler(void)
1125 for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1126 mpt3sas_base_release_callback_handler(cb_idx);
1131 * _base_build_zero_len_sge - build zero length sg entry
1132 * @ioc: per adapter object
1133 * @paddr: virtual address for SGE
1135 * Create a zero length scatter gather entry to insure the IOCs hardware has
1136 * something to use if the target device goes brain dead and tries
1137 * to send data even when none is asked for.
1142 _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1144 u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1145 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1146 MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1147 MPI2_SGE_FLAGS_SHIFT);
1148 ioc->base_add_sg_single(paddr, flags_length, -1);
1152 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1153 * @paddr: virtual address for SGE
1154 * @flags_length: SGE flags and data transfer length
1155 * @dma_addr: Physical address
1160 _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1162 Mpi2SGESimple32_t *sgel = paddr;
1164 flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1165 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1166 sgel->FlagsLength = cpu_to_le32(flags_length);
1167 sgel->Address = cpu_to_le32(dma_addr);
1172 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
1173 * @paddr: virtual address for SGE
1174 * @flags_length: SGE flags and data transfer length
1175 * @dma_addr: Physical address
1180 _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1182 Mpi2SGESimple64_t *sgel = paddr;
1184 flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
1185 MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1186 sgel->FlagsLength = cpu_to_le32(flags_length);
1187 sgel->Address = cpu_to_le64(dma_addr);
1191 * _base_get_chain_buffer_tracker - obtain chain tracker
1192 * @ioc: per adapter object
1193 * @smid: smid associated to an IO request
1195 * Returns chain tracker(from ioc->free_chain_list)
1197 static struct chain_tracker *
1198 _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1200 struct chain_tracker *chain_req;
1201 unsigned long flags;
1203 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
1204 if (list_empty(&ioc->free_chain_list)) {
1205 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1206 dfailprintk(ioc, pr_warn(MPT3SAS_FMT
1207 "chain buffers not available\n", ioc->name));
1210 chain_req = list_entry(ioc->free_chain_list.next,
1211 struct chain_tracker, tracker_list);
1212 list_del_init(&chain_req->tracker_list);
1213 list_add_tail(&chain_req->tracker_list,
1214 &ioc->scsi_lookup[smid - 1].chain_list);
1215 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
1221 * _base_build_sg - build generic sg
1222 * @ioc: per adapter object
1223 * @psge: virtual address for SGE
1224 * @data_out_dma: physical address for WRITES
1225 * @data_out_sz: data xfer size for WRITES
1226 * @data_in_dma: physical address for READS
1227 * @data_in_sz: data xfer size for READS
1232 _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
1233 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1238 if (!data_out_sz && !data_in_sz) {
1239 _base_build_zero_len_sge(ioc, psge);
1243 if (data_out_sz && data_in_sz) {
1244 /* WRITE sgel first */
1245 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1246 MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
1247 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1248 ioc->base_add_sg_single(psge, sgl_flags |
1249 data_out_sz, data_out_dma);
1252 psge += ioc->sge_size;
1254 /* READ sgel last */
1255 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1256 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1257 MPI2_SGE_FLAGS_END_OF_LIST);
1258 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1259 ioc->base_add_sg_single(psge, sgl_flags |
1260 data_in_sz, data_in_dma);
1261 } else if (data_out_sz) /* WRITE */ {
1262 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1263 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1264 MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
1265 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1266 ioc->base_add_sg_single(psge, sgl_flags |
1267 data_out_sz, data_out_dma);
1268 } else if (data_in_sz) /* READ */ {
1269 sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
1270 MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
1271 MPI2_SGE_FLAGS_END_OF_LIST);
1272 sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
1273 ioc->base_add_sg_single(psge, sgl_flags |
1274 data_in_sz, data_in_dma);
1278 /* IEEE format sgls */
1281 * _base_add_sg_single_ieee - add sg element for IEEE format
1282 * @paddr: virtual address for SGE
1284 * @chain_offset: number of 128 byte elements from start of segment
1285 * @length: data transfer length
1286 * @dma_addr: Physical address
1291 _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
1292 dma_addr_t dma_addr)
1294 Mpi25IeeeSgeChain64_t *sgel = paddr;
1296 sgel->Flags = flags;
1297 sgel->NextChainOffset = chain_offset;
1298 sgel->Length = cpu_to_le32(length);
1299 sgel->Address = cpu_to_le64(dma_addr);
1303 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
1304 * @ioc: per adapter object
1305 * @paddr: virtual address for SGE
1307 * Create a zero length scatter gather entry to insure the IOCs hardware has
1308 * something to use if the target device goes brain dead and tries
1309 * to send data even when none is asked for.
1314 _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1316 u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1317 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
1318 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
1319 _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
1323 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
1324 * @ioc: per adapter object
1325 * @scmd: scsi command
1326 * @smid: system request message index
1329 * The main routine that builds scatter gather table from a given
1330 * scsi request sent via the .queuecommand main handler.
1332 * Returns 0 success, anything else error
1335 _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
1336 struct scsi_cmnd *scmd, u16 smid)
1338 Mpi2SCSIIORequest_t *mpi_request;
1339 dma_addr_t chain_dma;
1340 struct scatterlist *sg_scmd;
1341 void *sg_local, *chain;
1345 u32 sges_in_segment;
1346 u8 simple_sgl_flags;
1347 u8 simple_sgl_flags_last;
1349 struct chain_tracker *chain_req;
1351 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
1353 /* init scatter gather flags */
1354 simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1355 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1356 simple_sgl_flags_last = simple_sgl_flags |
1357 MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1358 chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
1359 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1361 sg_scmd = scsi_sglist(scmd);
1362 sges_left = scsi_dma_map(scmd);
1364 sdev_printk(KERN_ERR, scmd->device,
1365 "pci_map_sg failed: request for %d bytes!\n",
1366 scsi_bufflen(scmd));
1370 sg_local = &mpi_request->SGL;
1371 sges_in_segment = (ioc->request_sz -
1372 offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
1373 if (sges_left <= sges_in_segment)
1374 goto fill_in_last_segment;
1376 mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
1377 (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
1379 /* fill in main message segment when there is a chain following */
1380 while (sges_in_segment > 1) {
1381 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1382 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1383 sg_scmd = sg_next(sg_scmd);
1384 sg_local += ioc->sge_size_ieee;
1389 /* initializing the pointers */
1390 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1393 chain = chain_req->chain_buffer;
1394 chain_dma = chain_req->chain_buffer_dma;
1396 sges_in_segment = (sges_left <=
1397 ioc->max_sges_in_chain_message) ? sges_left :
1398 ioc->max_sges_in_chain_message;
1399 chain_offset = (sges_left == sges_in_segment) ?
1400 0 : sges_in_segment;
1401 chain_length = sges_in_segment * ioc->sge_size_ieee;
1403 chain_length += ioc->sge_size_ieee;
1404 _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
1405 chain_offset, chain_length, chain_dma);
1409 goto fill_in_last_segment;
1411 /* fill in chain segments */
1412 while (sges_in_segment) {
1413 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1414 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1415 sg_scmd = sg_next(sg_scmd);
1416 sg_local += ioc->sge_size_ieee;
1421 chain_req = _base_get_chain_buffer_tracker(ioc, smid);
1424 chain = chain_req->chain_buffer;
1425 chain_dma = chain_req->chain_buffer_dma;
1429 fill_in_last_segment:
1431 /* fill the last segment */
1434 _base_add_sg_single_ieee(sg_local,
1435 simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
1436 sg_dma_address(sg_scmd));
1438 _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
1439 sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
1440 sg_scmd = sg_next(sg_scmd);
1441 sg_local += ioc->sge_size_ieee;
1449 * _base_build_sg_ieee - build generic sg for IEEE format
1450 * @ioc: per adapter object
1451 * @psge: virtual address for SGE
1452 * @data_out_dma: physical address for WRITES
1453 * @data_out_sz: data xfer size for WRITES
1454 * @data_in_dma: physical address for READS
1455 * @data_in_sz: data xfer size for READS
1460 _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
1461 dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
1466 if (!data_out_sz && !data_in_sz) {
1467 _base_build_zero_len_sge_ieee(ioc, psge);
1471 if (data_out_sz && data_in_sz) {
1472 /* WRITE sgel first */
1473 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1474 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1475 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1479 psge += ioc->sge_size_ieee;
1481 /* READ sgel last */
1482 sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
1483 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1485 } else if (data_out_sz) /* WRITE */ {
1486 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1487 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1488 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1489 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
1491 } else if (data_in_sz) /* READ */ {
1492 sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
1493 MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
1494 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
1495 _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
1500 #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
1503 * _base_config_dma_addressing - set dma addressing
1504 * @ioc: per adapter object
1505 * @pdev: PCI device struct
1507 * Returns 0 for success, non-zero for failure.
1510 _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
1513 u64 consistent_dma_mask;
1516 consistent_dma_mask = DMA_BIT_MASK(64);
1518 consistent_dma_mask = DMA_BIT_MASK(32);
1520 if (sizeof(dma_addr_t) > 4) {
1521 const uint64_t required_mask =
1522 dma_get_required_mask(&pdev->dev);
1523 if ((required_mask > DMA_BIT_MASK(32)) &&
1524 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1525 !pci_set_consistent_dma_mask(pdev, consistent_dma_mask)) {
1526 ioc->base_add_sg_single = &_base_add_sg_single_64;
1527 ioc->sge_size = sizeof(Mpi2SGESimple64_t);
1533 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1534 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1535 ioc->base_add_sg_single = &_base_add_sg_single_32;
1536 ioc->sge_size = sizeof(Mpi2SGESimple32_t);
1544 "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
1545 ioc->name, ioc->dma_mask, convert_to_kb(s.totalram));
1551 _base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
1552 struct pci_dev *pdev)
1554 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1555 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
1562 * _base_check_enable_msix - checks MSIX capabable.
1563 * @ioc: per adapter object
1565 * Check to see if card is capable of MSIX, and set number
1566 * of available msix vectors
1569 _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1572 u16 message_control;
1574 base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
1576 dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
1581 /* get msix vector count */
1583 pci_read_config_word(ioc->pdev, base + 2, &message_control);
1584 ioc->msix_vector_count = (message_control & 0x3FF) + 1;
1585 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1586 "msix is supported, vector_count(%d)\n",
1587 ioc->name, ioc->msix_vector_count));
1592 * _base_free_irq - free irq
1593 * @ioc: per adapter object
1595 * Freeing respective reply_queue from the list.
1598 _base_free_irq(struct MPT3SAS_ADAPTER *ioc)
1600 struct adapter_reply_queue *reply_q, *next;
1602 if (list_empty(&ioc->reply_queue_list))
1605 list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1606 list_del(&reply_q->list);
1607 irq_set_affinity_hint(reply_q->vector, NULL);
1608 free_cpumask_var(reply_q->affinity_hint);
1609 synchronize_irq(reply_q->vector);
1610 free_irq(reply_q->vector, reply_q);
1616 * _base_request_irq - request irq
1617 * @ioc: per adapter object
1618 * @index: msix index into vector table
1619 * @vector: irq vector
1621 * Inserting respective reply_queue into the list.
1624 _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
1626 struct adapter_reply_queue *reply_q;
1629 reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
1631 pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
1632 ioc->name, (int)sizeof(struct adapter_reply_queue));
1636 reply_q->msix_index = index;
1637 reply_q->vector = vector;
1639 if (!alloc_cpumask_var(&reply_q->affinity_hint, GFP_KERNEL))
1641 cpumask_clear(reply_q->affinity_hint);
1643 atomic_set(&reply_q->busy, 0);
1644 if (ioc->msix_enable)
1645 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
1646 MPT3SAS_DRIVER_NAME, ioc->id, index);
1648 snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
1649 MPT3SAS_DRIVER_NAME, ioc->id);
1650 r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
1653 pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
1654 reply_q->name, vector);
1659 INIT_LIST_HEAD(&reply_q->list);
1660 list_add_tail(&reply_q->list, &ioc->reply_queue_list);
1665 * _base_assign_reply_queues - assigning msix index for each cpu
1666 * @ioc: per adapter object
1668 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
1670 * It would nice if we could call irq_set_affinity, however it is not
1671 * an exported symbol
1674 _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
1676 unsigned int cpu, nr_cpus, nr_msix, index = 0;
1677 struct adapter_reply_queue *reply_q;
1679 if (!_base_is_controller_msix_enabled(ioc))
1682 memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
1684 nr_cpus = num_online_cpus();
1685 nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
1686 ioc->facts.MaxMSIxVectors);
1690 cpu = cpumask_first(cpu_online_mask);
1692 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1694 unsigned int i, group = nr_cpus / nr_msix;
1699 if (index < nr_cpus % nr_msix)
1702 for (i = 0 ; i < group ; i++) {
1703 ioc->cpu_msix_table[cpu] = index;
1704 cpumask_or(reply_q->affinity_hint,
1705 reply_q->affinity_hint, get_cpu_mask(cpu));
1706 cpu = cpumask_next(cpu, cpu_online_mask);
1709 if (irq_set_affinity_hint(reply_q->vector,
1710 reply_q->affinity_hint))
1711 dinitprintk(ioc, pr_info(MPT3SAS_FMT
1712 "error setting affinity hint for irq vector %d\n",
1713 ioc->name, reply_q->vector));
1719 * _base_disable_msix - disables msix
1720 * @ioc: per adapter object
1724 _base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
1726 if (!ioc->msix_enable)
1728 pci_disable_msix(ioc->pdev);
1729 ioc->msix_enable = 0;
1733 * _base_enable_msix - enables msix, failback to io_apic
1734 * @ioc: per adapter object
1738 _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
1740 struct msix_entry *entries, *a;
1745 if (msix_disable == -1 || msix_disable == 0)
1751 if (_base_check_enable_msix(ioc) != 0)
1754 ioc->reply_queue_count = min_t(int, ioc->cpu_count,
1755 ioc->msix_vector_count);
1757 printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
1758 ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
1759 ioc->cpu_count, max_msix_vectors);
1761 if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
1762 max_msix_vectors = 8;
1764 if (max_msix_vectors > 0) {
1765 ioc->reply_queue_count = min_t(int, max_msix_vectors,
1766 ioc->reply_queue_count);
1767 ioc->msix_vector_count = ioc->reply_queue_count;
1768 } else if (max_msix_vectors == 0)
1771 entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
1774 dfailprintk(ioc, pr_info(MPT3SAS_FMT
1775 "kcalloc failed @ at %s:%d/%s() !!!\n",
1776 ioc->name, __FILE__, __LINE__, __func__));
1780 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
1783 r = pci_enable_msix_exact(ioc->pdev, entries, ioc->reply_queue_count);
1785 dfailprintk(ioc, pr_info(MPT3SAS_FMT
1786 "pci_enable_msix_exact failed (r=%d) !!!\n",
1792 ioc->msix_enable = 1;
1793 for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
1794 r = _base_request_irq(ioc, i, a->vector);
1796 _base_free_irq(ioc);
1797 _base_disable_msix(ioc);
1806 /* failback to io_apic interrupt routing */
1809 ioc->reply_queue_count = 1;
1810 r = _base_request_irq(ioc, 0, ioc->pdev->irq);
1816 * mpt3sas_base_unmap_resources - free controller resources
1817 * @ioc: per adapter object
1820 mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
1822 struct pci_dev *pdev = ioc->pdev;
1824 dexitprintk(ioc, printk(MPT3SAS_FMT "%s\n",
1825 ioc->name, __func__));
1827 _base_free_irq(ioc);
1828 _base_disable_msix(ioc);
1830 if (ioc->msix96_vector)
1831 kfree(ioc->replyPostRegisterIndex);
1833 if (ioc->chip_phys) {
1838 if (pci_is_enabled(pdev)) {
1839 pci_release_selected_regions(ioc->pdev, ioc->bars);
1840 pci_disable_pcie_error_reporting(pdev);
1841 pci_disable_device(pdev);
1846 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
1847 * @ioc: per adapter object
1849 * Returns 0 for success, non-zero for failure.
1852 mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
1854 struct pci_dev *pdev = ioc->pdev;
1860 struct adapter_reply_queue *reply_q;
1862 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
1863 ioc->name, __func__));
1865 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
1866 if (pci_enable_device_mem(pdev)) {
1867 pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
1874 if (pci_request_selected_regions(pdev, ioc->bars,
1875 MPT3SAS_DRIVER_NAME)) {
1876 pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
1883 /* AER (Advanced Error Reporting) hooks */
1884 pci_enable_pcie_error_reporting(pdev);
1886 pci_set_master(pdev);
1889 if (_base_config_dma_addressing(ioc, pdev) != 0) {
1890 pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
1891 ioc->name, pci_name(pdev));
1896 for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
1897 (!memap_sz || !pio_sz); i++) {
1898 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1901 pio_chip = (u64)pci_resource_start(pdev, i);
1902 pio_sz = pci_resource_len(pdev, i);
1903 } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
1906 ioc->chip_phys = pci_resource_start(pdev, i);
1907 chip_phys = (u64)ioc->chip_phys;
1908 memap_sz = pci_resource_len(pdev, i);
1909 ioc->chip = ioremap(ioc->chip_phys, memap_sz);
1913 if (ioc->chip == NULL) {
1914 pr_err(MPT3SAS_FMT "unable to map adapter memory! "
1915 " or resource not found\n", ioc->name);
1920 _base_mask_interrupts(ioc);
1922 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
1926 if (!ioc->rdpq_array_enable_assigned) {
1927 ioc->rdpq_array_enable = ioc->rdpq_array_capable;
1928 ioc->rdpq_array_enable_assigned = 1;
1931 r = _base_enable_msix(ioc);
1935 /* Use the Combined reply queue feature only for SAS3 C0 & higher
1936 * revision HBAs and also only when reply queue count is greater than 8
1938 if (ioc->msix96_vector && ioc->reply_queue_count > 8) {
1939 /* Determine the Supplemental Reply Post Host Index Registers
1940 * Addresse. Supplemental Reply Post Host Index Registers
1941 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
1942 * each register is at offset bytes of
1943 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
1945 ioc->replyPostRegisterIndex = kcalloc(
1946 MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT,
1947 sizeof(resource_size_t *), GFP_KERNEL);
1948 if (!ioc->replyPostRegisterIndex) {
1949 dfailprintk(ioc, printk(MPT3SAS_FMT
1950 "allocation for reply Post Register Index failed!!!\n",
1956 for (i = 0; i < MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT; i++) {
1957 ioc->replyPostRegisterIndex[i] = (resource_size_t *)
1958 ((u8 *)&ioc->chip->Doorbell +
1959 MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
1960 (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
1963 ioc->msix96_vector = 0;
1965 list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
1966 pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
1967 reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
1968 "IO-APIC enabled"), reply_q->vector);
1970 pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
1971 ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
1972 pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
1973 ioc->name, (unsigned long long)pio_chip, pio_sz);
1975 /* Save PCI configuration state for recovery from PCI AER/EEH errors */
1976 pci_save_state(pdev);
1980 mpt3sas_base_unmap_resources(ioc);
1985 * mpt3sas_base_get_msg_frame - obtain request mf pointer
1986 * @ioc: per adapter object
1987 * @smid: system request message index(smid zero is invalid)
1989 * Returns virt pointer to message frame.
1992 mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1994 return (void *)(ioc->request + (smid * ioc->request_sz));
1998 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
1999 * @ioc: per adapter object
2000 * @smid: system request message index
2002 * Returns virt pointer to sense buffer.
2005 mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2007 return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
2011 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
2012 * @ioc: per adapter object
2013 * @smid: system request message index
2015 * Returns phys pointer to the low 32bit address of the sense buffer.
2018 mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2020 return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
2021 SCSI_SENSE_BUFFERSIZE));
2025 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
2026 * @ioc: per adapter object
2027 * @phys_addr: lower 32 physical addr of the reply
2029 * Converts 32bit lower physical addr into a virt address.
2032 mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
2036 return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
2040 * mpt3sas_base_get_smid - obtain a free smid from internal queue
2041 * @ioc: per adapter object
2042 * @cb_idx: callback index
2044 * Returns smid (zero is invalid)
2047 mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2049 unsigned long flags;
2050 struct request_tracker *request;
2053 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2054 if (list_empty(&ioc->internal_free_list)) {
2055 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2056 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2057 ioc->name, __func__);
2061 request = list_entry(ioc->internal_free_list.next,
2062 struct request_tracker, tracker_list);
2063 request->cb_idx = cb_idx;
2064 smid = request->smid;
2065 list_del(&request->tracker_list);
2066 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2071 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
2072 * @ioc: per adapter object
2073 * @cb_idx: callback index
2074 * @scmd: pointer to scsi command object
2076 * Returns smid (zero is invalid)
2079 mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
2080 struct scsi_cmnd *scmd)
2082 unsigned long flags;
2083 struct scsiio_tracker *request;
2086 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2087 if (list_empty(&ioc->free_list)) {
2088 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2089 pr_err(MPT3SAS_FMT "%s: smid not available\n",
2090 ioc->name, __func__);
2094 request = list_entry(ioc->free_list.next,
2095 struct scsiio_tracker, tracker_list);
2096 request->scmd = scmd;
2097 request->cb_idx = cb_idx;
2098 smid = request->smid;
2099 list_del(&request->tracker_list);
2100 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2105 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
2106 * @ioc: per adapter object
2107 * @cb_idx: callback index
2109 * Returns smid (zero is invalid)
2112 mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
2114 unsigned long flags;
2115 struct request_tracker *request;
2118 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2119 if (list_empty(&ioc->hpr_free_list)) {
2120 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2124 request = list_entry(ioc->hpr_free_list.next,
2125 struct request_tracker, tracker_list);
2126 request->cb_idx = cb_idx;
2127 smid = request->smid;
2128 list_del(&request->tracker_list);
2129 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2134 * mpt3sas_base_free_smid - put smid back on free_list
2135 * @ioc: per adapter object
2136 * @smid: system request message index
2141 mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2143 unsigned long flags;
2145 struct chain_tracker *chain_req, *next;
2147 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
2148 if (smid < ioc->hi_priority_smid) {
2151 if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
2152 list_for_each_entry_safe(chain_req, next,
2153 &ioc->scsi_lookup[i].chain_list, tracker_list) {
2154 list_del_init(&chain_req->tracker_list);
2155 list_add(&chain_req->tracker_list,
2156 &ioc->free_chain_list);
2159 ioc->scsi_lookup[i].cb_idx = 0xFF;
2160 ioc->scsi_lookup[i].scmd = NULL;
2161 list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
2162 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2165 * See _wait_for_commands_to_complete() call with regards
2168 if (ioc->shost_recovery && ioc->pending_io_count) {
2169 if (ioc->pending_io_count == 1)
2170 wake_up(&ioc->reset_wq);
2171 ioc->pending_io_count--;
2174 } else if (smid < ioc->internal_smid) {
2176 i = smid - ioc->hi_priority_smid;
2177 ioc->hpr_lookup[i].cb_idx = 0xFF;
2178 list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
2179 } else if (smid <= ioc->hba_queue_depth) {
2180 /* internal queue */
2181 i = smid - ioc->internal_smid;
2182 ioc->internal_lookup[i].cb_idx = 0xFF;
2183 list_add(&ioc->internal_lookup[i].tracker_list,
2184 &ioc->internal_free_list);
2186 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
2190 * _base_writeq - 64 bit write to MMIO
2191 * @ioc: per adapter object
2193 * @addr: address in MMIO space
2194 * @writeq_lock: spin lock
2196 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
2197 * care of 32 bit environment where its not quarenteed to send the entire word
2200 #if defined(writeq) && defined(CONFIG_64BIT)
2202 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2204 writeq(cpu_to_le64(b), addr);
2208 _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
2210 unsigned long flags;
2211 __u64 data_out = cpu_to_le64(b);
2213 spin_lock_irqsave(writeq_lock, flags);
2214 writel((u32)(data_out), addr);
2215 writel((u32)(data_out >> 32), (addr + 4));
2216 spin_unlock_irqrestore(writeq_lock, flags);
2221 _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
2223 return ioc->cpu_msix_table[raw_smp_processor_id()];
2227 * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
2228 * @ioc: per adapter object
2229 * @smid: system request message index
2230 * @handle: device handle
2235 mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
2237 Mpi2RequestDescriptorUnion_t descriptor;
2238 u64 *request = (u64 *)&descriptor;
2241 descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
2242 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2243 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2244 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2245 descriptor.SCSIIO.LMID = 0;
2246 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2247 &ioc->scsi_lookup_lock);
2251 * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
2252 * @ioc: per adapter object
2253 * @smid: system request message index
2254 * @handle: device handle
2259 mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2262 Mpi2RequestDescriptorUnion_t descriptor;
2263 u64 *request = (u64 *)&descriptor;
2265 descriptor.SCSIIO.RequestFlags =
2266 MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
2267 descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
2268 descriptor.SCSIIO.SMID = cpu_to_le16(smid);
2269 descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
2270 descriptor.SCSIIO.LMID = 0;
2271 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2272 &ioc->scsi_lookup_lock);
2276 * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
2277 * @ioc: per adapter object
2278 * @smid: system request message index
2283 mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2285 Mpi2RequestDescriptorUnion_t descriptor;
2286 u64 *request = (u64 *)&descriptor;
2288 descriptor.HighPriority.RequestFlags =
2289 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
2290 descriptor.HighPriority.MSIxIndex = 0;
2291 descriptor.HighPriority.SMID = cpu_to_le16(smid);
2292 descriptor.HighPriority.LMID = 0;
2293 descriptor.HighPriority.Reserved1 = 0;
2294 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2295 &ioc->scsi_lookup_lock);
2299 * mpt3sas_base_put_smid_default - Default, primarily used for config pages
2300 * @ioc: per adapter object
2301 * @smid: system request message index
2306 mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
2308 Mpi2RequestDescriptorUnion_t descriptor;
2309 u64 *request = (u64 *)&descriptor;
2311 descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2312 descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
2313 descriptor.Default.SMID = cpu_to_le16(smid);
2314 descriptor.Default.LMID = 0;
2315 descriptor.Default.DescriptorTypeDependent = 0;
2316 _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
2317 &ioc->scsi_lookup_lock);
2321 * _base_display_intel_branding - Display branding string
2322 * @ioc: per adapter object
2327 _base_display_intel_branding(struct MPT3SAS_ADAPTER *ioc)
2329 if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
2332 switch (ioc->pdev->device) {
2333 case MPI25_MFGPAGE_DEVID_SAS3008:
2334 switch (ioc->pdev->subsystem_device) {
2335 case MPT3SAS_INTEL_RMS3JC080_SSDID:
2336 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2337 MPT3SAS_INTEL_RMS3JC080_BRANDING);
2340 case MPT3SAS_INTEL_RS3GC008_SSDID:
2341 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2342 MPT3SAS_INTEL_RS3GC008_BRANDING);
2344 case MPT3SAS_INTEL_RS3FC044_SSDID:
2345 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2346 MPT3SAS_INTEL_RS3FC044_BRANDING);
2348 case MPT3SAS_INTEL_RS3UC080_SSDID:
2349 pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2350 MPT3SAS_INTEL_RS3UC080_BRANDING);
2354 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2355 ioc->name, ioc->pdev->subsystem_device);
2361 "Intel(R) Controller: Subsystem ID: 0x%X\n",
2362 ioc->name, ioc->pdev->subsystem_device);
2370 * _base_display_ioc_capabilities - Disply IOC's capabilities.
2371 * @ioc: per adapter object
2376 _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
2380 u32 iounit_pg1_flags;
2383 bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
2384 strncpy(desc, ioc->manu_pg0.ChipName, 16);
2385 pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
2386 "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
2388 (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
2389 (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
2390 (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
2391 ioc->facts.FWVersion.Word & 0x000000FF,
2392 ioc->pdev->revision,
2393 (bios_version & 0xFF000000) >> 24,
2394 (bios_version & 0x00FF0000) >> 16,
2395 (bios_version & 0x0000FF00) >> 8,
2396 bios_version & 0x000000FF);
2398 _base_display_intel_branding(ioc);
2400 pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
2402 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
2403 pr_info("Initiator");
2407 if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
2408 pr_info("%sTarget", i ? "," : "");
2414 pr_info("Capabilities=(");
2416 if (ioc->facts.IOCCapabilities &
2417 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
2422 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
2423 pr_info("%sTLR", i ? "," : "");
2427 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
2428 pr_info("%sMulticast", i ? "," : "");
2432 if (ioc->facts.IOCCapabilities &
2433 MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
2434 pr_info("%sBIDI Target", i ? "," : "");
2438 if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
2439 pr_info("%sEEDP", i ? "," : "");
2443 if (ioc->facts.IOCCapabilities &
2444 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
2445 pr_info("%sSnapshot Buffer", i ? "," : "");
2449 if (ioc->facts.IOCCapabilities &
2450 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
2451 pr_info("%sDiag Trace Buffer", i ? "," : "");
2455 if (ioc->facts.IOCCapabilities &
2456 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
2457 pr_info("%sDiag Extended Buffer", i ? "," : "");
2461 if (ioc->facts.IOCCapabilities &
2462 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
2463 pr_info("%sTask Set Full", i ? "," : "");
2467 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2468 if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
2469 pr_info("%sNCQ", i ? "," : "");
2477 * mpt3sas_base_update_missing_delay - change the missing delay timers
2478 * @ioc: per adapter object
2479 * @device_missing_delay: amount of time till device is reported missing
2480 * @io_missing_delay: interval IO is returned when there is a missing device
2484 * Passed on the command line, this function will modify the device missing
2485 * delay, as well as the io missing delay. This should be called at driver
2489 mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
2490 u16 device_missing_delay, u8 io_missing_delay)
2492 u16 dmd, dmd_new, dmd_orignal;
2493 u8 io_missing_delay_original;
2495 Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
2496 Mpi2ConfigReply_t mpi_reply;
2500 mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
2504 sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
2505 sizeof(Mpi2SasIOUnit1PhyData_t));
2506 sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
2507 if (!sas_iounit_pg1) {
2508 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2509 ioc->name, __FILE__, __LINE__, __func__);
2512 if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
2513 sas_iounit_pg1, sz))) {
2514 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2515 ioc->name, __FILE__, __LINE__, __func__);
2518 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
2519 MPI2_IOCSTATUS_MASK;
2520 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
2521 pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
2522 ioc->name, __FILE__, __LINE__, __func__);
2526 /* device missing delay */
2527 dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
2528 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2529 dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2531 dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2533 if (device_missing_delay > 0x7F) {
2534 dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
2535 device_missing_delay;
2537 dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
2539 dmd = device_missing_delay;
2540 sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
2542 /* io missing delay */
2543 io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
2544 sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
2546 if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
2548 if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
2550 MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
2553 dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
2554 pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
2555 ioc->name, dmd_orignal, dmd_new);
2556 pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
2557 ioc->name, io_missing_delay_original,
2559 ioc->device_missing_delay = dmd_new;
2560 ioc->io_missing_delay = io_missing_delay;
2564 kfree(sas_iounit_pg1);
2567 * _base_static_config_pages - static start of day config pages
2568 * @ioc: per adapter object
2573 _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
2575 Mpi2ConfigReply_t mpi_reply;
2576 u32 iounit_pg1_flags;
2578 mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
2579 if (ioc->ir_firmware)
2580 mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
2584 * Ensure correct T10 PI operation if vendor left EEDPTagMode
2585 * flag unset in NVDATA.
2587 mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
2588 if (ioc->manu_pg11.EEDPTagMode == 0) {
2589 pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
2591 ioc->manu_pg11.EEDPTagMode &= ~0x3;
2592 ioc->manu_pg11.EEDPTagMode |= 0x1;
2593 mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
2597 mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
2598 mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
2599 mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
2600 mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
2601 mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2602 mpt3sas_config_get_iounit_pg8(ioc, &mpi_reply, &ioc->iounit_pg8);
2603 _base_display_ioc_capabilities(ioc);
2606 * Enable task_set_full handling in iounit_pg1 when the
2607 * facts capabilities indicate that its supported.
2609 iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
2610 if ((ioc->facts.IOCCapabilities &
2611 MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
2613 ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
2616 MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
2617 ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
2618 mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
2620 if (ioc->iounit_pg8.NumSensors)
2621 ioc->temp_sensors_count = ioc->iounit_pg8.NumSensors;
2625 * _base_release_memory_pools - release memory
2626 * @ioc: per adapter object
2628 * Free memory allocated from _base_allocate_memory_pools.
2633 _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
2636 struct reply_post_struct *rps;
2638 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2642 pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
2643 ioc->request, ioc->request_dma);
2644 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2645 "request_pool(0x%p): free\n",
2646 ioc->name, ioc->request));
2647 ioc->request = NULL;
2651 pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
2652 if (ioc->sense_dma_pool)
2653 pci_pool_destroy(ioc->sense_dma_pool);
2654 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2655 "sense_pool(0x%p): free\n",
2656 ioc->name, ioc->sense));
2661 pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
2662 if (ioc->reply_dma_pool)
2663 pci_pool_destroy(ioc->reply_dma_pool);
2664 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2665 "reply_pool(0x%p): free\n",
2666 ioc->name, ioc->reply));
2670 if (ioc->reply_free) {
2671 pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
2672 ioc->reply_free_dma);
2673 if (ioc->reply_free_dma_pool)
2674 pci_pool_destroy(ioc->reply_free_dma_pool);
2675 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2676 "reply_free_pool(0x%p): free\n",
2677 ioc->name, ioc->reply_free));
2678 ioc->reply_free = NULL;
2681 if (ioc->reply_post) {
2683 rps = &ioc->reply_post[i];
2684 if (rps->reply_post_free) {
2686 ioc->reply_post_free_dma_pool,
2687 rps->reply_post_free,
2688 rps->reply_post_free_dma);
2689 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2690 "reply_post_free_pool(0x%p): free\n",
2691 ioc->name, rps->reply_post_free));
2692 rps->reply_post_free = NULL;
2694 } while (ioc->rdpq_array_enable &&
2695 (++i < ioc->reply_queue_count));
2697 if (ioc->reply_post_free_dma_pool)
2698 pci_pool_destroy(ioc->reply_post_free_dma_pool);
2699 kfree(ioc->reply_post);
2702 if (ioc->config_page) {
2703 dexitprintk(ioc, pr_info(MPT3SAS_FMT
2704 "config_page(0x%p): free\n", ioc->name,
2706 pci_free_consistent(ioc->pdev, ioc->config_page_sz,
2707 ioc->config_page, ioc->config_page_dma);
2710 if (ioc->scsi_lookup) {
2711 free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
2712 ioc->scsi_lookup = NULL;
2714 kfree(ioc->hpr_lookup);
2715 kfree(ioc->internal_lookup);
2716 if (ioc->chain_lookup) {
2717 for (i = 0; i < ioc->chain_depth; i++) {
2718 if (ioc->chain_lookup[i].chain_buffer)
2719 pci_pool_free(ioc->chain_dma_pool,
2720 ioc->chain_lookup[i].chain_buffer,
2721 ioc->chain_lookup[i].chain_buffer_dma);
2723 if (ioc->chain_dma_pool)
2724 pci_pool_destroy(ioc->chain_dma_pool);
2725 free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
2726 ioc->chain_lookup = NULL;
2731 * _base_allocate_memory_pools - allocate start of day memory pools
2732 * @ioc: per adapter object
2733 * @sleep_flag: CAN_SLEEP or NO_SLEEP
2735 * Returns 0 success, anything else error
2738 _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
2740 struct mpt3sas_facts *facts;
2741 u16 max_sge_elements;
2742 u16 chains_needed_per_io;
2743 u32 sz, total_sz, reply_post_free_sz;
2745 u16 max_request_credit;
2746 unsigned short sg_tablesize;
2750 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
2755 facts = &ioc->facts;
2757 /* command line tunables for max sgl entries */
2758 if (max_sgl_entries != -1)
2759 sg_tablesize = max_sgl_entries;
2761 sg_tablesize = MPT3SAS_SG_DEPTH;
2763 if (sg_tablesize < MPT3SAS_MIN_PHYS_SEGMENTS)
2764 sg_tablesize = MPT3SAS_MIN_PHYS_SEGMENTS;
2765 else if (sg_tablesize > MPT3SAS_MAX_PHYS_SEGMENTS) {
2766 sg_tablesize = min_t(unsigned short, sg_tablesize,
2767 SCSI_MAX_SG_CHAIN_SEGMENTS);
2769 "sg_tablesize(%u) is bigger than kernel"
2770 " defined SCSI_MAX_SG_SEGMENTS(%u)\n", ioc->name,
2771 sg_tablesize, MPT3SAS_MAX_PHYS_SEGMENTS);
2773 ioc->shost->sg_tablesize = sg_tablesize;
2775 ioc->hi_priority_depth = facts->HighPriorityCredit;
2776 ioc->internal_depth = ioc->hi_priority_depth + (5);
2777 /* command line tunables for max controller queue depth */
2778 if (max_queue_depth != -1 && max_queue_depth != 0) {
2779 max_request_credit = min_t(u16, max_queue_depth +
2780 ioc->hi_priority_depth + ioc->internal_depth,
2781 facts->RequestCredit);
2782 if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
2783 max_request_credit = MAX_HBA_QUEUE_DEPTH;
2785 max_request_credit = min_t(u16, facts->RequestCredit,
2786 MAX_HBA_QUEUE_DEPTH);
2788 ioc->hba_queue_depth = max_request_credit;
2790 /* request frame size */
2791 ioc->request_sz = facts->IOCRequestFrameSize * 4;
2793 /* reply frame size */
2794 ioc->reply_sz = facts->ReplyFrameSize * 4;
2796 /* calculate the max scatter element size */
2797 sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
2801 /* calculate number of sg elements left over in the 1st frame */
2802 max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
2803 sizeof(Mpi2SGEIOUnion_t)) + sge_size);
2804 ioc->max_sges_in_main_message = max_sge_elements/sge_size;
2806 /* now do the same for a chain buffer */
2807 max_sge_elements = ioc->request_sz - sge_size;
2808 ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
2811 * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
2813 chains_needed_per_io = ((ioc->shost->sg_tablesize -
2814 ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
2816 if (chains_needed_per_io > facts->MaxChainDepth) {
2817 chains_needed_per_io = facts->MaxChainDepth;
2818 ioc->shost->sg_tablesize = min_t(u16,
2819 ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
2820 * chains_needed_per_io), ioc->shost->sg_tablesize);
2822 ioc->chains_needed_per_io = chains_needed_per_io;
2824 /* reply free queue sizing - taking into account for 64 FW events */
2825 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
2827 /* calculate reply descriptor post queue depth */
2828 ioc->reply_post_queue_depth = ioc->hba_queue_depth +
2829 ioc->reply_free_queue_depth + 1 ;
2830 /* align the reply post queue on the next 16 count boundary */
2831 if (ioc->reply_post_queue_depth % 16)
2832 ioc->reply_post_queue_depth += 16 -
2833 (ioc->reply_post_queue_depth % 16);
2836 if (ioc->reply_post_queue_depth >
2837 facts->MaxReplyDescriptorPostQueueDepth) {
2838 ioc->reply_post_queue_depth =
2839 facts->MaxReplyDescriptorPostQueueDepth -
2840 (facts->MaxReplyDescriptorPostQueueDepth % 16);
2841 ioc->hba_queue_depth =
2842 ((ioc->reply_post_queue_depth - 64) / 2) - 1;
2843 ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
2846 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
2847 "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
2848 "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
2849 ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
2850 ioc->chains_needed_per_io));
2852 /* reply post queue, 16 byte align */
2853 reply_post_free_sz = ioc->reply_post_queue_depth *
2854 sizeof(Mpi2DefaultReplyDescriptor_t);
2856 sz = reply_post_free_sz;
2857 if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
2858 sz *= ioc->reply_queue_count;
2860 ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
2861 (ioc->reply_queue_count):1,
2862 sizeof(struct reply_post_struct), GFP_KERNEL);
2864 if (!ioc->reply_post) {
2865 pr_err(MPT3SAS_FMT "reply_post_free pool: kcalloc failed\n",
2869 ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
2870 ioc->pdev, sz, 16, 0);
2871 if (!ioc->reply_post_free_dma_pool) {
2873 "reply_post_free pool: pci_pool_create failed\n",
2879 ioc->reply_post[i].reply_post_free =
2880 pci_pool_alloc(ioc->reply_post_free_dma_pool,
2882 &ioc->reply_post[i].reply_post_free_dma);
2883 if (!ioc->reply_post[i].reply_post_free) {
2885 "reply_post_free pool: pci_pool_alloc failed\n",
2889 memset(ioc->reply_post[i].reply_post_free, 0, sz);
2890 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2891 "reply post free pool (0x%p): depth(%d),"
2892 "element_size(%d), pool_size(%d kB)\n", ioc->name,
2893 ioc->reply_post[i].reply_post_free,
2894 ioc->reply_post_queue_depth, 8, sz/1024));
2895 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2896 "reply_post_free_dma = (0x%llx)\n", ioc->name,
2897 (unsigned long long)
2898 ioc->reply_post[i].reply_post_free_dma));
2900 } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
2902 if (ioc->dma_mask == 64) {
2903 if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
2905 "no suitable consistent DMA mask for %s\n",
2906 ioc->name, pci_name(ioc->pdev));
2911 ioc->scsiio_depth = ioc->hba_queue_depth -
2912 ioc->hi_priority_depth - ioc->internal_depth;
2914 /* set the scsi host can_queue depth
2915 * with some internal commands that could be outstanding
2917 ioc->shost->can_queue = ioc->scsiio_depth;
2918 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2919 "scsi host: can_queue depth (%d)\n",
2920 ioc->name, ioc->shost->can_queue));
2923 /* contiguous pool for request and chains, 16 byte align, one extra "
2926 ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
2927 sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
2929 /* hi-priority queue */
2930 sz += (ioc->hi_priority_depth * ioc->request_sz);
2932 /* internal queue */
2933 sz += (ioc->internal_depth * ioc->request_sz);
2935 ioc->request_dma_sz = sz;
2936 ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
2937 if (!ioc->request) {
2938 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
2939 "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
2940 "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
2941 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
2942 if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
2945 ioc->hba_queue_depth = max_request_credit - retry_sz;
2946 goto retry_allocation;
2950 pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
2951 "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
2952 "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
2953 ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
2955 /* hi-priority queue */
2956 ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
2958 ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
2961 /* internal queue */
2962 ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
2964 ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
2967 dinitprintk(ioc, pr_info(MPT3SAS_FMT
2968 "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
2969 ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
2970 (ioc->hba_queue_depth * ioc->request_sz)/1024));
2972 dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
2973 ioc->name, (unsigned long long) ioc->request_dma));
2976 sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
2977 ioc->scsi_lookup_pages = get_order(sz);
2978 ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
2979 GFP_KERNEL, ioc->scsi_lookup_pages);
2980 if (!ioc->scsi_lookup) {
2981 pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
2982 ioc->name, (int)sz);
2986 dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
2987 ioc->name, ioc->request, ioc->scsiio_depth));
2989 ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
2990 sz = ioc->chain_depth * sizeof(struct chain_tracker);
2991 ioc->chain_pages = get_order(sz);
2992 ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
2993 GFP_KERNEL, ioc->chain_pages);
2994 if (!ioc->chain_lookup) {
2995 pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
2999 ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
3000 ioc->request_sz, 16, 0);
3001 if (!ioc->chain_dma_pool) {
3002 pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
3006 for (i = 0; i < ioc->chain_depth; i++) {
3007 ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
3008 ioc->chain_dma_pool , GFP_KERNEL,
3009 &ioc->chain_lookup[i].chain_buffer_dma);
3010 if (!ioc->chain_lookup[i].chain_buffer) {
3011 ioc->chain_depth = i;
3014 total_sz += ioc->request_sz;
3017 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3018 "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
3019 ioc->name, ioc->chain_depth, ioc->request_sz,
3020 ((ioc->chain_depth * ioc->request_sz))/1024));
3022 /* initialize hi-priority queue smid's */
3023 ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
3024 sizeof(struct request_tracker), GFP_KERNEL);
3025 if (!ioc->hpr_lookup) {
3026 pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
3030 ioc->hi_priority_smid = ioc->scsiio_depth + 1;
3031 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3032 "hi_priority(0x%p): depth(%d), start smid(%d)\n",
3033 ioc->name, ioc->hi_priority,
3034 ioc->hi_priority_depth, ioc->hi_priority_smid));
3036 /* initialize internal queue smid's */
3037 ioc->internal_lookup = kcalloc(ioc->internal_depth,
3038 sizeof(struct request_tracker), GFP_KERNEL);
3039 if (!ioc->internal_lookup) {
3040 pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
3044 ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
3045 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3046 "internal(0x%p): depth(%d), start smid(%d)\n",
3047 ioc->name, ioc->internal,
3048 ioc->internal_depth, ioc->internal_smid));
3050 /* sense buffers, 4 byte align */
3051 sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
3052 ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
3054 if (!ioc->sense_dma_pool) {
3055 pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
3059 ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
3062 pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
3066 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3067 "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
3068 "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
3069 SCSI_SENSE_BUFFERSIZE, sz/1024));
3070 dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
3071 ioc->name, (unsigned long long)ioc->sense_dma));
3074 /* reply pool, 4 byte align */
3075 sz = ioc->reply_free_queue_depth * ioc->reply_sz;
3076 ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
3078 if (!ioc->reply_dma_pool) {
3079 pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
3083 ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
3086 pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
3090 ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
3091 ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
3092 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3093 "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
3094 ioc->name, ioc->reply,
3095 ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
3096 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
3097 ioc->name, (unsigned long long)ioc->reply_dma));
3100 /* reply free queue, 16 byte align */
3101 sz = ioc->reply_free_queue_depth * 4;
3102 ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
3103 ioc->pdev, sz, 16, 0);
3104 if (!ioc->reply_free_dma_pool) {
3105 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
3109 ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
3110 &ioc->reply_free_dma);
3111 if (!ioc->reply_free) {
3112 pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
3116 memset(ioc->reply_free, 0, sz);
3117 dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
3118 "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
3119 ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
3120 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3121 "reply_free_dma (0x%llx)\n",
3122 ioc->name, (unsigned long long)ioc->reply_free_dma));
3125 ioc->config_page_sz = 512;
3126 ioc->config_page = pci_alloc_consistent(ioc->pdev,
3127 ioc->config_page_sz, &ioc->config_page_dma);
3128 if (!ioc->config_page) {
3130 "config page: pci_pool_alloc failed\n",
3134 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3135 "config page(0x%p): size(%d)\n",
3136 ioc->name, ioc->config_page, ioc->config_page_sz));
3137 dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
3138 ioc->name, (unsigned long long)ioc->config_page_dma));
3139 total_sz += ioc->config_page_sz;
3141 pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
3142 ioc->name, total_sz/1024);
3144 "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
3145 ioc->name, ioc->shost->can_queue, facts->RequestCredit);
3146 pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
3147 ioc->name, ioc->shost->sg_tablesize);
3155 * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
3156 * @ioc: Pointer to MPT_ADAPTER structure
3157 * @cooked: Request raw or cooked IOC state
3159 * Returns all IOC Doorbell register bits if cooked==0, else just the
3160 * Doorbell bits in MPI_IOC_STATE_MASK.
3163 mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
3167 s = readl(&ioc->chip->Doorbell);
3168 sc = s & MPI2_IOC_STATE_MASK;
3169 return cooked ? sc : s;
3173 * _base_wait_on_iocstate - waiting on a particular ioc state
3174 * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
3175 * @timeout: timeout in second
3176 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3178 * Returns 0 for success, non-zero for failure.
3181 _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
3188 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3190 current_state = mpt3sas_base_get_iocstate(ioc, 1);
3191 if (current_state == ioc_state)
3193 if (count && current_state == MPI2_IOC_STATE_FAULT)
3195 if (sleep_flag == CAN_SLEEP)
3196 usleep_range(1000, 1500);
3202 return current_state;
3206 * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
3207 * a write to the doorbell)
3208 * @ioc: per adapter object
3209 * @timeout: timeout in second
3210 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3212 * Returns 0 for success, non-zero for failure.
3214 * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
3217 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag);
3220 _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout,
3227 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3229 int_status = readl(&ioc->chip->HostInterruptStatus);
3230 if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3231 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3232 "%s: successful count(%d), timeout(%d)\n",
3233 ioc->name, __func__, count, timeout));
3236 if (sleep_flag == CAN_SLEEP)
3237 usleep_range(1000, 1500);
3244 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3245 ioc->name, __func__, count, int_status);
3250 * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
3251 * @ioc: per adapter object
3252 * @timeout: timeout in second
3253 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3255 * Returns 0 for success, non-zero for failure.
3257 * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
3261 _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout,
3269 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3271 int_status = readl(&ioc->chip->HostInterruptStatus);
3272 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
3273 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3274 "%s: successful count(%d), timeout(%d)\n",
3275 ioc->name, __func__, count, timeout));
3277 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
3278 doorbell = readl(&ioc->chip->Doorbell);
3279 if ((doorbell & MPI2_IOC_STATE_MASK) ==
3280 MPI2_IOC_STATE_FAULT) {
3281 mpt3sas_base_fault_info(ioc , doorbell);
3284 } else if (int_status == 0xFFFFFFFF)
3287 if (sleep_flag == CAN_SLEEP)
3288 usleep_range(1000, 1500);
3296 "%s: failed due to timeout count(%d), int_status(%x)!\n",
3297 ioc->name, __func__, count, int_status);
3302 * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
3303 * @ioc: per adapter object
3304 * @timeout: timeout in second
3305 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3307 * Returns 0 for success, non-zero for failure.
3311 _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout,
3318 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
3320 doorbell_reg = readl(&ioc->chip->Doorbell);
3321 if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
3322 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3323 "%s: successful count(%d), timeout(%d)\n",
3324 ioc->name, __func__, count, timeout));
3327 if (sleep_flag == CAN_SLEEP)
3328 usleep_range(1000, 1500);
3335 "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
3336 ioc->name, __func__, count, doorbell_reg);
3341 * _base_send_ioc_reset - send doorbell reset
3342 * @ioc: per adapter object
3343 * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
3344 * @timeout: timeout in second
3345 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3347 * Returns 0 for success, non-zero for failure.
3350 _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout,
3356 if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
3357 pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
3358 ioc->name, __func__);
3362 if (!(ioc->facts.IOCCapabilities &
3363 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
3366 pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
3368 writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
3369 &ioc->chip->Doorbell);
3370 if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
3374 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
3375 timeout, sleep_flag);
3378 "%s: failed going to ready state (ioc_state=0x%x)\n",
3379 ioc->name, __func__, ioc_state);
3384 pr_info(MPT3SAS_FMT "message unit reset: %s\n",
3385 ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
3390 * _base_handshake_req_reply_wait - send request thru doorbell interface
3391 * @ioc: per adapter object
3392 * @request_bytes: request length
3393 * @request: pointer having request payload
3394 * @reply_bytes: reply length
3395 * @reply: pointer to reply payload
3396 * @timeout: timeout in second
3397 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3399 * Returns 0 for success, non-zero for failure.
3402 _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
3403 u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
3405 MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
3411 /* make sure doorbell is not in use */
3412 if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
3414 "doorbell is in use (line=%d)\n",
3415 ioc->name, __LINE__);
3419 /* clear pending doorbell interrupts from previous state changes */
3420 if (readl(&ioc->chip->HostInterruptStatus) &
3421 MPI2_HIS_IOC2SYS_DB_STATUS)
3422 writel(0, &ioc->chip->HostInterruptStatus);
3424 /* send message to ioc */
3425 writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
3426 ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
3427 &ioc->chip->Doorbell);
3429 if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
3431 "doorbell handshake int failed (line=%d)\n",
3432 ioc->name, __LINE__);
3435 writel(0, &ioc->chip->HostInterruptStatus);
3437 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
3439 "doorbell handshake ack failed (line=%d)\n",
3440 ioc->name, __LINE__);
3444 /* send message 32-bits at a time */
3445 for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
3446 writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
3447 if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
3453 "doorbell handshake sending request failed (line=%d)\n",
3454 ioc->name, __LINE__);
3458 /* now wait for the reply */
3459 if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
3461 "doorbell handshake int failed (line=%d)\n",
3462 ioc->name, __LINE__);
3466 /* read the first two 16-bits, it gives the total length of the reply */
3467 reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3468 & MPI2_DOORBELL_DATA_MASK);
3469 writel(0, &ioc->chip->HostInterruptStatus);
3470 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3472 "doorbell handshake int failed (line=%d)\n",
3473 ioc->name, __LINE__);
3476 reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3477 & MPI2_DOORBELL_DATA_MASK);
3478 writel(0, &ioc->chip->HostInterruptStatus);
3480 for (i = 2; i < default_reply->MsgLength * 2; i++) {
3481 if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
3483 "doorbell handshake int failed (line=%d)\n",
3484 ioc->name, __LINE__);
3487 if (i >= reply_bytes/2) /* overflow case */
3488 dummy = readl(&ioc->chip->Doorbell);
3490 reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
3491 & MPI2_DOORBELL_DATA_MASK);
3492 writel(0, &ioc->chip->HostInterruptStatus);
3495 _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
3496 if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
3497 dhsprintk(ioc, pr_info(MPT3SAS_FMT
3498 "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
3500 writel(0, &ioc->chip->HostInterruptStatus);
3502 if (ioc->logging_level & MPT_DEBUG_INIT) {
3503 mfp = (__le32 *)reply;
3504 pr_info("\toffset:data\n");
3505 for (i = 0; i < reply_bytes/4; i++)
3506 pr_info("\t[0x%02x]:%08x\n", i*4,
3507 le32_to_cpu(mfp[i]));
3513 * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
3514 * @ioc: per adapter object
3515 * @mpi_reply: the reply payload from FW
3516 * @mpi_request: the request payload sent to FW
3518 * The SAS IO Unit Control Request message allows the host to perform low-level
3519 * operations, such as resets on the PHYs of the IO Unit, also allows the host
3520 * to obtain the IOC assigned device handles for a device if it has other
3521 * identifying information about the device, in addition allows the host to
3522 * remove IOC resources associated with the device.
3524 * Returns 0 for success, non-zero for failure.
3527 mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
3528 Mpi2SasIoUnitControlReply_t *mpi_reply,
3529 Mpi2SasIoUnitControlRequest_t *mpi_request)
3533 unsigned long timeleft;
3534 bool issue_reset = false;
3537 u16 wait_state_count;
3539 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3542 mutex_lock(&ioc->base_cmds.mutex);
3544 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
3545 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
3546 ioc->name, __func__);
3551 wait_state_count = 0;
3552 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3553 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3554 if (wait_state_count++ == 10) {
3556 "%s: failed due to ioc not operational\n",
3557 ioc->name, __func__);
3562 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3564 "%s: waiting for operational state(count=%d)\n",
3565 ioc->name, __func__, wait_state_count);
3568 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3570 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3571 ioc->name, __func__);
3577 ioc->base_cmds.status = MPT3_CMD_PENDING;
3578 request = mpt3sas_base_get_msg_frame(ioc, smid);
3579 ioc->base_cmds.smid = smid;
3580 memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
3581 if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3582 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
3583 ioc->ioc_link_reset_in_progress = 1;
3584 init_completion(&ioc->base_cmds.done);
3585 mpt3sas_base_put_smid_default(ioc, smid);
3586 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3587 msecs_to_jiffies(10000));
3588 if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
3589 mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
3590 ioc->ioc_link_reset_in_progress)
3591 ioc->ioc_link_reset_in_progress = 0;
3592 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
3593 pr_err(MPT3SAS_FMT "%s: timeout\n",
3594 ioc->name, __func__);
3595 _debug_dump_mf(mpi_request,
3596 sizeof(Mpi2SasIoUnitControlRequest_t)/4);
3597 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
3599 goto issue_host_reset;
3601 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
3602 memcpy(mpi_reply, ioc->base_cmds.reply,
3603 sizeof(Mpi2SasIoUnitControlReply_t));
3605 memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
3606 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3611 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
3613 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3616 mutex_unlock(&ioc->base_cmds.mutex);
3621 * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
3622 * @ioc: per adapter object
3623 * @mpi_reply: the reply payload from FW
3624 * @mpi_request: the request payload sent to FW
3626 * The SCSI Enclosure Processor request message causes the IOC to
3627 * communicate with SES devices to control LED status signals.
3629 * Returns 0 for success, non-zero for failure.
3632 mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
3633 Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
3637 unsigned long timeleft;
3638 bool issue_reset = false;
3641 u16 wait_state_count;
3643 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3646 mutex_lock(&ioc->base_cmds.mutex);
3648 if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
3649 pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
3650 ioc->name, __func__);
3655 wait_state_count = 0;
3656 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3657 while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
3658 if (wait_state_count++ == 10) {
3660 "%s: failed due to ioc not operational\n",
3661 ioc->name, __func__);
3666 ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
3668 "%s: waiting for operational state(count=%d)\n",
3670 __func__, wait_state_count);
3673 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
3675 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
3676 ioc->name, __func__);
3682 ioc->base_cmds.status = MPT3_CMD_PENDING;
3683 request = mpt3sas_base_get_msg_frame(ioc, smid);
3684 ioc->base_cmds.smid = smid;
3685 memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
3686 init_completion(&ioc->base_cmds.done);
3687 mpt3sas_base_put_smid_default(ioc, smid);
3688 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
3689 msecs_to_jiffies(10000));
3690 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
3691 pr_err(MPT3SAS_FMT "%s: timeout\n",
3692 ioc->name, __func__);
3693 _debug_dump_mf(mpi_request,
3694 sizeof(Mpi2SepRequest_t)/4);
3695 if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
3696 issue_reset = false;
3697 goto issue_host_reset;
3699 if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
3700 memcpy(mpi_reply, ioc->base_cmds.reply,
3701 sizeof(Mpi2SepReply_t));
3703 memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
3704 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3709 mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
3711 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
3714 mutex_unlock(&ioc->base_cmds.mutex);
3719 * _base_get_port_facts - obtain port facts reply and save in ioc
3720 * @ioc: per adapter object
3721 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3723 * Returns 0 for success, non-zero for failure.
3726 _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port, int sleep_flag)
3728 Mpi2PortFactsRequest_t mpi_request;
3729 Mpi2PortFactsReply_t mpi_reply;
3730 struct mpt3sas_port_facts *pfacts;
3731 int mpi_reply_sz, mpi_request_sz, r;
3733 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3736 mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
3737 mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
3738 memset(&mpi_request, 0, mpi_request_sz);
3739 mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
3740 mpi_request.PortNumber = port;
3741 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
3742 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
3745 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
3746 ioc->name, __func__, r);
3750 pfacts = &ioc->pfacts[port];
3751 memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
3752 pfacts->PortNumber = mpi_reply.PortNumber;
3753 pfacts->VP_ID = mpi_reply.VP_ID;
3754 pfacts->VF_ID = mpi_reply.VF_ID;
3755 pfacts->MaxPostedCmdBuffers =
3756 le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
3762 * _base_wait_for_iocstate - Wait until the card is in READY or OPERATIONAL
3763 * @ioc: per adapter object
3765 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3767 * Returns 0 for success, non-zero for failure.
3770 _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout,
3776 dinitprintk(ioc, printk(MPT3SAS_FMT "%s\n", ioc->name,
3779 if (ioc->pci_error_recovery) {
3780 dfailprintk(ioc, printk(MPT3SAS_FMT
3781 "%s: host in pci error recovery\n", ioc->name, __func__));
3785 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
3786 dhsprintk(ioc, printk(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
3787 ioc->name, __func__, ioc_state));
3789 if (((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY) ||
3790 (ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
3793 if (ioc_state & MPI2_DOORBELL_USED) {
3794 dhsprintk(ioc, printk(MPT3SAS_FMT
3795 "unexpected doorbell active!\n", ioc->name));
3796 goto issue_diag_reset;
3799 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
3800 mpt3sas_base_fault_info(ioc, ioc_state &
3801 MPI2_DOORBELL_DATA_MASK);
3802 goto issue_diag_reset;
3805 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
3806 timeout, sleep_flag);
3808 dfailprintk(ioc, printk(MPT3SAS_FMT
3809 "%s: failed going to ready state (ioc_state=0x%x)\n",
3810 ioc->name, __func__, ioc_state));
3815 rc = _base_diag_reset(ioc, sleep_flag);
3820 * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
3821 * @ioc: per adapter object
3822 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3824 * Returns 0 for success, non-zero for failure.
3827 _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
3829 Mpi2IOCFactsRequest_t mpi_request;
3830 Mpi2IOCFactsReply_t mpi_reply;
3831 struct mpt3sas_facts *facts;
3832 int mpi_reply_sz, mpi_request_sz, r;
3834 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3837 r = _base_wait_for_iocstate(ioc, 10, sleep_flag);
3839 dfailprintk(ioc, printk(MPT3SAS_FMT
3840 "%s: failed getting to correct state\n",
3841 ioc->name, __func__));
3844 mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
3845 mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
3846 memset(&mpi_request, 0, mpi_request_sz);
3847 mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
3848 r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
3849 (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
3852 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
3853 ioc->name, __func__, r);
3857 facts = &ioc->facts;
3858 memset(facts, 0, sizeof(struct mpt3sas_facts));
3859 facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
3860 facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
3861 facts->VP_ID = mpi_reply.VP_ID;
3862 facts->VF_ID = mpi_reply.VF_ID;
3863 facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
3864 facts->MaxChainDepth = mpi_reply.MaxChainDepth;
3865 facts->WhoInit = mpi_reply.WhoInit;
3866 facts->NumberOfPorts = mpi_reply.NumberOfPorts;
3867 facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
3868 facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
3869 facts->MaxReplyDescriptorPostQueueDepth =
3870 le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
3871 facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
3872 facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
3873 if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
3874 ioc->ir_firmware = 1;
3875 if ((facts->IOCCapabilities &
3876 MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE))
3877 ioc->rdpq_array_capable = 1;
3878 facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
3879 facts->IOCRequestFrameSize =
3880 le16_to_cpu(mpi_reply.IOCRequestFrameSize);
3881 facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
3882 facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
3883 ioc->shost->max_id = -1;
3884 facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
3885 facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
3886 facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
3887 facts->HighPriorityCredit =
3888 le16_to_cpu(mpi_reply.HighPriorityCredit);
3889 facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
3890 facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
3892 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3893 "hba queue depth(%d), max chains per io(%d)\n",
3894 ioc->name, facts->RequestCredit,
3895 facts->MaxChainDepth));
3896 dinitprintk(ioc, pr_info(MPT3SAS_FMT
3897 "request frame size(%d), reply frame size(%d)\n", ioc->name,
3898 facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
3903 * _base_send_ioc_init - send ioc_init to firmware
3904 * @ioc: per adapter object
3905 * @sleep_flag: CAN_SLEEP or NO_SLEEP
3907 * Returns 0 for success, non-zero for failure.
3910 _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
3912 Mpi2IOCInitRequest_t mpi_request;
3913 Mpi2IOCInitReply_t mpi_reply;
3915 struct timeval current_time;
3917 u32 reply_post_free_array_sz = 0;
3918 Mpi2IOCInitRDPQArrayEntry *reply_post_free_array = NULL;
3919 dma_addr_t reply_post_free_array_dma;
3921 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
3924 memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
3925 mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
3926 mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
3927 mpi_request.VF_ID = 0; /* TODO */
3928 mpi_request.VP_ID = 0;
3929 mpi_request.MsgVersion = cpu_to_le16(MPI25_VERSION);
3930 mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
3932 if (_base_is_controller_msix_enabled(ioc))
3933 mpi_request.HostMSIxVectors = ioc->reply_queue_count;
3934 mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
3935 mpi_request.ReplyDescriptorPostQueueDepth =
3936 cpu_to_le16(ioc->reply_post_queue_depth);
3937 mpi_request.ReplyFreeQueueDepth =
3938 cpu_to_le16(ioc->reply_free_queue_depth);
3940 mpi_request.SenseBufferAddressHigh =
3941 cpu_to_le32((u64)ioc->sense_dma >> 32);
3942 mpi_request.SystemReplyAddressHigh =
3943 cpu_to_le32((u64)ioc->reply_dma >> 32);
3944 mpi_request.SystemRequestFrameBaseAddress =
3945 cpu_to_le64((u64)ioc->request_dma);
3946 mpi_request.ReplyFreeQueueAddress =
3947 cpu_to_le64((u64)ioc->reply_free_dma);
3949 if (ioc->rdpq_array_enable) {
3950 reply_post_free_array_sz = ioc->reply_queue_count *
3951 sizeof(Mpi2IOCInitRDPQArrayEntry);
3952 reply_post_free_array = pci_alloc_consistent(ioc->pdev,
3953 reply_post_free_array_sz, &reply_post_free_array_dma);
3954 if (!reply_post_free_array) {
3956 "reply_post_free_array: pci_alloc_consistent failed\n",
3961 memset(reply_post_free_array, 0, reply_post_free_array_sz);
3962 for (i = 0; i < ioc->reply_queue_count; i++)
3963 reply_post_free_array[i].RDPQBaseAddress =
3965 (u64)ioc->reply_post[i].reply_post_free_dma);
3966 mpi_request.MsgFlags = MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE;
3967 mpi_request.ReplyDescriptorPostQueueAddress =
3968 cpu_to_le64((u64)reply_post_free_array_dma);
3970 mpi_request.ReplyDescriptorPostQueueAddress =
3971 cpu_to_le64((u64)ioc->reply_post[0].reply_post_free_dma);
3974 /* This time stamp specifies number of milliseconds
3975 * since epoch ~ midnight January 1, 1970.
3977 do_gettimeofday(¤t_time);
3978 mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
3979 (current_time.tv_usec / 1000));
3981 if (ioc->logging_level & MPT_DEBUG_INIT) {
3985 mfp = (__le32 *)&mpi_request;
3986 pr_info("\toffset:data\n");
3987 for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
3988 pr_info("\t[0x%02x]:%08x\n", i*4,
3989 le32_to_cpu(mfp[i]));
3992 r = _base_handshake_req_reply_wait(ioc,
3993 sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
3994 sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
3998 pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
3999 ioc->name, __func__, r);
4003 ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
4004 if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
4005 mpi_reply.IOCLogInfo) {
4006 pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
4011 if (reply_post_free_array)
4012 pci_free_consistent(ioc->pdev, reply_post_free_array_sz,
4013 reply_post_free_array,
4014 reply_post_free_array_dma);
4019 * mpt3sas_port_enable_done - command completion routine for port enable
4020 * @ioc: per adapter object
4021 * @smid: system request message index
4022 * @msix_index: MSIX table index supplied by the OS
4023 * @reply: reply message frame(lower 32bit addr)
4025 * Return 1 meaning mf should be freed from _base_interrupt
4026 * 0 means the mf is freed from this function.
4029 mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
4032 MPI2DefaultReply_t *mpi_reply;
4035 if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
4038 mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
4042 if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
4045 ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
4046 ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
4047 ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
4048 memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
4049 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4050 if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
4051 ioc->port_enable_failed = 1;
4053 if (ioc->is_driver_loading) {
4054 if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
4055 mpt3sas_port_enable_complete(ioc);
4058 ioc->start_scan_failed = ioc_status;
4059 ioc->start_scan = 0;
4063 complete(&ioc->port_enable_cmds.done);
4068 * _base_send_port_enable - send port_enable(discovery stuff) to firmware
4069 * @ioc: per adapter object
4070 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4072 * Returns 0 for success, non-zero for failure.
4075 _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4077 Mpi2PortEnableRequest_t *mpi_request;
4078 Mpi2PortEnableReply_t *mpi_reply;
4079 unsigned long timeleft;
4084 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4086 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4087 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4088 ioc->name, __func__);
4092 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4094 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4095 ioc->name, __func__);
4099 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4100 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4101 ioc->port_enable_cmds.smid = smid;
4102 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4103 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4105 init_completion(&ioc->port_enable_cmds.done);
4106 mpt3sas_base_put_smid_default(ioc, smid);
4107 timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done,
4109 if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
4110 pr_err(MPT3SAS_FMT "%s: timeout\n",
4111 ioc->name, __func__);
4112 _debug_dump_mf(mpi_request,
4113 sizeof(Mpi2PortEnableRequest_t)/4);
4114 if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
4121 mpi_reply = ioc->port_enable_cmds.reply;
4122 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
4123 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
4124 pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
4125 ioc->name, __func__, ioc_status);
4131 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4132 pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
4133 "SUCCESS" : "FAILED"));
4138 * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
4139 * @ioc: per adapter object
4141 * Returns 0 for success, non-zero for failure.
4144 mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
4146 Mpi2PortEnableRequest_t *mpi_request;
4149 pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
4151 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
4152 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4153 ioc->name, __func__);
4157 smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
4159 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4160 ioc->name, __func__);
4164 ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
4165 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4166 ioc->port_enable_cmds.smid = smid;
4167 memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
4168 mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
4170 mpt3sas_base_put_smid_default(ioc, smid);
4175 * _base_determine_wait_on_discovery - desposition
4176 * @ioc: per adapter object
4178 * Decide whether to wait on discovery to complete. Used to either
4179 * locate boot device, or report volumes ahead of physical devices.
4181 * Returns 1 for wait, 0 for don't wait
4184 _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
4186 /* We wait for discovery to complete if IR firmware is loaded.
4187 * The sas topology events arrive before PD events, so we need time to
4188 * turn on the bit in ioc->pd_handles to indicate PD
4189 * Also, it maybe required to report Volumes ahead of physical
4190 * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
4192 if (ioc->ir_firmware)
4195 /* if no Bios, then we don't need to wait */
4196 if (!ioc->bios_pg3.BiosVersion)
4199 /* Bios is present, then we drop down here.
4201 * If there any entries in the Bios Page 2, then we wait
4202 * for discovery to complete.
4205 /* Current Boot Device */
4206 if ((ioc->bios_pg2.CurrentBootDeviceForm &
4207 MPI2_BIOSPAGE2_FORM_MASK) ==
4208 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4209 /* Request Boot Device */
4210 (ioc->bios_pg2.ReqBootDeviceForm &
4211 MPI2_BIOSPAGE2_FORM_MASK) ==
4212 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
4213 /* Alternate Request Boot Device */
4214 (ioc->bios_pg2.ReqAltBootDeviceForm &
4215 MPI2_BIOSPAGE2_FORM_MASK) ==
4216 MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
4223 * _base_unmask_events - turn on notification for this event
4224 * @ioc: per adapter object
4225 * @event: firmware event
4227 * The mask is stored in ioc->event_masks.
4230 _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
4237 desired_event = (1 << (event % 32));
4240 ioc->event_masks[0] &= ~desired_event;
4241 else if (event < 64)
4242 ioc->event_masks[1] &= ~desired_event;
4243 else if (event < 96)
4244 ioc->event_masks[2] &= ~desired_event;
4245 else if (event < 128)
4246 ioc->event_masks[3] &= ~desired_event;
4250 * _base_event_notification - send event notification
4251 * @ioc: per adapter object
4252 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4254 * Returns 0 for success, non-zero for failure.
4257 _base_event_notification(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4259 Mpi2EventNotificationRequest_t *mpi_request;
4260 unsigned long timeleft;
4265 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4268 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
4269 pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
4270 ioc->name, __func__);
4274 smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
4276 pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
4277 ioc->name, __func__);
4280 ioc->base_cmds.status = MPT3_CMD_PENDING;
4281 mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
4282 ioc->base_cmds.smid = smid;
4283 memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
4284 mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
4285 mpi_request->VF_ID = 0; /* TODO */
4286 mpi_request->VP_ID = 0;
4287 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4288 mpi_request->EventMasks[i] =
4289 cpu_to_le32(ioc->event_masks[i]);
4290 init_completion(&ioc->base_cmds.done);
4291 mpt3sas_base_put_smid_default(ioc, smid);
4292 timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
4293 if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
4294 pr_err(MPT3SAS_FMT "%s: timeout\n",
4295 ioc->name, __func__);
4296 _debug_dump_mf(mpi_request,
4297 sizeof(Mpi2EventNotificationRequest_t)/4);
4298 if (ioc->base_cmds.status & MPT3_CMD_RESET)
4303 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
4304 ioc->name, __func__));
4305 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4310 * mpt3sas_base_validate_event_type - validating event types
4311 * @ioc: per adapter object
4312 * @event: firmware event
4314 * This will turn on firmware event notification when application
4315 * ask for that event. We don't mask events that are already enabled.
4318 mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
4321 u32 event_mask, desired_event;
4322 u8 send_update_to_fw;
4324 for (i = 0, send_update_to_fw = 0; i <
4325 MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
4326 event_mask = ~event_type[i];
4328 for (j = 0; j < 32; j++) {
4329 if (!(event_mask & desired_event) &&
4330 (ioc->event_masks[i] & desired_event)) {
4331 ioc->event_masks[i] &= ~desired_event;
4332 send_update_to_fw = 1;
4334 desired_event = (desired_event << 1);
4338 if (!send_update_to_fw)
4341 mutex_lock(&ioc->base_cmds.mutex);
4342 _base_event_notification(ioc, CAN_SLEEP);
4343 mutex_unlock(&ioc->base_cmds.mutex);
4347 * _base_diag_reset - the "big hammer" start of day reset
4348 * @ioc: per adapter object
4349 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4351 * Returns 0 for success, non-zero for failure.
4354 _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4356 u32 host_diagnostic;
4361 pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
4363 drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
4368 /* Write magic sequence to WriteSequence register
4369 * Loop until in diagnostic mode
4371 drsprintk(ioc, pr_info(MPT3SAS_FMT
4372 "write magic sequence\n", ioc->name));
4373 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4374 writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
4375 writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
4376 writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
4377 writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
4378 writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
4379 writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
4382 if (sleep_flag == CAN_SLEEP)
4390 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4391 drsprintk(ioc, pr_info(MPT3SAS_FMT
4392 "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
4393 ioc->name, count, host_diagnostic));
4395 } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
4397 hcb_size = readl(&ioc->chip->HCBSize);
4399 drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
4401 writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
4402 &ioc->chip->HostDiagnostic);
4404 /*This delay allows the chip PCIe hardware time to finish reset tasks*/
4405 if (sleep_flag == CAN_SLEEP)
4406 msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4408 mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
4410 /* Approximately 300 second max wait */
4411 for (count = 0; count < (300000000 /
4412 MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
4414 host_diagnostic = readl(&ioc->chip->HostDiagnostic);
4416 if (host_diagnostic == 0xFFFFFFFF)
4418 if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
4421 /* Wait to pass the second read delay window */
4422 if (sleep_flag == CAN_SLEEP)
4423 msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4426 mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
4430 if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
4432 drsprintk(ioc, pr_info(MPT3SAS_FMT
4433 "restart the adapter assuming the HCB Address points to good F/W\n",
4435 host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
4436 host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
4437 writel(host_diagnostic, &ioc->chip->HostDiagnostic);
4439 drsprintk(ioc, pr_info(MPT3SAS_FMT
4440 "re-enable the HCDW\n", ioc->name));
4441 writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
4442 &ioc->chip->HCBSize);
4445 drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
4447 writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
4448 &ioc->chip->HostDiagnostic);
4450 drsprintk(ioc, pr_info(MPT3SAS_FMT
4451 "disable writes to the diagnostic register\n", ioc->name));
4452 writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
4454 drsprintk(ioc, pr_info(MPT3SAS_FMT
4455 "Wait for FW to go to the READY state\n", ioc->name));
4456 ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
4460 "%s: failed going to ready state (ioc_state=0x%x)\n",
4461 ioc->name, __func__, ioc_state);
4465 pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
4469 pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
4474 * _base_make_ioc_ready - put controller in READY state
4475 * @ioc: per adapter object
4476 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4477 * @type: FORCE_BIG_HAMMER or SOFT_RESET
4479 * Returns 0 for success, non-zero for failure.
4482 _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
4483 enum reset_type type)
4489 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4492 if (ioc->pci_error_recovery)
4495 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4496 dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
4497 ioc->name, __func__, ioc_state));
4499 /* if in RESET state, it should move to READY state shortly */
4501 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
4502 while ((ioc_state & MPI2_IOC_STATE_MASK) !=
4503 MPI2_IOC_STATE_READY) {
4504 if (count++ == 10) {
4506 "%s: failed going to ready state (ioc_state=0x%x)\n",
4507 ioc->name, __func__, ioc_state);
4510 if (sleep_flag == CAN_SLEEP)
4514 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
4518 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
4521 if (ioc_state & MPI2_DOORBELL_USED) {
4522 dhsprintk(ioc, pr_info(MPT3SAS_FMT
4523 "unexpected doorbell active!\n",
4525 goto issue_diag_reset;
4528 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
4529 mpt3sas_base_fault_info(ioc, ioc_state &
4530 MPI2_DOORBELL_DATA_MASK);
4531 goto issue_diag_reset;
4534 if (type == FORCE_BIG_HAMMER)
4535 goto issue_diag_reset;
4537 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
4538 if (!(_base_send_ioc_reset(ioc,
4539 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
4544 rc = _base_diag_reset(ioc, CAN_SLEEP);
4549 * _base_make_ioc_operational - put controller in OPERATIONAL state
4550 * @ioc: per adapter object
4551 * @sleep_flag: CAN_SLEEP or NO_SLEEP
4553 * Returns 0 for success, non-zero for failure.
4556 _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
4559 unsigned long flags;
4562 struct _tr_list *delayed_tr, *delayed_tr_next;
4563 struct adapter_reply_queue *reply_q;
4564 long reply_post_free;
4565 u32 reply_post_free_sz, index = 0;
4567 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4570 /* clean the delayed target reset list */
4571 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4572 &ioc->delayed_tr_list, list) {
4573 list_del(&delayed_tr->list);
4578 list_for_each_entry_safe(delayed_tr, delayed_tr_next,
4579 &ioc->delayed_tr_volume_list, list) {
4580 list_del(&delayed_tr->list);
4584 /* initialize the scsi lookup free list */
4585 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
4586 INIT_LIST_HEAD(&ioc->free_list);
4588 for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
4589 INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
4590 ioc->scsi_lookup[i].cb_idx = 0xFF;
4591 ioc->scsi_lookup[i].smid = smid;
4592 ioc->scsi_lookup[i].scmd = NULL;
4593 list_add_tail(&ioc->scsi_lookup[i].tracker_list,
4597 /* hi-priority queue */
4598 INIT_LIST_HEAD(&ioc->hpr_free_list);
4599 smid = ioc->hi_priority_smid;
4600 for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
4601 ioc->hpr_lookup[i].cb_idx = 0xFF;
4602 ioc->hpr_lookup[i].smid = smid;
4603 list_add_tail(&ioc->hpr_lookup[i].tracker_list,
4604 &ioc->hpr_free_list);
4607 /* internal queue */
4608 INIT_LIST_HEAD(&ioc->internal_free_list);
4609 smid = ioc->internal_smid;
4610 for (i = 0; i < ioc->internal_depth; i++, smid++) {
4611 ioc->internal_lookup[i].cb_idx = 0xFF;
4612 ioc->internal_lookup[i].smid = smid;
4613 list_add_tail(&ioc->internal_lookup[i].tracker_list,
4614 &ioc->internal_free_list);
4618 INIT_LIST_HEAD(&ioc->free_chain_list);
4619 for (i = 0; i < ioc->chain_depth; i++)
4620 list_add_tail(&ioc->chain_lookup[i].tracker_list,
4621 &ioc->free_chain_list);
4623 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
4625 /* initialize Reply Free Queue */
4626 for (i = 0, reply_address = (u32)ioc->reply_dma ;
4627 i < ioc->reply_free_queue_depth ; i++, reply_address +=
4629 ioc->reply_free[i] = cpu_to_le32(reply_address);
4631 /* initialize reply queues */
4632 if (ioc->is_driver_loading)
4633 _base_assign_reply_queues(ioc);
4635 /* initialize Reply Post Free Queue */
4636 reply_post_free_sz = ioc->reply_post_queue_depth *
4637 sizeof(Mpi2DefaultReplyDescriptor_t);
4638 reply_post_free = (long)ioc->reply_post[index].reply_post_free;
4639 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
4640 reply_q->reply_post_host_index = 0;
4641 reply_q->reply_post_free = (Mpi2ReplyDescriptorsUnion_t *)
4643 for (i = 0; i < ioc->reply_post_queue_depth; i++)
4644 reply_q->reply_post_free[i].Words =
4645 cpu_to_le64(ULLONG_MAX);
4646 if (!_base_is_controller_msix_enabled(ioc))
4647 goto skip_init_reply_post_free_queue;
4649 * If RDPQ is enabled, switch to the next allocation.
4650 * Otherwise advance within the contiguous region.
4652 if (ioc->rdpq_array_enable)
4653 reply_post_free = (long)
4654 ioc->reply_post[++index].reply_post_free;
4656 reply_post_free += reply_post_free_sz;
4658 skip_init_reply_post_free_queue:
4660 r = _base_send_ioc_init(ioc, sleep_flag);
4664 /* initialize reply free host index */
4665 ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
4666 writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
4668 /* initialize reply post host index */
4669 list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
4670 if (ioc->msix96_vector)
4671 writel((reply_q->msix_index & 7)<<
4672 MPI2_RPHI_MSIX_INDEX_SHIFT,
4673 ioc->replyPostRegisterIndex[reply_q->msix_index/8]);
4675 writel(reply_q->msix_index <<
4676 MPI2_RPHI_MSIX_INDEX_SHIFT,
4677 &ioc->chip->ReplyPostHostIndex);
4679 if (!_base_is_controller_msix_enabled(ioc))
4680 goto skip_init_reply_post_host_index;
4683 skip_init_reply_post_host_index:
4685 _base_unmask_interrupts(ioc);
4686 r = _base_event_notification(ioc, sleep_flag);
4690 if (sleep_flag == CAN_SLEEP)
4691 _base_static_config_pages(ioc);
4694 if (ioc->is_driver_loading) {
4695 ioc->wait_for_discovery_to_complete =
4696 _base_determine_wait_on_discovery(ioc);
4698 return r; /* scan_start and scan_finished support */
4701 r = _base_send_port_enable(ioc, sleep_flag);
4709 * mpt3sas_base_free_resources - free resources controller resources
4710 * @ioc: per adapter object
4715 mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
4717 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4720 if (ioc->chip_phys && ioc->chip) {
4721 _base_mask_interrupts(ioc);
4722 ioc->shost_recovery = 1;
4723 _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
4724 ioc->shost_recovery = 0;
4727 mpt3sas_base_unmap_resources(ioc);
4732 * mpt3sas_base_attach - attach controller instance
4733 * @ioc: per adapter object
4735 * Returns 0 for success, non-zero for failure.
4738 mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
4741 int cpu_id, last_cpu_id = 0;
4744 dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4747 /* setup cpu_msix_table */
4748 ioc->cpu_count = num_online_cpus();
4749 for_each_online_cpu(cpu_id)
4750 last_cpu_id = cpu_id;
4751 ioc->cpu_msix_table_sz = last_cpu_id + 1;
4752 ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
4753 ioc->reply_queue_count = 1;
4754 if (!ioc->cpu_msix_table) {
4755 dfailprintk(ioc, pr_info(MPT3SAS_FMT
4756 "allocation for cpu_msix_table failed!!!\n",
4759 goto out_free_resources;
4762 /* Check whether the controller revision is C0 or above.
4763 * only C0 and above revision controllers support 96 MSI-X vectors.
4765 revision = ioc->pdev->revision;
4767 if ((ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3004 ||
4768 ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3008 ||
4769 ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3108_1 ||
4770 ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3108_2 ||
4771 ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3108_5 ||
4772 ioc->pdev->device == MPI25_MFGPAGE_DEVID_SAS3108_6) &&
4774 ioc->msix96_vector = 1;
4776 ioc->rdpq_array_enable_assigned = 0;
4778 r = mpt3sas_base_map_resources(ioc);
4780 goto out_free_resources;
4783 pci_set_drvdata(ioc->pdev, ioc->shost);
4784 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
4786 goto out_free_resources;
4790 * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
4791 * Target Status - all require the IEEE formated scatter gather
4795 ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
4796 ioc->build_sg = &_base_build_sg_ieee;
4797 ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
4798 ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
4801 * These function pointers for other requests that don't
4802 * the require IEEE scatter gather elements.
4804 * For example Configuration Pages and SAS IOUNIT Control don't.
4806 ioc->build_sg_mpi = &_base_build_sg;
4807 ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
4809 r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
4811 goto out_free_resources;
4813 ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
4814 sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
4817 goto out_free_resources;
4820 for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
4821 r = _base_get_port_facts(ioc, i, CAN_SLEEP);
4823 goto out_free_resources;
4826 r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
4828 goto out_free_resources;
4830 init_waitqueue_head(&ioc->reset_wq);
4832 /* allocate memory pd handle bitmask list */
4833 ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
4834 if (ioc->facts.MaxDevHandle % 8)
4835 ioc->pd_handles_sz++;
4836 ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
4838 if (!ioc->pd_handles) {
4840 goto out_free_resources;
4842 ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
4844 if (!ioc->blocking_handles) {
4846 goto out_free_resources;
4849 ioc->fwfault_debug = mpt3sas_fwfault_debug;
4851 /* base internal command bits */
4852 mutex_init(&ioc->base_cmds.mutex);
4853 ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4854 ioc->base_cmds.status = MPT3_CMD_NOT_USED;
4856 /* port_enable command bits */
4857 ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4858 ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
4860 /* transport internal command bits */
4861 ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4862 ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
4863 mutex_init(&ioc->transport_cmds.mutex);
4865 /* scsih internal command bits */
4866 ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4867 ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
4868 mutex_init(&ioc->scsih_cmds.mutex);
4870 /* task management internal command bits */
4871 ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4872 ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
4873 mutex_init(&ioc->tm_cmds.mutex);
4875 /* config page internal command bits */
4876 ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4877 ioc->config_cmds.status = MPT3_CMD_NOT_USED;
4878 mutex_init(&ioc->config_cmds.mutex);
4880 /* ctl module internal command bits */
4881 ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
4882 ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
4883 ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
4884 mutex_init(&ioc->ctl_cmds.mutex);
4886 if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
4887 !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
4888 !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
4889 !ioc->ctl_cmds.sense) {
4891 goto out_free_resources;
4894 for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4895 ioc->event_masks[i] = -1;
4897 /* here we enable the events we care about */
4898 _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
4899 _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
4900 _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
4901 _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
4902 _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
4903 _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
4904 _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
4905 _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
4906 _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
4907 _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
4908 _base_unmask_events(ioc, MPI2_EVENT_TEMP_THRESHOLD);
4910 r = _base_make_ioc_operational(ioc, CAN_SLEEP);
4912 goto out_free_resources;
4918 ioc->remove_host = 1;
4920 mpt3sas_base_free_resources(ioc);
4921 _base_release_memory_pools(ioc);
4922 pci_set_drvdata(ioc->pdev, NULL);
4923 kfree(ioc->cpu_msix_table);
4924 kfree(ioc->pd_handles);
4925 kfree(ioc->blocking_handles);
4926 kfree(ioc->tm_cmds.reply);
4927 kfree(ioc->transport_cmds.reply);
4928 kfree(ioc->scsih_cmds.reply);
4929 kfree(ioc->config_cmds.reply);
4930 kfree(ioc->base_cmds.reply);
4931 kfree(ioc->port_enable_cmds.reply);
4932 kfree(ioc->ctl_cmds.reply);
4933 kfree(ioc->ctl_cmds.sense);
4935 ioc->ctl_cmds.reply = NULL;
4936 ioc->base_cmds.reply = NULL;
4937 ioc->tm_cmds.reply = NULL;
4938 ioc->scsih_cmds.reply = NULL;
4939 ioc->transport_cmds.reply = NULL;
4940 ioc->config_cmds.reply = NULL;
4947 * mpt3sas_base_detach - remove controller instance
4948 * @ioc: per adapter object
4953 mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
4955 dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
4958 mpt3sas_base_stop_watchdog(ioc);
4959 mpt3sas_base_free_resources(ioc);
4960 _base_release_memory_pools(ioc);
4961 pci_set_drvdata(ioc->pdev, NULL);
4962 kfree(ioc->cpu_msix_table);
4963 kfree(ioc->pd_handles);
4964 kfree(ioc->blocking_handles);
4966 kfree(ioc->ctl_cmds.reply);
4967 kfree(ioc->ctl_cmds.sense);
4968 kfree(ioc->base_cmds.reply);
4969 kfree(ioc->port_enable_cmds.reply);
4970 kfree(ioc->tm_cmds.reply);
4971 kfree(ioc->transport_cmds.reply);
4972 kfree(ioc->scsih_cmds.reply);
4973 kfree(ioc->config_cmds.reply);
4977 * _base_reset_handler - reset callback handler (for base)
4978 * @ioc: per adapter object
4979 * @reset_phase: phase
4981 * The handler for doing any required cleanup or initialization.
4983 * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
4984 * MPT3_IOC_DONE_RESET
4989 _base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
4991 mpt3sas_scsih_reset_handler(ioc, reset_phase);
4992 mpt3sas_ctl_reset_handler(ioc, reset_phase);
4993 switch (reset_phase) {
4994 case MPT3_IOC_PRE_RESET:
4995 dtmprintk(ioc, pr_info(MPT3SAS_FMT
4996 "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
4998 case MPT3_IOC_AFTER_RESET:
4999 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5000 "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
5001 if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
5002 ioc->transport_cmds.status |= MPT3_CMD_RESET;
5003 mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
5004 complete(&ioc->transport_cmds.done);
5006 if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
5007 ioc->base_cmds.status |= MPT3_CMD_RESET;
5008 mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
5009 complete(&ioc->base_cmds.done);
5011 if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
5012 ioc->port_enable_failed = 1;
5013 ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
5014 mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
5015 if (ioc->is_driver_loading) {
5016 ioc->start_scan_failed =
5017 MPI2_IOCSTATUS_INTERNAL_ERROR;
5018 ioc->start_scan = 0;
5019 ioc->port_enable_cmds.status =
5022 complete(&ioc->port_enable_cmds.done);
5024 if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
5025 ioc->config_cmds.status |= MPT3_CMD_RESET;
5026 mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
5027 ioc->config_cmds.smid = USHRT_MAX;
5028 complete(&ioc->config_cmds.done);
5031 case MPT3_IOC_DONE_RESET:
5032 dtmprintk(ioc, pr_info(MPT3SAS_FMT
5033 "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
5039 * _wait_for_commands_to_complete - reset controller
5040 * @ioc: Pointer to MPT_ADAPTER structure
5041 * @sleep_flag: CAN_SLEEP or NO_SLEEP
5043 * This function waiting(3s) for all pending commands to complete
5044 * prior to putting controller in reset.
5047 _wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
5050 unsigned long flags;
5053 ioc->pending_io_count = 0;
5054 if (sleep_flag != CAN_SLEEP)
5057 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5058 if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
5061 /* pending command count */
5062 spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
5063 for (i = 0; i < ioc->scsiio_depth; i++)
5064 if (ioc->scsi_lookup[i].cb_idx != 0xFF)
5065 ioc->pending_io_count++;
5066 spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
5068 if (!ioc->pending_io_count)
5071 /* wait for pending commands to complete */
5072 wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
5076 * mpt3sas_base_hard_reset_handler - reset controller
5077 * @ioc: Pointer to MPT_ADAPTER structure
5078 * @sleep_flag: CAN_SLEEP or NO_SLEEP
5079 * @type: FORCE_BIG_HAMMER or SOFT_RESET
5081 * Returns 0 for success, non-zero for failure.
5084 mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
5085 enum reset_type type)
5088 unsigned long flags;
5090 u8 is_fault = 0, is_trigger = 0;
5092 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
5095 if (ioc->pci_error_recovery) {
5096 pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
5097 ioc->name, __func__);
5102 if (mpt3sas_fwfault_debug)
5103 mpt3sas_halt_firmware(ioc);
5105 /* TODO - What we really should be doing is pulling
5106 * out all the code associated with NO_SLEEP; its never used.
5107 * That is legacy code from mpt fusion driver, ported over.
5108 * I will leave this BUG_ON here for now till its been resolved.
5110 BUG_ON(sleep_flag == NO_SLEEP);
5112 /* wait for an active reset in progress to complete */
5113 if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
5116 } while (ioc->shost_recovery == 1);
5117 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
5119 return ioc->ioc_reset_in_progress_status;
5122 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5123 ioc->shost_recovery = 1;
5124 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5126 if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5127 MPT3_DIAG_BUFFER_IS_REGISTERED) &&
5128 (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
5129 MPT3_DIAG_BUFFER_IS_RELEASED))) {
5131 ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
5132 if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
5135 _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
5136 _wait_for_commands_to_complete(ioc, sleep_flag);
5137 _base_mask_interrupts(ioc);
5138 r = _base_make_ioc_ready(ioc, sleep_flag, type);
5141 _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
5143 /* If this hard reset is called while port enable is active, then
5144 * there is no reason to call make_ioc_operational
5146 if (ioc->is_driver_loading && ioc->port_enable_failed) {
5147 ioc->remove_host = 1;
5151 r = _base_get_ioc_facts(ioc, CAN_SLEEP);
5155 if (ioc->rdpq_array_enable && !ioc->rdpq_array_capable)
5156 panic("%s: Issue occurred with flashing controller firmware."
5157 "Please reboot the system and ensure that the correct"
5158 " firmware version is running\n", ioc->name);
5160 r = _base_make_ioc_operational(ioc, sleep_flag);
5162 _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
5165 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
5166 ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
5168 spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
5169 ioc->ioc_reset_in_progress_status = r;
5170 ioc->shost_recovery = 0;
5171 spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
5172 ioc->ioc_reset_count++;
5173 mutex_unlock(&ioc->reset_in_progress_mutex);
5176 if ((r == 0) && is_trigger) {
5178 mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
5180 mpt3sas_trigger_master(ioc,
5181 MASTER_TRIGGER_ADAPTER_RESET);
5183 dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,