2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm8001_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
47 * read_main_config_table - read the configure table and save it.
48 * @pm8001_ha: our hba card information
50 static void __devinit read_main_config_table(struct pm8001_hba_info *pm8001_ha)
52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
53 pm8001_ha->main_cfg_tbl.signature = pm8001_mr32(address, 0x00);
54 pm8001_ha->main_cfg_tbl.interface_rev = pm8001_mr32(address, 0x04);
55 pm8001_ha->main_cfg_tbl.firmware_rev = pm8001_mr32(address, 0x08);
56 pm8001_ha->main_cfg_tbl.max_out_io = pm8001_mr32(address, 0x0C);
57 pm8001_ha->main_cfg_tbl.max_sgl = pm8001_mr32(address, 0x10);
58 pm8001_ha->main_cfg_tbl.ctrl_cap_flag = pm8001_mr32(address, 0x14);
59 pm8001_ha->main_cfg_tbl.gst_offset = pm8001_mr32(address, 0x18);
60 pm8001_ha->main_cfg_tbl.inbound_queue_offset =
61 pm8001_mr32(address, MAIN_IBQ_OFFSET);
62 pm8001_ha->main_cfg_tbl.outbound_queue_offset =
63 pm8001_mr32(address, MAIN_OBQ_OFFSET);
64 pm8001_ha->main_cfg_tbl.hda_mode_flag =
65 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
67 /* read analog Setting offset from the configuration table */
68 pm8001_ha->main_cfg_tbl.anolog_setup_table_offset =
69 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
71 /* read Error Dump Offset and Length */
72 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 =
73 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
74 pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 =
75 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
76 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 =
77 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
78 pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 =
79 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
83 * read_general_status_table - read the general status table and save it.
84 * @pm8001_ha: our hba card information
87 read_general_status_table(struct pm8001_hba_info *pm8001_ha)
89 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
90 pm8001_ha->gs_tbl.gst_len_mpistate = pm8001_mr32(address, 0x00);
91 pm8001_ha->gs_tbl.iq_freeze_state0 = pm8001_mr32(address, 0x04);
92 pm8001_ha->gs_tbl.iq_freeze_state1 = pm8001_mr32(address, 0x08);
93 pm8001_ha->gs_tbl.msgu_tcnt = pm8001_mr32(address, 0x0C);
94 pm8001_ha->gs_tbl.iop_tcnt = pm8001_mr32(address, 0x10);
95 pm8001_ha->gs_tbl.reserved = pm8001_mr32(address, 0x14);
96 pm8001_ha->gs_tbl.phy_state[0] = pm8001_mr32(address, 0x18);
97 pm8001_ha->gs_tbl.phy_state[1] = pm8001_mr32(address, 0x1C);
98 pm8001_ha->gs_tbl.phy_state[2] = pm8001_mr32(address, 0x20);
99 pm8001_ha->gs_tbl.phy_state[3] = pm8001_mr32(address, 0x24);
100 pm8001_ha->gs_tbl.phy_state[4] = pm8001_mr32(address, 0x28);
101 pm8001_ha->gs_tbl.phy_state[5] = pm8001_mr32(address, 0x2C);
102 pm8001_ha->gs_tbl.phy_state[6] = pm8001_mr32(address, 0x30);
103 pm8001_ha->gs_tbl.phy_state[7] = pm8001_mr32(address, 0x34);
104 pm8001_ha->gs_tbl.reserved1 = pm8001_mr32(address, 0x38);
105 pm8001_ha->gs_tbl.reserved2 = pm8001_mr32(address, 0x3C);
106 pm8001_ha->gs_tbl.reserved3 = pm8001_mr32(address, 0x40);
107 pm8001_ha->gs_tbl.recover_err_info[0] = pm8001_mr32(address, 0x44);
108 pm8001_ha->gs_tbl.recover_err_info[1] = pm8001_mr32(address, 0x48);
109 pm8001_ha->gs_tbl.recover_err_info[2] = pm8001_mr32(address, 0x4C);
110 pm8001_ha->gs_tbl.recover_err_info[3] = pm8001_mr32(address, 0x50);
111 pm8001_ha->gs_tbl.recover_err_info[4] = pm8001_mr32(address, 0x54);
112 pm8001_ha->gs_tbl.recover_err_info[5] = pm8001_mr32(address, 0x58);
113 pm8001_ha->gs_tbl.recover_err_info[6] = pm8001_mr32(address, 0x5C);
114 pm8001_ha->gs_tbl.recover_err_info[7] = pm8001_mr32(address, 0x60);
118 * read_inbnd_queue_table - read the inbound queue table and save it.
119 * @pm8001_ha: our hba card information
121 static void __devinit
122 read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
126 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
127 for (i = 0; i < inbQ_num; i++) {
128 u32 offset = i * 0x20;
129 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
130 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
131 pm8001_ha->inbnd_q_tbl[i].pi_offset =
132 pm8001_mr32(address, (offset + 0x18));
137 * read_outbnd_queue_table - read the outbound queue table and save it.
138 * @pm8001_ha: our hba card information
140 static void __devinit
141 read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
145 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
146 for (i = 0; i < outbQ_num; i++) {
147 u32 offset = i * 0x24;
148 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
149 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
150 pm8001_ha->outbnd_q_tbl[i].ci_offset =
151 pm8001_mr32(address, (offset + 0x18));
156 * init_default_table_values - init the default table.
157 * @pm8001_ha: our hba card information
159 static void __devinit
160 init_default_table_values(struct pm8001_hba_info *pm8001_ha)
164 u32 offsetib, offsetob;
165 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
166 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
168 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd = 0;
169 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3 = 0;
170 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7 = 0;
171 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3 = 0;
172 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7 = 0;
173 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3 = 0;
174 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7 = 0;
175 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
176 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
177 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3 = 0;
178 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7 = 0;
180 pm8001_ha->main_cfg_tbl.upper_event_log_addr =
181 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
182 pm8001_ha->main_cfg_tbl.lower_event_log_addr =
183 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
184 pm8001_ha->main_cfg_tbl.event_log_size = PM8001_EVENT_LOG_SIZE;
185 pm8001_ha->main_cfg_tbl.event_log_option = 0x01;
186 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr =
187 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
188 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr =
189 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
190 pm8001_ha->main_cfg_tbl.iop_event_log_size = PM8001_EVENT_LOG_SIZE;
191 pm8001_ha->main_cfg_tbl.iop_event_log_option = 0x01;
192 pm8001_ha->main_cfg_tbl.fatal_err_interrupt = 0x01;
193 for (i = 0; i < qn; i++) {
194 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
195 0x00000100 | (0x00000040 << 16) | (0x00<<30);
196 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
197 pm8001_ha->memoryMap.region[IB].phys_addr_hi;
198 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
199 pm8001_ha->memoryMap.region[IB].phys_addr_lo;
200 pm8001_ha->inbnd_q_tbl[i].base_virt =
201 (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr;
202 pm8001_ha->inbnd_q_tbl[i].total_length =
203 pm8001_ha->memoryMap.region[IB].total_len;
204 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
205 pm8001_ha->memoryMap.region[CI].phys_addr_hi;
206 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
207 pm8001_ha->memoryMap.region[CI].phys_addr_lo;
208 pm8001_ha->inbnd_q_tbl[i].ci_virt =
209 pm8001_ha->memoryMap.region[CI].virt_ptr;
211 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
212 get_pci_bar_index(pm8001_mr32(addressib,
214 pm8001_ha->inbnd_q_tbl[i].pi_offset =
215 pm8001_mr32(addressib, (offsetib + 0x18));
216 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
217 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
219 for (i = 0; i < qn; i++) {
220 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
221 256 | (64 << 16) | (1<<30);
222 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
223 pm8001_ha->memoryMap.region[OB].phys_addr_hi;
224 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
225 pm8001_ha->memoryMap.region[OB].phys_addr_lo;
226 pm8001_ha->outbnd_q_tbl[i].base_virt =
227 (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr;
228 pm8001_ha->outbnd_q_tbl[i].total_length =
229 pm8001_ha->memoryMap.region[OB].total_len;
230 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
231 pm8001_ha->memoryMap.region[PI].phys_addr_hi;
232 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
233 pm8001_ha->memoryMap.region[PI].phys_addr_lo;
234 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
235 0 | (10 << 16) | (0 << 24);
236 pm8001_ha->outbnd_q_tbl[i].pi_virt =
237 pm8001_ha->memoryMap.region[PI].virt_ptr;
239 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
240 get_pci_bar_index(pm8001_mr32(addressob,
242 pm8001_ha->outbnd_q_tbl[i].ci_offset =
243 pm8001_mr32(addressob, (offsetob + 0x18));
244 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
245 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
250 * update_main_config_table - update the main default table to the HBA.
251 * @pm8001_ha: our hba card information
253 static void __devinit
254 update_main_config_table(struct pm8001_hba_info *pm8001_ha)
256 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
257 pm8001_mw32(address, 0x24,
258 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd);
259 pm8001_mw32(address, 0x28,
260 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3);
261 pm8001_mw32(address, 0x2C,
262 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7);
263 pm8001_mw32(address, 0x30,
264 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3);
265 pm8001_mw32(address, 0x34,
266 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7);
267 pm8001_mw32(address, 0x38,
268 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3);
269 pm8001_mw32(address, 0x3C,
270 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7);
271 pm8001_mw32(address, 0x40,
272 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3);
273 pm8001_mw32(address, 0x44,
274 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7);
275 pm8001_mw32(address, 0x48,
276 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3);
277 pm8001_mw32(address, 0x4C,
278 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7);
279 pm8001_mw32(address, 0x50,
280 pm8001_ha->main_cfg_tbl.upper_event_log_addr);
281 pm8001_mw32(address, 0x54,
282 pm8001_ha->main_cfg_tbl.lower_event_log_addr);
283 pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size);
284 pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option);
285 pm8001_mw32(address, 0x60,
286 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr);
287 pm8001_mw32(address, 0x64,
288 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr);
289 pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size);
290 pm8001_mw32(address, 0x6C,
291 pm8001_ha->main_cfg_tbl.iop_event_log_option);
292 pm8001_mw32(address, 0x70,
293 pm8001_ha->main_cfg_tbl.fatal_err_interrupt);
297 * update_inbnd_queue_table - update the inbound queue table to the HBA.
298 * @pm8001_ha: our hba card information
300 static void __devinit
301 update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
303 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
304 u16 offset = number * 0x20;
305 pm8001_mw32(address, offset + 0x00,
306 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
307 pm8001_mw32(address, offset + 0x04,
308 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
309 pm8001_mw32(address, offset + 0x08,
310 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
311 pm8001_mw32(address, offset + 0x0C,
312 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
313 pm8001_mw32(address, offset + 0x10,
314 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
318 * update_outbnd_queue_table - update the outbound queue table to the HBA.
319 * @pm8001_ha: our hba card information
321 static void __devinit
322 update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
324 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
325 u16 offset = number * 0x24;
326 pm8001_mw32(address, offset + 0x00,
327 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
328 pm8001_mw32(address, offset + 0x04,
329 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
330 pm8001_mw32(address, offset + 0x08,
331 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
332 pm8001_mw32(address, offset + 0x0C,
333 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
334 pm8001_mw32(address, offset + 0x10,
335 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
336 pm8001_mw32(address, offset + 0x1C,
337 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
341 * pm8001_bar4_shift - function is called to shift BAR base address
342 * @pm8001_ha : our hba card infomation
343 * @shiftValue : shifting value in memory bar.
345 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
350 /* program the inbound AXI translation Lower Address */
351 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
353 /* confirm the setting is written */
354 start = jiffies + HZ; /* 1 sec */
356 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
357 } while ((regVal != shiftValue) && time_before(jiffies, start));
359 if (regVal != shiftValue) {
360 PM8001_INIT_DBG(pm8001_ha,
361 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
362 " = 0x%x\n", regVal));
369 * mpi_set_phys_g3_with_ssc
370 * @pm8001_ha: our hba card information
371 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
373 static void __devinit
374 mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit)
376 u32 value, offset, i;
379 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
380 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
381 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
382 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
383 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
384 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
385 #define SNW3_PHY_CAPABILITIES_PARITY 31
388 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
389 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
391 spin_lock_irqsave(&pm8001_ha->lock, flags);
392 if (-1 == pm8001_bar4_shift(pm8001_ha,
393 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
394 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
398 for (i = 0; i < 4; i++) {
399 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
400 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
402 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
403 if (-1 == pm8001_bar4_shift(pm8001_ha,
404 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
405 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
408 for (i = 4; i < 8; i++) {
409 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
410 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
412 /*************************************************************
413 Change the SSC upspreading value to 0x0 so that upspreading is disabled.
414 Device MABC SMOD0 Controls
415 Address: (via MEMBASE-III):
416 Using shifted destination address 0x0_0000: with Offset 0xD8
418 31:28 R/W Reserved Do not change
419 27:24 R/W SAS_SMOD_SPRDUP 0000
420 23:20 R/W SAS_SMOD_SPRDDN 0000
421 19:0 R/W Reserved Do not change
422 Upon power-up this register will read as 0x8990c016,
423 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
424 so that the written value will be 0x8090c016.
425 This will ensure only down-spreading SSC is enabled on the SPC.
426 *************************************************************/
427 value = pm8001_cr32(pm8001_ha, 2, 0xd8);
428 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
430 /*set the shifted destination address to 0x0 to avoid error operation */
431 pm8001_bar4_shift(pm8001_ha, 0x0);
432 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
437 * mpi_set_open_retry_interval_reg
438 * @pm8001_ha: our hba card information
439 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
441 static void __devinit
442 mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
450 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
451 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
452 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
453 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
454 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
456 value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
457 spin_lock_irqsave(&pm8001_ha->lock, flags);
458 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
459 if (-1 == pm8001_bar4_shift(pm8001_ha,
460 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
461 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
464 for (i = 0; i < 4; i++) {
465 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
466 pm8001_cw32(pm8001_ha, 2, offset, value);
469 if (-1 == pm8001_bar4_shift(pm8001_ha,
470 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
471 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
474 for (i = 4; i < 8; i++) {
475 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
476 pm8001_cw32(pm8001_ha, 2, offset, value);
478 /*set the shifted destination address to 0x0 to avoid error operation */
479 pm8001_bar4_shift(pm8001_ha, 0x0);
480 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
485 * mpi_init_check - check firmware initialization status.
486 * @pm8001_ha: our hba card information
488 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
492 u32 gst_len_mpistate;
493 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
495 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
496 /* wait until Inbound DoorBell Clear Register toggled */
497 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
500 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
501 value &= SPC_MSGU_CFG_TABLE_UPDATE;
502 } while ((value != 0) && (--max_wait_count));
506 /* check the MPI-State for initialization */
508 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
509 GST_GSTLEN_MPIS_OFFSET);
510 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
512 /* check MPI Initialization error */
513 gst_len_mpistate = gst_len_mpistate >> 16;
514 if (0x0000 != gst_len_mpistate)
520 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
521 * @pm8001_ha: our hba card information
523 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
527 /* check error state */
528 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
529 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
530 /* check AAP error */
531 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
533 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
537 /* check IOP error */
538 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
540 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
544 /* bit 4-31 of scratch pad1 should be zeros if it is not
546 if (value & SCRATCH_PAD1_STATE_MASK) {
548 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
552 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
554 if (value1 & SCRATCH_PAD2_STATE_MASK) {
559 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
561 /* wait until scratch pad 1 and 2 registers in ready state */
564 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
566 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
568 if ((--max_wait_count) == 0)
570 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
574 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
576 void __iomem *base_addr;
582 value = pm8001_cr32(pm8001_ha, 0, 0x44);
583 offset = value & 0x03FFFFFF;
584 PM8001_INIT_DBG(pm8001_ha,
585 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
586 pcilogic = (value & 0xFC000000) >> 26;
587 pcibar = get_pci_bar_index(pcilogic);
588 PM8001_INIT_DBG(pm8001_ha,
589 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
590 pm8001_ha->main_cfg_tbl_addr = base_addr =
591 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
592 pm8001_ha->general_stat_tbl_addr =
593 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
594 pm8001_ha->inbnd_q_tbl_addr =
595 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
596 pm8001_ha->outbnd_q_tbl_addr =
597 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
601 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
602 * @pm8001_ha: our hba card information
604 static int __devinit pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
606 /* check the firmware status */
607 if (-1 == check_fw_ready(pm8001_ha)) {
608 PM8001_FAIL_DBG(pm8001_ha,
609 pm8001_printk("Firmware is not ready!\n"));
613 /* Initialize pci space address eg: mpi offset */
614 init_pci_device_addresses(pm8001_ha);
615 init_default_table_values(pm8001_ha);
616 read_main_config_table(pm8001_ha);
617 read_general_status_table(pm8001_ha);
618 read_inbnd_queue_table(pm8001_ha);
619 read_outbnd_queue_table(pm8001_ha);
620 /* update main config table ,inbound table and outbound table */
621 update_main_config_table(pm8001_ha);
622 update_inbnd_queue_table(pm8001_ha, 0);
623 update_outbnd_queue_table(pm8001_ha, 0);
624 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
625 /* 7->130ms, 34->500ms, 119->1.5s */
626 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
627 /* notify firmware update finished and check initialization status */
628 if (0 == mpi_init_check(pm8001_ha)) {
629 PM8001_INIT_DBG(pm8001_ha,
630 pm8001_printk("MPI initialize successful!\n"));
633 /*This register is a 16-bit timer with a resolution of 1us. This is the
634 timer used for interrupt delay/coalescing in the PCIe Application Layer.
635 Zero is not a valid value. A value of 1 in the register will cause the
636 interrupts to be normal. A value greater than 1 will cause coalescing
638 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
639 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
643 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
647 u32 gst_len_mpistate;
648 init_pci_device_addresses(pm8001_ha);
649 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
651 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
653 /* wait until Inbound DoorBell Clear Register toggled */
654 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
657 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
658 value &= SPC_MSGU_CFG_TABLE_RESET;
659 } while ((value != 0) && (--max_wait_count));
661 if (!max_wait_count) {
662 PM8001_FAIL_DBG(pm8001_ha,
663 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
667 /* check the MPI-State for termination in progress */
668 /* wait until Inbound DoorBell Clear Register toggled */
669 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
673 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
674 GST_GSTLEN_MPIS_OFFSET);
675 if (GST_MPI_STATE_UNINIT ==
676 (gst_len_mpistate & GST_MPI_STATE_MASK))
678 } while (--max_wait_count);
679 if (!max_wait_count) {
680 PM8001_FAIL_DBG(pm8001_ha,
681 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
682 gst_len_mpistate & GST_MPI_STATE_MASK));
689 * soft_reset_ready_check - Function to check FW is ready for soft reset.
690 * @pm8001_ha: our hba card information
692 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
694 u32 regVal, regVal1, regVal2;
695 if (mpi_uninit_check(pm8001_ha) != 0) {
696 PM8001_FAIL_DBG(pm8001_ha,
697 pm8001_printk("MPI state is not ready\n"));
700 /* read the scratch pad 2 register bit 2 */
701 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
702 & SCRATCH_PAD2_FWRDY_RST;
703 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
704 PM8001_INIT_DBG(pm8001_ha,
705 pm8001_printk("Firmware is ready for reset .\n"));
708 /* Trigger NMI twice via RB6 */
709 spin_lock_irqsave(&pm8001_ha->lock, flags);
710 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
711 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
712 PM8001_FAIL_DBG(pm8001_ha,
713 pm8001_printk("Shift Bar4 to 0x%x failed\n",
717 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
718 RB6_MAGIC_NUMBER_RST);
719 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
720 /* wait for 100 ms */
722 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
723 SCRATCH_PAD2_FWRDY_RST;
724 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
725 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
726 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
727 PM8001_FAIL_DBG(pm8001_ha,
728 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
729 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
731 PM8001_FAIL_DBG(pm8001_ha,
732 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
733 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
734 PM8001_FAIL_DBG(pm8001_ha,
735 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
736 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
737 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
740 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
746 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
747 * the FW register status to the originated status.
748 * @pm8001_ha: our hba card information
749 * @signature: signature in host scratch pad0 register.
752 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
754 u32 regVal, toggleVal;
756 u32 regVal1, regVal2, regVal3;
759 /* step1: Check FW is ready for soft reset */
760 if (soft_reset_ready_check(pm8001_ha) != 0) {
761 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
765 /* step 2: clear NMI status register on AAP1 and IOP, write the same
767 /* map 0x60000 to BAR4(0x20), BAR2(win) */
768 spin_lock_irqsave(&pm8001_ha->lock, flags);
769 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
770 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
771 PM8001_FAIL_DBG(pm8001_ha,
772 pm8001_printk("Shift Bar4 to 0x%x failed\n",
773 MBIC_AAP1_ADDR_BASE));
776 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
777 PM8001_INIT_DBG(pm8001_ha,
778 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
779 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
780 /* map 0x70000 to BAR4(0x20), BAR2(win) */
781 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
782 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
783 PM8001_FAIL_DBG(pm8001_ha,
784 pm8001_printk("Shift Bar4 to 0x%x failed\n",
785 MBIC_IOP_ADDR_BASE));
788 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
789 PM8001_INIT_DBG(pm8001_ha,
790 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
791 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
793 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
794 PM8001_INIT_DBG(pm8001_ha,
795 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
796 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
798 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
799 PM8001_INIT_DBG(pm8001_ha,
800 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal));
801 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
803 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
804 PM8001_INIT_DBG(pm8001_ha,
805 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
806 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
808 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
809 PM8001_INIT_DBG(pm8001_ha,
810 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
811 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
813 /* read the scratch pad 1 register bit 2 */
814 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
816 toggleVal = regVal ^ SCRATCH_PAD1_RST;
818 /* set signature in host scratch pad0 register to tell SPC that the
819 host performs the soft reset */
820 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
822 /* read required registers for confirmming */
823 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
824 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
825 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
826 PM8001_FAIL_DBG(pm8001_ha,
827 pm8001_printk("Shift Bar4 to 0x%x failed\n",
831 PM8001_INIT_DBG(pm8001_ha,
832 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
834 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
836 /* step 3: host read GSM Configuration and Reset register */
837 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
838 /* Put those bits to low */
839 /* GSM XCBI offset = 0x70 0000
840 0x00 Bit 13 COM_SLV_SW_RSTB 1
841 0x00 Bit 12 QSSP_SW_RSTB 1
842 0x00 Bit 11 RAAE_SW_RSTB 1
843 0x00 Bit 9 RB_1_SW_RSTB 1
844 0x00 Bit 8 SM_SW_RSTB 1
846 regVal &= ~(0x00003b00);
847 /* host write GSM Configuration and Reset register */
848 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
849 PM8001_INIT_DBG(pm8001_ha,
850 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
851 "Configuration and Reset is set to = 0x%x\n",
852 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
855 /* disable GSM - Read Address Parity Check */
856 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
857 PM8001_INIT_DBG(pm8001_ha,
858 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
859 "Enable = 0x%x\n", regVal1));
860 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
861 PM8001_INIT_DBG(pm8001_ha,
862 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
863 "is set to = 0x%x\n",
864 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
866 /* disable GSM - Write Address Parity Check */
867 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
868 PM8001_INIT_DBG(pm8001_ha,
869 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
870 " Enable = 0x%x\n", regVal2));
871 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
872 PM8001_INIT_DBG(pm8001_ha,
873 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
874 "Enable is set to = 0x%x\n",
875 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
877 /* disable GSM - Write Data Parity Check */
878 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
879 PM8001_INIT_DBG(pm8001_ha,
880 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
881 " Enable = 0x%x\n", regVal3));
882 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
883 PM8001_INIT_DBG(pm8001_ha,
884 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
885 "is set to = 0x%x\n",
886 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
888 /* step 5: delay 10 usec */
890 /* step 5-b: set GPIO-0 output control to tristate anyway */
891 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
892 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
893 PM8001_INIT_DBG(pm8001_ha,
894 pm8001_printk("Shift Bar4 to 0x%x failed\n",
898 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
899 PM8001_INIT_DBG(pm8001_ha,
900 pm8001_printk("GPIO Output Control Register:"
901 " = 0x%x\n", regVal));
902 /* set GPIO-0 output control to tri-state */
903 regVal &= 0xFFFFFFFC;
904 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
906 /* Step 6: Reset the IOP and AAP1 */
907 /* map 0x00000 to BAR4(0x20), BAR2(win) */
908 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
909 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
910 PM8001_FAIL_DBG(pm8001_ha,
911 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
912 SPC_TOP_LEVEL_ADDR_BASE));
915 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
916 PM8001_INIT_DBG(pm8001_ha,
917 pm8001_printk("Top Register before resetting IOP/AAP1"
918 ":= 0x%x\n", regVal));
919 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
920 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
922 /* step 7: Reset the BDMA/OSSP */
923 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
924 PM8001_INIT_DBG(pm8001_ha,
925 pm8001_printk("Top Register before resetting BDMA/OSSP"
926 ": = 0x%x\n", regVal));
927 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
928 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
930 /* step 8: delay 10 usec */
933 /* step 9: bring the BDMA and OSSP out of reset */
934 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
935 PM8001_INIT_DBG(pm8001_ha,
936 pm8001_printk("Top Register before bringing up BDMA/OSSP"
937 ":= 0x%x\n", regVal));
938 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
939 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
941 /* step 10: delay 10 usec */
944 /* step 11: reads and sets the GSM Configuration and Reset Register */
945 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
946 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
947 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
948 PM8001_FAIL_DBG(pm8001_ha,
949 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
953 PM8001_INIT_DBG(pm8001_ha,
954 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
955 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
956 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
957 /* Put those bits to high */
958 /* GSM XCBI offset = 0x70 0000
959 0x00 Bit 13 COM_SLV_SW_RSTB 1
960 0x00 Bit 12 QSSP_SW_RSTB 1
961 0x00 Bit 11 RAAE_SW_RSTB 1
962 0x00 Bit 9 RB_1_SW_RSTB 1
963 0x00 Bit 8 SM_SW_RSTB 1
965 regVal |= (GSM_CONFIG_RESET_VALUE);
966 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
967 PM8001_INIT_DBG(pm8001_ha,
968 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
969 " Configuration and Reset is set to = 0x%x\n",
970 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
972 /* step 12: Restore GSM - Read Address Parity Check */
973 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
974 /* just for debugging */
975 PM8001_INIT_DBG(pm8001_ha,
976 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
977 " = 0x%x\n", regVal));
978 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
979 PM8001_INIT_DBG(pm8001_ha,
980 pm8001_printk("GSM 0x700038 - Read Address Parity"
981 " Check Enable is set to = 0x%x\n",
982 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
983 /* Restore GSM - Write Address Parity Check */
984 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
985 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
986 PM8001_INIT_DBG(pm8001_ha,
987 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
988 " Enable is set to = 0x%x\n",
989 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
990 /* Restore GSM - Write Data Parity Check */
991 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
992 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
993 PM8001_INIT_DBG(pm8001_ha,
994 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
995 "is set to = 0x%x\n",
996 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
998 /* step 13: bring the IOP and AAP1 out of reset */
999 /* map 0x00000 to BAR4(0x20), BAR2(win) */
1000 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1001 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1002 PM8001_FAIL_DBG(pm8001_ha,
1003 pm8001_printk("Shift Bar4 to 0x%x failed\n",
1004 SPC_TOP_LEVEL_ADDR_BASE));
1007 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1008 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1009 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1011 /* step 14: delay 10 usec - Normal Mode */
1013 /* check Soft Reset Normal mode or Soft Reset HDA mode */
1014 if (signature == SPC_SOFT_RESET_SIGNATURE) {
1015 /* step 15 (Normal Mode): wait until scratch pad1 register
1017 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1020 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1022 } while ((regVal != toggleVal) && (--max_wait_count));
1024 if (!max_wait_count) {
1025 regVal = pm8001_cr32(pm8001_ha, 0,
1026 MSGU_SCRATCH_PAD_1);
1027 PM8001_FAIL_DBG(pm8001_ha,
1028 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1029 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1030 toggleVal, regVal));
1031 PM8001_FAIL_DBG(pm8001_ha,
1032 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1033 pm8001_cr32(pm8001_ha, 0,
1034 MSGU_SCRATCH_PAD_0)));
1035 PM8001_FAIL_DBG(pm8001_ha,
1036 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1037 pm8001_cr32(pm8001_ha, 0,
1038 MSGU_SCRATCH_PAD_2)));
1039 PM8001_FAIL_DBG(pm8001_ha,
1040 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1041 pm8001_cr32(pm8001_ha, 0,
1042 MSGU_SCRATCH_PAD_3)));
1043 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1047 /* step 16 (Normal) - Clear ODMR and ODCR */
1048 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1049 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1051 /* step 17 (Normal Mode): wait for the FW and IOP to get
1052 ready - 1 sec timeout */
1053 /* Wait for the SPC Configuration Table to be ready */
1054 if (check_fw_ready(pm8001_ha) == -1) {
1055 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1056 /* return error if MPI Configuration Table not ready */
1057 PM8001_INIT_DBG(pm8001_ha,
1058 pm8001_printk("FW not ready SCRATCH_PAD1"
1059 " = 0x%x\n", regVal));
1060 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1061 /* return error if MPI Configuration Table not ready */
1062 PM8001_INIT_DBG(pm8001_ha,
1063 pm8001_printk("FW not ready SCRATCH_PAD2"
1064 " = 0x%x\n", regVal));
1065 PM8001_INIT_DBG(pm8001_ha,
1066 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1067 pm8001_cr32(pm8001_ha, 0,
1068 MSGU_SCRATCH_PAD_0)));
1069 PM8001_INIT_DBG(pm8001_ha,
1070 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1071 pm8001_cr32(pm8001_ha, 0,
1072 MSGU_SCRATCH_PAD_3)));
1073 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1077 pm8001_bar4_shift(pm8001_ha, 0);
1078 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1080 PM8001_INIT_DBG(pm8001_ha,
1081 pm8001_printk("SPC soft reset Complete\n"));
1085 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1089 PM8001_INIT_DBG(pm8001_ha,
1090 pm8001_printk("chip reset start\n"));
1092 /* do SPC chip reset. */
1093 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1094 regVal &= ~(SPC_REG_RESET_DEVICE);
1095 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1100 /* bring chip reset out of reset */
1101 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1102 regVal |= SPC_REG_RESET_DEVICE;
1103 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1108 /* wait for 20 msec until the firmware gets reloaded */
1112 } while ((--i) != 0);
1114 PM8001_INIT_DBG(pm8001_ha,
1115 pm8001_printk("chip reset finished\n"));
1119 * pm8001_chip_iounmap - which maped when initialized.
1120 * @pm8001_ha: our hba card information
1122 static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1124 s8 bar, logical = 0;
1125 for (bar = 0; bar < 6; bar++) {
1127 ** logical BARs for SPC:
1128 ** bar 0 and 1 - logical BAR0
1129 ** bar 2 and 3 - logical BAR1
1130 ** bar4 - logical BAR2
1131 ** bar5 - logical BAR3
1132 ** Skip the appropriate assignments:
1134 if ((bar == 1) || (bar == 3))
1136 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1137 iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1144 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1145 * @pm8001_ha: our hba card information
1148 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1150 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1151 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1155 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1156 * @pm8001_ha: our hba card information
1159 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1161 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1165 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1166 * @pm8001_ha: our hba card information
1169 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1174 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1175 msi_index += MSIX_TABLE_BASE;
1176 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1177 value = (1 << int_vec_idx);
1178 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
1183 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1184 * @pm8001_ha: our hba card information
1187 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1191 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1192 msi_index += MSIX_TABLE_BASE;
1193 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
1197 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1198 * @pm8001_ha: our hba card information
1201 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1203 #ifdef PM8001_USE_MSIX
1204 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1207 pm8001_chip_intx_interrupt_enable(pm8001_ha);
1212 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1213 * @pm8001_ha: our hba card information
1216 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1218 #ifdef PM8001_USE_MSIX
1219 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1222 pm8001_chip_intx_interrupt_disable(pm8001_ha);
1227 * mpi_msg_free_get- get the free message buffer for transfer inbound queue.
1228 * @circularQ: the inbound queue we want to transfer to HBA.
1229 * @messageSize: the message size of this transfer, normally it is 64 bytes
1230 * @messagePtr: the pointer to message.
1232 static int mpi_msg_free_get(struct inbound_queue_table *circularQ,
1233 u16 messageSize, void **messagePtr)
1235 u32 offset, consumer_index;
1236 struct mpi_msg_hdr *msgHeader;
1237 u8 bcCount = 1; /* only support single buffer */
1239 /* Checks is the requested message size can be allocated in this queue*/
1240 if (messageSize > 64) {
1245 /* Stores the new consumer index */
1246 consumer_index = pm8001_read_32(circularQ->ci_virt);
1247 circularQ->consumer_index = cpu_to_le32(consumer_index);
1248 if (((circularQ->producer_idx + bcCount) % 256) ==
1249 le32_to_cpu(circularQ->consumer_index)) {
1253 /* get memory IOMB buffer address */
1254 offset = circularQ->producer_idx * 64;
1255 /* increment to next bcCount element */
1256 circularQ->producer_idx = (circularQ->producer_idx + bcCount) % 256;
1257 /* Adds that distance to the base of the region virtual address plus
1258 the message header size*/
1259 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1260 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1265 * mpi_build_cmd- build the message queue for transfer, update the PI to FW
1266 * to tell the fw to get this message from IOMB.
1267 * @pm8001_ha: our hba card information
1268 * @circularQ: the inbound queue we want to transfer to HBA.
1269 * @opCode: the operation code represents commands which LLDD and fw recognized.
1270 * @payload: the command payload of each operation command.
1272 static int mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1273 struct inbound_queue_table *circularQ,
1274 u32 opCode, void *payload)
1276 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1277 u32 responseQueue = 0;
1280 if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) {
1281 PM8001_IO_DBG(pm8001_ha,
1282 pm8001_printk("No free mpi buffer\n"));
1286 /*Copy to the payload*/
1287 memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr)));
1289 /*Build the header*/
1290 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1291 | ((responseQueue & 0x3F) << 16)
1292 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1294 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1295 /*Update the PI to the firmware*/
1296 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1297 circularQ->pi_offset, circularQ->producer_idx);
1298 PM8001_IO_DBG(pm8001_ha,
1299 pm8001_printk("after PI= %d CI= %d\n", circularQ->producer_idx,
1300 circularQ->consumer_index));
1304 static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1305 struct outbound_queue_table *circularQ, u8 bc)
1308 struct mpi_msg_hdr *msgHeader;
1309 struct mpi_msg_hdr *pOutBoundMsgHeader;
1311 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1312 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1313 circularQ->consumer_idx * 64);
1314 if (pOutBoundMsgHeader != msgHeader) {
1315 PM8001_FAIL_DBG(pm8001_ha,
1316 pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1317 circularQ->consumer_idx, msgHeader));
1319 /* Update the producer index from SPC */
1320 producer_index = pm8001_read_32(circularQ->pi_virt);
1321 circularQ->producer_index = cpu_to_le32(producer_index);
1322 PM8001_FAIL_DBG(pm8001_ha,
1323 pm8001_printk("consumer_idx = %d producer_index = %d"
1324 "msgHeader = %p\n", circularQ->consumer_idx,
1325 circularQ->producer_index, msgHeader));
1328 /* free the circular queue buffer elements associated with the message*/
1329 circularQ->consumer_idx = (circularQ->consumer_idx + bc) % 256;
1330 /* update the CI of outbound queue */
1331 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1332 circularQ->consumer_idx);
1333 /* Update the producer index from SPC*/
1334 producer_index = pm8001_read_32(circularQ->pi_virt);
1335 circularQ->producer_index = cpu_to_le32(producer_index);
1336 PM8001_IO_DBG(pm8001_ha,
1337 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1338 circularQ->producer_index));
1343 * mpi_msg_consume- get the MPI message from outbound queue message table.
1344 * @pm8001_ha: our hba card information
1345 * @circularQ: the outbound queue table.
1346 * @messagePtr1: the message contents of this outbound message.
1347 * @pBC: the message size.
1349 static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1350 struct outbound_queue_table *circularQ,
1351 void **messagePtr1, u8 *pBC)
1353 struct mpi_msg_hdr *msgHeader;
1354 __le32 msgHeader_tmp;
1357 /* If there are not-yet-delivered messages ... */
1358 if (le32_to_cpu(circularQ->producer_index)
1359 != circularQ->consumer_idx) {
1360 /*Get the pointer to the circular queue buffer element*/
1361 msgHeader = (struct mpi_msg_hdr *)
1362 (circularQ->base_virt +
1363 circularQ->consumer_idx * 64);
1365 header_tmp = pm8001_read_32(msgHeader);
1366 msgHeader_tmp = cpu_to_le32(header_tmp);
1367 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1368 if (OPC_OUB_SKIP_ENTRY !=
1369 (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1372 sizeof(struct mpi_msg_hdr);
1373 *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1375 PM8001_IO_DBG(pm8001_ha,
1376 pm8001_printk(": CI=%d PI=%d "
1378 circularQ->consumer_idx,
1379 circularQ->producer_index,
1381 return MPI_IO_STATUS_SUCCESS;
1383 circularQ->consumer_idx =
1384 (circularQ->consumer_idx +
1385 ((le32_to_cpu(msgHeader_tmp)
1386 >> 24) & 0x1f)) % 256;
1388 pm8001_write_32(msgHeader, 0, 0);
1389 /* update the CI of outbound queue */
1390 pm8001_cw32(pm8001_ha,
1391 circularQ->ci_pci_bar,
1392 circularQ->ci_offset,
1393 circularQ->consumer_idx);
1396 circularQ->consumer_idx =
1397 (circularQ->consumer_idx +
1398 ((le32_to_cpu(msgHeader_tmp) >> 24) &
1401 pm8001_write_32(msgHeader, 0, 0);
1402 /* update the CI of outbound queue */
1403 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1404 circularQ->ci_offset,
1405 circularQ->consumer_idx);
1406 return MPI_IO_STATUS_FAIL;
1410 void *pi_virt = circularQ->pi_virt;
1411 /* Update the producer index from SPC */
1412 producer_index = pm8001_read_32(pi_virt);
1413 circularQ->producer_index = cpu_to_le32(producer_index);
1415 } while (le32_to_cpu(circularQ->producer_index) !=
1416 circularQ->consumer_idx);
1417 /* while we don't have any more not-yet-delivered message */
1419 return MPI_IO_STATUS_BUSY;
1422 static void pm8001_work_fn(struct work_struct *work)
1424 struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1425 struct pm8001_device *pm8001_dev;
1426 struct domain_device *dev;
1429 * So far, all users of this stash an associated structure here.
1430 * If we get here, and this pointer is null, then the action
1431 * was cancelled. This nullification happens when the device
1434 pm8001_dev = pw->data; /* Most stash device structure */
1435 if ((pm8001_dev == NULL)
1436 || ((pw->handler != IO_XFER_ERROR_BREAK)
1437 && (pm8001_dev->dev_type == NO_DEVICE))) {
1442 switch (pw->handler) {
1443 case IO_XFER_ERROR_BREAK:
1444 { /* This one stashes the sas_task instead */
1445 struct sas_task *t = (struct sas_task *)pm8001_dev;
1447 struct pm8001_ccb_info *ccb;
1448 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1449 unsigned long flags, flags1;
1450 struct task_status_struct *ts;
1453 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1454 break; /* Task still on lu */
1455 spin_lock_irqsave(&pm8001_ha->lock, flags);
1457 spin_lock_irqsave(&t->task_state_lock, flags1);
1458 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1459 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1460 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1461 break; /* Task got completed by another */
1463 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1465 /* Search for a possible ccb that matches the task */
1466 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1467 ccb = &pm8001_ha->ccb_info[i];
1469 if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1473 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1474 break; /* Task got freed by another */
1476 ts = &t->task_status;
1477 ts->resp = SAS_TASK_COMPLETE;
1478 /* Force the midlayer to retry */
1479 ts->stat = SAS_QUEUE_FULL;
1480 pm8001_dev = ccb->device;
1482 pm8001_dev->running_req--;
1483 spin_lock_irqsave(&t->task_state_lock, flags1);
1484 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1485 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1486 t->task_state_flags |= SAS_TASK_STATE_DONE;
1487 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1488 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1489 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
1490 " done with event 0x%x resp 0x%x stat 0x%x but"
1491 " aborted by upper layer!\n",
1492 t, pw->handler, ts->resp, ts->stat));
1493 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1494 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1496 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1497 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1498 mb();/* in order to force CPU ordering */
1499 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1503 case IO_XFER_OPEN_RETRY_TIMEOUT:
1504 { /* This one stashes the sas_task instead */
1505 struct sas_task *t = (struct sas_task *)pm8001_dev;
1507 struct pm8001_ccb_info *ccb;
1508 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1509 unsigned long flags, flags1;
1512 PM8001_IO_DBG(pm8001_ha,
1513 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1515 ret = pm8001_query_task(t);
1517 PM8001_IO_DBG(pm8001_ha,
1519 case TMF_RESP_FUNC_SUCC:
1520 pm8001_printk("...Task on lu\n");
1523 case TMF_RESP_FUNC_COMPLETE:
1524 pm8001_printk("...Task NOT on lu\n");
1528 pm8001_printk("...query task failed!!!\n");
1532 spin_lock_irqsave(&pm8001_ha->lock, flags);
1534 spin_lock_irqsave(&t->task_state_lock, flags1);
1536 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1537 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1538 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1539 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1540 (void)pm8001_abort_task(t);
1541 break; /* Task got completed by another */
1544 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1546 /* Search for a possible ccb that matches the task */
1547 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1548 ccb = &pm8001_ha->ccb_info[i];
1550 if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1554 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1555 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1556 (void)pm8001_abort_task(t);
1557 break; /* Task got freed by another */
1560 pm8001_dev = ccb->device;
1561 dev = pm8001_dev->sas_device;
1564 case TMF_RESP_FUNC_SUCC: /* task on lu */
1565 ccb->open_retry = 1; /* Snub completion */
1566 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1567 ret = pm8001_abort_task(t);
1568 ccb->open_retry = 0;
1570 case TMF_RESP_FUNC_SUCC:
1571 case TMF_RESP_FUNC_COMPLETE:
1573 default: /* device misbehavior */
1574 ret = TMF_RESP_FUNC_FAILED;
1575 PM8001_IO_DBG(pm8001_ha,
1576 pm8001_printk("...Reset phy\n"));
1577 pm8001_I_T_nexus_reset(dev);
1582 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1583 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1584 /* Do we need to abort the task locally? */
1587 default: /* device misbehavior */
1588 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1589 ret = TMF_RESP_FUNC_FAILED;
1590 PM8001_IO_DBG(pm8001_ha,
1591 pm8001_printk("...Reset phy\n"));
1592 pm8001_I_T_nexus_reset(dev);
1595 if (ret == TMF_RESP_FUNC_FAILED)
1597 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1598 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
1600 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1601 dev = pm8001_dev->sas_device;
1602 pm8001_I_T_nexus_reset(dev);
1604 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1605 dev = pm8001_dev->sas_device;
1606 pm8001_I_T_nexus_reset(dev);
1608 case IO_DS_IN_ERROR:
1609 dev = pm8001_dev->sas_device;
1610 pm8001_I_T_nexus_reset(dev);
1612 case IO_DS_NON_OPERATIONAL:
1613 dev = pm8001_dev->sas_device;
1614 pm8001_I_T_nexus_reset(dev);
1620 static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1623 struct pm8001_work *pw;
1626 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1628 pw->pm8001_ha = pm8001_ha;
1630 pw->handler = handler;
1631 INIT_WORK(&pw->work, pm8001_work_fn);
1632 queue_work(pm8001_wq, &pw->work);
1640 * mpi_ssp_completion- process the event that FW response to the SSP request.
1641 * @pm8001_ha: our hba card information
1642 * @piomb: the message contents of this outbound message.
1644 * When FW has completed a ssp request for example a IO request, after it has
1645 * filled the SG data with the data, it will trigger this event represent
1646 * that he has finished the job,please check the coresponding buffer.
1647 * So we will tell the caller who maybe waiting the result to tell upper layer
1648 * that the task has been finished.
1651 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1654 struct pm8001_ccb_info *ccb;
1655 unsigned long flags;
1659 struct ssp_completion_resp *psspPayload;
1660 struct task_status_struct *ts;
1661 struct ssp_response_iu *iu;
1662 struct pm8001_device *pm8001_dev;
1663 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1664 status = le32_to_cpu(psspPayload->status);
1665 tag = le32_to_cpu(psspPayload->tag);
1666 ccb = &pm8001_ha->ccb_info[tag];
1667 if ((status == IO_ABORTED) && ccb->open_retry) {
1668 /* Being completed by another */
1669 ccb->open_retry = 0;
1672 pm8001_dev = ccb->device;
1673 param = le32_to_cpu(psspPayload->param);
1677 if (status && status != IO_UNDERFLOW)
1678 PM8001_FAIL_DBG(pm8001_ha,
1679 pm8001_printk("sas IO status 0x%x\n", status));
1680 if (unlikely(!t || !t->lldd_task || !t->dev))
1682 ts = &t->task_status;
1685 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1686 ",param = %d\n", param));
1688 ts->resp = SAS_TASK_COMPLETE;
1689 ts->stat = SAM_STAT_GOOD;
1691 ts->resp = SAS_TASK_COMPLETE;
1692 ts->stat = SAS_PROTO_RESPONSE;
1693 ts->residual = param;
1694 iu = &psspPayload->ssp_resp_iu;
1695 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1698 pm8001_dev->running_req--;
1701 PM8001_IO_DBG(pm8001_ha,
1702 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1703 ts->resp = SAS_TASK_COMPLETE;
1704 ts->stat = SAS_ABORTED_TASK;
1707 /* SSP Completion with error */
1708 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1709 ",param = %d\n", param));
1710 ts->resp = SAS_TASK_COMPLETE;
1711 ts->stat = SAS_DATA_UNDERRUN;
1712 ts->residual = param;
1714 pm8001_dev->running_req--;
1717 PM8001_IO_DBG(pm8001_ha,
1718 pm8001_printk("IO_NO_DEVICE\n"));
1719 ts->resp = SAS_TASK_UNDELIVERED;
1720 ts->stat = SAS_PHY_DOWN;
1722 case IO_XFER_ERROR_BREAK:
1723 PM8001_IO_DBG(pm8001_ha,
1724 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1725 ts->resp = SAS_TASK_COMPLETE;
1726 ts->stat = SAS_OPEN_REJECT;
1727 /* Force the midlayer to retry */
1728 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1730 case IO_XFER_ERROR_PHY_NOT_READY:
1731 PM8001_IO_DBG(pm8001_ha,
1732 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1733 ts->resp = SAS_TASK_COMPLETE;
1734 ts->stat = SAS_OPEN_REJECT;
1735 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1737 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1738 PM8001_IO_DBG(pm8001_ha,
1739 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1740 ts->resp = SAS_TASK_COMPLETE;
1741 ts->stat = SAS_OPEN_REJECT;
1742 ts->open_rej_reason = SAS_OREJ_EPROTO;
1744 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1745 PM8001_IO_DBG(pm8001_ha,
1746 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1747 ts->resp = SAS_TASK_COMPLETE;
1748 ts->stat = SAS_OPEN_REJECT;
1749 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1751 case IO_OPEN_CNX_ERROR_BREAK:
1752 PM8001_IO_DBG(pm8001_ha,
1753 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1754 ts->resp = SAS_TASK_COMPLETE;
1755 ts->stat = SAS_OPEN_REJECT;
1756 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1758 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1759 PM8001_IO_DBG(pm8001_ha,
1760 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1761 ts->resp = SAS_TASK_COMPLETE;
1762 ts->stat = SAS_OPEN_REJECT;
1763 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1765 pm8001_handle_event(pm8001_ha,
1767 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1769 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1770 PM8001_IO_DBG(pm8001_ha,
1771 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1772 ts->resp = SAS_TASK_COMPLETE;
1773 ts->stat = SAS_OPEN_REJECT;
1774 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1776 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1777 PM8001_IO_DBG(pm8001_ha,
1778 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1779 "NOT_SUPPORTED\n"));
1780 ts->resp = SAS_TASK_COMPLETE;
1781 ts->stat = SAS_OPEN_REJECT;
1782 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1784 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1785 PM8001_IO_DBG(pm8001_ha,
1786 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1787 ts->resp = SAS_TASK_UNDELIVERED;
1788 ts->stat = SAS_OPEN_REJECT;
1789 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1791 case IO_XFER_ERROR_NAK_RECEIVED:
1792 PM8001_IO_DBG(pm8001_ha,
1793 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1794 ts->resp = SAS_TASK_COMPLETE;
1795 ts->stat = SAS_OPEN_REJECT;
1796 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1798 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1799 PM8001_IO_DBG(pm8001_ha,
1800 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1801 ts->resp = SAS_TASK_COMPLETE;
1802 ts->stat = SAS_NAK_R_ERR;
1804 case IO_XFER_ERROR_DMA:
1805 PM8001_IO_DBG(pm8001_ha,
1806 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1807 ts->resp = SAS_TASK_COMPLETE;
1808 ts->stat = SAS_OPEN_REJECT;
1810 case IO_XFER_OPEN_RETRY_TIMEOUT:
1811 PM8001_IO_DBG(pm8001_ha,
1812 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1813 ts->resp = SAS_TASK_COMPLETE;
1814 ts->stat = SAS_OPEN_REJECT;
1815 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1817 case IO_XFER_ERROR_OFFSET_MISMATCH:
1818 PM8001_IO_DBG(pm8001_ha,
1819 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1820 ts->resp = SAS_TASK_COMPLETE;
1821 ts->stat = SAS_OPEN_REJECT;
1823 case IO_PORT_IN_RESET:
1824 PM8001_IO_DBG(pm8001_ha,
1825 pm8001_printk("IO_PORT_IN_RESET\n"));
1826 ts->resp = SAS_TASK_COMPLETE;
1827 ts->stat = SAS_OPEN_REJECT;
1829 case IO_DS_NON_OPERATIONAL:
1830 PM8001_IO_DBG(pm8001_ha,
1831 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1832 ts->resp = SAS_TASK_COMPLETE;
1833 ts->stat = SAS_OPEN_REJECT;
1835 pm8001_handle_event(pm8001_ha,
1837 IO_DS_NON_OPERATIONAL);
1839 case IO_DS_IN_RECOVERY:
1840 PM8001_IO_DBG(pm8001_ha,
1841 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1842 ts->resp = SAS_TASK_COMPLETE;
1843 ts->stat = SAS_OPEN_REJECT;
1845 case IO_TM_TAG_NOT_FOUND:
1846 PM8001_IO_DBG(pm8001_ha,
1847 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1848 ts->resp = SAS_TASK_COMPLETE;
1849 ts->stat = SAS_OPEN_REJECT;
1851 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1852 PM8001_IO_DBG(pm8001_ha,
1853 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1854 ts->resp = SAS_TASK_COMPLETE;
1855 ts->stat = SAS_OPEN_REJECT;
1857 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1858 PM8001_IO_DBG(pm8001_ha,
1859 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1860 ts->resp = SAS_TASK_COMPLETE;
1861 ts->stat = SAS_OPEN_REJECT;
1862 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1865 PM8001_IO_DBG(pm8001_ha,
1866 pm8001_printk("Unknown status 0x%x\n", status));
1867 /* not allowed case. Therefore, return failed status */
1868 ts->resp = SAS_TASK_COMPLETE;
1869 ts->stat = SAS_OPEN_REJECT;
1872 PM8001_IO_DBG(pm8001_ha,
1873 pm8001_printk("scsi_status = %x \n ",
1874 psspPayload->ssp_resp_iu.status));
1875 spin_lock_irqsave(&t->task_state_lock, flags);
1876 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1877 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1878 t->task_state_flags |= SAS_TASK_STATE_DONE;
1879 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1880 spin_unlock_irqrestore(&t->task_state_lock, flags);
1881 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1882 " io_status 0x%x resp 0x%x "
1883 "stat 0x%x but aborted by upper layer!\n",
1884 t, status, ts->resp, ts->stat));
1885 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1887 spin_unlock_irqrestore(&t->task_state_lock, flags);
1888 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1889 mb();/* in order to force CPU ordering */
1894 /*See the comments for mpi_ssp_completion */
1895 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1898 unsigned long flags;
1899 struct task_status_struct *ts;
1900 struct pm8001_ccb_info *ccb;
1901 struct pm8001_device *pm8001_dev;
1902 struct ssp_event_resp *psspPayload =
1903 (struct ssp_event_resp *)(piomb + 4);
1904 u32 event = le32_to_cpu(psspPayload->event);
1905 u32 tag = le32_to_cpu(psspPayload->tag);
1906 u32 port_id = le32_to_cpu(psspPayload->port_id);
1907 u32 dev_id = le32_to_cpu(psspPayload->device_id);
1909 ccb = &pm8001_ha->ccb_info[tag];
1911 pm8001_dev = ccb->device;
1913 PM8001_FAIL_DBG(pm8001_ha,
1914 pm8001_printk("sas IO status 0x%x\n", event));
1915 if (unlikely(!t || !t->lldd_task || !t->dev))
1917 ts = &t->task_status;
1918 PM8001_IO_DBG(pm8001_ha,
1919 pm8001_printk("port_id = %x,device_id = %x\n",
1923 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1924 ts->resp = SAS_TASK_COMPLETE;
1925 ts->stat = SAS_DATA_OVERRUN;
1928 pm8001_dev->running_req--;
1930 case IO_XFER_ERROR_BREAK:
1931 PM8001_IO_DBG(pm8001_ha,
1932 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1933 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1935 case IO_XFER_ERROR_PHY_NOT_READY:
1936 PM8001_IO_DBG(pm8001_ha,
1937 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1938 ts->resp = SAS_TASK_COMPLETE;
1939 ts->stat = SAS_OPEN_REJECT;
1940 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1942 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1943 PM8001_IO_DBG(pm8001_ha,
1944 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1946 ts->resp = SAS_TASK_COMPLETE;
1947 ts->stat = SAS_OPEN_REJECT;
1948 ts->open_rej_reason = SAS_OREJ_EPROTO;
1950 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1951 PM8001_IO_DBG(pm8001_ha,
1952 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1953 ts->resp = SAS_TASK_COMPLETE;
1954 ts->stat = SAS_OPEN_REJECT;
1955 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1957 case IO_OPEN_CNX_ERROR_BREAK:
1958 PM8001_IO_DBG(pm8001_ha,
1959 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1960 ts->resp = SAS_TASK_COMPLETE;
1961 ts->stat = SAS_OPEN_REJECT;
1962 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1964 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1965 PM8001_IO_DBG(pm8001_ha,
1966 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1967 ts->resp = SAS_TASK_COMPLETE;
1968 ts->stat = SAS_OPEN_REJECT;
1969 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1971 pm8001_handle_event(pm8001_ha,
1973 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1975 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1976 PM8001_IO_DBG(pm8001_ha,
1977 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1978 ts->resp = SAS_TASK_COMPLETE;
1979 ts->stat = SAS_OPEN_REJECT;
1980 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1982 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1983 PM8001_IO_DBG(pm8001_ha,
1984 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1985 "NOT_SUPPORTED\n"));
1986 ts->resp = SAS_TASK_COMPLETE;
1987 ts->stat = SAS_OPEN_REJECT;
1988 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1990 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1991 PM8001_IO_DBG(pm8001_ha,
1992 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1993 ts->resp = SAS_TASK_COMPLETE;
1994 ts->stat = SAS_OPEN_REJECT;
1995 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1997 case IO_XFER_ERROR_NAK_RECEIVED:
1998 PM8001_IO_DBG(pm8001_ha,
1999 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2000 ts->resp = SAS_TASK_COMPLETE;
2001 ts->stat = SAS_OPEN_REJECT;
2002 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2004 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2005 PM8001_IO_DBG(pm8001_ha,
2006 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2007 ts->resp = SAS_TASK_COMPLETE;
2008 ts->stat = SAS_NAK_R_ERR;
2010 case IO_XFER_OPEN_RETRY_TIMEOUT:
2011 PM8001_IO_DBG(pm8001_ha,
2012 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2013 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2015 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2016 PM8001_IO_DBG(pm8001_ha,
2017 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2018 ts->resp = SAS_TASK_COMPLETE;
2019 ts->stat = SAS_DATA_OVERRUN;
2021 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2022 PM8001_IO_DBG(pm8001_ha,
2023 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2024 ts->resp = SAS_TASK_COMPLETE;
2025 ts->stat = SAS_DATA_OVERRUN;
2027 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2028 PM8001_IO_DBG(pm8001_ha,
2029 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2030 ts->resp = SAS_TASK_COMPLETE;
2031 ts->stat = SAS_DATA_OVERRUN;
2033 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2034 PM8001_IO_DBG(pm8001_ha,
2035 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2036 ts->resp = SAS_TASK_COMPLETE;
2037 ts->stat = SAS_DATA_OVERRUN;
2039 case IO_XFER_ERROR_OFFSET_MISMATCH:
2040 PM8001_IO_DBG(pm8001_ha,
2041 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2042 ts->resp = SAS_TASK_COMPLETE;
2043 ts->stat = SAS_DATA_OVERRUN;
2045 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2046 PM8001_IO_DBG(pm8001_ha,
2047 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2048 ts->resp = SAS_TASK_COMPLETE;
2049 ts->stat = SAS_DATA_OVERRUN;
2051 case IO_XFER_CMD_FRAME_ISSUED:
2052 PM8001_IO_DBG(pm8001_ha,
2053 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n"));
2056 PM8001_IO_DBG(pm8001_ha,
2057 pm8001_printk("Unknown status 0x%x\n", event));
2058 /* not allowed case. Therefore, return failed status */
2059 ts->resp = SAS_TASK_COMPLETE;
2060 ts->stat = SAS_DATA_OVERRUN;
2063 spin_lock_irqsave(&t->task_state_lock, flags);
2064 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2065 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2066 t->task_state_flags |= SAS_TASK_STATE_DONE;
2067 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2068 spin_unlock_irqrestore(&t->task_state_lock, flags);
2069 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2070 " event 0x%x resp 0x%x "
2071 "stat 0x%x but aborted by upper layer!\n",
2072 t, event, ts->resp, ts->stat));
2073 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2075 spin_unlock_irqrestore(&t->task_state_lock, flags);
2076 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2077 mb();/* in order to force CPU ordering */
2082 /*See the comments for mpi_ssp_completion */
2084 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2087 struct pm8001_ccb_info *ccb;
2091 struct sata_completion_resp *psataPayload;
2092 struct task_status_struct *ts;
2093 struct ata_task_resp *resp ;
2095 struct pm8001_device *pm8001_dev;
2097 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2098 status = le32_to_cpu(psataPayload->status);
2099 tag = le32_to_cpu(psataPayload->tag);
2101 ccb = &pm8001_ha->ccb_info[tag];
2102 param = le32_to_cpu(psataPayload->param);
2104 ts = &t->task_status;
2105 pm8001_dev = ccb->device;
2107 PM8001_FAIL_DBG(pm8001_ha,
2108 pm8001_printk("sata IO status 0x%x\n", status));
2109 if (unlikely(!t || !t->lldd_task || !t->dev))
2114 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2116 ts->resp = SAS_TASK_COMPLETE;
2117 ts->stat = SAM_STAT_GOOD;
2120 ts->resp = SAS_TASK_COMPLETE;
2121 ts->stat = SAS_PROTO_RESPONSE;
2122 ts->residual = param;
2123 PM8001_IO_DBG(pm8001_ha,
2124 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2126 sata_resp = &psataPayload->sata_resp[0];
2127 resp = (struct ata_task_resp *)ts->buf;
2128 if (t->ata_task.dma_xfer == 0 &&
2129 t->data_dir == PCI_DMA_FROMDEVICE) {
2130 len = sizeof(struct pio_setup_fis);
2131 PM8001_IO_DBG(pm8001_ha,
2132 pm8001_printk("PIO read len = %d\n", len));
2133 } else if (t->ata_task.use_ncq) {
2134 len = sizeof(struct set_dev_bits_fis);
2135 PM8001_IO_DBG(pm8001_ha,
2136 pm8001_printk("FPDMA len = %d\n", len));
2138 len = sizeof(struct dev_to_host_fis);
2139 PM8001_IO_DBG(pm8001_ha,
2140 pm8001_printk("other len = %d\n", len));
2142 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2143 resp->frame_len = len;
2144 memcpy(&resp->ending_fis[0], sata_resp, len);
2145 ts->buf_valid_size = sizeof(*resp);
2147 PM8001_IO_DBG(pm8001_ha,
2148 pm8001_printk("response to large\n"));
2151 pm8001_dev->running_req--;
2154 PM8001_IO_DBG(pm8001_ha,
2155 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2156 ts->resp = SAS_TASK_COMPLETE;
2157 ts->stat = SAS_ABORTED_TASK;
2159 pm8001_dev->running_req--;
2161 /* following cases are to do cases */
2163 /* SATA Completion with error */
2164 PM8001_IO_DBG(pm8001_ha,
2165 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2166 ts->resp = SAS_TASK_COMPLETE;
2167 ts->stat = SAS_DATA_UNDERRUN;
2168 ts->residual = param;
2170 pm8001_dev->running_req--;
2173 PM8001_IO_DBG(pm8001_ha,
2174 pm8001_printk("IO_NO_DEVICE\n"));
2175 ts->resp = SAS_TASK_UNDELIVERED;
2176 ts->stat = SAS_PHY_DOWN;
2178 case IO_XFER_ERROR_BREAK:
2179 PM8001_IO_DBG(pm8001_ha,
2180 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2181 ts->resp = SAS_TASK_COMPLETE;
2182 ts->stat = SAS_INTERRUPTED;
2184 case IO_XFER_ERROR_PHY_NOT_READY:
2185 PM8001_IO_DBG(pm8001_ha,
2186 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2187 ts->resp = SAS_TASK_COMPLETE;
2188 ts->stat = SAS_OPEN_REJECT;
2189 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2191 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2192 PM8001_IO_DBG(pm8001_ha,
2193 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2195 ts->resp = SAS_TASK_COMPLETE;
2196 ts->stat = SAS_OPEN_REJECT;
2197 ts->open_rej_reason = SAS_OREJ_EPROTO;
2199 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2200 PM8001_IO_DBG(pm8001_ha,
2201 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2202 ts->resp = SAS_TASK_COMPLETE;
2203 ts->stat = SAS_OPEN_REJECT;
2204 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2206 case IO_OPEN_CNX_ERROR_BREAK:
2207 PM8001_IO_DBG(pm8001_ha,
2208 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2209 ts->resp = SAS_TASK_COMPLETE;
2210 ts->stat = SAS_OPEN_REJECT;
2211 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2213 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2214 PM8001_IO_DBG(pm8001_ha,
2215 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2216 ts->resp = SAS_TASK_COMPLETE;
2217 ts->stat = SAS_DEV_NO_RESPONSE;
2218 if (!t->uldd_task) {
2219 pm8001_handle_event(pm8001_ha,
2221 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2222 ts->resp = SAS_TASK_UNDELIVERED;
2223 ts->stat = SAS_QUEUE_FULL;
2224 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2225 mb();/*in order to force CPU ordering*/
2226 spin_unlock_irq(&pm8001_ha->lock);
2228 spin_lock_irq(&pm8001_ha->lock);
2232 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2233 PM8001_IO_DBG(pm8001_ha,
2234 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2235 ts->resp = SAS_TASK_UNDELIVERED;
2236 ts->stat = SAS_OPEN_REJECT;
2237 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2238 if (!t->uldd_task) {
2239 pm8001_handle_event(pm8001_ha,
2241 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2242 ts->resp = SAS_TASK_UNDELIVERED;
2243 ts->stat = SAS_QUEUE_FULL;
2244 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2246 spin_unlock_irq(&pm8001_ha->lock);
2248 spin_lock_irq(&pm8001_ha->lock);
2252 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2253 PM8001_IO_DBG(pm8001_ha,
2254 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2255 "NOT_SUPPORTED\n"));
2256 ts->resp = SAS_TASK_COMPLETE;
2257 ts->stat = SAS_OPEN_REJECT;
2258 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2260 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2261 PM8001_IO_DBG(pm8001_ha,
2262 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2264 ts->resp = SAS_TASK_COMPLETE;
2265 ts->stat = SAS_DEV_NO_RESPONSE;
2266 if (!t->uldd_task) {
2267 pm8001_handle_event(pm8001_ha,
2269 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2270 ts->resp = SAS_TASK_UNDELIVERED;
2271 ts->stat = SAS_QUEUE_FULL;
2272 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2274 spin_unlock_irq(&pm8001_ha->lock);
2276 spin_lock_irq(&pm8001_ha->lock);
2280 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2281 PM8001_IO_DBG(pm8001_ha,
2282 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2283 ts->resp = SAS_TASK_COMPLETE;
2284 ts->stat = SAS_OPEN_REJECT;
2285 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2287 case IO_XFER_ERROR_NAK_RECEIVED:
2288 PM8001_IO_DBG(pm8001_ha,
2289 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2290 ts->resp = SAS_TASK_COMPLETE;
2291 ts->stat = SAS_NAK_R_ERR;
2293 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2294 PM8001_IO_DBG(pm8001_ha,
2295 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2296 ts->resp = SAS_TASK_COMPLETE;
2297 ts->stat = SAS_NAK_R_ERR;
2299 case IO_XFER_ERROR_DMA:
2300 PM8001_IO_DBG(pm8001_ha,
2301 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2302 ts->resp = SAS_TASK_COMPLETE;
2303 ts->stat = SAS_ABORTED_TASK;
2305 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2306 PM8001_IO_DBG(pm8001_ha,
2307 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2308 ts->resp = SAS_TASK_UNDELIVERED;
2309 ts->stat = SAS_DEV_NO_RESPONSE;
2311 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2312 PM8001_IO_DBG(pm8001_ha,
2313 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2314 ts->resp = SAS_TASK_COMPLETE;
2315 ts->stat = SAS_DATA_UNDERRUN;
2317 case IO_XFER_OPEN_RETRY_TIMEOUT:
2318 PM8001_IO_DBG(pm8001_ha,
2319 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2320 ts->resp = SAS_TASK_COMPLETE;
2321 ts->stat = SAS_OPEN_TO;
2323 case IO_PORT_IN_RESET:
2324 PM8001_IO_DBG(pm8001_ha,
2325 pm8001_printk("IO_PORT_IN_RESET\n"));
2326 ts->resp = SAS_TASK_COMPLETE;
2327 ts->stat = SAS_DEV_NO_RESPONSE;
2329 case IO_DS_NON_OPERATIONAL:
2330 PM8001_IO_DBG(pm8001_ha,
2331 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2332 ts->resp = SAS_TASK_COMPLETE;
2333 ts->stat = SAS_DEV_NO_RESPONSE;
2334 if (!t->uldd_task) {
2335 pm8001_handle_event(pm8001_ha, pm8001_dev,
2336 IO_DS_NON_OPERATIONAL);
2337 ts->resp = SAS_TASK_UNDELIVERED;
2338 ts->stat = SAS_QUEUE_FULL;
2339 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2341 spin_unlock_irq(&pm8001_ha->lock);
2343 spin_lock_irq(&pm8001_ha->lock);
2347 case IO_DS_IN_RECOVERY:
2348 PM8001_IO_DBG(pm8001_ha,
2349 pm8001_printk(" IO_DS_IN_RECOVERY\n"));
2350 ts->resp = SAS_TASK_COMPLETE;
2351 ts->stat = SAS_DEV_NO_RESPONSE;
2353 case IO_DS_IN_ERROR:
2354 PM8001_IO_DBG(pm8001_ha,
2355 pm8001_printk("IO_DS_IN_ERROR\n"));
2356 ts->resp = SAS_TASK_COMPLETE;
2357 ts->stat = SAS_DEV_NO_RESPONSE;
2358 if (!t->uldd_task) {
2359 pm8001_handle_event(pm8001_ha, pm8001_dev,
2361 ts->resp = SAS_TASK_UNDELIVERED;
2362 ts->stat = SAS_QUEUE_FULL;
2363 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2365 spin_unlock_irq(&pm8001_ha->lock);
2367 spin_lock_irq(&pm8001_ha->lock);
2371 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2372 PM8001_IO_DBG(pm8001_ha,
2373 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2374 ts->resp = SAS_TASK_COMPLETE;
2375 ts->stat = SAS_OPEN_REJECT;
2376 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2378 PM8001_IO_DBG(pm8001_ha,
2379 pm8001_printk("Unknown status 0x%x\n", status));
2380 /* not allowed case. Therefore, return failed status */
2381 ts->resp = SAS_TASK_COMPLETE;
2382 ts->stat = SAS_DEV_NO_RESPONSE;
2385 spin_lock_irq(&t->task_state_lock);
2386 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2387 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2388 t->task_state_flags |= SAS_TASK_STATE_DONE;
2389 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2390 spin_unlock_irq(&t->task_state_lock);
2391 PM8001_FAIL_DBG(pm8001_ha,
2392 pm8001_printk("task 0x%p done with io_status 0x%x"
2393 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2394 t, status, ts->resp, ts->stat));
2395 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2396 } else if (t->uldd_task) {
2397 spin_unlock_irq(&t->task_state_lock);
2398 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2400 spin_unlock_irq(&pm8001_ha->lock);
2402 spin_lock_irq(&pm8001_ha->lock);
2403 } else if (!t->uldd_task) {
2404 spin_unlock_irq(&t->task_state_lock);
2405 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2407 spin_unlock_irq(&pm8001_ha->lock);
2409 spin_lock_irq(&pm8001_ha->lock);
2413 /*See the comments for mpi_ssp_completion */
2414 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2417 struct task_status_struct *ts;
2418 struct pm8001_ccb_info *ccb;
2419 struct pm8001_device *pm8001_dev;
2420 struct sata_event_resp *psataPayload =
2421 (struct sata_event_resp *)(piomb + 4);
2422 u32 event = le32_to_cpu(psataPayload->event);
2423 u32 tag = le32_to_cpu(psataPayload->tag);
2424 u32 port_id = le32_to_cpu(psataPayload->port_id);
2425 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2427 ccb = &pm8001_ha->ccb_info[tag];
2429 pm8001_dev = ccb->device;
2431 PM8001_FAIL_DBG(pm8001_ha,
2432 pm8001_printk("sata IO status 0x%x\n", event));
2433 if (unlikely(!t || !t->lldd_task || !t->dev))
2435 ts = &t->task_status;
2436 PM8001_IO_DBG(pm8001_ha,
2437 pm8001_printk("port_id = %x,device_id = %x\n",
2441 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2442 ts->resp = SAS_TASK_COMPLETE;
2443 ts->stat = SAS_DATA_OVERRUN;
2446 pm8001_dev->running_req--;
2448 case IO_XFER_ERROR_BREAK:
2449 PM8001_IO_DBG(pm8001_ha,
2450 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2451 ts->resp = SAS_TASK_COMPLETE;
2452 ts->stat = SAS_INTERRUPTED;
2454 case IO_XFER_ERROR_PHY_NOT_READY:
2455 PM8001_IO_DBG(pm8001_ha,
2456 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2457 ts->resp = SAS_TASK_COMPLETE;
2458 ts->stat = SAS_OPEN_REJECT;
2459 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2461 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2462 PM8001_IO_DBG(pm8001_ha,
2463 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2465 ts->resp = SAS_TASK_COMPLETE;
2466 ts->stat = SAS_OPEN_REJECT;
2467 ts->open_rej_reason = SAS_OREJ_EPROTO;
2469 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2470 PM8001_IO_DBG(pm8001_ha,
2471 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2472 ts->resp = SAS_TASK_COMPLETE;
2473 ts->stat = SAS_OPEN_REJECT;
2474 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2476 case IO_OPEN_CNX_ERROR_BREAK:
2477 PM8001_IO_DBG(pm8001_ha,
2478 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2479 ts->resp = SAS_TASK_COMPLETE;
2480 ts->stat = SAS_OPEN_REJECT;
2481 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2483 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2484 PM8001_IO_DBG(pm8001_ha,
2485 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2486 ts->resp = SAS_TASK_UNDELIVERED;
2487 ts->stat = SAS_DEV_NO_RESPONSE;
2488 if (!t->uldd_task) {
2489 pm8001_handle_event(pm8001_ha,
2491 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2492 ts->resp = SAS_TASK_COMPLETE;
2493 ts->stat = SAS_QUEUE_FULL;
2494 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2496 spin_unlock_irq(&pm8001_ha->lock);
2498 spin_lock_irq(&pm8001_ha->lock);
2502 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2503 PM8001_IO_DBG(pm8001_ha,
2504 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2505 ts->resp = SAS_TASK_UNDELIVERED;
2506 ts->stat = SAS_OPEN_REJECT;
2507 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2509 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2510 PM8001_IO_DBG(pm8001_ha,
2511 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2512 "NOT_SUPPORTED\n"));
2513 ts->resp = SAS_TASK_COMPLETE;
2514 ts->stat = SAS_OPEN_REJECT;
2515 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2517 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2518 PM8001_IO_DBG(pm8001_ha,
2519 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2520 ts->resp = SAS_TASK_COMPLETE;
2521 ts->stat = SAS_OPEN_REJECT;
2522 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2524 case IO_XFER_ERROR_NAK_RECEIVED:
2525 PM8001_IO_DBG(pm8001_ha,
2526 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2527 ts->resp = SAS_TASK_COMPLETE;
2528 ts->stat = SAS_NAK_R_ERR;
2530 case IO_XFER_ERROR_PEER_ABORTED:
2531 PM8001_IO_DBG(pm8001_ha,
2532 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2533 ts->resp = SAS_TASK_COMPLETE;
2534 ts->stat = SAS_NAK_R_ERR;
2536 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2537 PM8001_IO_DBG(pm8001_ha,
2538 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2539 ts->resp = SAS_TASK_COMPLETE;
2540 ts->stat = SAS_DATA_UNDERRUN;
2542 case IO_XFER_OPEN_RETRY_TIMEOUT:
2543 PM8001_IO_DBG(pm8001_ha,
2544 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2545 ts->resp = SAS_TASK_COMPLETE;
2546 ts->stat = SAS_OPEN_TO;
2548 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2549 PM8001_IO_DBG(pm8001_ha,
2550 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2551 ts->resp = SAS_TASK_COMPLETE;
2552 ts->stat = SAS_OPEN_TO;
2554 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2555 PM8001_IO_DBG(pm8001_ha,
2556 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2557 ts->resp = SAS_TASK_COMPLETE;
2558 ts->stat = SAS_OPEN_TO;
2560 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2561 PM8001_IO_DBG(pm8001_ha,
2562 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2563 ts->resp = SAS_TASK_COMPLETE;
2564 ts->stat = SAS_OPEN_TO;
2566 case IO_XFER_ERROR_OFFSET_MISMATCH:
2567 PM8001_IO_DBG(pm8001_ha,
2568 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2569 ts->resp = SAS_TASK_COMPLETE;
2570 ts->stat = SAS_OPEN_TO;
2572 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2573 PM8001_IO_DBG(pm8001_ha,
2574 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2575 ts->resp = SAS_TASK_COMPLETE;
2576 ts->stat = SAS_OPEN_TO;
2578 case IO_XFER_CMD_FRAME_ISSUED:
2579 PM8001_IO_DBG(pm8001_ha,
2580 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2582 case IO_XFER_PIO_SETUP_ERROR:
2583 PM8001_IO_DBG(pm8001_ha,
2584 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2585 ts->resp = SAS_TASK_COMPLETE;
2586 ts->stat = SAS_OPEN_TO;
2589 PM8001_IO_DBG(pm8001_ha,
2590 pm8001_printk("Unknown status 0x%x\n", event));
2591 /* not allowed case. Therefore, return failed status */
2592 ts->resp = SAS_TASK_COMPLETE;
2593 ts->stat = SAS_OPEN_TO;
2596 spin_lock_irq(&t->task_state_lock);
2597 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2598 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2599 t->task_state_flags |= SAS_TASK_STATE_DONE;
2600 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2601 spin_unlock_irq(&t->task_state_lock);
2602 PM8001_FAIL_DBG(pm8001_ha,
2603 pm8001_printk("task 0x%p done with io_status 0x%x"
2604 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2605 t, event, ts->resp, ts->stat));
2606 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2607 } else if (t->uldd_task) {
2608 spin_unlock_irq(&t->task_state_lock);
2609 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2611 spin_unlock_irq(&pm8001_ha->lock);
2613 spin_lock_irq(&pm8001_ha->lock);
2614 } else if (!t->uldd_task) {
2615 spin_unlock_irq(&t->task_state_lock);
2616 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2618 spin_unlock_irq(&pm8001_ha->lock);
2620 spin_lock_irq(&pm8001_ha->lock);
2624 /*See the comments for mpi_ssp_completion */
2626 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2630 struct pm8001_ccb_info *ccb;
2631 unsigned long flags;
2634 struct smp_completion_resp *psmpPayload;
2635 struct task_status_struct *ts;
2636 struct pm8001_device *pm8001_dev;
2638 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2639 status = le32_to_cpu(psmpPayload->status);
2640 tag = le32_to_cpu(psmpPayload->tag);
2642 ccb = &pm8001_ha->ccb_info[tag];
2643 param = le32_to_cpu(psmpPayload->param);
2645 ts = &t->task_status;
2646 pm8001_dev = ccb->device;
2648 PM8001_FAIL_DBG(pm8001_ha,
2649 pm8001_printk("smp IO status 0x%x\n", status));
2650 if (unlikely(!t || !t->lldd_task || !t->dev))
2655 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2656 ts->resp = SAS_TASK_COMPLETE;
2657 ts->stat = SAM_STAT_GOOD;
2659 pm8001_dev->running_req--;
2662 PM8001_IO_DBG(pm8001_ha,
2663 pm8001_printk("IO_ABORTED IOMB\n"));
2664 ts->resp = SAS_TASK_COMPLETE;
2665 ts->stat = SAS_ABORTED_TASK;
2667 pm8001_dev->running_req--;
2670 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2671 ts->resp = SAS_TASK_COMPLETE;
2672 ts->stat = SAS_DATA_OVERRUN;
2675 pm8001_dev->running_req--;
2678 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2679 ts->resp = SAS_TASK_COMPLETE;
2680 ts->stat = SAS_PHY_DOWN;
2682 case IO_ERROR_HW_TIMEOUT:
2683 PM8001_IO_DBG(pm8001_ha,
2684 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2685 ts->resp = SAS_TASK_COMPLETE;
2686 ts->stat = SAM_STAT_BUSY;
2688 case IO_XFER_ERROR_BREAK:
2689 PM8001_IO_DBG(pm8001_ha,
2690 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2691 ts->resp = SAS_TASK_COMPLETE;
2692 ts->stat = SAM_STAT_BUSY;
2694 case IO_XFER_ERROR_PHY_NOT_READY:
2695 PM8001_IO_DBG(pm8001_ha,
2696 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2697 ts->resp = SAS_TASK_COMPLETE;
2698 ts->stat = SAM_STAT_BUSY;
2700 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2701 PM8001_IO_DBG(pm8001_ha,
2702 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2703 ts->resp = SAS_TASK_COMPLETE;
2704 ts->stat = SAS_OPEN_REJECT;
2705 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2707 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2708 PM8001_IO_DBG(pm8001_ha,
2709 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2710 ts->resp = SAS_TASK_COMPLETE;
2711 ts->stat = SAS_OPEN_REJECT;
2712 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2714 case IO_OPEN_CNX_ERROR_BREAK:
2715 PM8001_IO_DBG(pm8001_ha,
2716 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2717 ts->resp = SAS_TASK_COMPLETE;
2718 ts->stat = SAS_OPEN_REJECT;
2719 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2721 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2722 PM8001_IO_DBG(pm8001_ha,
2723 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2724 ts->resp = SAS_TASK_COMPLETE;
2725 ts->stat = SAS_OPEN_REJECT;
2726 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2727 pm8001_handle_event(pm8001_ha,
2729 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2731 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2732 PM8001_IO_DBG(pm8001_ha,
2733 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2734 ts->resp = SAS_TASK_COMPLETE;
2735 ts->stat = SAS_OPEN_REJECT;
2736 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2738 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2739 PM8001_IO_DBG(pm8001_ha,
2740 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2741 "NOT_SUPPORTED\n"));
2742 ts->resp = SAS_TASK_COMPLETE;
2743 ts->stat = SAS_OPEN_REJECT;
2744 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2746 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2747 PM8001_IO_DBG(pm8001_ha,
2748 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2749 ts->resp = SAS_TASK_COMPLETE;
2750 ts->stat = SAS_OPEN_REJECT;
2751 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2753 case IO_XFER_ERROR_RX_FRAME:
2754 PM8001_IO_DBG(pm8001_ha,
2755 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2756 ts->resp = SAS_TASK_COMPLETE;
2757 ts->stat = SAS_DEV_NO_RESPONSE;
2759 case IO_XFER_OPEN_RETRY_TIMEOUT:
2760 PM8001_IO_DBG(pm8001_ha,
2761 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2762 ts->resp = SAS_TASK_COMPLETE;
2763 ts->stat = SAS_OPEN_REJECT;
2764 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2766 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2767 PM8001_IO_DBG(pm8001_ha,
2768 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2769 ts->resp = SAS_TASK_COMPLETE;
2770 ts->stat = SAS_QUEUE_FULL;
2772 case IO_PORT_IN_RESET:
2773 PM8001_IO_DBG(pm8001_ha,
2774 pm8001_printk("IO_PORT_IN_RESET\n"));
2775 ts->resp = SAS_TASK_COMPLETE;
2776 ts->stat = SAS_OPEN_REJECT;
2777 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2779 case IO_DS_NON_OPERATIONAL:
2780 PM8001_IO_DBG(pm8001_ha,
2781 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2782 ts->resp = SAS_TASK_COMPLETE;
2783 ts->stat = SAS_DEV_NO_RESPONSE;
2785 case IO_DS_IN_RECOVERY:
2786 PM8001_IO_DBG(pm8001_ha,
2787 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2788 ts->resp = SAS_TASK_COMPLETE;
2789 ts->stat = SAS_OPEN_REJECT;
2790 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2792 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2793 PM8001_IO_DBG(pm8001_ha,
2794 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2795 ts->resp = SAS_TASK_COMPLETE;
2796 ts->stat = SAS_OPEN_REJECT;
2797 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2800 PM8001_IO_DBG(pm8001_ha,
2801 pm8001_printk("Unknown status 0x%x\n", status));
2802 ts->resp = SAS_TASK_COMPLETE;
2803 ts->stat = SAS_DEV_NO_RESPONSE;
2804 /* not allowed case. Therefore, return failed status */
2807 spin_lock_irqsave(&t->task_state_lock, flags);
2808 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2809 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2810 t->task_state_flags |= SAS_TASK_STATE_DONE;
2811 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2812 spin_unlock_irqrestore(&t->task_state_lock, flags);
2813 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2814 " io_status 0x%x resp 0x%x "
2815 "stat 0x%x but aborted by upper layer!\n",
2816 t, status, ts->resp, ts->stat));
2817 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2819 spin_unlock_irqrestore(&t->task_state_lock, flags);
2820 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2821 mb();/* in order to force CPU ordering */
2827 mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2829 struct set_dev_state_resp *pPayload =
2830 (struct set_dev_state_resp *)(piomb + 4);
2831 u32 tag = le32_to_cpu(pPayload->tag);
2832 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2833 struct pm8001_device *pm8001_dev = ccb->device;
2834 u32 status = le32_to_cpu(pPayload->status);
2835 u32 device_id = le32_to_cpu(pPayload->device_id);
2836 u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
2837 u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
2838 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
2839 "from 0x%x to 0x%x status = 0x%x!\n",
2840 device_id, pds, nds, status));
2841 complete(pm8001_dev->setds_completion);
2843 ccb->ccb_tag = 0xFFFFFFFF;
2844 pm8001_ccb_free(pm8001_ha, tag);
2848 mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2850 struct get_nvm_data_resp *pPayload =
2851 (struct get_nvm_data_resp *)(piomb + 4);
2852 u32 tag = le32_to_cpu(pPayload->tag);
2853 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2854 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2855 complete(pm8001_ha->nvmd_completion);
2856 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
2857 if ((dlen_status & NVMD_STAT) != 0) {
2858 PM8001_FAIL_DBG(pm8001_ha,
2859 pm8001_printk("Set nvm data error!\n"));
2863 ccb->ccb_tag = 0xFFFFFFFF;
2864 pm8001_ccb_free(pm8001_ha, tag);
2868 mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2870 struct fw_control_ex *fw_control_context;
2871 struct get_nvm_data_resp *pPayload =
2872 (struct get_nvm_data_resp *)(piomb + 4);
2873 u32 tag = le32_to_cpu(pPayload->tag);
2874 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2875 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2876 u32 ir_tds_bn_dps_das_nvm =
2877 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
2878 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
2879 fw_control_context = ccb->fw_control_context;
2881 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
2882 if ((dlen_status & NVMD_STAT) != 0) {
2883 PM8001_FAIL_DBG(pm8001_ha,
2884 pm8001_printk("Get nvm data error!\n"));
2885 complete(pm8001_ha->nvmd_completion);
2889 if (ir_tds_bn_dps_das_nvm & IPMode) {
2890 /* indirect mode - IR bit set */
2891 PM8001_MSG_DBG(pm8001_ha,
2892 pm8001_printk("Get NVMD success, IR=1\n"));
2893 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
2894 if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
2895 memcpy(pm8001_ha->sas_addr,
2896 ((u8 *)virt_addr + 4),
2898 PM8001_MSG_DBG(pm8001_ha,
2899 pm8001_printk("Get SAS address"
2900 " from VPD successfully!\n"));
2902 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
2903 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
2904 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
2906 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
2907 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
2910 /* Should not be happened*/
2911 PM8001_MSG_DBG(pm8001_ha,
2912 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
2913 ir_tds_bn_dps_das_nvm));
2915 } else /* direct mode */{
2916 PM8001_MSG_DBG(pm8001_ha,
2917 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
2918 (dlen_status & NVMD_LEN) >> 24));
2920 memcpy(fw_control_context->usrAddr,
2921 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
2922 fw_control_context->len);
2923 complete(pm8001_ha->nvmd_completion);
2925 ccb->ccb_tag = 0xFFFFFFFF;
2926 pm8001_ccb_free(pm8001_ha, tag);
2929 static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
2931 struct local_phy_ctl_resp *pPayload =
2932 (struct local_phy_ctl_resp *)(piomb + 4);
2933 u32 status = le32_to_cpu(pPayload->status);
2934 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
2935 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
2937 PM8001_MSG_DBG(pm8001_ha,
2938 pm8001_printk("%x phy execute %x phy op failed!\n",
2941 PM8001_MSG_DBG(pm8001_ha,
2942 pm8001_printk("%x phy execute %x phy op success!\n",
2948 * pm8001_bytes_dmaed - one of the interface function communication with libsas
2949 * @pm8001_ha: our hba card information
2950 * @i: which phy that received the event.
2952 * when HBA driver received the identify done event or initiate FIS received
2953 * event(for SATA), it will invoke this function to notify the sas layer that
2954 * the sas toplogy has formed, please discover the the whole sas domain,
2955 * while receive a broadcast(change) primitive just tell the sas
2956 * layer to discover the changed domain rather than the whole domain.
2958 static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
2960 struct pm8001_phy *phy = &pm8001_ha->phy[i];
2961 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2962 struct sas_ha_struct *sas_ha;
2963 if (!phy->phy_attached)
2966 sas_ha = pm8001_ha->sas;
2968 struct sas_phy *sphy = sas_phy->phy;
2969 sphy->negotiated_linkrate = sas_phy->linkrate;
2970 sphy->minimum_linkrate = phy->minimum_linkrate;
2971 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2972 sphy->maximum_linkrate = phy->maximum_linkrate;
2973 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
2976 if (phy->phy_type & PORT_TYPE_SAS) {
2977 struct sas_identify_frame *id;
2978 id = (struct sas_identify_frame *)phy->frame_rcvd;
2979 id->dev_type = phy->identify.device_type;
2980 id->initiator_bits = SAS_PROTOCOL_ALL;
2981 id->target_bits = phy->identify.target_port_protocols;
2982 } else if (phy->phy_type & PORT_TYPE_SATA) {
2985 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
2987 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
2988 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
2991 /* Get the link rate speed */
2992 static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
2994 struct sas_phy *sas_phy = phy->sas_phy.phy;
2996 switch (link_rate) {
2998 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
2999 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3002 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3003 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3006 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3007 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3010 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3011 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3012 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3013 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3014 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3018 * asd_get_attached_sas_addr -- extract/generate attached SAS address
3019 * @phy: pointer to asd_phy
3020 * @sas_addr: pointer to buffer where the SAS address is to be written
3022 * This function extracts the SAS address from an IDENTIFY frame
3023 * received. If OOB is SATA, then a SAS address is generated from the
3026 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3029 static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3032 if (phy->sas_phy.frame_rcvd[0] == 0x34
3033 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3034 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3035 /* FIS device-to-host */
3036 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3037 addr += phy->sas_phy.id;
3038 *(__be64 *)sas_addr = cpu_to_be64(addr);
3040 struct sas_identify_frame *idframe =
3041 (void *) phy->sas_phy.frame_rcvd;
3042 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3047 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3048 * @pm8001_ha: our hba card information
3049 * @Qnum: the outbound queue message number.
3050 * @SEA: source of event to ack
3051 * @port_id: port id.
3053 * @param0: parameter 0.
3054 * @param1: parameter 1.
3056 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3057 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3059 struct hw_event_ack_req payload;
3060 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3062 struct inbound_queue_table *circularQ;
3064 memset((u8 *)&payload, 0, sizeof(payload));
3065 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3066 payload.tag = cpu_to_le32(1);
3067 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3068 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3069 payload.param0 = cpu_to_le32(param0);
3070 payload.param1 = cpu_to_le32(param1);
3071 mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
3074 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3075 u32 phyId, u32 phy_op);
3078 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3079 * @pm8001_ha: our hba card information
3080 * @piomb: IO message buffer
3083 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3085 struct hw_event_resp *pPayload =
3086 (struct hw_event_resp *)(piomb + 4);
3087 u32 lr_evt_status_phyid_portid =
3088 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3090 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3091 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3093 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3094 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3095 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3096 struct pm8001_port *port = &pm8001_ha->port[port_id];
3097 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3098 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3099 unsigned long flags;
3100 u8 deviceType = pPayload->sas_identify.dev_type;
3101 port->port_state = portstate;
3102 PM8001_MSG_DBG(pm8001_ha,
3103 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3106 switch (deviceType) {
3107 case SAS_PHY_UNUSED:
3108 PM8001_MSG_DBG(pm8001_ha,
3109 pm8001_printk("device type no device.\n"));
3111 case SAS_END_DEVICE:
3112 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3113 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3114 PHY_NOTIFY_ENABLE_SPINUP);
3115 port->port_attached = 1;
3116 get_lrate_mode(phy, link_rate);
3118 case SAS_EDGE_EXPANDER_DEVICE:
3119 PM8001_MSG_DBG(pm8001_ha,
3120 pm8001_printk("expander device.\n"));
3121 port->port_attached = 1;
3122 get_lrate_mode(phy, link_rate);
3124 case SAS_FANOUT_EXPANDER_DEVICE:
3125 PM8001_MSG_DBG(pm8001_ha,
3126 pm8001_printk("fanout expander device.\n"));
3127 port->port_attached = 1;
3128 get_lrate_mode(phy, link_rate);
3131 PM8001_MSG_DBG(pm8001_ha,
3132 pm8001_printk("unknown device type(%x)\n", deviceType));
3135 phy->phy_type |= PORT_TYPE_SAS;
3136 phy->identify.device_type = deviceType;
3137 phy->phy_attached = 1;
3138 if (phy->identify.device_type == SAS_END_DEVICE)
3139 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3140 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3141 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3142 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3143 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3144 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3145 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3146 sizeof(struct sas_identify_frame)-4);
3147 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3148 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3149 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3150 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3151 mdelay(200);/*delay a moment to wait disk to spinup*/
3152 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3156 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3157 * @pm8001_ha: our hba card information
3158 * @piomb: IO message buffer
3161 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3163 struct hw_event_resp *pPayload =
3164 (struct hw_event_resp *)(piomb + 4);
3165 u32 lr_evt_status_phyid_portid =
3166 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3168 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3169 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3171 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3172 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3173 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3174 struct pm8001_port *port = &pm8001_ha->port[port_id];
3175 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3176 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3177 unsigned long flags;
3178 PM8001_MSG_DBG(pm8001_ha,
3179 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3180 " phy id = %d\n", port_id, phy_id));
3181 port->port_state = portstate;
3182 port->port_attached = 1;
3183 get_lrate_mode(phy, link_rate);
3184 phy->phy_type |= PORT_TYPE_SATA;
3185 phy->phy_attached = 1;
3186 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3187 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3188 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3189 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3190 sizeof(struct dev_to_host_fis));
3191 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3192 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3193 phy->identify.device_type = SATA_DEV;
3194 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3195 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3196 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3200 * hw_event_phy_down -we should notify the libsas the phy is down.
3201 * @pm8001_ha: our hba card information
3202 * @piomb: IO message buffer
3205 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3207 struct hw_event_resp *pPayload =
3208 (struct hw_event_resp *)(piomb + 4);
3209 u32 lr_evt_status_phyid_portid =
3210 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3211 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3213 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3214 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3215 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3216 struct pm8001_port *port = &pm8001_ha->port[port_id];
3217 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3218 port->port_state = portstate;
3220 phy->identify.device_type = 0;
3221 phy->phy_attached = 0;
3222 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3223 switch (portstate) {
3227 PM8001_MSG_DBG(pm8001_ha,
3228 pm8001_printk(" PortInvalid portID %d\n", port_id));
3229 PM8001_MSG_DBG(pm8001_ha,
3230 pm8001_printk(" Last phy Down and port invalid\n"));
3231 port->port_attached = 0;
3232 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3233 port_id, phy_id, 0, 0);
3236 PM8001_MSG_DBG(pm8001_ha,
3237 pm8001_printk(" Port In Reset portID %d\n", port_id));
3239 case PORT_NOT_ESTABLISHED:
3240 PM8001_MSG_DBG(pm8001_ha,
3241 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3242 port->port_attached = 0;
3245 PM8001_MSG_DBG(pm8001_ha,
3246 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3247 PM8001_MSG_DBG(pm8001_ha,
3248 pm8001_printk(" Last phy Down and port invalid\n"));
3249 port->port_attached = 0;
3250 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3251 port_id, phy_id, 0, 0);
3254 port->port_attached = 0;
3255 PM8001_MSG_DBG(pm8001_ha,
3256 pm8001_printk(" phy Down and(default) = %x\n",
3264 * mpi_reg_resp -process register device ID response.
3265 * @pm8001_ha: our hba card information
3266 * @piomb: IO message buffer
3268 * when sas layer find a device it will notify LLDD, then the driver register
3269 * the domain device to FW, this event is the return device ID which the FW
3270 * has assigned, from now,inter-communication with FW is no longer using the
3271 * SAS address, use device ID which FW assigned.
3273 static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3278 struct pm8001_ccb_info *ccb;
3279 struct pm8001_device *pm8001_dev;
3280 struct dev_reg_resp *registerRespPayload =
3281 (struct dev_reg_resp *)(piomb + 4);
3283 htag = le32_to_cpu(registerRespPayload->tag);
3284 ccb = &pm8001_ha->ccb_info[htag];
3285 pm8001_dev = ccb->device;
3286 status = le32_to_cpu(registerRespPayload->status);
3287 device_id = le32_to_cpu(registerRespPayload->device_id);
3288 PM8001_MSG_DBG(pm8001_ha,
3289 pm8001_printk(" register device is status = %d\n", status));
3291 case DEVREG_SUCCESS:
3292 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3293 pm8001_dev->device_id = device_id;
3295 case DEVREG_FAILURE_OUT_OF_RESOURCE:
3296 PM8001_MSG_DBG(pm8001_ha,
3297 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3299 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3300 PM8001_MSG_DBG(pm8001_ha,
3301 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3303 case DEVREG_FAILURE_INVALID_PHY_ID:
3304 PM8001_MSG_DBG(pm8001_ha,
3305 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3307 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3308 PM8001_MSG_DBG(pm8001_ha,
3309 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3311 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3312 PM8001_MSG_DBG(pm8001_ha,
3313 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3315 case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3316 PM8001_MSG_DBG(pm8001_ha,
3317 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3319 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3320 PM8001_MSG_DBG(pm8001_ha,
3321 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3324 PM8001_MSG_DBG(pm8001_ha,
3325 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3328 complete(pm8001_dev->dcompletion);
3330 ccb->ccb_tag = 0xFFFFFFFF;
3331 pm8001_ccb_free(pm8001_ha, htag);
3335 static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3339 struct dev_reg_resp *registerRespPayload =
3340 (struct dev_reg_resp *)(piomb + 4);
3342 status = le32_to_cpu(registerRespPayload->status);
3343 device_id = le32_to_cpu(registerRespPayload->device_id);
3345 PM8001_MSG_DBG(pm8001_ha,
3346 pm8001_printk(" deregister device failed ,status = %x"
3347 ", device_id = %x\n", status, device_id));
3352 mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3355 struct fw_control_ex fw_control_context;
3356 struct fw_flash_Update_resp *ppayload =
3357 (struct fw_flash_Update_resp *)(piomb + 4);
3358 u32 tag = ppayload->tag;
3359 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3360 status = le32_to_cpu(ppayload->status);
3361 memcpy(&fw_control_context,
3362 ccb->fw_control_context,
3363 sizeof(fw_control_context));
3365 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3366 PM8001_MSG_DBG(pm8001_ha,
3367 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3369 case FLASH_UPDATE_IN_PROGRESS:
3370 PM8001_MSG_DBG(pm8001_ha,
3371 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3373 case FLASH_UPDATE_HDR_ERR:
3374 PM8001_MSG_DBG(pm8001_ha,
3375 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3377 case FLASH_UPDATE_OFFSET_ERR:
3378 PM8001_MSG_DBG(pm8001_ha,
3379 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3381 case FLASH_UPDATE_CRC_ERR:
3382 PM8001_MSG_DBG(pm8001_ha,
3383 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3385 case FLASH_UPDATE_LENGTH_ERR:
3386 PM8001_MSG_DBG(pm8001_ha,
3387 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3389 case FLASH_UPDATE_HW_ERR:
3390 PM8001_MSG_DBG(pm8001_ha,
3391 pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3393 case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3394 PM8001_MSG_DBG(pm8001_ha,
3395 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3397 case FLASH_UPDATE_DISABLED:
3398 PM8001_MSG_DBG(pm8001_ha,
3399 pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3402 PM8001_MSG_DBG(pm8001_ha,
3403 pm8001_printk("No matched status = %d\n", status));
3406 ccb->fw_control_context->fw_control->retcode = status;
3407 pci_free_consistent(pm8001_ha->pdev,
3408 fw_control_context.len,
3409 fw_control_context.virtAddr,
3410 fw_control_context.phys_addr);
3411 complete(pm8001_ha->nvmd_completion);
3413 ccb->ccb_tag = 0xFFFFFFFF;
3414 pm8001_ccb_free(pm8001_ha, tag);
3419 mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3423 struct general_event_resp *pPayload =
3424 (struct general_event_resp *)(piomb + 4);
3425 status = le32_to_cpu(pPayload->status);
3426 PM8001_MSG_DBG(pm8001_ha,
3427 pm8001_printk(" status = 0x%x\n", status));
3428 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3429 PM8001_MSG_DBG(pm8001_ha,
3430 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3431 pPayload->inb_IOMB_payload[i]));
3436 mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3439 struct pm8001_ccb_info *ccb;
3440 unsigned long flags;
3443 struct task_status_struct *ts;
3445 struct task_abort_resp *pPayload =
3446 (struct task_abort_resp *)(piomb + 4);
3448 status = le32_to_cpu(pPayload->status);
3449 tag = le32_to_cpu(pPayload->tag);
3450 scp = le32_to_cpu(pPayload->scp);
3451 ccb = &pm8001_ha->ccb_info[tag];
3453 PM8001_IO_DBG(pm8001_ha,
3454 pm8001_printk(" status = 0x%x\n", status));
3457 ts = &t->task_status;
3459 PM8001_FAIL_DBG(pm8001_ha,
3460 pm8001_printk("task abort failed status 0x%x ,"
3461 "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3464 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3465 ts->resp = SAS_TASK_COMPLETE;
3466 ts->stat = SAM_STAT_GOOD;
3469 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3470 ts->resp = TMF_RESP_FUNC_FAILED;
3473 spin_lock_irqsave(&t->task_state_lock, flags);
3474 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3475 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3476 t->task_state_flags |= SAS_TASK_STATE_DONE;
3477 spin_unlock_irqrestore(&t->task_state_lock, flags);
3478 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3485 * mpi_hw_event -The hw event has come.
3486 * @pm8001_ha: our hba card information
3487 * @piomb: IO message buffer
3489 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3491 unsigned long flags;
3492 struct hw_event_resp *pPayload =
3493 (struct hw_event_resp *)(piomb + 4);
3494 u32 lr_evt_status_phyid_portid =
3495 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3496 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3498 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3500 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3502 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3503 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3504 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3505 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3506 PM8001_MSG_DBG(pm8001_ha,
3507 pm8001_printk("outbound queue HW event & event type : "));
3508 switch (eventType) {
3509 case HW_EVENT_PHY_START_STATUS:
3510 PM8001_MSG_DBG(pm8001_ha,
3511 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3512 " status = %x\n", status));
3515 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3516 complete(phy->enable_completion);
3519 case HW_EVENT_SAS_PHY_UP:
3520 PM8001_MSG_DBG(pm8001_ha,
3521 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3522 hw_event_sas_phy_up(pm8001_ha, piomb);
3524 case HW_EVENT_SATA_PHY_UP:
3525 PM8001_MSG_DBG(pm8001_ha,
3526 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3527 hw_event_sata_phy_up(pm8001_ha, piomb);
3529 case HW_EVENT_PHY_STOP_STATUS:
3530 PM8001_MSG_DBG(pm8001_ha,
3531 pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3532 "status = %x\n", status));
3536 case HW_EVENT_SATA_SPINUP_HOLD:
3537 PM8001_MSG_DBG(pm8001_ha,
3538 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3539 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3541 case HW_EVENT_PHY_DOWN:
3542 PM8001_MSG_DBG(pm8001_ha,
3543 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3544 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3545 phy->phy_attached = 0;
3547 hw_event_phy_down(pm8001_ha, piomb);
3549 case HW_EVENT_PORT_INVALID:
3550 PM8001_MSG_DBG(pm8001_ha,
3551 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3552 sas_phy_disconnected(sas_phy);
3553 phy->phy_attached = 0;
3554 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3556 /* the broadcast change primitive received, tell the LIBSAS this event
3557 to revalidate the sas domain*/
3558 case HW_EVENT_BROADCAST_CHANGE:
3559 PM8001_MSG_DBG(pm8001_ha,
3560 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3561 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3562 port_id, phy_id, 1, 0);
3563 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3564 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3565 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3566 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3568 case HW_EVENT_PHY_ERROR:
3569 PM8001_MSG_DBG(pm8001_ha,
3570 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3571 sas_phy_disconnected(&phy->sas_phy);
3572 phy->phy_attached = 0;
3573 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3575 case HW_EVENT_BROADCAST_EXP:
3576 PM8001_MSG_DBG(pm8001_ha,
3577 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3578 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3579 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3580 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3581 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3583 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3584 PM8001_MSG_DBG(pm8001_ha,
3585 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3586 pm8001_hw_event_ack_req(pm8001_ha, 0,
3587 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3588 sas_phy_disconnected(sas_phy);
3589 phy->phy_attached = 0;
3590 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3592 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3593 PM8001_MSG_DBG(pm8001_ha,
3594 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3595 pm8001_hw_event_ack_req(pm8001_ha, 0,
3596 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3597 port_id, phy_id, 0, 0);
3598 sas_phy_disconnected(sas_phy);
3599 phy->phy_attached = 0;
3600 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3602 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3603 PM8001_MSG_DBG(pm8001_ha,
3604 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3605 pm8001_hw_event_ack_req(pm8001_ha, 0,
3606 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3607 port_id, phy_id, 0, 0);
3608 sas_phy_disconnected(sas_phy);
3609 phy->phy_attached = 0;
3610 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3612 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3613 PM8001_MSG_DBG(pm8001_ha,
3614 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3615 pm8001_hw_event_ack_req(pm8001_ha, 0,
3616 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3617 port_id, phy_id, 0, 0);
3618 sas_phy_disconnected(sas_phy);
3619 phy->phy_attached = 0;
3620 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3622 case HW_EVENT_MALFUNCTION:
3623 PM8001_MSG_DBG(pm8001_ha,
3624 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3626 case HW_EVENT_BROADCAST_SES:
3627 PM8001_MSG_DBG(pm8001_ha,
3628 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3629 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3630 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3631 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3632 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3634 case HW_EVENT_INBOUND_CRC_ERROR:
3635 PM8001_MSG_DBG(pm8001_ha,
3636 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3637 pm8001_hw_event_ack_req(pm8001_ha, 0,
3638 HW_EVENT_INBOUND_CRC_ERROR,
3639 port_id, phy_id, 0, 0);
3641 case HW_EVENT_HARD_RESET_RECEIVED:
3642 PM8001_MSG_DBG(pm8001_ha,
3643 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3644 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3646 case HW_EVENT_ID_FRAME_TIMEOUT:
3647 PM8001_MSG_DBG(pm8001_ha,
3648 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3649 sas_phy_disconnected(sas_phy);
3650 phy->phy_attached = 0;
3651 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3653 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3654 PM8001_MSG_DBG(pm8001_ha,
3655 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3656 pm8001_hw_event_ack_req(pm8001_ha, 0,
3657 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3658 port_id, phy_id, 0, 0);
3659 sas_phy_disconnected(sas_phy);
3660 phy->phy_attached = 0;
3661 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3663 case HW_EVENT_PORT_RESET_TIMER_TMO:
3664 PM8001_MSG_DBG(pm8001_ha,
3665 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3666 sas_phy_disconnected(sas_phy);
3667 phy->phy_attached = 0;
3668 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3670 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3671 PM8001_MSG_DBG(pm8001_ha,
3672 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3673 sas_phy_disconnected(sas_phy);
3674 phy->phy_attached = 0;
3675 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3677 case HW_EVENT_PORT_RECOVER:
3678 PM8001_MSG_DBG(pm8001_ha,
3679 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3681 case HW_EVENT_PORT_RESET_COMPLETE:
3682 PM8001_MSG_DBG(pm8001_ha,
3683 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3685 case EVENT_BROADCAST_ASYNCH_EVENT:
3686 PM8001_MSG_DBG(pm8001_ha,
3687 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3690 PM8001_MSG_DBG(pm8001_ha,
3691 pm8001_printk("Unknown event type = %x\n", eventType));
3698 * process_one_iomb - process one outbound Queue memory block
3699 * @pm8001_ha: our hba card information
3700 * @piomb: IO message buffer
3702 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3704 u32 pHeader = (u32)*(u32 *)piomb;
3705 u8 opc = (u8)(pHeader & 0xFFF);
3707 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
3711 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3713 case OPC_OUB_HW_EVENT:
3714 PM8001_MSG_DBG(pm8001_ha,
3715 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3716 mpi_hw_event(pm8001_ha, piomb);
3718 case OPC_OUB_SSP_COMP:
3719 PM8001_MSG_DBG(pm8001_ha,
3720 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3721 mpi_ssp_completion(pm8001_ha, piomb);
3723 case OPC_OUB_SMP_COMP:
3724 PM8001_MSG_DBG(pm8001_ha,
3725 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3726 mpi_smp_completion(pm8001_ha, piomb);
3728 case OPC_OUB_LOCAL_PHY_CNTRL:
3729 PM8001_MSG_DBG(pm8001_ha,
3730 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3731 mpi_local_phy_ctl(pm8001_ha, piomb);
3733 case OPC_OUB_DEV_REGIST:
3734 PM8001_MSG_DBG(pm8001_ha,
3735 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3736 mpi_reg_resp(pm8001_ha, piomb);
3738 case OPC_OUB_DEREG_DEV:
3739 PM8001_MSG_DBG(pm8001_ha,
3740 pm8001_printk("unresgister the deviece\n"));
3741 mpi_dereg_resp(pm8001_ha, piomb);
3743 case OPC_OUB_GET_DEV_HANDLE:
3744 PM8001_MSG_DBG(pm8001_ha,
3745 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3747 case OPC_OUB_SATA_COMP:
3748 PM8001_MSG_DBG(pm8001_ha,
3749 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3750 mpi_sata_completion(pm8001_ha, piomb);
3752 case OPC_OUB_SATA_EVENT:
3753 PM8001_MSG_DBG(pm8001_ha,
3754 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3755 mpi_sata_event(pm8001_ha, piomb);
3757 case OPC_OUB_SSP_EVENT:
3758 PM8001_MSG_DBG(pm8001_ha,
3759 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3760 mpi_ssp_event(pm8001_ha, piomb);
3762 case OPC_OUB_DEV_HANDLE_ARRIV:
3763 PM8001_MSG_DBG(pm8001_ha,
3764 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3765 /*This is for target*/
3767 case OPC_OUB_SSP_RECV_EVENT:
3768 PM8001_MSG_DBG(pm8001_ha,
3769 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3770 /*This is for target*/
3772 case OPC_OUB_DEV_INFO:
3773 PM8001_MSG_DBG(pm8001_ha,
3774 pm8001_printk("OPC_OUB_DEV_INFO\n"));
3776 case OPC_OUB_FW_FLASH_UPDATE:
3777 PM8001_MSG_DBG(pm8001_ha,
3778 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3779 mpi_fw_flash_update_resp(pm8001_ha, piomb);
3781 case OPC_OUB_GPIO_RESPONSE:
3782 PM8001_MSG_DBG(pm8001_ha,
3783 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3785 case OPC_OUB_GPIO_EVENT:
3786 PM8001_MSG_DBG(pm8001_ha,
3787 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3789 case OPC_OUB_GENERAL_EVENT:
3790 PM8001_MSG_DBG(pm8001_ha,
3791 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3792 mpi_general_event(pm8001_ha, piomb);
3794 case OPC_OUB_SSP_ABORT_RSP:
3795 PM8001_MSG_DBG(pm8001_ha,
3796 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3797 mpi_task_abort_resp(pm8001_ha, piomb);
3799 case OPC_OUB_SATA_ABORT_RSP:
3800 PM8001_MSG_DBG(pm8001_ha,
3801 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3802 mpi_task_abort_resp(pm8001_ha, piomb);
3804 case OPC_OUB_SAS_DIAG_MODE_START_END:
3805 PM8001_MSG_DBG(pm8001_ha,
3806 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3808 case OPC_OUB_SAS_DIAG_EXECUTE:
3809 PM8001_MSG_DBG(pm8001_ha,
3810 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3812 case OPC_OUB_GET_TIME_STAMP:
3813 PM8001_MSG_DBG(pm8001_ha,
3814 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3816 case OPC_OUB_SAS_HW_EVENT_ACK:
3817 PM8001_MSG_DBG(pm8001_ha,
3818 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3820 case OPC_OUB_PORT_CONTROL:
3821 PM8001_MSG_DBG(pm8001_ha,
3822 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3824 case OPC_OUB_SMP_ABORT_RSP:
3825 PM8001_MSG_DBG(pm8001_ha,
3826 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3827 mpi_task_abort_resp(pm8001_ha, piomb);
3829 case OPC_OUB_GET_NVMD_DATA:
3830 PM8001_MSG_DBG(pm8001_ha,
3831 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3832 mpi_get_nvmd_resp(pm8001_ha, piomb);
3834 case OPC_OUB_SET_NVMD_DATA:
3835 PM8001_MSG_DBG(pm8001_ha,
3836 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3837 mpi_set_nvmd_resp(pm8001_ha, piomb);
3839 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3840 PM8001_MSG_DBG(pm8001_ha,
3841 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3843 case OPC_OUB_SET_DEVICE_STATE:
3844 PM8001_MSG_DBG(pm8001_ha,
3845 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3846 mpi_set_dev_state_resp(pm8001_ha, piomb);
3848 case OPC_OUB_GET_DEVICE_STATE:
3849 PM8001_MSG_DBG(pm8001_ha,
3850 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3852 case OPC_OUB_SET_DEV_INFO:
3853 PM8001_MSG_DBG(pm8001_ha,
3854 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3856 case OPC_OUB_SAS_RE_INITIALIZE:
3857 PM8001_MSG_DBG(pm8001_ha,
3858 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
3861 PM8001_MSG_DBG(pm8001_ha,
3862 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
3868 static int process_oq(struct pm8001_hba_info *pm8001_ha)
3870 struct outbound_queue_table *circularQ;
3872 u8 uninitialized_var(bc);
3873 u32 ret = MPI_IO_STATUS_FAIL;
3874 unsigned long flags;
3876 spin_lock_irqsave(&pm8001_ha->lock, flags);
3877 circularQ = &pm8001_ha->outbnd_q_tbl[0];
3879 ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3880 if (MPI_IO_STATUS_SUCCESS == ret) {
3881 /* process the outbound message */
3882 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3883 /* free the message from the outbound circular buffer */
3884 mpi_msg_free_set(pm8001_ha, pMsg1, circularQ, bc);
3886 if (MPI_IO_STATUS_BUSY == ret) {
3887 /* Update the producer index from SPC */
3888 circularQ->producer_index =
3889 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3890 if (le32_to_cpu(circularQ->producer_index) ==
3891 circularQ->consumer_idx)
3896 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3900 /* PCI_DMA_... to our direction translation. */
3901 static const u8 data_dir_flags[] = {
3902 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3903 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3904 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3905 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3908 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
3911 struct scatterlist *sg;
3912 struct pm8001_prd *buf_prd = prd;
3914 for_each_sg(scatter, sg, nr, i) {
3915 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
3916 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
3917 buf_prd->im_len.e = 0;
3922 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
3924 psmp_cmd->tag = hTag;
3925 psmp_cmd->device_id = cpu_to_le32(deviceID);
3926 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3930 * pm8001_chip_smp_req - send a SMP task to FW
3931 * @pm8001_ha: our hba card information.
3932 * @ccb: the ccb information this request used.
3934 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3935 struct pm8001_ccb_info *ccb)
3938 struct sas_task *task = ccb->task;
3939 struct domain_device *dev = task->dev;
3940 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3941 struct scatterlist *sg_req, *sg_resp;
3942 u32 req_len, resp_len;
3943 struct smp_req smp_cmd;
3945 struct inbound_queue_table *circularQ;
3947 memset(&smp_cmd, 0, sizeof(smp_cmd));
3949 * DMA-map SMP request, response buffers
3951 sg_req = &task->smp_task.smp_req;
3952 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3955 req_len = sg_dma_len(sg_req);
3957 sg_resp = &task->smp_task.smp_resp;
3958 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3963 resp_len = sg_dma_len(sg_resp);
3964 /* must be in dwords */
3965 if ((req_len & 0x3) || (resp_len & 0x3)) {
3970 opc = OPC_INB_SMP_REQUEST;
3971 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3972 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3973 smp_cmd.long_smp_req.long_req_addr =
3974 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3975 smp_cmd.long_smp_req.long_req_size =
3976 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3977 smp_cmd.long_smp_req.long_resp_addr =
3978 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
3979 smp_cmd.long_smp_req.long_resp_size =
3980 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3981 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
3982 mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd);
3986 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3987 PCI_DMA_FROMDEVICE);
3989 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3995 * pm8001_chip_ssp_io_req - send a SSP task to FW
3996 * @pm8001_ha: our hba card information.
3997 * @ccb: the ccb information this request used.
3999 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4000 struct pm8001_ccb_info *ccb)
4002 struct sas_task *task = ccb->task;
4003 struct domain_device *dev = task->dev;
4004 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4005 struct ssp_ini_io_start_req ssp_cmd;
4006 u32 tag = ccb->ccb_tag;
4009 struct inbound_queue_table *circularQ;
4010 u32 opc = OPC_INB_SSPINIIOSTART;
4011 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4012 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4014 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4015 SAS 1.1 compatible TLR*/
4016 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4017 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4018 ssp_cmd.tag = cpu_to_le32(tag);
4019 if (task->ssp_task.enable_first_burst)
4020 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4021 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4022 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4023 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
4024 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4026 /* fill in PRD (scatter/gather) table, if any */
4027 if (task->num_scatter > 1) {
4028 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4029 phys_addr = ccb->ccb_dma_handle +
4030 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4031 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4032 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4033 ssp_cmd.esgl = cpu_to_le32(1<<31);
4034 } else if (task->num_scatter == 1) {
4035 u64 dma_addr = sg_dma_address(task->scatter);
4036 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4037 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4038 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4040 } else if (task->num_scatter == 0) {
4041 ssp_cmd.addr_low = 0;
4042 ssp_cmd.addr_high = 0;
4043 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4046 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd);
4050 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4051 struct pm8001_ccb_info *ccb)
4053 struct sas_task *task = ccb->task;
4054 struct domain_device *dev = task->dev;
4055 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4056 u32 tag = ccb->ccb_tag;
4058 struct sata_start_req sata_cmd;
4059 u32 hdr_tag, ncg_tag = 0;
4063 struct inbound_queue_table *circularQ;
4064 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4065 memset(&sata_cmd, 0, sizeof(sata_cmd));
4066 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4067 if (task->data_dir == PCI_DMA_NONE) {
4068 ATAP = 0x04; /* no data*/
4069 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4070 } else if (likely(!task->ata_task.device_control_reg_update)) {
4071 if (task->ata_task.dma_xfer) {
4072 ATAP = 0x06; /* DMA */
4073 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4075 ATAP = 0x05; /* PIO*/
4076 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4078 if (task->ata_task.use_ncq &&
4079 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
4080 ATAP = 0x07; /* FPDMA */
4081 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4084 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
4086 dir = data_dir_flags[task->data_dir] << 8;
4087 sata_cmd.tag = cpu_to_le32(tag);
4088 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4089 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4090 sata_cmd.ncqtag_atap_dir_m =
4091 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4092 sata_cmd.sata_fis = task->ata_task.fis;
4093 if (likely(!task->ata_task.device_control_reg_update))
4094 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4095 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4096 /* fill in PRD (scatter/gather) table, if any */
4097 if (task->num_scatter > 1) {
4098 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4099 phys_addr = ccb->ccb_dma_handle +
4100 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4101 sata_cmd.addr_low = lower_32_bits(phys_addr);
4102 sata_cmd.addr_high = upper_32_bits(phys_addr);
4103 sata_cmd.esgl = cpu_to_le32(1 << 31);
4104 } else if (task->num_scatter == 1) {
4105 u64 dma_addr = sg_dma_address(task->scatter);
4106 sata_cmd.addr_low = lower_32_bits(dma_addr);
4107 sata_cmd.addr_high = upper_32_bits(dma_addr);
4108 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4110 } else if (task->num_scatter == 0) {
4111 sata_cmd.addr_low = 0;
4112 sata_cmd.addr_high = 0;
4113 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4116 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd);
4121 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4122 * @pm8001_ha: our hba card information.
4123 * @num: the inbound queue number
4124 * @phy_id: the phy id which we wanted to start up.
4127 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4129 struct phy_start_req payload;
4130 struct inbound_queue_table *circularQ;
4133 u32 opcode = OPC_INB_PHYSTART;
4134 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4135 memset(&payload, 0, sizeof(payload));
4136 payload.tag = cpu_to_le32(tag);
4138 ** [0:7] PHY Identifier
4139 ** [8:11] link rate 1.5G, 3G, 6G
4140 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4141 ** [14] 0b disable spin up hold; 1b enable spin up hold
4143 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4144 LINKMODE_AUTO | LINKRATE_15 |
4145 LINKRATE_30 | LINKRATE_60 | phy_id);
4146 payload.sas_identify.dev_type = SAS_END_DEV;
4147 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4148 memcpy(payload.sas_identify.sas_addr,
4149 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4150 payload.sas_identify.phy_id = phy_id;
4151 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
4156 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4157 * @pm8001_ha: our hba card information.
4158 * @num: the inbound queue number
4159 * @phy_id: the phy id which we wanted to start up.
4161 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4164 struct phy_stop_req payload;
4165 struct inbound_queue_table *circularQ;
4168 u32 opcode = OPC_INB_PHYSTOP;
4169 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4170 memset(&payload, 0, sizeof(payload));
4171 payload.tag = cpu_to_le32(tag);
4172 payload.phy_id = cpu_to_le32(phy_id);
4173 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
4178 * see comments on mpi_reg_resp.
4180 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4181 struct pm8001_device *pm8001_dev, u32 flag)
4183 struct reg_dev_req payload;
4185 u32 stp_sspsmp_sata = 0x4;
4186 struct inbound_queue_table *circularQ;
4187 u32 linkrate, phy_id;
4188 int rc, tag = 0xdeadbeef;
4189 struct pm8001_ccb_info *ccb;
4191 u16 firstBurstSize = 0;
4193 struct domain_device *dev = pm8001_dev->sas_device;
4194 struct domain_device *parent_dev = dev->parent;
4195 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4197 memset(&payload, 0, sizeof(payload));
4198 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4201 ccb = &pm8001_ha->ccb_info[tag];
4202 ccb->device = pm8001_dev;
4204 payload.tag = cpu_to_le32(tag);
4206 stp_sspsmp_sata = 0x02; /*direct attached sata */
4208 if (pm8001_dev->dev_type == SATA_DEV)
4209 stp_sspsmp_sata = 0x00; /* stp*/
4210 else if (pm8001_dev->dev_type == SAS_END_DEV ||
4211 pm8001_dev->dev_type == EDGE_DEV ||
4212 pm8001_dev->dev_type == FANOUT_DEV)
4213 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4215 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4216 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4218 phy_id = pm8001_dev->attached_phy;
4219 opc = OPC_INB_REG_DEV;
4220 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4221 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4222 payload.phyid_portid =
4223 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4224 ((phy_id & 0x0F) << 4));
4225 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4226 ((linkrate & 0x0F) * 0x1000000) |
4227 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4228 payload.firstburstsize_ITNexustimeout =
4229 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4230 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4232 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4237 * see comments on mpi_reg_resp.
4239 static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4242 struct dereg_dev_req payload;
4243 u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4245 struct inbound_queue_table *circularQ;
4247 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4248 memset(&payload, 0, sizeof(payload));
4249 payload.tag = cpu_to_le32(1);
4250 payload.device_id = cpu_to_le32(device_id);
4251 PM8001_MSG_DBG(pm8001_ha,
4252 pm8001_printk("unregister device device_id = %d\n", device_id));
4253 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4258 * pm8001_chip_phy_ctl_req - support the local phy operation
4259 * @pm8001_ha: our hba card information.
4260 * @num: the inbound queue number
4261 * @phy_id: the phy id which we wanted to operate
4264 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4265 u32 phyId, u32 phy_op)
4267 struct local_phy_ctl_req payload;
4268 struct inbound_queue_table *circularQ;
4270 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4271 memset(&payload, 0, sizeof(payload));
4272 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4273 payload.tag = cpu_to_le32(1);
4274 payload.phyop_phyid =
4275 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4276 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4280 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4283 #ifdef PM8001_USE_MSIX
4286 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4294 * pm8001_chip_isr - PM8001 isr handler.
4295 * @pm8001_ha: our hba card information.
4300 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha)
4302 pm8001_chip_interrupt_disable(pm8001_ha);
4303 process_oq(pm8001_ha);
4304 pm8001_chip_interrupt_enable(pm8001_ha);
4308 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4309 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4311 struct task_abort_req task_abort;
4312 struct inbound_queue_table *circularQ;
4314 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4315 memset(&task_abort, 0, sizeof(task_abort));
4316 if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4317 task_abort.abort_all = 0;
4318 task_abort.device_id = cpu_to_le32(dev_id);
4319 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4320 task_abort.tag = cpu_to_le32(cmd_tag);
4321 } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4322 task_abort.abort_all = cpu_to_le32(1);
4323 task_abort.device_id = cpu_to_le32(dev_id);
4324 task_abort.tag = cpu_to_le32(cmd_tag);
4326 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort);
4331 * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4332 * @task: the task we wanted to aborted.
4333 * @flag: the abort flag.
4335 static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4336 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4339 int rc = TMF_RESP_FUNC_FAILED;
4340 PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag"
4341 " = %x", cmd_tag, task_tag));
4342 if (pm8001_dev->dev_type == SAS_END_DEV)
4343 opc = OPC_INB_SSP_ABORT;
4344 else if (pm8001_dev->dev_type == SATA_DEV)
4345 opc = OPC_INB_SATA_ABORT;
4347 opc = OPC_INB_SMP_ABORT;/* SMP */
4348 device_id = pm8001_dev->device_id;
4349 rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4351 if (rc != TMF_RESP_FUNC_COMPLETE)
4352 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4357 * pm8001_chip_ssp_tm_req - built the task management command.
4358 * @pm8001_ha: our hba card information.
4359 * @ccb: the ccb information.
4360 * @tmf: task management function.
4362 static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4363 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4365 struct sas_task *task = ccb->task;
4366 struct domain_device *dev = task->dev;
4367 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4368 u32 opc = OPC_INB_SSPINITMSTART;
4369 struct inbound_queue_table *circularQ;
4370 struct ssp_ini_tm_start_req sspTMCmd;
4373 memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4374 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4375 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4376 sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4377 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4378 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4379 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4380 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd);
4384 static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4387 u32 opc = OPC_INB_GET_NVMD_DATA;
4391 struct pm8001_ccb_info *ccb;
4392 struct inbound_queue_table *circularQ;
4393 struct get_nvm_data_req nvmd_req;
4394 struct fw_control_ex *fw_control_context;
4395 struct pm8001_ioctl_payload *ioctl_payload = payload;
4397 nvmd_type = ioctl_payload->minor_function;
4398 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4399 if (!fw_control_context)
4401 fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0];
4402 fw_control_context->len = ioctl_payload->length;
4403 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4404 memset(&nvmd_req, 0, sizeof(nvmd_req));
4405 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4407 kfree(fw_control_context);
4410 ccb = &pm8001_ha->ccb_info[tag];
4412 ccb->fw_control_context = fw_control_context;
4413 nvmd_req.tag = cpu_to_le32(tag);
4415 switch (nvmd_type) {
4417 u32 twi_addr, twi_page_size;
4421 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4422 twi_page_size << 8 | TWI_DEVICE);
4423 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4424 nvmd_req.resp_addr_hi =
4425 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4426 nvmd_req.resp_addr_lo =
4427 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4431 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4432 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4433 nvmd_req.resp_addr_hi =
4434 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4435 nvmd_req.resp_addr_lo =
4436 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4440 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4441 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4442 nvmd_req.resp_addr_hi =
4443 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4444 nvmd_req.resp_addr_lo =
4445 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4449 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4450 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4451 nvmd_req.resp_addr_hi =
4452 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4453 nvmd_req.resp_addr_lo =
4454 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4460 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4464 static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4467 u32 opc = OPC_INB_SET_NVMD_DATA;
4471 struct pm8001_ccb_info *ccb;
4472 struct inbound_queue_table *circularQ;
4473 struct set_nvm_data_req nvmd_req;
4474 struct fw_control_ex *fw_control_context;
4475 struct pm8001_ioctl_payload *ioctl_payload = payload;
4477 nvmd_type = ioctl_payload->minor_function;
4478 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4479 if (!fw_control_context)
4481 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4482 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4483 ioctl_payload->func_specific,
4484 ioctl_payload->length);
4485 memset(&nvmd_req, 0, sizeof(nvmd_req));
4486 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4488 kfree(fw_control_context);
4491 ccb = &pm8001_ha->ccb_info[tag];
4492 ccb->fw_control_context = fw_control_context;
4494 nvmd_req.tag = cpu_to_le32(tag);
4495 switch (nvmd_type) {
4497 u32 twi_addr, twi_page_size;
4500 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4501 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4502 twi_page_size << 8 | TWI_DEVICE);
4503 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4504 nvmd_req.resp_addr_hi =
4505 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4506 nvmd_req.resp_addr_lo =
4507 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4511 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4512 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4513 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4514 nvmd_req.resp_addr_hi =
4515 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4516 nvmd_req.resp_addr_lo =
4517 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4520 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4521 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4522 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4523 nvmd_req.resp_addr_hi =
4524 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4525 nvmd_req.resp_addr_lo =
4526 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4529 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4530 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4531 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4532 nvmd_req.resp_addr_hi =
4533 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4534 nvmd_req.resp_addr_lo =
4535 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4540 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4545 * pm8001_chip_fw_flash_update_build - support the firmware update operation
4546 * @pm8001_ha: our hba card information.
4547 * @fw_flash_updata_info: firmware flash update param
4550 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4551 void *fw_flash_updata_info, u32 tag)
4553 struct fw_flash_Update_req payload;
4554 struct fw_flash_updata_info *info;
4555 struct inbound_queue_table *circularQ;
4557 u32 opc = OPC_INB_FW_FLASH_UPDATE;
4559 memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4560 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4561 info = fw_flash_updata_info;
4562 payload.tag = cpu_to_le32(tag);
4563 payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4564 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4565 payload.total_image_len = cpu_to_le32(info->total_image_len);
4566 payload.len = info->sgl.im_len.len ;
4567 payload.sgl_addr_lo =
4568 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4569 payload.sgl_addr_hi =
4570 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4571 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4576 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4579 struct fw_flash_updata_info flash_update_info;
4580 struct fw_control_info *fw_control;
4581 struct fw_control_ex *fw_control_context;
4584 struct pm8001_ccb_info *ccb;
4585 void *buffer = NULL;
4586 dma_addr_t phys_addr;
4589 struct pm8001_ioctl_payload *ioctl_payload = payload;
4591 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4592 if (!fw_control_context)
4594 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0];
4595 if (fw_control->len != 0) {
4596 if (pm8001_mem_alloc(pm8001_ha->pdev,
4601 fw_control->len, 0) != 0) {
4602 PM8001_FAIL_DBG(pm8001_ha,
4603 pm8001_printk("Mem alloc failure\n"));
4604 kfree(fw_control_context);
4608 memcpy(buffer, fw_control->buffer, fw_control->len);
4609 flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4610 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4611 flash_update_info.sgl.im_len.e = 0;
4612 flash_update_info.cur_image_offset = fw_control->offset;
4613 flash_update_info.cur_image_len = fw_control->len;
4614 flash_update_info.total_image_len = fw_control->size;
4615 fw_control_context->fw_control = fw_control;
4616 fw_control_context->virtAddr = buffer;
4617 fw_control_context->len = fw_control->len;
4618 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4620 kfree(fw_control_context);
4623 ccb = &pm8001_ha->ccb_info[tag];
4624 ccb->fw_control_context = fw_control_context;
4626 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4632 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4633 struct pm8001_device *pm8001_dev, u32 state)
4635 struct set_dev_state_req payload;
4636 struct inbound_queue_table *circularQ;
4637 struct pm8001_ccb_info *ccb;
4640 u32 opc = OPC_INB_SET_DEVICE_STATE;
4641 memset(&payload, 0, sizeof(payload));
4642 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4645 ccb = &pm8001_ha->ccb_info[tag];
4647 ccb->device = pm8001_dev;
4648 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4649 payload.tag = cpu_to_le32(tag);
4650 payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4651 payload.nds = cpu_to_le32(state);
4652 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4658 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4660 struct sas_re_initialization_req payload;
4661 struct inbound_queue_table *circularQ;
4662 struct pm8001_ccb_info *ccb;
4665 u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4666 memset(&payload, 0, sizeof(payload));
4667 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4670 ccb = &pm8001_ha->ccb_info[tag];
4672 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4673 payload.tag = cpu_to_le32(tag);
4674 payload.SSAHOLT = cpu_to_le32(0xd << 25);
4675 payload.sata_hol_tmo = cpu_to_le32(80);
4676 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4677 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4682 const struct pm8001_dispatch pm8001_8001_dispatch = {
4684 .chip_init = pm8001_chip_init,
4685 .chip_soft_rst = pm8001_chip_soft_rst,
4686 .chip_rst = pm8001_hw_chip_rst,
4687 .chip_iounmap = pm8001_chip_iounmap,
4688 .isr = pm8001_chip_isr,
4689 .is_our_interupt = pm8001_chip_is_our_interupt,
4690 .isr_process_oq = process_oq,
4691 .interrupt_enable = pm8001_chip_interrupt_enable,
4692 .interrupt_disable = pm8001_chip_interrupt_disable,
4693 .make_prd = pm8001_chip_make_sg,
4694 .smp_req = pm8001_chip_smp_req,
4695 .ssp_io_req = pm8001_chip_ssp_io_req,
4696 .sata_req = pm8001_chip_sata_req,
4697 .phy_start_req = pm8001_chip_phy_start_req,
4698 .phy_stop_req = pm8001_chip_phy_stop_req,
4699 .reg_dev_req = pm8001_chip_reg_dev_req,
4700 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4701 .phy_ctl_req = pm8001_chip_phy_ctl_req,
4702 .task_abort = pm8001_chip_abort_task,
4703 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4704 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4705 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4706 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4707 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4708 .sas_re_init_req = pm8001_chip_sas_re_initialization,