2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm8001_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
47 * read_main_config_table - read the configure table and save it.
48 * @pm8001_ha: our hba card information
50 static void __devinit read_main_config_table(struct pm8001_hba_info *pm8001_ha)
52 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
53 pm8001_ha->main_cfg_tbl.signature = pm8001_mr32(address, 0x00);
54 pm8001_ha->main_cfg_tbl.interface_rev = pm8001_mr32(address, 0x04);
55 pm8001_ha->main_cfg_tbl.firmware_rev = pm8001_mr32(address, 0x08);
56 pm8001_ha->main_cfg_tbl.max_out_io = pm8001_mr32(address, 0x0C);
57 pm8001_ha->main_cfg_tbl.max_sgl = pm8001_mr32(address, 0x10);
58 pm8001_ha->main_cfg_tbl.ctrl_cap_flag = pm8001_mr32(address, 0x14);
59 pm8001_ha->main_cfg_tbl.gst_offset = pm8001_mr32(address, 0x18);
60 pm8001_ha->main_cfg_tbl.inbound_queue_offset =
61 pm8001_mr32(address, MAIN_IBQ_OFFSET);
62 pm8001_ha->main_cfg_tbl.outbound_queue_offset =
63 pm8001_mr32(address, MAIN_OBQ_OFFSET);
64 pm8001_ha->main_cfg_tbl.hda_mode_flag =
65 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
67 /* read analog Setting offset from the configuration table */
68 pm8001_ha->main_cfg_tbl.anolog_setup_table_offset =
69 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
71 /* read Error Dump Offset and Length */
72 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 =
73 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
74 pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 =
75 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
76 pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 =
77 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
78 pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 =
79 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
83 * read_general_status_table - read the general status table and save it.
84 * @pm8001_ha: our hba card information
87 read_general_status_table(struct pm8001_hba_info *pm8001_ha)
89 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
90 pm8001_ha->gs_tbl.gst_len_mpistate = pm8001_mr32(address, 0x00);
91 pm8001_ha->gs_tbl.iq_freeze_state0 = pm8001_mr32(address, 0x04);
92 pm8001_ha->gs_tbl.iq_freeze_state1 = pm8001_mr32(address, 0x08);
93 pm8001_ha->gs_tbl.msgu_tcnt = pm8001_mr32(address, 0x0C);
94 pm8001_ha->gs_tbl.iop_tcnt = pm8001_mr32(address, 0x10);
95 pm8001_ha->gs_tbl.reserved = pm8001_mr32(address, 0x14);
96 pm8001_ha->gs_tbl.phy_state[0] = pm8001_mr32(address, 0x18);
97 pm8001_ha->gs_tbl.phy_state[1] = pm8001_mr32(address, 0x1C);
98 pm8001_ha->gs_tbl.phy_state[2] = pm8001_mr32(address, 0x20);
99 pm8001_ha->gs_tbl.phy_state[3] = pm8001_mr32(address, 0x24);
100 pm8001_ha->gs_tbl.phy_state[4] = pm8001_mr32(address, 0x28);
101 pm8001_ha->gs_tbl.phy_state[5] = pm8001_mr32(address, 0x2C);
102 pm8001_ha->gs_tbl.phy_state[6] = pm8001_mr32(address, 0x30);
103 pm8001_ha->gs_tbl.phy_state[7] = pm8001_mr32(address, 0x34);
104 pm8001_ha->gs_tbl.reserved1 = pm8001_mr32(address, 0x38);
105 pm8001_ha->gs_tbl.reserved2 = pm8001_mr32(address, 0x3C);
106 pm8001_ha->gs_tbl.reserved3 = pm8001_mr32(address, 0x40);
107 pm8001_ha->gs_tbl.recover_err_info[0] = pm8001_mr32(address, 0x44);
108 pm8001_ha->gs_tbl.recover_err_info[1] = pm8001_mr32(address, 0x48);
109 pm8001_ha->gs_tbl.recover_err_info[2] = pm8001_mr32(address, 0x4C);
110 pm8001_ha->gs_tbl.recover_err_info[3] = pm8001_mr32(address, 0x50);
111 pm8001_ha->gs_tbl.recover_err_info[4] = pm8001_mr32(address, 0x54);
112 pm8001_ha->gs_tbl.recover_err_info[5] = pm8001_mr32(address, 0x58);
113 pm8001_ha->gs_tbl.recover_err_info[6] = pm8001_mr32(address, 0x5C);
114 pm8001_ha->gs_tbl.recover_err_info[7] = pm8001_mr32(address, 0x60);
118 * read_inbnd_queue_table - read the inbound queue table and save it.
119 * @pm8001_ha: our hba card information
121 static void __devinit
122 read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
126 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
127 for (i = 0; i < inbQ_num; i++) {
128 u32 offset = i * 0x20;
129 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
130 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
131 pm8001_ha->inbnd_q_tbl[i].pi_offset =
132 pm8001_mr32(address, (offset + 0x18));
137 * read_outbnd_queue_table - read the outbound queue table and save it.
138 * @pm8001_ha: our hba card information
140 static void __devinit
141 read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
145 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
146 for (i = 0; i < outbQ_num; i++) {
147 u32 offset = i * 0x24;
148 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
149 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
150 pm8001_ha->outbnd_q_tbl[i].ci_offset =
151 pm8001_mr32(address, (offset + 0x18));
156 * init_default_table_values - init the default table.
157 * @pm8001_ha: our hba card information
159 static void __devinit
160 init_default_table_values(struct pm8001_hba_info *pm8001_ha)
164 u32 offsetib, offsetob;
165 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
166 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
168 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd = 0;
169 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3 = 0;
170 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7 = 0;
171 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3 = 0;
172 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7 = 0;
173 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3 = 0;
174 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7 = 0;
175 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
176 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
177 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3 = 0;
178 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7 = 0;
180 pm8001_ha->main_cfg_tbl.upper_event_log_addr =
181 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
182 pm8001_ha->main_cfg_tbl.lower_event_log_addr =
183 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
184 pm8001_ha->main_cfg_tbl.event_log_size = PM8001_EVENT_LOG_SIZE;
185 pm8001_ha->main_cfg_tbl.event_log_option = 0x01;
186 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr =
187 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
188 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr =
189 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
190 pm8001_ha->main_cfg_tbl.iop_event_log_size = PM8001_EVENT_LOG_SIZE;
191 pm8001_ha->main_cfg_tbl.iop_event_log_option = 0x01;
192 pm8001_ha->main_cfg_tbl.fatal_err_interrupt = 0x01;
193 for (i = 0; i < qn; i++) {
194 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
195 0x00000100 | (0x00000040 << 16) | (0x00<<30);
196 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
197 pm8001_ha->memoryMap.region[IB].phys_addr_hi;
198 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
199 pm8001_ha->memoryMap.region[IB].phys_addr_lo;
200 pm8001_ha->inbnd_q_tbl[i].base_virt =
201 (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr;
202 pm8001_ha->inbnd_q_tbl[i].total_length =
203 pm8001_ha->memoryMap.region[IB].total_len;
204 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
205 pm8001_ha->memoryMap.region[CI].phys_addr_hi;
206 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
207 pm8001_ha->memoryMap.region[CI].phys_addr_lo;
208 pm8001_ha->inbnd_q_tbl[i].ci_virt =
209 pm8001_ha->memoryMap.region[CI].virt_ptr;
211 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
212 get_pci_bar_index(pm8001_mr32(addressib,
214 pm8001_ha->inbnd_q_tbl[i].pi_offset =
215 pm8001_mr32(addressib, (offsetib + 0x18));
216 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
217 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
219 for (i = 0; i < qn; i++) {
220 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
221 256 | (64 << 16) | (1<<30);
222 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
223 pm8001_ha->memoryMap.region[OB].phys_addr_hi;
224 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
225 pm8001_ha->memoryMap.region[OB].phys_addr_lo;
226 pm8001_ha->outbnd_q_tbl[i].base_virt =
227 (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr;
228 pm8001_ha->outbnd_q_tbl[i].total_length =
229 pm8001_ha->memoryMap.region[OB].total_len;
230 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
231 pm8001_ha->memoryMap.region[PI].phys_addr_hi;
232 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
233 pm8001_ha->memoryMap.region[PI].phys_addr_lo;
234 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
235 0 | (10 << 16) | (0 << 24);
236 pm8001_ha->outbnd_q_tbl[i].pi_virt =
237 pm8001_ha->memoryMap.region[PI].virt_ptr;
239 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
240 get_pci_bar_index(pm8001_mr32(addressob,
242 pm8001_ha->outbnd_q_tbl[i].ci_offset =
243 pm8001_mr32(addressob, (offsetob + 0x18));
244 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
245 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
250 * update_main_config_table - update the main default table to the HBA.
251 * @pm8001_ha: our hba card information
253 static void __devinit
254 update_main_config_table(struct pm8001_hba_info *pm8001_ha)
256 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
257 pm8001_mw32(address, 0x24,
258 pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd);
259 pm8001_mw32(address, 0x28,
260 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3);
261 pm8001_mw32(address, 0x2C,
262 pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7);
263 pm8001_mw32(address, 0x30,
264 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3);
265 pm8001_mw32(address, 0x34,
266 pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7);
267 pm8001_mw32(address, 0x38,
268 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3);
269 pm8001_mw32(address, 0x3C,
270 pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7);
271 pm8001_mw32(address, 0x40,
272 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3);
273 pm8001_mw32(address, 0x44,
274 pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7);
275 pm8001_mw32(address, 0x48,
276 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3);
277 pm8001_mw32(address, 0x4C,
278 pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7);
279 pm8001_mw32(address, 0x50,
280 pm8001_ha->main_cfg_tbl.upper_event_log_addr);
281 pm8001_mw32(address, 0x54,
282 pm8001_ha->main_cfg_tbl.lower_event_log_addr);
283 pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size);
284 pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option);
285 pm8001_mw32(address, 0x60,
286 pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr);
287 pm8001_mw32(address, 0x64,
288 pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr);
289 pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size);
290 pm8001_mw32(address, 0x6C,
291 pm8001_ha->main_cfg_tbl.iop_event_log_option);
292 pm8001_mw32(address, 0x70,
293 pm8001_ha->main_cfg_tbl.fatal_err_interrupt);
297 * update_inbnd_queue_table - update the inbound queue table to the HBA.
298 * @pm8001_ha: our hba card information
300 static void __devinit
301 update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
303 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
304 u16 offset = number * 0x20;
305 pm8001_mw32(address, offset + 0x00,
306 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
307 pm8001_mw32(address, offset + 0x04,
308 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
309 pm8001_mw32(address, offset + 0x08,
310 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
311 pm8001_mw32(address, offset + 0x0C,
312 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
313 pm8001_mw32(address, offset + 0x10,
314 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
318 * update_outbnd_queue_table - update the outbound queue table to the HBA.
319 * @pm8001_ha: our hba card information
321 static void __devinit
322 update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
324 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
325 u16 offset = number * 0x24;
326 pm8001_mw32(address, offset + 0x00,
327 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
328 pm8001_mw32(address, offset + 0x04,
329 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
330 pm8001_mw32(address, offset + 0x08,
331 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
332 pm8001_mw32(address, offset + 0x0C,
333 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
334 pm8001_mw32(address, offset + 0x10,
335 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
336 pm8001_mw32(address, offset + 0x1C,
337 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
341 * pm8001_bar4_shift - function is called to shift BAR base address
342 * @pm8001_ha : our hba card infomation
343 * @shiftValue : shifting value in memory bar.
345 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
350 /* program the inbound AXI translation Lower Address */
351 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
353 /* confirm the setting is written */
354 start = jiffies + HZ; /* 1 sec */
356 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
357 } while ((regVal != shiftValue) && time_before(jiffies, start));
359 if (regVal != shiftValue) {
360 PM8001_INIT_DBG(pm8001_ha,
361 pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
362 " = 0x%x\n", regVal));
369 * mpi_set_phys_g3_with_ssc
370 * @pm8001_ha: our hba card information
371 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
373 static void __devinit
374 mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit)
376 u32 value, offset, i;
379 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
380 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
381 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
382 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
383 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
384 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
385 #define SNW3_PHY_CAPABILITIES_PARITY 31
388 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
389 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
391 spin_lock_irqsave(&pm8001_ha->lock, flags);
392 if (-1 == pm8001_bar4_shift(pm8001_ha,
393 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
394 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
398 for (i = 0; i < 4; i++) {
399 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
400 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
402 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
403 if (-1 == pm8001_bar4_shift(pm8001_ha,
404 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
405 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
408 for (i = 4; i < 8; i++) {
409 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
410 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
412 /*************************************************************
413 Change the SSC upspreading value to 0x0 so that upspreading is disabled.
414 Device MABC SMOD0 Controls
415 Address: (via MEMBASE-III):
416 Using shifted destination address 0x0_0000: with Offset 0xD8
418 31:28 R/W Reserved Do not change
419 27:24 R/W SAS_SMOD_SPRDUP 0000
420 23:20 R/W SAS_SMOD_SPRDDN 0000
421 19:0 R/W Reserved Do not change
422 Upon power-up this register will read as 0x8990c016,
423 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
424 so that the written value will be 0x8090c016.
425 This will ensure only down-spreading SSC is enabled on the SPC.
426 *************************************************************/
427 value = pm8001_cr32(pm8001_ha, 2, 0xd8);
428 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
430 /*set the shifted destination address to 0x0 to avoid error operation */
431 pm8001_bar4_shift(pm8001_ha, 0x0);
432 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
437 * mpi_set_open_retry_interval_reg
438 * @pm8001_ha: our hba card information
439 * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
441 static void __devinit
442 mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
450 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
451 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
452 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
453 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
454 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
456 value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
457 spin_lock_irqsave(&pm8001_ha->lock, flags);
458 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
459 if (-1 == pm8001_bar4_shift(pm8001_ha,
460 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
461 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
464 for (i = 0; i < 4; i++) {
465 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
466 pm8001_cw32(pm8001_ha, 2, offset, value);
469 if (-1 == pm8001_bar4_shift(pm8001_ha,
470 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
471 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
474 for (i = 4; i < 8; i++) {
475 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
476 pm8001_cw32(pm8001_ha, 2, offset, value);
478 /*set the shifted destination address to 0x0 to avoid error operation */
479 pm8001_bar4_shift(pm8001_ha, 0x0);
480 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
485 * mpi_init_check - check firmware initialization status.
486 * @pm8001_ha: our hba card information
488 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
492 u32 gst_len_mpistate;
493 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
495 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
496 /* wait until Inbound DoorBell Clear Register toggled */
497 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
500 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
501 value &= SPC_MSGU_CFG_TABLE_UPDATE;
502 } while ((value != 0) && (--max_wait_count));
506 /* check the MPI-State for initialization */
508 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
509 GST_GSTLEN_MPIS_OFFSET);
510 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
512 /* check MPI Initialization error */
513 gst_len_mpistate = gst_len_mpistate >> 16;
514 if (0x0000 != gst_len_mpistate)
520 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
521 * @pm8001_ha: our hba card information
523 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
527 /* check error state */
528 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
529 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
530 /* check AAP error */
531 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
533 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
537 /* check IOP error */
538 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
540 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
544 /* bit 4-31 of scratch pad1 should be zeros if it is not
546 if (value & SCRATCH_PAD1_STATE_MASK) {
548 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
552 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
554 if (value1 & SCRATCH_PAD2_STATE_MASK) {
559 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
561 /* wait until scratch pad 1 and 2 registers in ready state */
564 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
566 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
568 if ((--max_wait_count) == 0)
570 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
574 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
576 void __iomem *base_addr;
582 value = pm8001_cr32(pm8001_ha, 0, 0x44);
583 offset = value & 0x03FFFFFF;
584 PM8001_INIT_DBG(pm8001_ha,
585 pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
586 pcilogic = (value & 0xFC000000) >> 26;
587 pcibar = get_pci_bar_index(pcilogic);
588 PM8001_INIT_DBG(pm8001_ha,
589 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
590 pm8001_ha->main_cfg_tbl_addr = base_addr =
591 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
592 pm8001_ha->general_stat_tbl_addr =
593 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
594 pm8001_ha->inbnd_q_tbl_addr =
595 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
596 pm8001_ha->outbnd_q_tbl_addr =
597 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
601 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
602 * @pm8001_ha: our hba card information
604 static int __devinit pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
606 /* check the firmware status */
607 if (-1 == check_fw_ready(pm8001_ha)) {
608 PM8001_FAIL_DBG(pm8001_ha,
609 pm8001_printk("Firmware is not ready!\n"));
613 /* Initialize pci space address eg: mpi offset */
614 init_pci_device_addresses(pm8001_ha);
615 init_default_table_values(pm8001_ha);
616 read_main_config_table(pm8001_ha);
617 read_general_status_table(pm8001_ha);
618 read_inbnd_queue_table(pm8001_ha);
619 read_outbnd_queue_table(pm8001_ha);
620 /* update main config table ,inbound table and outbound table */
621 update_main_config_table(pm8001_ha);
622 update_inbnd_queue_table(pm8001_ha, 0);
623 update_outbnd_queue_table(pm8001_ha, 0);
624 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
625 /* 7->130ms, 34->500ms, 119->1.5s */
626 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
627 /* notify firmware update finished and check initialization status */
628 if (0 == mpi_init_check(pm8001_ha)) {
629 PM8001_INIT_DBG(pm8001_ha,
630 pm8001_printk("MPI initialize successful!\n"));
633 /*This register is a 16-bit timer with a resolution of 1us. This is the
634 timer used for interrupt delay/coalescing in the PCIe Application Layer.
635 Zero is not a valid value. A value of 1 in the register will cause the
636 interrupts to be normal. A value greater than 1 will cause coalescing
638 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
639 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
643 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
647 u32 gst_len_mpistate;
648 init_pci_device_addresses(pm8001_ha);
649 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
651 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
653 /* wait until Inbound DoorBell Clear Register toggled */
654 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
657 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
658 value &= SPC_MSGU_CFG_TABLE_RESET;
659 } while ((value != 0) && (--max_wait_count));
661 if (!max_wait_count) {
662 PM8001_FAIL_DBG(pm8001_ha,
663 pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
667 /* check the MPI-State for termination in progress */
668 /* wait until Inbound DoorBell Clear Register toggled */
669 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
673 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
674 GST_GSTLEN_MPIS_OFFSET);
675 if (GST_MPI_STATE_UNINIT ==
676 (gst_len_mpistate & GST_MPI_STATE_MASK))
678 } while (--max_wait_count);
679 if (!max_wait_count) {
680 PM8001_FAIL_DBG(pm8001_ha,
681 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
682 gst_len_mpistate & GST_MPI_STATE_MASK));
689 * soft_reset_ready_check - Function to check FW is ready for soft reset.
690 * @pm8001_ha: our hba card information
692 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
694 u32 regVal, regVal1, regVal2;
695 if (mpi_uninit_check(pm8001_ha) != 0) {
696 PM8001_FAIL_DBG(pm8001_ha,
697 pm8001_printk("MPI state is not ready\n"));
700 /* read the scratch pad 2 register bit 2 */
701 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
702 & SCRATCH_PAD2_FWRDY_RST;
703 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
704 PM8001_INIT_DBG(pm8001_ha,
705 pm8001_printk("Firmware is ready for reset .\n"));
708 /* Trigger NMI twice via RB6 */
709 spin_lock_irqsave(&pm8001_ha->lock, flags);
710 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
711 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
712 PM8001_FAIL_DBG(pm8001_ha,
713 pm8001_printk("Shift Bar4 to 0x%x failed\n",
717 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
718 RB6_MAGIC_NUMBER_RST);
719 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
720 /* wait for 100 ms */
722 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
723 SCRATCH_PAD2_FWRDY_RST;
724 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
725 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
726 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
727 PM8001_FAIL_DBG(pm8001_ha,
728 pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
729 "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
731 PM8001_FAIL_DBG(pm8001_ha,
732 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
733 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
734 PM8001_FAIL_DBG(pm8001_ha,
735 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
736 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
737 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
740 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
746 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
747 * the FW register status to the originated status.
748 * @pm8001_ha: our hba card information
749 * @signature: signature in host scratch pad0 register.
752 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
754 u32 regVal, toggleVal;
756 u32 regVal1, regVal2, regVal3;
759 /* step1: Check FW is ready for soft reset */
760 if (soft_reset_ready_check(pm8001_ha) != 0) {
761 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
765 /* step 2: clear NMI status register on AAP1 and IOP, write the same
767 /* map 0x60000 to BAR4(0x20), BAR2(win) */
768 spin_lock_irqsave(&pm8001_ha->lock, flags);
769 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
770 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
771 PM8001_FAIL_DBG(pm8001_ha,
772 pm8001_printk("Shift Bar4 to 0x%x failed\n",
773 MBIC_AAP1_ADDR_BASE));
776 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
777 PM8001_INIT_DBG(pm8001_ha,
778 pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
779 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
780 /* map 0x70000 to BAR4(0x20), BAR2(win) */
781 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
782 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
783 PM8001_FAIL_DBG(pm8001_ha,
784 pm8001_printk("Shift Bar4 to 0x%x failed\n",
785 MBIC_IOP_ADDR_BASE));
788 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
789 PM8001_INIT_DBG(pm8001_ha,
790 pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
791 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
793 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
794 PM8001_INIT_DBG(pm8001_ha,
795 pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
796 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
798 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
799 PM8001_INIT_DBG(pm8001_ha,
800 pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal));
801 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
803 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
804 PM8001_INIT_DBG(pm8001_ha,
805 pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
806 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
808 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
809 PM8001_INIT_DBG(pm8001_ha,
810 pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
811 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
813 /* read the scratch pad 1 register bit 2 */
814 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
816 toggleVal = regVal ^ SCRATCH_PAD1_RST;
818 /* set signature in host scratch pad0 register to tell SPC that the
819 host performs the soft reset */
820 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
822 /* read required registers for confirmming */
823 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
824 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
825 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
826 PM8001_FAIL_DBG(pm8001_ha,
827 pm8001_printk("Shift Bar4 to 0x%x failed\n",
831 PM8001_INIT_DBG(pm8001_ha,
832 pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
834 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
836 /* step 3: host read GSM Configuration and Reset register */
837 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
838 /* Put those bits to low */
839 /* GSM XCBI offset = 0x70 0000
840 0x00 Bit 13 COM_SLV_SW_RSTB 1
841 0x00 Bit 12 QSSP_SW_RSTB 1
842 0x00 Bit 11 RAAE_SW_RSTB 1
843 0x00 Bit 9 RB_1_SW_RSTB 1
844 0x00 Bit 8 SM_SW_RSTB 1
846 regVal &= ~(0x00003b00);
847 /* host write GSM Configuration and Reset register */
848 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
849 PM8001_INIT_DBG(pm8001_ha,
850 pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
851 "Configuration and Reset is set to = 0x%x\n",
852 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
855 /* disable GSM - Read Address Parity Check */
856 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
857 PM8001_INIT_DBG(pm8001_ha,
858 pm8001_printk("GSM 0x700038 - Read Address Parity Check "
859 "Enable = 0x%x\n", regVal1));
860 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
861 PM8001_INIT_DBG(pm8001_ha,
862 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
863 "is set to = 0x%x\n",
864 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
866 /* disable GSM - Write Address Parity Check */
867 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
868 PM8001_INIT_DBG(pm8001_ha,
869 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
870 " Enable = 0x%x\n", regVal2));
871 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
872 PM8001_INIT_DBG(pm8001_ha,
873 pm8001_printk("GSM 0x700040 - Write Address Parity Check "
874 "Enable is set to = 0x%x\n",
875 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
877 /* disable GSM - Write Data Parity Check */
878 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
879 PM8001_INIT_DBG(pm8001_ha,
880 pm8001_printk("GSM 0x300048 - Write Data Parity Check"
881 " Enable = 0x%x\n", regVal3));
882 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
883 PM8001_INIT_DBG(pm8001_ha,
884 pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
885 "is set to = 0x%x\n",
886 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
888 /* step 5: delay 10 usec */
890 /* step 5-b: set GPIO-0 output control to tristate anyway */
891 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
892 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
893 PM8001_INIT_DBG(pm8001_ha,
894 pm8001_printk("Shift Bar4 to 0x%x failed\n",
898 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
899 PM8001_INIT_DBG(pm8001_ha,
900 pm8001_printk("GPIO Output Control Register:"
901 " = 0x%x\n", regVal));
902 /* set GPIO-0 output control to tri-state */
903 regVal &= 0xFFFFFFFC;
904 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
906 /* Step 6: Reset the IOP and AAP1 */
907 /* map 0x00000 to BAR4(0x20), BAR2(win) */
908 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
909 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
910 PM8001_FAIL_DBG(pm8001_ha,
911 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
912 SPC_TOP_LEVEL_ADDR_BASE));
915 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
916 PM8001_INIT_DBG(pm8001_ha,
917 pm8001_printk("Top Register before resetting IOP/AAP1"
918 ":= 0x%x\n", regVal));
919 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
920 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
922 /* step 7: Reset the BDMA/OSSP */
923 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
924 PM8001_INIT_DBG(pm8001_ha,
925 pm8001_printk("Top Register before resetting BDMA/OSSP"
926 ": = 0x%x\n", regVal));
927 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
928 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
930 /* step 8: delay 10 usec */
933 /* step 9: bring the BDMA and OSSP out of reset */
934 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
935 PM8001_INIT_DBG(pm8001_ha,
936 pm8001_printk("Top Register before bringing up BDMA/OSSP"
937 ":= 0x%x\n", regVal));
938 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
939 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
941 /* step 10: delay 10 usec */
944 /* step 11: reads and sets the GSM Configuration and Reset Register */
945 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
946 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
947 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
948 PM8001_FAIL_DBG(pm8001_ha,
949 pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
953 PM8001_INIT_DBG(pm8001_ha,
954 pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
955 "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
956 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
957 /* Put those bits to high */
958 /* GSM XCBI offset = 0x70 0000
959 0x00 Bit 13 COM_SLV_SW_RSTB 1
960 0x00 Bit 12 QSSP_SW_RSTB 1
961 0x00 Bit 11 RAAE_SW_RSTB 1
962 0x00 Bit 9 RB_1_SW_RSTB 1
963 0x00 Bit 8 SM_SW_RSTB 1
965 regVal |= (GSM_CONFIG_RESET_VALUE);
966 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
967 PM8001_INIT_DBG(pm8001_ha,
968 pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
969 " Configuration and Reset is set to = 0x%x\n",
970 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
972 /* step 12: Restore GSM - Read Address Parity Check */
973 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
974 /* just for debugging */
975 PM8001_INIT_DBG(pm8001_ha,
976 pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
977 " = 0x%x\n", regVal));
978 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
979 PM8001_INIT_DBG(pm8001_ha,
980 pm8001_printk("GSM 0x700038 - Read Address Parity"
981 " Check Enable is set to = 0x%x\n",
982 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
983 /* Restore GSM - Write Address Parity Check */
984 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
985 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
986 PM8001_INIT_DBG(pm8001_ha,
987 pm8001_printk("GSM 0x700040 - Write Address Parity Check"
988 " Enable is set to = 0x%x\n",
989 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
990 /* Restore GSM - Write Data Parity Check */
991 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
992 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
993 PM8001_INIT_DBG(pm8001_ha,
994 pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
995 "is set to = 0x%x\n",
996 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
998 /* step 13: bring the IOP and AAP1 out of reset */
999 /* map 0x00000 to BAR4(0x20), BAR2(win) */
1000 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1001 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1002 PM8001_FAIL_DBG(pm8001_ha,
1003 pm8001_printk("Shift Bar4 to 0x%x failed\n",
1004 SPC_TOP_LEVEL_ADDR_BASE));
1007 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1008 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1009 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1011 /* step 14: delay 10 usec - Normal Mode */
1013 /* check Soft Reset Normal mode or Soft Reset HDA mode */
1014 if (signature == SPC_SOFT_RESET_SIGNATURE) {
1015 /* step 15 (Normal Mode): wait until scratch pad1 register
1017 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1020 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1022 } while ((regVal != toggleVal) && (--max_wait_count));
1024 if (!max_wait_count) {
1025 regVal = pm8001_cr32(pm8001_ha, 0,
1026 MSGU_SCRATCH_PAD_1);
1027 PM8001_FAIL_DBG(pm8001_ha,
1028 pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
1029 "MSGU_SCRATCH_PAD1 = 0x%x\n",
1030 toggleVal, regVal));
1031 PM8001_FAIL_DBG(pm8001_ha,
1032 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1033 pm8001_cr32(pm8001_ha, 0,
1034 MSGU_SCRATCH_PAD_0)));
1035 PM8001_FAIL_DBG(pm8001_ha,
1036 pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
1037 pm8001_cr32(pm8001_ha, 0,
1038 MSGU_SCRATCH_PAD_2)));
1039 PM8001_FAIL_DBG(pm8001_ha,
1040 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1041 pm8001_cr32(pm8001_ha, 0,
1042 MSGU_SCRATCH_PAD_3)));
1043 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1047 /* step 16 (Normal) - Clear ODMR and ODCR */
1048 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1049 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1051 /* step 17 (Normal Mode): wait for the FW and IOP to get
1052 ready - 1 sec timeout */
1053 /* Wait for the SPC Configuration Table to be ready */
1054 if (check_fw_ready(pm8001_ha) == -1) {
1055 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1056 /* return error if MPI Configuration Table not ready */
1057 PM8001_INIT_DBG(pm8001_ha,
1058 pm8001_printk("FW not ready SCRATCH_PAD1"
1059 " = 0x%x\n", regVal));
1060 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1061 /* return error if MPI Configuration Table not ready */
1062 PM8001_INIT_DBG(pm8001_ha,
1063 pm8001_printk("FW not ready SCRATCH_PAD2"
1064 " = 0x%x\n", regVal));
1065 PM8001_INIT_DBG(pm8001_ha,
1066 pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
1067 pm8001_cr32(pm8001_ha, 0,
1068 MSGU_SCRATCH_PAD_0)));
1069 PM8001_INIT_DBG(pm8001_ha,
1070 pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
1071 pm8001_cr32(pm8001_ha, 0,
1072 MSGU_SCRATCH_PAD_3)));
1073 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1077 pm8001_bar4_shift(pm8001_ha, 0);
1078 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1080 PM8001_INIT_DBG(pm8001_ha,
1081 pm8001_printk("SPC soft reset Complete\n"));
1085 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1089 PM8001_INIT_DBG(pm8001_ha,
1090 pm8001_printk("chip reset start\n"));
1092 /* do SPC chip reset. */
1093 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1094 regVal &= ~(SPC_REG_RESET_DEVICE);
1095 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1100 /* bring chip reset out of reset */
1101 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1102 regVal |= SPC_REG_RESET_DEVICE;
1103 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1108 /* wait for 20 msec until the firmware gets reloaded */
1112 } while ((--i) != 0);
1114 PM8001_INIT_DBG(pm8001_ha,
1115 pm8001_printk("chip reset finished\n"));
1119 * pm8001_chip_iounmap - which maped when initialized.
1120 * @pm8001_ha: our hba card information
1122 static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1124 s8 bar, logical = 0;
1125 for (bar = 0; bar < 6; bar++) {
1127 ** logical BARs for SPC:
1128 ** bar 0 and 1 - logical BAR0
1129 ** bar 2 and 3 - logical BAR1
1130 ** bar4 - logical BAR2
1131 ** bar5 - logical BAR3
1132 ** Skip the appropriate assignments:
1134 if ((bar == 1) || (bar == 3))
1136 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1137 iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1144 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1145 * @pm8001_ha: our hba card information
1148 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1150 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1151 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1155 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1156 * @pm8001_ha: our hba card information
1159 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1161 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1165 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1166 * @pm8001_ha: our hba card information
1169 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1174 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1175 msi_index += MSIX_TABLE_BASE;
1176 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1177 value = (1 << int_vec_idx);
1178 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
1183 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1184 * @pm8001_ha: our hba card information
1187 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1191 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1192 msi_index += MSIX_TABLE_BASE;
1193 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
1197 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1198 * @pm8001_ha: our hba card information
1201 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1203 #ifdef PM8001_USE_MSIX
1204 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1207 pm8001_chip_intx_interrupt_enable(pm8001_ha);
1212 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1213 * @pm8001_ha: our hba card information
1216 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1218 #ifdef PM8001_USE_MSIX
1219 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1222 pm8001_chip_intx_interrupt_disable(pm8001_ha);
1227 * mpi_msg_free_get- get the free message buffer for transfer inbound queue.
1228 * @circularQ: the inbound queue we want to transfer to HBA.
1229 * @messageSize: the message size of this transfer, normally it is 64 bytes
1230 * @messagePtr: the pointer to message.
1232 static int mpi_msg_free_get(struct inbound_queue_table *circularQ,
1233 u16 messageSize, void **messagePtr)
1235 u32 offset, consumer_index;
1236 struct mpi_msg_hdr *msgHeader;
1237 u8 bcCount = 1; /* only support single buffer */
1239 /* Checks is the requested message size can be allocated in this queue*/
1240 if (messageSize > 64) {
1245 /* Stores the new consumer index */
1246 consumer_index = pm8001_read_32(circularQ->ci_virt);
1247 circularQ->consumer_index = cpu_to_le32(consumer_index);
1248 if (((circularQ->producer_idx + bcCount) % 256) ==
1249 circularQ->consumer_index) {
1253 /* get memory IOMB buffer address */
1254 offset = circularQ->producer_idx * 64;
1255 /* increment to next bcCount element */
1256 circularQ->producer_idx = (circularQ->producer_idx + bcCount) % 256;
1257 /* Adds that distance to the base of the region virtual address plus
1258 the message header size*/
1259 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1260 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1265 * mpi_build_cmd- build the message queue for transfer, update the PI to FW
1266 * to tell the fw to get this message from IOMB.
1267 * @pm8001_ha: our hba card information
1268 * @circularQ: the inbound queue we want to transfer to HBA.
1269 * @opCode: the operation code represents commands which LLDD and fw recognized.
1270 * @payload: the command payload of each operation command.
1272 static int mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1273 struct inbound_queue_table *circularQ,
1274 u32 opCode, void *payload)
1276 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1277 u32 responseQueue = 0;
1280 if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) {
1281 PM8001_IO_DBG(pm8001_ha,
1282 pm8001_printk("No free mpi buffer\n"));
1286 /*Copy to the payload*/
1287 memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr)));
1289 /*Build the header*/
1290 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1291 | ((responseQueue & 0x3F) << 16)
1292 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1294 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1295 /*Update the PI to the firmware*/
1296 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1297 circularQ->pi_offset, circularQ->producer_idx);
1298 PM8001_IO_DBG(pm8001_ha,
1299 pm8001_printk("after PI= %d CI= %d\n", circularQ->producer_idx,
1300 circularQ->consumer_index));
1304 static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1305 struct outbound_queue_table *circularQ, u8 bc)
1308 struct mpi_msg_hdr *msgHeader;
1309 struct mpi_msg_hdr *pOutBoundMsgHeader;
1311 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1312 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1313 circularQ->consumer_idx * 64);
1314 if (pOutBoundMsgHeader != msgHeader) {
1315 PM8001_FAIL_DBG(pm8001_ha,
1316 pm8001_printk("consumer_idx = %d msgHeader = %p\n",
1317 circularQ->consumer_idx, msgHeader));
1319 /* Update the producer index from SPC */
1320 producer_index = pm8001_read_32(circularQ->pi_virt);
1321 circularQ->producer_index = cpu_to_le32(producer_index);
1322 PM8001_FAIL_DBG(pm8001_ha,
1323 pm8001_printk("consumer_idx = %d producer_index = %d"
1324 "msgHeader = %p\n", circularQ->consumer_idx,
1325 circularQ->producer_index, msgHeader));
1328 /* free the circular queue buffer elements associated with the message*/
1329 circularQ->consumer_idx = (circularQ->consumer_idx + bc) % 256;
1330 /* update the CI of outbound queue */
1331 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1332 circularQ->consumer_idx);
1333 /* Update the producer index from SPC*/
1334 producer_index = pm8001_read_32(circularQ->pi_virt);
1335 circularQ->producer_index = cpu_to_le32(producer_index);
1336 PM8001_IO_DBG(pm8001_ha,
1337 pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
1338 circularQ->producer_index));
1343 * mpi_msg_consume- get the MPI message from outbound queue message table.
1344 * @pm8001_ha: our hba card information
1345 * @circularQ: the outbound queue table.
1346 * @messagePtr1: the message contents of this outbound message.
1347 * @pBC: the message size.
1349 static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1350 struct outbound_queue_table *circularQ,
1351 void **messagePtr1, u8 *pBC)
1353 struct mpi_msg_hdr *msgHeader;
1354 __le32 msgHeader_tmp;
1357 /* If there are not-yet-delivered messages ... */
1358 if (circularQ->producer_index != circularQ->consumer_idx) {
1359 /*Get the pointer to the circular queue buffer element*/
1360 msgHeader = (struct mpi_msg_hdr *)
1361 (circularQ->base_virt +
1362 circularQ->consumer_idx * 64);
1364 header_tmp = pm8001_read_32(msgHeader);
1365 msgHeader_tmp = cpu_to_le32(header_tmp);
1366 if (0 != (msgHeader_tmp & 0x80000000)) {
1367 if (OPC_OUB_SKIP_ENTRY !=
1368 (msgHeader_tmp & 0xfff)) {
1371 sizeof(struct mpi_msg_hdr);
1372 *pBC = (u8)((msgHeader_tmp >> 24) &
1374 PM8001_IO_DBG(pm8001_ha,
1375 pm8001_printk(": CI=%d PI=%d "
1377 circularQ->consumer_idx,
1378 circularQ->producer_index,
1380 return MPI_IO_STATUS_SUCCESS;
1382 circularQ->consumer_idx =
1383 (circularQ->consumer_idx +
1384 ((msgHeader_tmp >> 24) & 0x1f))
1387 pm8001_write_32(msgHeader, 0, 0);
1388 /* update the CI of outbound queue */
1389 pm8001_cw32(pm8001_ha,
1390 circularQ->ci_pci_bar,
1391 circularQ->ci_offset,
1392 circularQ->consumer_idx);
1395 circularQ->consumer_idx =
1396 (circularQ->consumer_idx +
1397 ((msgHeader_tmp >> 24) & 0x1f)) % 256;
1399 pm8001_write_32(msgHeader, 0, 0);
1400 /* update the CI of outbound queue */
1401 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1402 circularQ->ci_offset,
1403 circularQ->consumer_idx);
1404 return MPI_IO_STATUS_FAIL;
1408 void *pi_virt = circularQ->pi_virt;
1409 /* Update the producer index from SPC */
1410 producer_index = pm8001_read_32(pi_virt);
1411 circularQ->producer_index = cpu_to_le32(producer_index);
1413 } while (circularQ->producer_index != circularQ->consumer_idx);
1414 /* while we don't have any more not-yet-delivered message */
1416 return MPI_IO_STATUS_BUSY;
1419 static void pm8001_work_fn(struct work_struct *work)
1421 struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1422 struct pm8001_device *pm8001_dev;
1423 struct domain_device *dev;
1426 * So far, all users of this stash an associated structure here.
1427 * If we get here, and this pointer is null, then the action
1428 * was cancelled. This nullification happens when the device
1431 pm8001_dev = pw->data; /* Most stash device structure */
1432 if ((pm8001_dev == NULL)
1433 || ((pw->handler != IO_XFER_ERROR_BREAK)
1434 && (pm8001_dev->dev_type == NO_DEVICE))) {
1439 switch (pw->handler) {
1440 case IO_XFER_ERROR_BREAK:
1441 { /* This one stashes the sas_task instead */
1442 struct sas_task *t = (struct sas_task *)pm8001_dev;
1444 struct pm8001_ccb_info *ccb;
1445 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1446 unsigned long flags, flags1;
1447 struct task_status_struct *ts;
1450 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1451 break; /* Task still on lu */
1452 spin_lock_irqsave(&pm8001_ha->lock, flags);
1454 spin_lock_irqsave(&t->task_state_lock, flags1);
1455 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1456 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1457 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1458 break; /* Task got completed by another */
1460 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1462 /* Search for a possible ccb that matches the task */
1463 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1464 ccb = &pm8001_ha->ccb_info[i];
1466 if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1470 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1471 break; /* Task got freed by another */
1473 ts = &t->task_status;
1474 ts->resp = SAS_TASK_COMPLETE;
1475 /* Force the midlayer to retry */
1476 ts->stat = SAS_QUEUE_FULL;
1477 pm8001_dev = ccb->device;
1479 pm8001_dev->running_req--;
1480 spin_lock_irqsave(&t->task_state_lock, flags1);
1481 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1482 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1483 t->task_state_flags |= SAS_TASK_STATE_DONE;
1484 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1485 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1486 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
1487 " done with event 0x%x resp 0x%x stat 0x%x but"
1488 " aborted by upper layer!\n",
1489 t, pw->handler, ts->resp, ts->stat));
1490 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1491 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1493 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1494 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1495 mb();/* in order to force CPU ordering */
1496 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1500 case IO_XFER_OPEN_RETRY_TIMEOUT:
1501 { /* This one stashes the sas_task instead */
1502 struct sas_task *t = (struct sas_task *)pm8001_dev;
1504 struct pm8001_ccb_info *ccb;
1505 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1506 unsigned long flags, flags1;
1509 PM8001_IO_DBG(pm8001_ha,
1510 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1512 ret = pm8001_query_task(t);
1514 PM8001_IO_DBG(pm8001_ha,
1516 case TMF_RESP_FUNC_SUCC:
1517 pm8001_printk("...Task on lu\n");
1520 case TMF_RESP_FUNC_COMPLETE:
1521 pm8001_printk("...Task NOT on lu\n");
1525 pm8001_printk("...query task failed!!!\n");
1529 spin_lock_irqsave(&pm8001_ha->lock, flags);
1531 spin_lock_irqsave(&t->task_state_lock, flags1);
1533 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1534 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1535 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1536 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1537 (void)pm8001_abort_task(t);
1538 break; /* Task got completed by another */
1541 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1543 /* Search for a possible ccb that matches the task */
1544 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1545 ccb = &pm8001_ha->ccb_info[i];
1547 if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1551 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1552 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1553 (void)pm8001_abort_task(t);
1554 break; /* Task got freed by another */
1557 pm8001_dev = ccb->device;
1558 dev = pm8001_dev->sas_device;
1561 case TMF_RESP_FUNC_SUCC: /* task on lu */
1562 ccb->open_retry = 1; /* Snub completion */
1563 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1564 ret = pm8001_abort_task(t);
1565 ccb->open_retry = 0;
1567 case TMF_RESP_FUNC_SUCC:
1568 case TMF_RESP_FUNC_COMPLETE:
1570 default: /* device misbehavior */
1571 ret = TMF_RESP_FUNC_FAILED;
1572 PM8001_IO_DBG(pm8001_ha,
1573 pm8001_printk("...Reset phy\n"));
1574 pm8001_I_T_nexus_reset(dev);
1579 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1580 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1581 /* Do we need to abort the task locally? */
1584 default: /* device misbehavior */
1585 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1586 ret = TMF_RESP_FUNC_FAILED;
1587 PM8001_IO_DBG(pm8001_ha,
1588 pm8001_printk("...Reset phy\n"));
1589 pm8001_I_T_nexus_reset(dev);
1592 if (ret == TMF_RESP_FUNC_FAILED)
1594 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1595 PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
1597 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1598 dev = pm8001_dev->sas_device;
1599 pm8001_I_T_nexus_reset(dev);
1601 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1602 dev = pm8001_dev->sas_device;
1603 pm8001_I_T_nexus_reset(dev);
1605 case IO_DS_IN_ERROR:
1606 dev = pm8001_dev->sas_device;
1607 pm8001_I_T_nexus_reset(dev);
1609 case IO_DS_NON_OPERATIONAL:
1610 dev = pm8001_dev->sas_device;
1611 pm8001_I_T_nexus_reset(dev);
1617 static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1620 struct pm8001_work *pw;
1623 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1625 pw->pm8001_ha = pm8001_ha;
1627 pw->handler = handler;
1628 INIT_WORK(&pw->work, pm8001_work_fn);
1629 queue_work(pm8001_wq, &pw->work);
1637 * mpi_ssp_completion- process the event that FW response to the SSP request.
1638 * @pm8001_ha: our hba card information
1639 * @piomb: the message contents of this outbound message.
1641 * When FW has completed a ssp request for example a IO request, after it has
1642 * filled the SG data with the data, it will trigger this event represent
1643 * that he has finished the job,please check the coresponding buffer.
1644 * So we will tell the caller who maybe waiting the result to tell upper layer
1645 * that the task has been finished.
1648 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1651 struct pm8001_ccb_info *ccb;
1652 unsigned long flags;
1656 struct ssp_completion_resp *psspPayload;
1657 struct task_status_struct *ts;
1658 struct ssp_response_iu *iu;
1659 struct pm8001_device *pm8001_dev;
1660 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1661 status = le32_to_cpu(psspPayload->status);
1662 tag = le32_to_cpu(psspPayload->tag);
1663 ccb = &pm8001_ha->ccb_info[tag];
1664 if ((status == IO_ABORTED) && ccb->open_retry) {
1665 /* Being completed by another */
1666 ccb->open_retry = 0;
1669 pm8001_dev = ccb->device;
1670 param = le32_to_cpu(psspPayload->param);
1674 if (status && status != IO_UNDERFLOW)
1675 PM8001_FAIL_DBG(pm8001_ha,
1676 pm8001_printk("sas IO status 0x%x\n", status));
1677 if (unlikely(!t || !t->lldd_task || !t->dev))
1679 ts = &t->task_status;
1682 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
1683 ",param = %d\n", param));
1685 ts->resp = SAS_TASK_COMPLETE;
1686 ts->stat = SAM_STAT_GOOD;
1688 ts->resp = SAS_TASK_COMPLETE;
1689 ts->stat = SAS_PROTO_RESPONSE;
1690 ts->residual = param;
1691 iu = &psspPayload->ssp_resp_iu;
1692 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1695 pm8001_dev->running_req--;
1698 PM8001_IO_DBG(pm8001_ha,
1699 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1700 ts->resp = SAS_TASK_COMPLETE;
1701 ts->stat = SAS_ABORTED_TASK;
1704 /* SSP Completion with error */
1705 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
1706 ",param = %d\n", param));
1707 ts->resp = SAS_TASK_COMPLETE;
1708 ts->stat = SAS_DATA_UNDERRUN;
1709 ts->residual = param;
1711 pm8001_dev->running_req--;
1714 PM8001_IO_DBG(pm8001_ha,
1715 pm8001_printk("IO_NO_DEVICE\n"));
1716 ts->resp = SAS_TASK_UNDELIVERED;
1717 ts->stat = SAS_PHY_DOWN;
1719 case IO_XFER_ERROR_BREAK:
1720 PM8001_IO_DBG(pm8001_ha,
1721 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1722 ts->resp = SAS_TASK_COMPLETE;
1723 ts->stat = SAS_OPEN_REJECT;
1724 /* Force the midlayer to retry */
1725 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1727 case IO_XFER_ERROR_PHY_NOT_READY:
1728 PM8001_IO_DBG(pm8001_ha,
1729 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1730 ts->resp = SAS_TASK_COMPLETE;
1731 ts->stat = SAS_OPEN_REJECT;
1732 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1734 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1735 PM8001_IO_DBG(pm8001_ha,
1736 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1737 ts->resp = SAS_TASK_COMPLETE;
1738 ts->stat = SAS_OPEN_REJECT;
1739 ts->open_rej_reason = SAS_OREJ_EPROTO;
1741 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1742 PM8001_IO_DBG(pm8001_ha,
1743 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1744 ts->resp = SAS_TASK_COMPLETE;
1745 ts->stat = SAS_OPEN_REJECT;
1746 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1748 case IO_OPEN_CNX_ERROR_BREAK:
1749 PM8001_IO_DBG(pm8001_ha,
1750 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1751 ts->resp = SAS_TASK_COMPLETE;
1752 ts->stat = SAS_OPEN_REJECT;
1753 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1755 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1756 PM8001_IO_DBG(pm8001_ha,
1757 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1758 ts->resp = SAS_TASK_COMPLETE;
1759 ts->stat = SAS_OPEN_REJECT;
1760 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1762 pm8001_handle_event(pm8001_ha,
1764 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1766 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1767 PM8001_IO_DBG(pm8001_ha,
1768 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1769 ts->resp = SAS_TASK_COMPLETE;
1770 ts->stat = SAS_OPEN_REJECT;
1771 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1773 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1774 PM8001_IO_DBG(pm8001_ha,
1775 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1776 "NOT_SUPPORTED\n"));
1777 ts->resp = SAS_TASK_COMPLETE;
1778 ts->stat = SAS_OPEN_REJECT;
1779 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1781 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1782 PM8001_IO_DBG(pm8001_ha,
1783 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1784 ts->resp = SAS_TASK_UNDELIVERED;
1785 ts->stat = SAS_OPEN_REJECT;
1786 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1788 case IO_XFER_ERROR_NAK_RECEIVED:
1789 PM8001_IO_DBG(pm8001_ha,
1790 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1791 ts->resp = SAS_TASK_COMPLETE;
1792 ts->stat = SAS_OPEN_REJECT;
1793 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1795 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1796 PM8001_IO_DBG(pm8001_ha,
1797 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1798 ts->resp = SAS_TASK_COMPLETE;
1799 ts->stat = SAS_NAK_R_ERR;
1801 case IO_XFER_ERROR_DMA:
1802 PM8001_IO_DBG(pm8001_ha,
1803 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1804 ts->resp = SAS_TASK_COMPLETE;
1805 ts->stat = SAS_OPEN_REJECT;
1807 case IO_XFER_OPEN_RETRY_TIMEOUT:
1808 PM8001_IO_DBG(pm8001_ha,
1809 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1810 ts->resp = SAS_TASK_COMPLETE;
1811 ts->stat = SAS_OPEN_REJECT;
1812 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1814 case IO_XFER_ERROR_OFFSET_MISMATCH:
1815 PM8001_IO_DBG(pm8001_ha,
1816 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1817 ts->resp = SAS_TASK_COMPLETE;
1818 ts->stat = SAS_OPEN_REJECT;
1820 case IO_PORT_IN_RESET:
1821 PM8001_IO_DBG(pm8001_ha,
1822 pm8001_printk("IO_PORT_IN_RESET\n"));
1823 ts->resp = SAS_TASK_COMPLETE;
1824 ts->stat = SAS_OPEN_REJECT;
1826 case IO_DS_NON_OPERATIONAL:
1827 PM8001_IO_DBG(pm8001_ha,
1828 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1829 ts->resp = SAS_TASK_COMPLETE;
1830 ts->stat = SAS_OPEN_REJECT;
1832 pm8001_handle_event(pm8001_ha,
1834 IO_DS_NON_OPERATIONAL);
1836 case IO_DS_IN_RECOVERY:
1837 PM8001_IO_DBG(pm8001_ha,
1838 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1839 ts->resp = SAS_TASK_COMPLETE;
1840 ts->stat = SAS_OPEN_REJECT;
1842 case IO_TM_TAG_NOT_FOUND:
1843 PM8001_IO_DBG(pm8001_ha,
1844 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1845 ts->resp = SAS_TASK_COMPLETE;
1846 ts->stat = SAS_OPEN_REJECT;
1848 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1849 PM8001_IO_DBG(pm8001_ha,
1850 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1851 ts->resp = SAS_TASK_COMPLETE;
1852 ts->stat = SAS_OPEN_REJECT;
1854 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1855 PM8001_IO_DBG(pm8001_ha,
1856 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1857 ts->resp = SAS_TASK_COMPLETE;
1858 ts->stat = SAS_OPEN_REJECT;
1859 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1862 PM8001_IO_DBG(pm8001_ha,
1863 pm8001_printk("Unknown status 0x%x\n", status));
1864 /* not allowed case. Therefore, return failed status */
1865 ts->resp = SAS_TASK_COMPLETE;
1866 ts->stat = SAS_OPEN_REJECT;
1869 PM8001_IO_DBG(pm8001_ha,
1870 pm8001_printk("scsi_status = %x \n ",
1871 psspPayload->ssp_resp_iu.status));
1872 spin_lock_irqsave(&t->task_state_lock, flags);
1873 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1874 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1875 t->task_state_flags |= SAS_TASK_STATE_DONE;
1876 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1877 spin_unlock_irqrestore(&t->task_state_lock, flags);
1878 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
1879 " io_status 0x%x resp 0x%x "
1880 "stat 0x%x but aborted by upper layer!\n",
1881 t, status, ts->resp, ts->stat));
1882 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1884 spin_unlock_irqrestore(&t->task_state_lock, flags);
1885 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1886 mb();/* in order to force CPU ordering */
1891 /*See the comments for mpi_ssp_completion */
1892 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1895 unsigned long flags;
1896 struct task_status_struct *ts;
1897 struct pm8001_ccb_info *ccb;
1898 struct pm8001_device *pm8001_dev;
1899 struct ssp_event_resp *psspPayload =
1900 (struct ssp_event_resp *)(piomb + 4);
1901 u32 event = le32_to_cpu(psspPayload->event);
1902 u32 tag = le32_to_cpu(psspPayload->tag);
1903 u32 port_id = le32_to_cpu(psspPayload->port_id);
1904 u32 dev_id = le32_to_cpu(psspPayload->device_id);
1906 ccb = &pm8001_ha->ccb_info[tag];
1908 pm8001_dev = ccb->device;
1910 PM8001_FAIL_DBG(pm8001_ha,
1911 pm8001_printk("sas IO status 0x%x\n", event));
1912 if (unlikely(!t || !t->lldd_task || !t->dev))
1914 ts = &t->task_status;
1915 PM8001_IO_DBG(pm8001_ha,
1916 pm8001_printk("port_id = %x,device_id = %x\n",
1920 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1921 ts->resp = SAS_TASK_COMPLETE;
1922 ts->stat = SAS_DATA_OVERRUN;
1925 pm8001_dev->running_req--;
1927 case IO_XFER_ERROR_BREAK:
1928 PM8001_IO_DBG(pm8001_ha,
1929 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1930 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1932 case IO_XFER_ERROR_PHY_NOT_READY:
1933 PM8001_IO_DBG(pm8001_ha,
1934 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1935 ts->resp = SAS_TASK_COMPLETE;
1936 ts->stat = SAS_OPEN_REJECT;
1937 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1939 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1940 PM8001_IO_DBG(pm8001_ha,
1941 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
1943 ts->resp = SAS_TASK_COMPLETE;
1944 ts->stat = SAS_OPEN_REJECT;
1945 ts->open_rej_reason = SAS_OREJ_EPROTO;
1947 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1948 PM8001_IO_DBG(pm8001_ha,
1949 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1950 ts->resp = SAS_TASK_COMPLETE;
1951 ts->stat = SAS_OPEN_REJECT;
1952 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1954 case IO_OPEN_CNX_ERROR_BREAK:
1955 PM8001_IO_DBG(pm8001_ha,
1956 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1957 ts->resp = SAS_TASK_COMPLETE;
1958 ts->stat = SAS_OPEN_REJECT;
1959 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1961 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1962 PM8001_IO_DBG(pm8001_ha,
1963 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1964 ts->resp = SAS_TASK_COMPLETE;
1965 ts->stat = SAS_OPEN_REJECT;
1966 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1968 pm8001_handle_event(pm8001_ha,
1970 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1972 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1973 PM8001_IO_DBG(pm8001_ha,
1974 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1975 ts->resp = SAS_TASK_COMPLETE;
1976 ts->stat = SAS_OPEN_REJECT;
1977 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1979 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1980 PM8001_IO_DBG(pm8001_ha,
1981 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
1982 "NOT_SUPPORTED\n"));
1983 ts->resp = SAS_TASK_COMPLETE;
1984 ts->stat = SAS_OPEN_REJECT;
1985 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1987 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1988 PM8001_IO_DBG(pm8001_ha,
1989 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1990 ts->resp = SAS_TASK_COMPLETE;
1991 ts->stat = SAS_OPEN_REJECT;
1992 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1994 case IO_XFER_ERROR_NAK_RECEIVED:
1995 PM8001_IO_DBG(pm8001_ha,
1996 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1997 ts->resp = SAS_TASK_COMPLETE;
1998 ts->stat = SAS_OPEN_REJECT;
1999 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2001 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2002 PM8001_IO_DBG(pm8001_ha,
2003 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2004 ts->resp = SAS_TASK_COMPLETE;
2005 ts->stat = SAS_NAK_R_ERR;
2007 case IO_XFER_OPEN_RETRY_TIMEOUT:
2008 PM8001_IO_DBG(pm8001_ha,
2009 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2010 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2012 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2013 PM8001_IO_DBG(pm8001_ha,
2014 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2015 ts->resp = SAS_TASK_COMPLETE;
2016 ts->stat = SAS_DATA_OVERRUN;
2018 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2019 PM8001_IO_DBG(pm8001_ha,
2020 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2021 ts->resp = SAS_TASK_COMPLETE;
2022 ts->stat = SAS_DATA_OVERRUN;
2024 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2025 PM8001_IO_DBG(pm8001_ha,
2026 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2027 ts->resp = SAS_TASK_COMPLETE;
2028 ts->stat = SAS_DATA_OVERRUN;
2030 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2031 PM8001_IO_DBG(pm8001_ha,
2032 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2033 ts->resp = SAS_TASK_COMPLETE;
2034 ts->stat = SAS_DATA_OVERRUN;
2036 case IO_XFER_ERROR_OFFSET_MISMATCH:
2037 PM8001_IO_DBG(pm8001_ha,
2038 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2039 ts->resp = SAS_TASK_COMPLETE;
2040 ts->stat = SAS_DATA_OVERRUN;
2042 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2043 PM8001_IO_DBG(pm8001_ha,
2044 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2045 ts->resp = SAS_TASK_COMPLETE;
2046 ts->stat = SAS_DATA_OVERRUN;
2048 case IO_XFER_CMD_FRAME_ISSUED:
2049 PM8001_IO_DBG(pm8001_ha,
2050 pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n"));
2053 PM8001_IO_DBG(pm8001_ha,
2054 pm8001_printk("Unknown status 0x%x\n", event));
2055 /* not allowed case. Therefore, return failed status */
2056 ts->resp = SAS_TASK_COMPLETE;
2057 ts->stat = SAS_DATA_OVERRUN;
2060 spin_lock_irqsave(&t->task_state_lock, flags);
2061 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2062 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2063 t->task_state_flags |= SAS_TASK_STATE_DONE;
2064 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2065 spin_unlock_irqrestore(&t->task_state_lock, flags);
2066 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2067 " event 0x%x resp 0x%x "
2068 "stat 0x%x but aborted by upper layer!\n",
2069 t, event, ts->resp, ts->stat));
2070 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2072 spin_unlock_irqrestore(&t->task_state_lock, flags);
2073 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2074 mb();/* in order to force CPU ordering */
2079 /*See the comments for mpi_ssp_completion */
2081 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2084 struct pm8001_ccb_info *ccb;
2088 struct sata_completion_resp *psataPayload;
2089 struct task_status_struct *ts;
2090 struct ata_task_resp *resp ;
2092 struct pm8001_device *pm8001_dev;
2094 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2095 status = le32_to_cpu(psataPayload->status);
2096 tag = le32_to_cpu(psataPayload->tag);
2098 ccb = &pm8001_ha->ccb_info[tag];
2099 param = le32_to_cpu(psataPayload->param);
2101 ts = &t->task_status;
2102 pm8001_dev = ccb->device;
2104 PM8001_FAIL_DBG(pm8001_ha,
2105 pm8001_printk("sata IO status 0x%x\n", status));
2106 if (unlikely(!t || !t->lldd_task || !t->dev))
2111 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2113 ts->resp = SAS_TASK_COMPLETE;
2114 ts->stat = SAM_STAT_GOOD;
2117 ts->resp = SAS_TASK_COMPLETE;
2118 ts->stat = SAS_PROTO_RESPONSE;
2119 ts->residual = param;
2120 PM8001_IO_DBG(pm8001_ha,
2121 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2123 sata_resp = &psataPayload->sata_resp[0];
2124 resp = (struct ata_task_resp *)ts->buf;
2125 if (t->ata_task.dma_xfer == 0 &&
2126 t->data_dir == PCI_DMA_FROMDEVICE) {
2127 len = sizeof(struct pio_setup_fis);
2128 PM8001_IO_DBG(pm8001_ha,
2129 pm8001_printk("PIO read len = %d\n", len));
2130 } else if (t->ata_task.use_ncq) {
2131 len = sizeof(struct set_dev_bits_fis);
2132 PM8001_IO_DBG(pm8001_ha,
2133 pm8001_printk("FPDMA len = %d\n", len));
2135 len = sizeof(struct dev_to_host_fis);
2136 PM8001_IO_DBG(pm8001_ha,
2137 pm8001_printk("other len = %d\n", len));
2139 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2140 resp->frame_len = len;
2141 memcpy(&resp->ending_fis[0], sata_resp, len);
2142 ts->buf_valid_size = sizeof(*resp);
2144 PM8001_IO_DBG(pm8001_ha,
2145 pm8001_printk("response to large\n"));
2148 pm8001_dev->running_req--;
2151 PM8001_IO_DBG(pm8001_ha,
2152 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2153 ts->resp = SAS_TASK_COMPLETE;
2154 ts->stat = SAS_ABORTED_TASK;
2156 pm8001_dev->running_req--;
2158 /* following cases are to do cases */
2160 /* SATA Completion with error */
2161 PM8001_IO_DBG(pm8001_ha,
2162 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2163 ts->resp = SAS_TASK_COMPLETE;
2164 ts->stat = SAS_DATA_UNDERRUN;
2165 ts->residual = param;
2167 pm8001_dev->running_req--;
2170 PM8001_IO_DBG(pm8001_ha,
2171 pm8001_printk("IO_NO_DEVICE\n"));
2172 ts->resp = SAS_TASK_UNDELIVERED;
2173 ts->stat = SAS_PHY_DOWN;
2175 case IO_XFER_ERROR_BREAK:
2176 PM8001_IO_DBG(pm8001_ha,
2177 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2178 ts->resp = SAS_TASK_COMPLETE;
2179 ts->stat = SAS_INTERRUPTED;
2181 case IO_XFER_ERROR_PHY_NOT_READY:
2182 PM8001_IO_DBG(pm8001_ha,
2183 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2184 ts->resp = SAS_TASK_COMPLETE;
2185 ts->stat = SAS_OPEN_REJECT;
2186 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2188 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2189 PM8001_IO_DBG(pm8001_ha,
2190 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2192 ts->resp = SAS_TASK_COMPLETE;
2193 ts->stat = SAS_OPEN_REJECT;
2194 ts->open_rej_reason = SAS_OREJ_EPROTO;
2196 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2197 PM8001_IO_DBG(pm8001_ha,
2198 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2199 ts->resp = SAS_TASK_COMPLETE;
2200 ts->stat = SAS_OPEN_REJECT;
2201 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2203 case IO_OPEN_CNX_ERROR_BREAK:
2204 PM8001_IO_DBG(pm8001_ha,
2205 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2206 ts->resp = SAS_TASK_COMPLETE;
2207 ts->stat = SAS_OPEN_REJECT;
2208 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2210 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2211 PM8001_IO_DBG(pm8001_ha,
2212 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2213 ts->resp = SAS_TASK_COMPLETE;
2214 ts->stat = SAS_DEV_NO_RESPONSE;
2215 if (!t->uldd_task) {
2216 pm8001_handle_event(pm8001_ha,
2218 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2219 ts->resp = SAS_TASK_UNDELIVERED;
2220 ts->stat = SAS_QUEUE_FULL;
2221 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2222 mb();/*in order to force CPU ordering*/
2223 spin_unlock_irq(&pm8001_ha->lock);
2225 spin_lock_irq(&pm8001_ha->lock);
2229 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2230 PM8001_IO_DBG(pm8001_ha,
2231 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2232 ts->resp = SAS_TASK_UNDELIVERED;
2233 ts->stat = SAS_OPEN_REJECT;
2234 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2235 if (!t->uldd_task) {
2236 pm8001_handle_event(pm8001_ha,
2238 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2239 ts->resp = SAS_TASK_UNDELIVERED;
2240 ts->stat = SAS_QUEUE_FULL;
2241 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2243 spin_unlock_irq(&pm8001_ha->lock);
2245 spin_lock_irq(&pm8001_ha->lock);
2249 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2250 PM8001_IO_DBG(pm8001_ha,
2251 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2252 "NOT_SUPPORTED\n"));
2253 ts->resp = SAS_TASK_COMPLETE;
2254 ts->stat = SAS_OPEN_REJECT;
2255 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2257 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2258 PM8001_IO_DBG(pm8001_ha,
2259 pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
2261 ts->resp = SAS_TASK_COMPLETE;
2262 ts->stat = SAS_DEV_NO_RESPONSE;
2263 if (!t->uldd_task) {
2264 pm8001_handle_event(pm8001_ha,
2266 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2267 ts->resp = SAS_TASK_UNDELIVERED;
2268 ts->stat = SAS_QUEUE_FULL;
2269 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2271 spin_unlock_irq(&pm8001_ha->lock);
2273 spin_lock_irq(&pm8001_ha->lock);
2277 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2278 PM8001_IO_DBG(pm8001_ha,
2279 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2280 ts->resp = SAS_TASK_COMPLETE;
2281 ts->stat = SAS_OPEN_REJECT;
2282 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2284 case IO_XFER_ERROR_NAK_RECEIVED:
2285 PM8001_IO_DBG(pm8001_ha,
2286 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2287 ts->resp = SAS_TASK_COMPLETE;
2288 ts->stat = SAS_NAK_R_ERR;
2290 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2291 PM8001_IO_DBG(pm8001_ha,
2292 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2293 ts->resp = SAS_TASK_COMPLETE;
2294 ts->stat = SAS_NAK_R_ERR;
2296 case IO_XFER_ERROR_DMA:
2297 PM8001_IO_DBG(pm8001_ha,
2298 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2299 ts->resp = SAS_TASK_COMPLETE;
2300 ts->stat = SAS_ABORTED_TASK;
2302 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2303 PM8001_IO_DBG(pm8001_ha,
2304 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2305 ts->resp = SAS_TASK_UNDELIVERED;
2306 ts->stat = SAS_DEV_NO_RESPONSE;
2308 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2309 PM8001_IO_DBG(pm8001_ha,
2310 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2311 ts->resp = SAS_TASK_COMPLETE;
2312 ts->stat = SAS_DATA_UNDERRUN;
2314 case IO_XFER_OPEN_RETRY_TIMEOUT:
2315 PM8001_IO_DBG(pm8001_ha,
2316 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2317 ts->resp = SAS_TASK_COMPLETE;
2318 ts->stat = SAS_OPEN_TO;
2320 case IO_PORT_IN_RESET:
2321 PM8001_IO_DBG(pm8001_ha,
2322 pm8001_printk("IO_PORT_IN_RESET\n"));
2323 ts->resp = SAS_TASK_COMPLETE;
2324 ts->stat = SAS_DEV_NO_RESPONSE;
2326 case IO_DS_NON_OPERATIONAL:
2327 PM8001_IO_DBG(pm8001_ha,
2328 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2329 ts->resp = SAS_TASK_COMPLETE;
2330 ts->stat = SAS_DEV_NO_RESPONSE;
2331 if (!t->uldd_task) {
2332 pm8001_handle_event(pm8001_ha, pm8001_dev,
2333 IO_DS_NON_OPERATIONAL);
2334 ts->resp = SAS_TASK_UNDELIVERED;
2335 ts->stat = SAS_QUEUE_FULL;
2336 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2338 spin_unlock_irq(&pm8001_ha->lock);
2340 spin_lock_irq(&pm8001_ha->lock);
2344 case IO_DS_IN_RECOVERY:
2345 PM8001_IO_DBG(pm8001_ha,
2346 pm8001_printk(" IO_DS_IN_RECOVERY\n"));
2347 ts->resp = SAS_TASK_COMPLETE;
2348 ts->stat = SAS_DEV_NO_RESPONSE;
2350 case IO_DS_IN_ERROR:
2351 PM8001_IO_DBG(pm8001_ha,
2352 pm8001_printk("IO_DS_IN_ERROR\n"));
2353 ts->resp = SAS_TASK_COMPLETE;
2354 ts->stat = SAS_DEV_NO_RESPONSE;
2355 if (!t->uldd_task) {
2356 pm8001_handle_event(pm8001_ha, pm8001_dev,
2358 ts->resp = SAS_TASK_UNDELIVERED;
2359 ts->stat = SAS_QUEUE_FULL;
2360 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2362 spin_unlock_irq(&pm8001_ha->lock);
2364 spin_lock_irq(&pm8001_ha->lock);
2368 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2369 PM8001_IO_DBG(pm8001_ha,
2370 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2371 ts->resp = SAS_TASK_COMPLETE;
2372 ts->stat = SAS_OPEN_REJECT;
2373 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2375 PM8001_IO_DBG(pm8001_ha,
2376 pm8001_printk("Unknown status 0x%x\n", status));
2377 /* not allowed case. Therefore, return failed status */
2378 ts->resp = SAS_TASK_COMPLETE;
2379 ts->stat = SAS_DEV_NO_RESPONSE;
2382 spin_lock_irq(&t->task_state_lock);
2383 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2384 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2385 t->task_state_flags |= SAS_TASK_STATE_DONE;
2386 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2387 spin_unlock_irq(&t->task_state_lock);
2388 PM8001_FAIL_DBG(pm8001_ha,
2389 pm8001_printk("task 0x%p done with io_status 0x%x"
2390 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2391 t, status, ts->resp, ts->stat));
2392 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2393 } else if (t->uldd_task) {
2394 spin_unlock_irq(&t->task_state_lock);
2395 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2397 spin_unlock_irq(&pm8001_ha->lock);
2399 spin_lock_irq(&pm8001_ha->lock);
2400 } else if (!t->uldd_task) {
2401 spin_unlock_irq(&t->task_state_lock);
2402 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2404 spin_unlock_irq(&pm8001_ha->lock);
2406 spin_lock_irq(&pm8001_ha->lock);
2410 /*See the comments for mpi_ssp_completion */
2411 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2414 struct task_status_struct *ts;
2415 struct pm8001_ccb_info *ccb;
2416 struct pm8001_device *pm8001_dev;
2417 struct sata_event_resp *psataPayload =
2418 (struct sata_event_resp *)(piomb + 4);
2419 u32 event = le32_to_cpu(psataPayload->event);
2420 u32 tag = le32_to_cpu(psataPayload->tag);
2421 u32 port_id = le32_to_cpu(psataPayload->port_id);
2422 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2424 ccb = &pm8001_ha->ccb_info[tag];
2426 pm8001_dev = ccb->device;
2428 PM8001_FAIL_DBG(pm8001_ha,
2429 pm8001_printk("sata IO status 0x%x\n", event));
2430 if (unlikely(!t || !t->lldd_task || !t->dev))
2432 ts = &t->task_status;
2433 PM8001_IO_DBG(pm8001_ha,
2434 pm8001_printk("port_id = %x,device_id = %x\n",
2438 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2439 ts->resp = SAS_TASK_COMPLETE;
2440 ts->stat = SAS_DATA_OVERRUN;
2443 pm8001_dev->running_req--;
2445 case IO_XFER_ERROR_BREAK:
2446 PM8001_IO_DBG(pm8001_ha,
2447 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2448 ts->resp = SAS_TASK_COMPLETE;
2449 ts->stat = SAS_INTERRUPTED;
2451 case IO_XFER_ERROR_PHY_NOT_READY:
2452 PM8001_IO_DBG(pm8001_ha,
2453 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2454 ts->resp = SAS_TASK_COMPLETE;
2455 ts->stat = SAS_OPEN_REJECT;
2456 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2458 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2459 PM8001_IO_DBG(pm8001_ha,
2460 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
2462 ts->resp = SAS_TASK_COMPLETE;
2463 ts->stat = SAS_OPEN_REJECT;
2464 ts->open_rej_reason = SAS_OREJ_EPROTO;
2466 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2467 PM8001_IO_DBG(pm8001_ha,
2468 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2469 ts->resp = SAS_TASK_COMPLETE;
2470 ts->stat = SAS_OPEN_REJECT;
2471 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2473 case IO_OPEN_CNX_ERROR_BREAK:
2474 PM8001_IO_DBG(pm8001_ha,
2475 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2476 ts->resp = SAS_TASK_COMPLETE;
2477 ts->stat = SAS_OPEN_REJECT;
2478 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2480 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2481 PM8001_IO_DBG(pm8001_ha,
2482 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2483 ts->resp = SAS_TASK_UNDELIVERED;
2484 ts->stat = SAS_DEV_NO_RESPONSE;
2485 if (!t->uldd_task) {
2486 pm8001_handle_event(pm8001_ha,
2488 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2489 ts->resp = SAS_TASK_COMPLETE;
2490 ts->stat = SAS_QUEUE_FULL;
2491 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2493 spin_unlock_irq(&pm8001_ha->lock);
2495 spin_lock_irq(&pm8001_ha->lock);
2499 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2500 PM8001_IO_DBG(pm8001_ha,
2501 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2502 ts->resp = SAS_TASK_UNDELIVERED;
2503 ts->stat = SAS_OPEN_REJECT;
2504 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2506 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2507 PM8001_IO_DBG(pm8001_ha,
2508 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2509 "NOT_SUPPORTED\n"));
2510 ts->resp = SAS_TASK_COMPLETE;
2511 ts->stat = SAS_OPEN_REJECT;
2512 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2514 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2515 PM8001_IO_DBG(pm8001_ha,
2516 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2517 ts->resp = SAS_TASK_COMPLETE;
2518 ts->stat = SAS_OPEN_REJECT;
2519 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2521 case IO_XFER_ERROR_NAK_RECEIVED:
2522 PM8001_IO_DBG(pm8001_ha,
2523 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2524 ts->resp = SAS_TASK_COMPLETE;
2525 ts->stat = SAS_NAK_R_ERR;
2527 case IO_XFER_ERROR_PEER_ABORTED:
2528 PM8001_IO_DBG(pm8001_ha,
2529 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2530 ts->resp = SAS_TASK_COMPLETE;
2531 ts->stat = SAS_NAK_R_ERR;
2533 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2534 PM8001_IO_DBG(pm8001_ha,
2535 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2536 ts->resp = SAS_TASK_COMPLETE;
2537 ts->stat = SAS_DATA_UNDERRUN;
2539 case IO_XFER_OPEN_RETRY_TIMEOUT:
2540 PM8001_IO_DBG(pm8001_ha,
2541 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2542 ts->resp = SAS_TASK_COMPLETE;
2543 ts->stat = SAS_OPEN_TO;
2545 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2546 PM8001_IO_DBG(pm8001_ha,
2547 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2548 ts->resp = SAS_TASK_COMPLETE;
2549 ts->stat = SAS_OPEN_TO;
2551 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2552 PM8001_IO_DBG(pm8001_ha,
2553 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2554 ts->resp = SAS_TASK_COMPLETE;
2555 ts->stat = SAS_OPEN_TO;
2557 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2558 PM8001_IO_DBG(pm8001_ha,
2559 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2560 ts->resp = SAS_TASK_COMPLETE;
2561 ts->stat = SAS_OPEN_TO;
2563 case IO_XFER_ERROR_OFFSET_MISMATCH:
2564 PM8001_IO_DBG(pm8001_ha,
2565 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2566 ts->resp = SAS_TASK_COMPLETE;
2567 ts->stat = SAS_OPEN_TO;
2569 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2570 PM8001_IO_DBG(pm8001_ha,
2571 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2572 ts->resp = SAS_TASK_COMPLETE;
2573 ts->stat = SAS_OPEN_TO;
2575 case IO_XFER_CMD_FRAME_ISSUED:
2576 PM8001_IO_DBG(pm8001_ha,
2577 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2579 case IO_XFER_PIO_SETUP_ERROR:
2580 PM8001_IO_DBG(pm8001_ha,
2581 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2582 ts->resp = SAS_TASK_COMPLETE;
2583 ts->stat = SAS_OPEN_TO;
2586 PM8001_IO_DBG(pm8001_ha,
2587 pm8001_printk("Unknown status 0x%x\n", event));
2588 /* not allowed case. Therefore, return failed status */
2589 ts->resp = SAS_TASK_COMPLETE;
2590 ts->stat = SAS_OPEN_TO;
2593 spin_lock_irq(&t->task_state_lock);
2594 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2595 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2596 t->task_state_flags |= SAS_TASK_STATE_DONE;
2597 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2598 spin_unlock_irq(&t->task_state_lock);
2599 PM8001_FAIL_DBG(pm8001_ha,
2600 pm8001_printk("task 0x%p done with io_status 0x%x"
2601 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2602 t, event, ts->resp, ts->stat));
2603 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2604 } else if (t->uldd_task) {
2605 spin_unlock_irq(&t->task_state_lock);
2606 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2608 spin_unlock_irq(&pm8001_ha->lock);
2610 spin_lock_irq(&pm8001_ha->lock);
2611 } else if (!t->uldd_task) {
2612 spin_unlock_irq(&t->task_state_lock);
2613 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2615 spin_unlock_irq(&pm8001_ha->lock);
2617 spin_lock_irq(&pm8001_ha->lock);
2621 /*See the comments for mpi_ssp_completion */
2623 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2627 struct pm8001_ccb_info *ccb;
2628 unsigned long flags;
2631 struct smp_completion_resp *psmpPayload;
2632 struct task_status_struct *ts;
2633 struct pm8001_device *pm8001_dev;
2635 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2636 status = le32_to_cpu(psmpPayload->status);
2637 tag = le32_to_cpu(psmpPayload->tag);
2639 ccb = &pm8001_ha->ccb_info[tag];
2640 param = le32_to_cpu(psmpPayload->param);
2642 ts = &t->task_status;
2643 pm8001_dev = ccb->device;
2645 PM8001_FAIL_DBG(pm8001_ha,
2646 pm8001_printk("smp IO status 0x%x\n", status));
2647 if (unlikely(!t || !t->lldd_task || !t->dev))
2652 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2653 ts->resp = SAS_TASK_COMPLETE;
2654 ts->stat = SAM_STAT_GOOD;
2656 pm8001_dev->running_req--;
2659 PM8001_IO_DBG(pm8001_ha,
2660 pm8001_printk("IO_ABORTED IOMB\n"));
2661 ts->resp = SAS_TASK_COMPLETE;
2662 ts->stat = SAS_ABORTED_TASK;
2664 pm8001_dev->running_req--;
2667 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2668 ts->resp = SAS_TASK_COMPLETE;
2669 ts->stat = SAS_DATA_OVERRUN;
2672 pm8001_dev->running_req--;
2675 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2676 ts->resp = SAS_TASK_COMPLETE;
2677 ts->stat = SAS_PHY_DOWN;
2679 case IO_ERROR_HW_TIMEOUT:
2680 PM8001_IO_DBG(pm8001_ha,
2681 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2682 ts->resp = SAS_TASK_COMPLETE;
2683 ts->stat = SAM_STAT_BUSY;
2685 case IO_XFER_ERROR_BREAK:
2686 PM8001_IO_DBG(pm8001_ha,
2687 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2688 ts->resp = SAS_TASK_COMPLETE;
2689 ts->stat = SAM_STAT_BUSY;
2691 case IO_XFER_ERROR_PHY_NOT_READY:
2692 PM8001_IO_DBG(pm8001_ha,
2693 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2694 ts->resp = SAS_TASK_COMPLETE;
2695 ts->stat = SAM_STAT_BUSY;
2697 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2698 PM8001_IO_DBG(pm8001_ha,
2699 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2700 ts->resp = SAS_TASK_COMPLETE;
2701 ts->stat = SAS_OPEN_REJECT;
2702 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2704 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2705 PM8001_IO_DBG(pm8001_ha,
2706 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2707 ts->resp = SAS_TASK_COMPLETE;
2708 ts->stat = SAS_OPEN_REJECT;
2709 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2711 case IO_OPEN_CNX_ERROR_BREAK:
2712 PM8001_IO_DBG(pm8001_ha,
2713 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2714 ts->resp = SAS_TASK_COMPLETE;
2715 ts->stat = SAS_OPEN_REJECT;
2716 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2718 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2719 PM8001_IO_DBG(pm8001_ha,
2720 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2721 ts->resp = SAS_TASK_COMPLETE;
2722 ts->stat = SAS_OPEN_REJECT;
2723 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2724 pm8001_handle_event(pm8001_ha,
2726 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2728 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2729 PM8001_IO_DBG(pm8001_ha,
2730 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2731 ts->resp = SAS_TASK_COMPLETE;
2732 ts->stat = SAS_OPEN_REJECT;
2733 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2735 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2736 PM8001_IO_DBG(pm8001_ha,
2737 pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
2738 "NOT_SUPPORTED\n"));
2739 ts->resp = SAS_TASK_COMPLETE;
2740 ts->stat = SAS_OPEN_REJECT;
2741 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2743 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2744 PM8001_IO_DBG(pm8001_ha,
2745 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2746 ts->resp = SAS_TASK_COMPLETE;
2747 ts->stat = SAS_OPEN_REJECT;
2748 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2750 case IO_XFER_ERROR_RX_FRAME:
2751 PM8001_IO_DBG(pm8001_ha,
2752 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2753 ts->resp = SAS_TASK_COMPLETE;
2754 ts->stat = SAS_DEV_NO_RESPONSE;
2756 case IO_XFER_OPEN_RETRY_TIMEOUT:
2757 PM8001_IO_DBG(pm8001_ha,
2758 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2759 ts->resp = SAS_TASK_COMPLETE;
2760 ts->stat = SAS_OPEN_REJECT;
2761 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2763 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2764 PM8001_IO_DBG(pm8001_ha,
2765 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2766 ts->resp = SAS_TASK_COMPLETE;
2767 ts->stat = SAS_QUEUE_FULL;
2769 case IO_PORT_IN_RESET:
2770 PM8001_IO_DBG(pm8001_ha,
2771 pm8001_printk("IO_PORT_IN_RESET\n"));
2772 ts->resp = SAS_TASK_COMPLETE;
2773 ts->stat = SAS_OPEN_REJECT;
2774 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2776 case IO_DS_NON_OPERATIONAL:
2777 PM8001_IO_DBG(pm8001_ha,
2778 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2779 ts->resp = SAS_TASK_COMPLETE;
2780 ts->stat = SAS_DEV_NO_RESPONSE;
2782 case IO_DS_IN_RECOVERY:
2783 PM8001_IO_DBG(pm8001_ha,
2784 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2785 ts->resp = SAS_TASK_COMPLETE;
2786 ts->stat = SAS_OPEN_REJECT;
2787 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2789 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2790 PM8001_IO_DBG(pm8001_ha,
2791 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2792 ts->resp = SAS_TASK_COMPLETE;
2793 ts->stat = SAS_OPEN_REJECT;
2794 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2797 PM8001_IO_DBG(pm8001_ha,
2798 pm8001_printk("Unknown status 0x%x\n", status));
2799 ts->resp = SAS_TASK_COMPLETE;
2800 ts->stat = SAS_DEV_NO_RESPONSE;
2801 /* not allowed case. Therefore, return failed status */
2804 spin_lock_irqsave(&t->task_state_lock, flags);
2805 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2806 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2807 t->task_state_flags |= SAS_TASK_STATE_DONE;
2808 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2809 spin_unlock_irqrestore(&t->task_state_lock, flags);
2810 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
2811 " io_status 0x%x resp 0x%x "
2812 "stat 0x%x but aborted by upper layer!\n",
2813 t, status, ts->resp, ts->stat));
2814 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2816 spin_unlock_irqrestore(&t->task_state_lock, flags);
2817 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2818 mb();/* in order to force CPU ordering */
2824 mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2826 struct set_dev_state_resp *pPayload =
2827 (struct set_dev_state_resp *)(piomb + 4);
2828 u32 tag = le32_to_cpu(pPayload->tag);
2829 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2830 struct pm8001_device *pm8001_dev = ccb->device;
2831 u32 status = le32_to_cpu(pPayload->status);
2832 u32 device_id = le32_to_cpu(pPayload->device_id);
2833 u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
2834 u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
2835 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
2836 "from 0x%x to 0x%x status = 0x%x!\n",
2837 device_id, pds, nds, status));
2838 complete(pm8001_dev->setds_completion);
2840 ccb->ccb_tag = 0xFFFFFFFF;
2841 pm8001_ccb_free(pm8001_ha, tag);
2845 mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2847 struct get_nvm_data_resp *pPayload =
2848 (struct get_nvm_data_resp *)(piomb + 4);
2849 u32 tag = le32_to_cpu(pPayload->tag);
2850 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2851 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2852 complete(pm8001_ha->nvmd_completion);
2853 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
2854 if ((dlen_status & NVMD_STAT) != 0) {
2855 PM8001_FAIL_DBG(pm8001_ha,
2856 pm8001_printk("Set nvm data error!\n"));
2860 ccb->ccb_tag = 0xFFFFFFFF;
2861 pm8001_ccb_free(pm8001_ha, tag);
2865 mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
2867 struct fw_control_ex *fw_control_context;
2868 struct get_nvm_data_resp *pPayload =
2869 (struct get_nvm_data_resp *)(piomb + 4);
2870 u32 tag = le32_to_cpu(pPayload->tag);
2871 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
2872 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
2873 u32 ir_tds_bn_dps_das_nvm =
2874 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
2875 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
2876 fw_control_context = ccb->fw_control_context;
2878 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
2879 if ((dlen_status & NVMD_STAT) != 0) {
2880 PM8001_FAIL_DBG(pm8001_ha,
2881 pm8001_printk("Get nvm data error!\n"));
2882 complete(pm8001_ha->nvmd_completion);
2886 if (ir_tds_bn_dps_das_nvm & IPMode) {
2887 /* indirect mode - IR bit set */
2888 PM8001_MSG_DBG(pm8001_ha,
2889 pm8001_printk("Get NVMD success, IR=1\n"));
2890 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
2891 if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
2892 memcpy(pm8001_ha->sas_addr,
2893 ((u8 *)virt_addr + 4),
2895 PM8001_MSG_DBG(pm8001_ha,
2896 pm8001_printk("Get SAS address"
2897 " from VPD successfully!\n"));
2899 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
2900 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
2901 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
2903 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
2904 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
2907 /* Should not be happened*/
2908 PM8001_MSG_DBG(pm8001_ha,
2909 pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
2910 ir_tds_bn_dps_das_nvm));
2912 } else /* direct mode */{
2913 PM8001_MSG_DBG(pm8001_ha,
2914 pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
2915 (dlen_status & NVMD_LEN) >> 24));
2917 memcpy(fw_control_context->usrAddr,
2918 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
2919 fw_control_context->len);
2920 complete(pm8001_ha->nvmd_completion);
2922 ccb->ccb_tag = 0xFFFFFFFF;
2923 pm8001_ccb_free(pm8001_ha, tag);
2926 static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
2928 struct local_phy_ctl_resp *pPayload =
2929 (struct local_phy_ctl_resp *)(piomb + 4);
2930 u32 status = le32_to_cpu(pPayload->status);
2931 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
2932 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
2934 PM8001_MSG_DBG(pm8001_ha,
2935 pm8001_printk("%x phy execute %x phy op failed!\n",
2938 PM8001_MSG_DBG(pm8001_ha,
2939 pm8001_printk("%x phy execute %x phy op success!\n",
2945 * pm8001_bytes_dmaed - one of the interface function communication with libsas
2946 * @pm8001_ha: our hba card information
2947 * @i: which phy that received the event.
2949 * when HBA driver received the identify done event or initiate FIS received
2950 * event(for SATA), it will invoke this function to notify the sas layer that
2951 * the sas toplogy has formed, please discover the the whole sas domain,
2952 * while receive a broadcast(change) primitive just tell the sas
2953 * layer to discover the changed domain rather than the whole domain.
2955 static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
2957 struct pm8001_phy *phy = &pm8001_ha->phy[i];
2958 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2959 struct sas_ha_struct *sas_ha;
2960 if (!phy->phy_attached)
2963 sas_ha = pm8001_ha->sas;
2965 struct sas_phy *sphy = sas_phy->phy;
2966 sphy->negotiated_linkrate = sas_phy->linkrate;
2967 sphy->minimum_linkrate = phy->minimum_linkrate;
2968 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2969 sphy->maximum_linkrate = phy->maximum_linkrate;
2970 sphy->maximum_linkrate_hw = phy->maximum_linkrate;
2973 if (phy->phy_type & PORT_TYPE_SAS) {
2974 struct sas_identify_frame *id;
2975 id = (struct sas_identify_frame *)phy->frame_rcvd;
2976 id->dev_type = phy->identify.device_type;
2977 id->initiator_bits = SAS_PROTOCOL_ALL;
2978 id->target_bits = phy->identify.target_port_protocols;
2979 } else if (phy->phy_type & PORT_TYPE_SATA) {
2982 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
2984 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
2985 pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
2988 /* Get the link rate speed */
2989 static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
2991 struct sas_phy *sas_phy = phy->sas_phy.phy;
2993 switch (link_rate) {
2995 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
2996 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
2999 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3000 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3003 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3004 phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3007 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3008 sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3009 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3010 sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3011 sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3015 * asd_get_attached_sas_addr -- extract/generate attached SAS address
3016 * @phy: pointer to asd_phy
3017 * @sas_addr: pointer to buffer where the SAS address is to be written
3019 * This function extracts the SAS address from an IDENTIFY frame
3020 * received. If OOB is SATA, then a SAS address is generated from the
3023 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3026 static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3029 if (phy->sas_phy.frame_rcvd[0] == 0x34
3030 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3031 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3032 /* FIS device-to-host */
3033 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3034 addr += phy->sas_phy.id;
3035 *(__be64 *)sas_addr = cpu_to_be64(addr);
3037 struct sas_identify_frame *idframe =
3038 (void *) phy->sas_phy.frame_rcvd;
3039 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3044 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3045 * @pm8001_ha: our hba card information
3046 * @Qnum: the outbound queue message number.
3047 * @SEA: source of event to ack
3048 * @port_id: port id.
3050 * @param0: parameter 0.
3051 * @param1: parameter 1.
3053 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3054 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3056 struct hw_event_ack_req payload;
3057 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3059 struct inbound_queue_table *circularQ;
3061 memset((u8 *)&payload, 0, sizeof(payload));
3062 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3064 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3065 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3066 payload.param0 = cpu_to_le32(param0);
3067 payload.param1 = cpu_to_le32(param1);
3068 mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
3071 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3072 u32 phyId, u32 phy_op);
3075 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3076 * @pm8001_ha: our hba card information
3077 * @piomb: IO message buffer
3080 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3082 struct hw_event_resp *pPayload =
3083 (struct hw_event_resp *)(piomb + 4);
3084 u32 lr_evt_status_phyid_portid =
3085 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3087 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3088 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3090 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3091 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3092 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3093 struct pm8001_port *port = &pm8001_ha->port[port_id];
3094 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3095 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3096 unsigned long flags;
3097 u8 deviceType = pPayload->sas_identify.dev_type;
3098 port->port_state = portstate;
3099 PM8001_MSG_DBG(pm8001_ha,
3100 pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3103 switch (deviceType) {
3104 case SAS_PHY_UNUSED:
3105 PM8001_MSG_DBG(pm8001_ha,
3106 pm8001_printk("device type no device.\n"));
3108 case SAS_END_DEVICE:
3109 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3110 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3111 PHY_NOTIFY_ENABLE_SPINUP);
3112 port->port_attached = 1;
3113 get_lrate_mode(phy, link_rate);
3115 case SAS_EDGE_EXPANDER_DEVICE:
3116 PM8001_MSG_DBG(pm8001_ha,
3117 pm8001_printk("expander device.\n"));
3118 port->port_attached = 1;
3119 get_lrate_mode(phy, link_rate);
3121 case SAS_FANOUT_EXPANDER_DEVICE:
3122 PM8001_MSG_DBG(pm8001_ha,
3123 pm8001_printk("fanout expander device.\n"));
3124 port->port_attached = 1;
3125 get_lrate_mode(phy, link_rate);
3128 PM8001_MSG_DBG(pm8001_ha,
3129 pm8001_printk("unknown device type(%x)\n", deviceType));
3132 phy->phy_type |= PORT_TYPE_SAS;
3133 phy->identify.device_type = deviceType;
3134 phy->phy_attached = 1;
3135 if (phy->identify.device_type == SAS_END_DEV)
3136 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3137 else if (phy->identify.device_type != NO_DEVICE)
3138 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3139 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3140 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3141 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3142 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3143 sizeof(struct sas_identify_frame)-4);
3144 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3145 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3146 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3147 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3148 mdelay(200);/*delay a moment to wait disk to spinup*/
3149 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3153 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3154 * @pm8001_ha: our hba card information
3155 * @piomb: IO message buffer
3158 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3160 struct hw_event_resp *pPayload =
3161 (struct hw_event_resp *)(piomb + 4);
3162 u32 lr_evt_status_phyid_portid =
3163 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3165 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3166 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3168 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3169 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3170 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3171 struct pm8001_port *port = &pm8001_ha->port[port_id];
3172 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3173 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3174 unsigned long flags;
3175 PM8001_MSG_DBG(pm8001_ha,
3176 pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
3177 " phy id = %d\n", port_id, phy_id));
3178 port->port_state = portstate;
3179 port->port_attached = 1;
3180 get_lrate_mode(phy, link_rate);
3181 phy->phy_type |= PORT_TYPE_SATA;
3182 phy->phy_attached = 1;
3183 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3184 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3185 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3186 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3187 sizeof(struct dev_to_host_fis));
3188 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3189 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3190 phy->identify.device_type = SATA_DEV;
3191 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3192 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3193 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3197 * hw_event_phy_down -we should notify the libsas the phy is down.
3198 * @pm8001_ha: our hba card information
3199 * @piomb: IO message buffer
3202 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3204 struct hw_event_resp *pPayload =
3205 (struct hw_event_resp *)(piomb + 4);
3206 u32 lr_evt_status_phyid_portid =
3207 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3208 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3210 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3211 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3212 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3213 struct pm8001_port *port = &pm8001_ha->port[port_id];
3214 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3215 port->port_state = portstate;
3217 phy->identify.device_type = 0;
3218 phy->phy_attached = 0;
3219 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3220 switch (portstate) {
3224 PM8001_MSG_DBG(pm8001_ha,
3225 pm8001_printk(" PortInvalid portID %d\n", port_id));
3226 PM8001_MSG_DBG(pm8001_ha,
3227 pm8001_printk(" Last phy Down and port invalid\n"));
3228 port->port_attached = 0;
3229 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3230 port_id, phy_id, 0, 0);
3233 PM8001_MSG_DBG(pm8001_ha,
3234 pm8001_printk(" Port In Reset portID %d\n", port_id));
3236 case PORT_NOT_ESTABLISHED:
3237 PM8001_MSG_DBG(pm8001_ha,
3238 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3239 port->port_attached = 0;
3242 PM8001_MSG_DBG(pm8001_ha,
3243 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3244 PM8001_MSG_DBG(pm8001_ha,
3245 pm8001_printk(" Last phy Down and port invalid\n"));
3246 port->port_attached = 0;
3247 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3248 port_id, phy_id, 0, 0);
3251 port->port_attached = 0;
3252 PM8001_MSG_DBG(pm8001_ha,
3253 pm8001_printk(" phy Down and(default) = %x\n",
3261 * mpi_reg_resp -process register device ID response.
3262 * @pm8001_ha: our hba card information
3263 * @piomb: IO message buffer
3265 * when sas layer find a device it will notify LLDD, then the driver register
3266 * the domain device to FW, this event is the return device ID which the FW
3267 * has assigned, from now,inter-communication with FW is no longer using the
3268 * SAS address, use device ID which FW assigned.
3270 static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3275 struct pm8001_ccb_info *ccb;
3276 struct pm8001_device *pm8001_dev;
3277 struct dev_reg_resp *registerRespPayload =
3278 (struct dev_reg_resp *)(piomb + 4);
3280 htag = le32_to_cpu(registerRespPayload->tag);
3281 ccb = &pm8001_ha->ccb_info[registerRespPayload->tag];
3282 pm8001_dev = ccb->device;
3283 status = le32_to_cpu(registerRespPayload->status);
3284 device_id = le32_to_cpu(registerRespPayload->device_id);
3285 PM8001_MSG_DBG(pm8001_ha,
3286 pm8001_printk(" register device is status = %d\n", status));
3288 case DEVREG_SUCCESS:
3289 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
3290 pm8001_dev->device_id = device_id;
3292 case DEVREG_FAILURE_OUT_OF_RESOURCE:
3293 PM8001_MSG_DBG(pm8001_ha,
3294 pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
3296 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3297 PM8001_MSG_DBG(pm8001_ha,
3298 pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
3300 case DEVREG_FAILURE_INVALID_PHY_ID:
3301 PM8001_MSG_DBG(pm8001_ha,
3302 pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
3304 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3305 PM8001_MSG_DBG(pm8001_ha,
3306 pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
3308 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3309 PM8001_MSG_DBG(pm8001_ha,
3310 pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
3312 case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3313 PM8001_MSG_DBG(pm8001_ha,
3314 pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
3316 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3317 PM8001_MSG_DBG(pm8001_ha,
3318 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
3321 PM8001_MSG_DBG(pm8001_ha,
3322 pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
3325 complete(pm8001_dev->dcompletion);
3327 ccb->ccb_tag = 0xFFFFFFFF;
3328 pm8001_ccb_free(pm8001_ha, htag);
3332 static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3336 struct dev_reg_resp *registerRespPayload =
3337 (struct dev_reg_resp *)(piomb + 4);
3339 status = le32_to_cpu(registerRespPayload->status);
3340 device_id = le32_to_cpu(registerRespPayload->device_id);
3342 PM8001_MSG_DBG(pm8001_ha,
3343 pm8001_printk(" deregister device failed ,status = %x"
3344 ", device_id = %x\n", status, device_id));
3349 mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3352 struct fw_control_ex fw_control_context;
3353 struct fw_flash_Update_resp *ppayload =
3354 (struct fw_flash_Update_resp *)(piomb + 4);
3355 u32 tag = le32_to_cpu(ppayload->tag);
3356 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3357 status = le32_to_cpu(ppayload->status);
3358 memcpy(&fw_control_context,
3359 ccb->fw_control_context,
3360 sizeof(fw_control_context));
3362 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3363 PM8001_MSG_DBG(pm8001_ha,
3364 pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
3366 case FLASH_UPDATE_IN_PROGRESS:
3367 PM8001_MSG_DBG(pm8001_ha,
3368 pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
3370 case FLASH_UPDATE_HDR_ERR:
3371 PM8001_MSG_DBG(pm8001_ha,
3372 pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
3374 case FLASH_UPDATE_OFFSET_ERR:
3375 PM8001_MSG_DBG(pm8001_ha,
3376 pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
3378 case FLASH_UPDATE_CRC_ERR:
3379 PM8001_MSG_DBG(pm8001_ha,
3380 pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
3382 case FLASH_UPDATE_LENGTH_ERR:
3383 PM8001_MSG_DBG(pm8001_ha,
3384 pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
3386 case FLASH_UPDATE_HW_ERR:
3387 PM8001_MSG_DBG(pm8001_ha,
3388 pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
3390 case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3391 PM8001_MSG_DBG(pm8001_ha,
3392 pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
3394 case FLASH_UPDATE_DISABLED:
3395 PM8001_MSG_DBG(pm8001_ha,
3396 pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
3399 PM8001_MSG_DBG(pm8001_ha,
3400 pm8001_printk("No matched status = %d\n", status));
3403 ccb->fw_control_context->fw_control->retcode = status;
3404 pci_free_consistent(pm8001_ha->pdev,
3405 fw_control_context.len,
3406 fw_control_context.virtAddr,
3407 fw_control_context.phys_addr);
3408 complete(pm8001_ha->nvmd_completion);
3410 ccb->ccb_tag = 0xFFFFFFFF;
3411 pm8001_ccb_free(pm8001_ha, tag);
3416 mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
3420 struct general_event_resp *pPayload =
3421 (struct general_event_resp *)(piomb + 4);
3422 status = le32_to_cpu(pPayload->status);
3423 PM8001_MSG_DBG(pm8001_ha,
3424 pm8001_printk(" status = 0x%x\n", status));
3425 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3426 PM8001_MSG_DBG(pm8001_ha,
3427 pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
3428 pPayload->inb_IOMB_payload[i]));
3433 mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3436 struct pm8001_ccb_info *ccb;
3437 unsigned long flags;
3440 struct task_status_struct *ts;
3442 struct task_abort_resp *pPayload =
3443 (struct task_abort_resp *)(piomb + 4);
3444 ccb = &pm8001_ha->ccb_info[pPayload->tag];
3448 status = le32_to_cpu(pPayload->status);
3449 tag = le32_to_cpu(pPayload->tag);
3450 scp = le32_to_cpu(pPayload->scp);
3451 PM8001_IO_DBG(pm8001_ha,
3452 pm8001_printk(" status = 0x%x\n", status));
3455 ts = &t->task_status;
3457 PM8001_FAIL_DBG(pm8001_ha,
3458 pm8001_printk("task abort failed status 0x%x ,"
3459 "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
3462 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
3463 ts->resp = SAS_TASK_COMPLETE;
3464 ts->stat = SAM_STAT_GOOD;
3467 PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
3468 ts->resp = TMF_RESP_FUNC_FAILED;
3471 spin_lock_irqsave(&t->task_state_lock, flags);
3472 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3473 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3474 t->task_state_flags |= SAS_TASK_STATE_DONE;
3475 spin_unlock_irqrestore(&t->task_state_lock, flags);
3476 pm8001_ccb_task_free(pm8001_ha, t, ccb, pPayload->tag);
3483 * mpi_hw_event -The hw event has come.
3484 * @pm8001_ha: our hba card information
3485 * @piomb: IO message buffer
3487 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
3489 unsigned long flags;
3490 struct hw_event_resp *pPayload =
3491 (struct hw_event_resp *)(piomb + 4);
3492 u32 lr_evt_status_phyid_portid =
3493 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3494 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3496 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3498 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3500 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3501 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3502 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3503 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3504 PM8001_MSG_DBG(pm8001_ha,
3505 pm8001_printk("outbound queue HW event & event type : "));
3506 switch (eventType) {
3507 case HW_EVENT_PHY_START_STATUS:
3508 PM8001_MSG_DBG(pm8001_ha,
3509 pm8001_printk("HW_EVENT_PHY_START_STATUS"
3510 " status = %x\n", status));
3513 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3514 complete(phy->enable_completion);
3517 case HW_EVENT_SAS_PHY_UP:
3518 PM8001_MSG_DBG(pm8001_ha,
3519 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3520 hw_event_sas_phy_up(pm8001_ha, piomb);
3522 case HW_EVENT_SATA_PHY_UP:
3523 PM8001_MSG_DBG(pm8001_ha,
3524 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3525 hw_event_sata_phy_up(pm8001_ha, piomb);
3527 case HW_EVENT_PHY_STOP_STATUS:
3528 PM8001_MSG_DBG(pm8001_ha,
3529 pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
3530 "status = %x\n", status));
3534 case HW_EVENT_SATA_SPINUP_HOLD:
3535 PM8001_MSG_DBG(pm8001_ha,
3536 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3537 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3539 case HW_EVENT_PHY_DOWN:
3540 PM8001_MSG_DBG(pm8001_ha,
3541 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3542 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3543 phy->phy_attached = 0;
3545 hw_event_phy_down(pm8001_ha, piomb);
3547 case HW_EVENT_PORT_INVALID:
3548 PM8001_MSG_DBG(pm8001_ha,
3549 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3550 sas_phy_disconnected(sas_phy);
3551 phy->phy_attached = 0;
3552 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3554 /* the broadcast change primitive received, tell the LIBSAS this event
3555 to revalidate the sas domain*/
3556 case HW_EVENT_BROADCAST_CHANGE:
3557 PM8001_MSG_DBG(pm8001_ha,
3558 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3559 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3560 port_id, phy_id, 1, 0);
3561 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3562 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3563 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3564 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3566 case HW_EVENT_PHY_ERROR:
3567 PM8001_MSG_DBG(pm8001_ha,
3568 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3569 sas_phy_disconnected(&phy->sas_phy);
3570 phy->phy_attached = 0;
3571 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3573 case HW_EVENT_BROADCAST_EXP:
3574 PM8001_MSG_DBG(pm8001_ha,
3575 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3576 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3577 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3578 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3579 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3581 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3582 PM8001_MSG_DBG(pm8001_ha,
3583 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3584 pm8001_hw_event_ack_req(pm8001_ha, 0,
3585 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3586 sas_phy_disconnected(sas_phy);
3587 phy->phy_attached = 0;
3588 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3590 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3591 PM8001_MSG_DBG(pm8001_ha,
3592 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3593 pm8001_hw_event_ack_req(pm8001_ha, 0,
3594 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3595 port_id, phy_id, 0, 0);
3596 sas_phy_disconnected(sas_phy);
3597 phy->phy_attached = 0;
3598 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3600 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3601 PM8001_MSG_DBG(pm8001_ha,
3602 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3603 pm8001_hw_event_ack_req(pm8001_ha, 0,
3604 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3605 port_id, phy_id, 0, 0);
3606 sas_phy_disconnected(sas_phy);
3607 phy->phy_attached = 0;
3608 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3610 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3611 PM8001_MSG_DBG(pm8001_ha,
3612 pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3613 pm8001_hw_event_ack_req(pm8001_ha, 0,
3614 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3615 port_id, phy_id, 0, 0);
3616 sas_phy_disconnected(sas_phy);
3617 phy->phy_attached = 0;
3618 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3620 case HW_EVENT_MALFUNCTION:
3621 PM8001_MSG_DBG(pm8001_ha,
3622 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3624 case HW_EVENT_BROADCAST_SES:
3625 PM8001_MSG_DBG(pm8001_ha,
3626 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3627 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3628 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3629 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3630 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3632 case HW_EVENT_INBOUND_CRC_ERROR:
3633 PM8001_MSG_DBG(pm8001_ha,
3634 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3635 pm8001_hw_event_ack_req(pm8001_ha, 0,
3636 HW_EVENT_INBOUND_CRC_ERROR,
3637 port_id, phy_id, 0, 0);
3639 case HW_EVENT_HARD_RESET_RECEIVED:
3640 PM8001_MSG_DBG(pm8001_ha,
3641 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3642 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3644 case HW_EVENT_ID_FRAME_TIMEOUT:
3645 PM8001_MSG_DBG(pm8001_ha,
3646 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3647 sas_phy_disconnected(sas_phy);
3648 phy->phy_attached = 0;
3649 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3651 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3652 PM8001_MSG_DBG(pm8001_ha,
3653 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3654 pm8001_hw_event_ack_req(pm8001_ha, 0,
3655 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3656 port_id, phy_id, 0, 0);
3657 sas_phy_disconnected(sas_phy);
3658 phy->phy_attached = 0;
3659 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3661 case HW_EVENT_PORT_RESET_TIMER_TMO:
3662 PM8001_MSG_DBG(pm8001_ha,
3663 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3664 sas_phy_disconnected(sas_phy);
3665 phy->phy_attached = 0;
3666 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3668 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3669 PM8001_MSG_DBG(pm8001_ha,
3670 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3671 sas_phy_disconnected(sas_phy);
3672 phy->phy_attached = 0;
3673 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3675 case HW_EVENT_PORT_RECOVER:
3676 PM8001_MSG_DBG(pm8001_ha,
3677 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3679 case HW_EVENT_PORT_RESET_COMPLETE:
3680 PM8001_MSG_DBG(pm8001_ha,
3681 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3683 case EVENT_BROADCAST_ASYNCH_EVENT:
3684 PM8001_MSG_DBG(pm8001_ha,
3685 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3688 PM8001_MSG_DBG(pm8001_ha,
3689 pm8001_printk("Unknown event type = %x\n", eventType));
3696 * process_one_iomb - process one outbound Queue memory block
3697 * @pm8001_ha: our hba card information
3698 * @piomb: IO message buffer
3700 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3702 u32 pHeader = (u32)*(u32 *)piomb;
3703 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3705 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
3709 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3711 case OPC_OUB_HW_EVENT:
3712 PM8001_MSG_DBG(pm8001_ha,
3713 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3714 mpi_hw_event(pm8001_ha, piomb);
3716 case OPC_OUB_SSP_COMP:
3717 PM8001_MSG_DBG(pm8001_ha,
3718 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3719 mpi_ssp_completion(pm8001_ha, piomb);
3721 case OPC_OUB_SMP_COMP:
3722 PM8001_MSG_DBG(pm8001_ha,
3723 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3724 mpi_smp_completion(pm8001_ha, piomb);
3726 case OPC_OUB_LOCAL_PHY_CNTRL:
3727 PM8001_MSG_DBG(pm8001_ha,
3728 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3729 mpi_local_phy_ctl(pm8001_ha, piomb);
3731 case OPC_OUB_DEV_REGIST:
3732 PM8001_MSG_DBG(pm8001_ha,
3733 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3734 mpi_reg_resp(pm8001_ha, piomb);
3736 case OPC_OUB_DEREG_DEV:
3737 PM8001_MSG_DBG(pm8001_ha,
3738 pm8001_printk("unresgister the deviece\n"));
3739 mpi_dereg_resp(pm8001_ha, piomb);
3741 case OPC_OUB_GET_DEV_HANDLE:
3742 PM8001_MSG_DBG(pm8001_ha,
3743 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3745 case OPC_OUB_SATA_COMP:
3746 PM8001_MSG_DBG(pm8001_ha,
3747 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3748 mpi_sata_completion(pm8001_ha, piomb);
3750 case OPC_OUB_SATA_EVENT:
3751 PM8001_MSG_DBG(pm8001_ha,
3752 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3753 mpi_sata_event(pm8001_ha, piomb);
3755 case OPC_OUB_SSP_EVENT:
3756 PM8001_MSG_DBG(pm8001_ha,
3757 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3758 mpi_ssp_event(pm8001_ha, piomb);
3760 case OPC_OUB_DEV_HANDLE_ARRIV:
3761 PM8001_MSG_DBG(pm8001_ha,
3762 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3763 /*This is for target*/
3765 case OPC_OUB_SSP_RECV_EVENT:
3766 PM8001_MSG_DBG(pm8001_ha,
3767 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3768 /*This is for target*/
3770 case OPC_OUB_DEV_INFO:
3771 PM8001_MSG_DBG(pm8001_ha,
3772 pm8001_printk("OPC_OUB_DEV_INFO\n"));
3774 case OPC_OUB_FW_FLASH_UPDATE:
3775 PM8001_MSG_DBG(pm8001_ha,
3776 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3777 mpi_fw_flash_update_resp(pm8001_ha, piomb);
3779 case OPC_OUB_GPIO_RESPONSE:
3780 PM8001_MSG_DBG(pm8001_ha,
3781 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3783 case OPC_OUB_GPIO_EVENT:
3784 PM8001_MSG_DBG(pm8001_ha,
3785 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3787 case OPC_OUB_GENERAL_EVENT:
3788 PM8001_MSG_DBG(pm8001_ha,
3789 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3790 mpi_general_event(pm8001_ha, piomb);
3792 case OPC_OUB_SSP_ABORT_RSP:
3793 PM8001_MSG_DBG(pm8001_ha,
3794 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3795 mpi_task_abort_resp(pm8001_ha, piomb);
3797 case OPC_OUB_SATA_ABORT_RSP:
3798 PM8001_MSG_DBG(pm8001_ha,
3799 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3800 mpi_task_abort_resp(pm8001_ha, piomb);
3802 case OPC_OUB_SAS_DIAG_MODE_START_END:
3803 PM8001_MSG_DBG(pm8001_ha,
3804 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3806 case OPC_OUB_SAS_DIAG_EXECUTE:
3807 PM8001_MSG_DBG(pm8001_ha,
3808 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3810 case OPC_OUB_GET_TIME_STAMP:
3811 PM8001_MSG_DBG(pm8001_ha,
3812 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3814 case OPC_OUB_SAS_HW_EVENT_ACK:
3815 PM8001_MSG_DBG(pm8001_ha,
3816 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3818 case OPC_OUB_PORT_CONTROL:
3819 PM8001_MSG_DBG(pm8001_ha,
3820 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3822 case OPC_OUB_SMP_ABORT_RSP:
3823 PM8001_MSG_DBG(pm8001_ha,
3824 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3825 mpi_task_abort_resp(pm8001_ha, piomb);
3827 case OPC_OUB_GET_NVMD_DATA:
3828 PM8001_MSG_DBG(pm8001_ha,
3829 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3830 mpi_get_nvmd_resp(pm8001_ha, piomb);
3832 case OPC_OUB_SET_NVMD_DATA:
3833 PM8001_MSG_DBG(pm8001_ha,
3834 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3835 mpi_set_nvmd_resp(pm8001_ha, piomb);
3837 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3838 PM8001_MSG_DBG(pm8001_ha,
3839 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3841 case OPC_OUB_SET_DEVICE_STATE:
3842 PM8001_MSG_DBG(pm8001_ha,
3843 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3844 mpi_set_dev_state_resp(pm8001_ha, piomb);
3846 case OPC_OUB_GET_DEVICE_STATE:
3847 PM8001_MSG_DBG(pm8001_ha,
3848 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3850 case OPC_OUB_SET_DEV_INFO:
3851 PM8001_MSG_DBG(pm8001_ha,
3852 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3854 case OPC_OUB_SAS_RE_INITIALIZE:
3855 PM8001_MSG_DBG(pm8001_ha,
3856 pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
3859 PM8001_MSG_DBG(pm8001_ha,
3860 pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
3866 static int process_oq(struct pm8001_hba_info *pm8001_ha)
3868 struct outbound_queue_table *circularQ;
3871 u32 ret = MPI_IO_STATUS_FAIL;
3872 unsigned long flags;
3874 spin_lock_irqsave(&pm8001_ha->lock, flags);
3875 circularQ = &pm8001_ha->outbnd_q_tbl[0];
3877 ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3878 if (MPI_IO_STATUS_SUCCESS == ret) {
3879 /* process the outbound message */
3880 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3881 /* free the message from the outbound circular buffer */
3882 mpi_msg_free_set(pm8001_ha, pMsg1, circularQ, bc);
3884 if (MPI_IO_STATUS_BUSY == ret) {
3886 /* Update the producer index from SPC */
3887 producer_idx = pm8001_read_32(circularQ->pi_virt);
3888 circularQ->producer_index = cpu_to_le32(producer_idx);
3889 if (circularQ->producer_index ==
3890 circularQ->consumer_idx)
3895 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3899 /* PCI_DMA_... to our direction translation. */
3900 static const u8 data_dir_flags[] = {
3901 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3902 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3903 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3904 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3907 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
3910 struct scatterlist *sg;
3911 struct pm8001_prd *buf_prd = prd;
3913 for_each_sg(scatter, sg, nr, i) {
3914 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
3915 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
3916 buf_prd->im_len.e = 0;
3921 static void build_smp_cmd(u32 deviceID, u32 hTag, struct smp_req *psmp_cmd)
3923 psmp_cmd->tag = cpu_to_le32(hTag);
3924 psmp_cmd->device_id = cpu_to_le32(deviceID);
3925 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3929 * pm8001_chip_smp_req - send a SMP task to FW
3930 * @pm8001_ha: our hba card information.
3931 * @ccb: the ccb information this request used.
3933 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3934 struct pm8001_ccb_info *ccb)
3937 struct sas_task *task = ccb->task;
3938 struct domain_device *dev = task->dev;
3939 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3940 struct scatterlist *sg_req, *sg_resp;
3941 u32 req_len, resp_len;
3942 struct smp_req smp_cmd;
3944 struct inbound_queue_table *circularQ;
3946 memset(&smp_cmd, 0, sizeof(smp_cmd));
3948 * DMA-map SMP request, response buffers
3950 sg_req = &task->smp_task.smp_req;
3951 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3954 req_len = sg_dma_len(sg_req);
3956 sg_resp = &task->smp_task.smp_resp;
3957 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3962 resp_len = sg_dma_len(sg_resp);
3963 /* must be in dwords */
3964 if ((req_len & 0x3) || (resp_len & 0x3)) {
3969 opc = OPC_INB_SMP_REQUEST;
3970 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3971 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3972 smp_cmd.long_smp_req.long_req_addr =
3973 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3974 smp_cmd.long_smp_req.long_req_size =
3975 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3976 smp_cmd.long_smp_req.long_resp_addr =
3977 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
3978 smp_cmd.long_smp_req.long_resp_size =
3979 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3980 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
3981 mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd);
3985 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3986 PCI_DMA_FROMDEVICE);
3988 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3994 * pm8001_chip_ssp_io_req - send a SSP task to FW
3995 * @pm8001_ha: our hba card information.
3996 * @ccb: the ccb information this request used.
3998 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3999 struct pm8001_ccb_info *ccb)
4001 struct sas_task *task = ccb->task;
4002 struct domain_device *dev = task->dev;
4003 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4004 struct ssp_ini_io_start_req ssp_cmd;
4005 u32 tag = ccb->ccb_tag;
4008 struct inbound_queue_table *circularQ;
4009 u32 opc = OPC_INB_SSPINIIOSTART;
4010 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4011 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4013 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4014 SAS 1.1 compatible TLR*/
4015 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4016 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4017 ssp_cmd.tag = cpu_to_le32(tag);
4018 if (task->ssp_task.enable_first_burst)
4019 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4020 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4021 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4022 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
4023 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4025 /* fill in PRD (scatter/gather) table, if any */
4026 if (task->num_scatter > 1) {
4027 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4028 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
4029 offsetof(struct pm8001_ccb_info, buf_prd[0]));
4030 ssp_cmd.addr_low = lower_32_bits(phys_addr);
4031 ssp_cmd.addr_high = upper_32_bits(phys_addr);
4032 ssp_cmd.esgl = cpu_to_le32(1<<31);
4033 } else if (task->num_scatter == 1) {
4034 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
4035 ssp_cmd.addr_low = lower_32_bits(dma_addr);
4036 ssp_cmd.addr_high = upper_32_bits(dma_addr);
4037 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4039 } else if (task->num_scatter == 0) {
4040 ssp_cmd.addr_low = 0;
4041 ssp_cmd.addr_high = 0;
4042 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4045 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd);
4049 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4050 struct pm8001_ccb_info *ccb)
4052 struct sas_task *task = ccb->task;
4053 struct domain_device *dev = task->dev;
4054 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4055 u32 tag = ccb->ccb_tag;
4057 struct sata_start_req sata_cmd;
4058 u32 hdr_tag, ncg_tag = 0;
4062 struct inbound_queue_table *circularQ;
4063 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4064 memset(&sata_cmd, 0, sizeof(sata_cmd));
4065 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4066 if (task->data_dir == PCI_DMA_NONE) {
4067 ATAP = 0x04; /* no data*/
4068 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4069 } else if (likely(!task->ata_task.device_control_reg_update)) {
4070 if (task->ata_task.dma_xfer) {
4071 ATAP = 0x06; /* DMA */
4072 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4074 ATAP = 0x05; /* PIO*/
4075 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4077 if (task->ata_task.use_ncq &&
4078 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
4079 ATAP = 0x07; /* FPDMA */
4080 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4083 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
4085 dir = data_dir_flags[task->data_dir] << 8;
4086 sata_cmd.tag = cpu_to_le32(tag);
4087 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4088 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4089 sata_cmd.ncqtag_atap_dir_m =
4090 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4091 sata_cmd.sata_fis = task->ata_task.fis;
4092 if (likely(!task->ata_task.device_control_reg_update))
4093 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4094 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4095 /* fill in PRD (scatter/gather) table, if any */
4096 if (task->num_scatter > 1) {
4097 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4098 phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
4099 offsetof(struct pm8001_ccb_info, buf_prd[0]));
4100 sata_cmd.addr_low = lower_32_bits(phys_addr);
4101 sata_cmd.addr_high = upper_32_bits(phys_addr);
4102 sata_cmd.esgl = cpu_to_le32(1 << 31);
4103 } else if (task->num_scatter == 1) {
4104 __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
4105 sata_cmd.addr_low = lower_32_bits(dma_addr);
4106 sata_cmd.addr_high = upper_32_bits(dma_addr);
4107 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4109 } else if (task->num_scatter == 0) {
4110 sata_cmd.addr_low = 0;
4111 sata_cmd.addr_high = 0;
4112 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4115 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd);
4120 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4121 * @pm8001_ha: our hba card information.
4122 * @num: the inbound queue number
4123 * @phy_id: the phy id which we wanted to start up.
4126 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4128 struct phy_start_req payload;
4129 struct inbound_queue_table *circularQ;
4132 u32 opcode = OPC_INB_PHYSTART;
4133 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4134 memset(&payload, 0, sizeof(payload));
4135 payload.tag = cpu_to_le32(tag);
4137 ** [0:7] PHY Identifier
4138 ** [8:11] link rate 1.5G, 3G, 6G
4139 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4140 ** [14] 0b disable spin up hold; 1b enable spin up hold
4142 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4143 LINKMODE_AUTO | LINKRATE_15 |
4144 LINKRATE_30 | LINKRATE_60 | phy_id);
4145 payload.sas_identify.dev_type = SAS_END_DEV;
4146 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4147 memcpy(payload.sas_identify.sas_addr,
4148 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4149 payload.sas_identify.phy_id = phy_id;
4150 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
4155 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4156 * @pm8001_ha: our hba card information.
4157 * @num: the inbound queue number
4158 * @phy_id: the phy id which we wanted to start up.
4160 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4163 struct phy_stop_req payload;
4164 struct inbound_queue_table *circularQ;
4167 u32 opcode = OPC_INB_PHYSTOP;
4168 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4169 memset(&payload, 0, sizeof(payload));
4170 payload.tag = cpu_to_le32(tag);
4171 payload.phy_id = cpu_to_le32(phy_id);
4172 ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
4177 * see comments on mpi_reg_resp.
4179 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4180 struct pm8001_device *pm8001_dev, u32 flag)
4182 struct reg_dev_req payload;
4184 u32 stp_sspsmp_sata = 0x4;
4185 struct inbound_queue_table *circularQ;
4186 u32 linkrate, phy_id;
4187 int rc, tag = 0xdeadbeef;
4188 struct pm8001_ccb_info *ccb;
4190 u16 firstBurstSize = 0;
4192 struct domain_device *dev = pm8001_dev->sas_device;
4193 struct domain_device *parent_dev = dev->parent;
4194 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4196 memset(&payload, 0, sizeof(payload));
4197 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4200 ccb = &pm8001_ha->ccb_info[tag];
4201 ccb->device = pm8001_dev;
4203 payload.tag = cpu_to_le32(tag);
4205 stp_sspsmp_sata = 0x02; /*direct attached sata */
4207 if (pm8001_dev->dev_type == SATA_DEV)
4208 stp_sspsmp_sata = 0x00; /* stp*/
4209 else if (pm8001_dev->dev_type == SAS_END_DEV ||
4210 pm8001_dev->dev_type == EDGE_DEV ||
4211 pm8001_dev->dev_type == FANOUT_DEV)
4212 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4214 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4215 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4217 phy_id = pm8001_dev->attached_phy;
4218 opc = OPC_INB_REG_DEV;
4219 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4220 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4221 payload.phyid_portid =
4222 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
4223 ((phy_id & 0x0F) << 4));
4224 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4225 ((linkrate & 0x0F) * 0x1000000) |
4226 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4227 payload.firstburstsize_ITNexustimeout =
4228 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4229 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4231 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4236 * see comments on mpi_reg_resp.
4238 static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4241 struct dereg_dev_req payload;
4242 u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4244 struct inbound_queue_table *circularQ;
4246 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4247 memset(&payload, 0, sizeof(payload));
4249 payload.device_id = cpu_to_le32(device_id);
4250 PM8001_MSG_DBG(pm8001_ha,
4251 pm8001_printk("unregister device device_id = %d\n", device_id));
4252 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4257 * pm8001_chip_phy_ctl_req - support the local phy operation
4258 * @pm8001_ha: our hba card information.
4259 * @num: the inbound queue number
4260 * @phy_id: the phy id which we wanted to operate
4263 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4264 u32 phyId, u32 phy_op)
4266 struct local_phy_ctl_req payload;
4267 struct inbound_queue_table *circularQ;
4269 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4270 memset(&payload, 0, sizeof(payload));
4271 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4273 payload.phyop_phyid =
4274 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4275 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4279 static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4282 #ifdef PM8001_USE_MSIX
4285 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4293 * pm8001_chip_isr - PM8001 isr handler.
4294 * @pm8001_ha: our hba card information.
4299 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha)
4301 pm8001_chip_interrupt_disable(pm8001_ha);
4302 process_oq(pm8001_ha);
4303 pm8001_chip_interrupt_enable(pm8001_ha);
4307 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4308 u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
4310 struct task_abort_req task_abort;
4311 struct inbound_queue_table *circularQ;
4313 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4314 memset(&task_abort, 0, sizeof(task_abort));
4315 if (ABORT_SINGLE == (flag & ABORT_MASK)) {
4316 task_abort.abort_all = 0;
4317 task_abort.device_id = cpu_to_le32(dev_id);
4318 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4319 task_abort.tag = cpu_to_le32(cmd_tag);
4320 } else if (ABORT_ALL == (flag & ABORT_MASK)) {
4321 task_abort.abort_all = cpu_to_le32(1);
4322 task_abort.device_id = cpu_to_le32(dev_id);
4323 task_abort.tag = cpu_to_le32(cmd_tag);
4325 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort);
4330 * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4331 * @task: the task we wanted to aborted.
4332 * @flag: the abort flag.
4334 static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4335 struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
4338 int rc = TMF_RESP_FUNC_FAILED;
4339 PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag"
4340 " = %x", cmd_tag, task_tag));
4341 if (pm8001_dev->dev_type == SAS_END_DEV)
4342 opc = OPC_INB_SSP_ABORT;
4343 else if (pm8001_dev->dev_type == SATA_DEV)
4344 opc = OPC_INB_SATA_ABORT;
4346 opc = OPC_INB_SMP_ABORT;/* SMP */
4347 device_id = pm8001_dev->device_id;
4348 rc = send_task_abort(pm8001_ha, opc, device_id, flag,
4350 if (rc != TMF_RESP_FUNC_COMPLETE)
4351 PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
4356 * pm8001_chip_ssp_tm_req - built the task management command.
4357 * @pm8001_ha: our hba card information.
4358 * @ccb: the ccb information.
4359 * @tmf: task management function.
4361 static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4362 struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
4364 struct sas_task *task = ccb->task;
4365 struct domain_device *dev = task->dev;
4366 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4367 u32 opc = OPC_INB_SSPINITMSTART;
4368 struct inbound_queue_table *circularQ;
4369 struct ssp_ini_tm_start_req sspTMCmd;
4372 memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4373 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4374 sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
4375 sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4376 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4377 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4378 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4379 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd);
4383 static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4386 u32 opc = OPC_INB_GET_NVMD_DATA;
4390 struct pm8001_ccb_info *ccb;
4391 struct inbound_queue_table *circularQ;
4392 struct get_nvm_data_req nvmd_req;
4393 struct fw_control_ex *fw_control_context;
4394 struct pm8001_ioctl_payload *ioctl_payload = payload;
4396 nvmd_type = ioctl_payload->minor_function;
4397 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4398 if (!fw_control_context)
4400 fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0];
4401 fw_control_context->len = ioctl_payload->length;
4402 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4403 memset(&nvmd_req, 0, sizeof(nvmd_req));
4404 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4406 kfree(fw_control_context);
4409 ccb = &pm8001_ha->ccb_info[tag];
4411 ccb->fw_control_context = fw_control_context;
4412 nvmd_req.tag = cpu_to_le32(tag);
4414 switch (nvmd_type) {
4416 u32 twi_addr, twi_page_size;
4420 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4421 twi_page_size << 8 | TWI_DEVICE);
4422 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4423 nvmd_req.resp_addr_hi =
4424 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4425 nvmd_req.resp_addr_lo =
4426 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4430 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4431 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4432 nvmd_req.resp_addr_hi =
4433 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4434 nvmd_req.resp_addr_lo =
4435 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4439 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4440 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4441 nvmd_req.resp_addr_hi =
4442 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4443 nvmd_req.resp_addr_lo =
4444 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4448 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4449 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4450 nvmd_req.resp_addr_hi =
4451 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4452 nvmd_req.resp_addr_lo =
4453 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4459 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4463 static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4466 u32 opc = OPC_INB_SET_NVMD_DATA;
4470 struct pm8001_ccb_info *ccb;
4471 struct inbound_queue_table *circularQ;
4472 struct set_nvm_data_req nvmd_req;
4473 struct fw_control_ex *fw_control_context;
4474 struct pm8001_ioctl_payload *ioctl_payload = payload;
4476 nvmd_type = ioctl_payload->minor_function;
4477 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4478 if (!fw_control_context)
4480 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4481 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4482 ioctl_payload->func_specific,
4483 ioctl_payload->length);
4484 memset(&nvmd_req, 0, sizeof(nvmd_req));
4485 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4487 kfree(fw_control_context);
4490 ccb = &pm8001_ha->ccb_info[tag];
4491 ccb->fw_control_context = fw_control_context;
4493 nvmd_req.tag = cpu_to_le32(tag);
4494 switch (nvmd_type) {
4496 u32 twi_addr, twi_page_size;
4499 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4500 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4501 twi_page_size << 8 | TWI_DEVICE);
4502 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4503 nvmd_req.resp_addr_hi =
4504 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4505 nvmd_req.resp_addr_lo =
4506 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4510 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4511 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4512 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4513 nvmd_req.resp_addr_hi =
4514 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4515 nvmd_req.resp_addr_lo =
4516 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4519 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4520 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4521 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4522 nvmd_req.resp_addr_hi =
4523 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4524 nvmd_req.resp_addr_lo =
4525 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4528 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4529 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
4530 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4531 nvmd_req.resp_addr_hi =
4532 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4533 nvmd_req.resp_addr_lo =
4534 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4539 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
4544 * pm8001_chip_fw_flash_update_build - support the firmware update operation
4545 * @pm8001_ha: our hba card information.
4546 * @fw_flash_updata_info: firmware flash update param
4549 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4550 void *fw_flash_updata_info, u32 tag)
4552 struct fw_flash_Update_req payload;
4553 struct fw_flash_updata_info *info;
4554 struct inbound_queue_table *circularQ;
4556 u32 opc = OPC_INB_FW_FLASH_UPDATE;
4558 memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4559 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4560 info = fw_flash_updata_info;
4561 payload.tag = cpu_to_le32(tag);
4562 payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4563 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4564 payload.total_image_len = cpu_to_le32(info->total_image_len);
4565 payload.len = info->sgl.im_len.len ;
4566 payload.sgl_addr_lo = lower_32_bits(info->sgl.addr);
4567 payload.sgl_addr_hi = upper_32_bits(info->sgl.addr);
4568 ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4573 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4576 struct fw_flash_updata_info flash_update_info;
4577 struct fw_control_info *fw_control;
4578 struct fw_control_ex *fw_control_context;
4581 struct pm8001_ccb_info *ccb;
4582 void *buffer = NULL;
4583 dma_addr_t phys_addr;
4586 struct pm8001_ioctl_payload *ioctl_payload = payload;
4588 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4589 if (!fw_control_context)
4591 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0];
4592 if (fw_control->len != 0) {
4593 if (pm8001_mem_alloc(pm8001_ha->pdev,
4598 fw_control->len, 0) != 0) {
4599 PM8001_FAIL_DBG(pm8001_ha,
4600 pm8001_printk("Mem alloc failure\n"));
4601 kfree(fw_control_context);
4605 memcpy(buffer, fw_control->buffer, fw_control->len);
4606 flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4607 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4608 flash_update_info.sgl.im_len.e = 0;
4609 flash_update_info.cur_image_offset = fw_control->offset;
4610 flash_update_info.cur_image_len = fw_control->len;
4611 flash_update_info.total_image_len = fw_control->size;
4612 fw_control_context->fw_control = fw_control;
4613 fw_control_context->virtAddr = buffer;
4614 fw_control_context->len = fw_control->len;
4615 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4617 kfree(fw_control_context);
4620 ccb = &pm8001_ha->ccb_info[tag];
4621 ccb->fw_control_context = fw_control_context;
4623 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4629 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4630 struct pm8001_device *pm8001_dev, u32 state)
4632 struct set_dev_state_req payload;
4633 struct inbound_queue_table *circularQ;
4634 struct pm8001_ccb_info *ccb;
4637 u32 opc = OPC_INB_SET_DEVICE_STATE;
4638 memset(&payload, 0, sizeof(payload));
4639 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4642 ccb = &pm8001_ha->ccb_info[tag];
4644 ccb->device = pm8001_dev;
4645 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4646 payload.tag = cpu_to_le32(tag);
4647 payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4648 payload.nds = cpu_to_le32(state);
4649 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4655 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4657 struct sas_re_initialization_req payload;
4658 struct inbound_queue_table *circularQ;
4659 struct pm8001_ccb_info *ccb;
4662 u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4663 memset(&payload, 0, sizeof(payload));
4664 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4667 ccb = &pm8001_ha->ccb_info[tag];
4669 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4670 payload.tag = cpu_to_le32(tag);
4671 payload.SSAHOLT = cpu_to_le32(0xd << 25);
4672 payload.sata_hol_tmo = cpu_to_le32(80);
4673 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4674 rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
4679 const struct pm8001_dispatch pm8001_8001_dispatch = {
4681 .chip_init = pm8001_chip_init,
4682 .chip_soft_rst = pm8001_chip_soft_rst,
4683 .chip_rst = pm8001_hw_chip_rst,
4684 .chip_iounmap = pm8001_chip_iounmap,
4685 .isr = pm8001_chip_isr,
4686 .is_our_interupt = pm8001_chip_is_our_interupt,
4687 .isr_process_oq = process_oq,
4688 .interrupt_enable = pm8001_chip_interrupt_enable,
4689 .interrupt_disable = pm8001_chip_interrupt_disable,
4690 .make_prd = pm8001_chip_make_sg,
4691 .smp_req = pm8001_chip_smp_req,
4692 .ssp_io_req = pm8001_chip_ssp_io_req,
4693 .sata_req = pm8001_chip_sata_req,
4694 .phy_start_req = pm8001_chip_phy_start_req,
4695 .phy_stop_req = pm8001_chip_phy_stop_req,
4696 .reg_dev_req = pm8001_chip_reg_dev_req,
4697 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4698 .phy_ctl_req = pm8001_chip_phy_ctl_req,
4699 .task_abort = pm8001_chip_abort_task,
4700 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4701 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4702 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4703 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4704 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4705 .sas_re_init_req = pm8001_chip_sas_re_initialization,