drivers/scsi/pm8001/pm8001_init.c

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #include <linux/slab.h>
  42 #include "pm8001_sas.h"
  43 #include "pm8001_chips.h"
  44
  45 static struct scsi_transport_template *pm8001_stt;
  46
  47 /**
  48  * chip info structure to identify chip key functionality as
  49  * encryption available/not, no of ports, hw specific function ref
  50  */
  51 static const struct pm8001_chip_info pm8001_chips[] = {
  52         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
  53         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
  54         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
  55         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
  56         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
  57         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
  58         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
  59         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
  60         [chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
  61         [chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
  62         [chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
  63 };
  64 static int pm8001_id;
  65
  66 LIST_HEAD(hba_list);
  67
  68 struct workqueue_struct *pm8001_wq;
  69
  70 /**
  71  * The main structure which LLDD must register for scsi core.
  72  */
  73 static struct scsi_host_template pm8001_sht = {
  74         .module                 = THIS_MODULE,
  75         .name                   = DRV_NAME,
  76         .queuecommand           = sas_queuecommand,
  77         .target_alloc           = sas_target_alloc,
  78         .slave_configure        = sas_slave_configure,
  79         .scan_finished          = pm8001_scan_finished,
  80         .scan_start             = pm8001_scan_start,
  81         .change_queue_depth     = sas_change_queue_depth,
  82         .bios_param             = sas_bios_param,
  83         .can_queue              = 1,
  84         .this_id                = -1,
  85         .sg_tablesize           = SG_ALL,
  86         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
  87         .use_clustering         = ENABLE_CLUSTERING,
  88         .eh_device_reset_handler = sas_eh_device_reset_handler,
  89         .eh_bus_reset_handler   = sas_eh_bus_reset_handler,
  90         .target_destroy         = sas_target_destroy,
  91         .ioctl                  = sas_ioctl,
  92         .shost_attrs            = pm8001_host_attrs,
  93         .use_blk_tags           = 1,
  94         .track_queue_depth      = 1,
  95 };
  96
  97 /**
  98  * Sas layer call this function to execute specific task.
  99  */
 100 static struct sas_domain_function_template pm8001_transport_ops = {
 101         .lldd_dev_found         = pm8001_dev_found,
 102         .lldd_dev_gone          = pm8001_dev_gone,
 103
 104         .lldd_execute_task      = pm8001_queue_command,
 105         .lldd_control_phy       = pm8001_phy_control,
 106
 107         .lldd_abort_task        = pm8001_abort_task,
 108         .lldd_abort_task_set    = pm8001_abort_task_set,
 109         .lldd_clear_aca         = pm8001_clear_aca,
 110         .lldd_clear_task_set    = pm8001_clear_task_set,
 111         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
 112         .lldd_lu_reset          = pm8001_lu_reset,
 113         .lldd_query_task        = pm8001_query_task,
 114 };
 115
 116 /**
 117  *pm8001_phy_init - initiate our adapter phys
 118  *@pm8001_ha: our hba structure.
 119  *@phy_id: phy id.
 120  */
 121 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
 122 {
 123         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
 124         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 125         phy->phy_state = 0;
 126         phy->pm8001_ha = pm8001_ha;
 127         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
 128         sas_phy->class = SAS;
 129         sas_phy->iproto = SAS_PROTOCOL_ALL;
 130         sas_phy->tproto = 0;
 131         sas_phy->type = PHY_TYPE_PHYSICAL;
 132         sas_phy->role = PHY_ROLE_INITIATOR;
 133         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 134         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 135         sas_phy->id = phy_id;
 136         sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
 137         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 138         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
 139         sas_phy->lldd_phy = phy;
 140 }
 141
 142 /**
 143  *pm8001_free - free hba
 144  *@pm8001_ha:   our hba structure.
 145  *
 146  */
 147 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
 148 {
 149         int i;
 150
 151         if (!pm8001_ha)
 152                 return;
 153
 154         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 155                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 156                         pci_free_consistent(pm8001_ha->pdev,
 157                                 (pm8001_ha->memoryMap.region[i].total_len +
 158                                 pm8001_ha->memoryMap.region[i].alignment),
 159                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 160                                 pm8001_ha->memoryMap.region[i].phys_addr);
 161                         }
 162         }
 163         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
 164         if (pm8001_ha->shost)
 165                 scsi_host_put(pm8001_ha->shost);
 166         flush_workqueue(pm8001_wq);
 167         kfree(pm8001_ha->tags);
 168         kfree(pm8001_ha);
 169 }
 170
 171 #ifdef PM8001_USE_TASKLET
 172
 173 /**
 174  * tasklet for 64 msi-x interrupt handler
 175  * @opaque: the passed general host adapter struct
 176  * Note: pm8001_tasklet is common for pm8001 & pm80xx
 177  */
 178 static void pm8001_tasklet(unsigned long opaque)
 179 {
 180         struct pm8001_hba_info *pm8001_ha;
 181         struct isr_param *irq_vector;
 182
 183         irq_vector = (struct isr_param *)opaque;
 184         pm8001_ha = irq_vector->drv_inst;
 185         if (unlikely(!pm8001_ha))
 186                 BUG_ON(1);
 187         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 188 }
 189 #endif
 190
 191 /**
 192  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
 193  * It obtains the vector number and calls the equivalent bottom
 194  * half or services directly.
 195  * @opaque: the passed outbound queue/vector. Host structure is
 196  * retrieved from the same.
 197  */
 198 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
 199 {
 200         struct isr_param *irq_vector;
 201         struct pm8001_hba_info *pm8001_ha;
 202         irqreturn_t ret = IRQ_HANDLED;
 203         irq_vector = (struct isr_param *)opaque;
 204         pm8001_ha = irq_vector->drv_inst;
 205
 206         if (unlikely(!pm8001_ha))
 207                 return IRQ_NONE;
 208         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
 209                 return IRQ_NONE;
 210 #ifdef PM8001_USE_TASKLET
 211         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
 212 #else
 213         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 214 #endif
 215         return ret;
 216 }
 217
 218 /**
 219  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
 220  * @dev_id: sas_ha structure. The HBA is retrieved from sas_has structure.
 221  */
 222
 223 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
 224 {
 225         struct pm8001_hba_info *pm8001_ha;
 226         irqreturn_t ret = IRQ_HANDLED;
 227         struct sas_ha_struct *sha = dev_id;
 228         pm8001_ha = sha->lldd_ha;
 229         if (unlikely(!pm8001_ha))
 230                 return IRQ_NONE;
 231         if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
 232                 return IRQ_NONE;
 233
 234 #ifdef PM8001_USE_TASKLET
 235         tasklet_schedule(&pm8001_ha->tasklet[0]);
 236 #else
 237         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
 238 #endif
 239         return ret;
 240 }
 241
 242 /**
 243  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
 244  * @pm8001_ha:our hba structure.
 245  *
 246  */
 247 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
 248                         const struct pci_device_id *ent)
 249 {
 250         int i;
 251         spin_lock_init(&pm8001_ha->lock);
 252         spin_lock_init(&pm8001_ha->bitmap_lock);
 253         PM8001_INIT_DBG(pm8001_ha,
 254                 pm8001_printk("pm8001_alloc: PHY:%x\n",
 255                                 pm8001_ha->chip->n_phy));
 256         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 257                 pm8001_phy_init(pm8001_ha, i);
 258                 pm8001_ha->port[i].wide_port_phymap = 0;
 259                 pm8001_ha->port[i].port_attached = 0;
 260                 pm8001_ha->port[i].port_state = 0;
 261                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
 262         }
 263
 264         pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
 265         if (!pm8001_ha->tags)
 266                 goto err_out;
 267         /* MPI Memory region 1 for AAP Event Log for fw */
 268         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
 269         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
 270         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
 271         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
 272
 273         /* MPI Memory region 2 for IOP Event Log for fw */
 274         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
 275         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
 276         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
 277         pm8001_ha->memoryMap.region[IOP].alignment = 32;
 278
 279         for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
 280                 /* MPI Memory region 3 for consumer Index of inbound queues */
 281                 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
 282                 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
 283                 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
 284                 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
 285
 286                 if ((ent->driver_data) != chip_8001) {
 287                         /* MPI Memory region 5 inbound queues */
 288                         pm8001_ha->memoryMap.region[IB+i].num_elements =
 289                                                 PM8001_MPI_QUEUE;
 290                         pm8001_ha->memoryMap.region[IB+i].element_size = 128;
 291                         pm8001_ha->memoryMap.region[IB+i].total_len =
 292                                                 PM8001_MPI_QUEUE * 128;
 293                         pm8001_ha->memoryMap.region[IB+i].alignment = 128;
 294                 } else {
 295                         pm8001_ha->memoryMap.region[IB+i].num_elements =
 296                                                 PM8001_MPI_QUEUE;
 297                         pm8001_ha->memoryMap.region[IB+i].element_size = 64;
 298                         pm8001_ha->memoryMap.region[IB+i].total_len =
 299                                                 PM8001_MPI_QUEUE * 64;
 300                         pm8001_ha->memoryMap.region[IB+i].alignment = 64;
 301                 }
 302         }
 303
 304         for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
 305                 /* MPI Memory region 4 for producer Index of outbound queues */
 306                 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
 307                 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
 308                 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
 309                 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
 310
 311                 if (ent->driver_data != chip_8001) {
 312                         /* MPI Memory region 6 Outbound queues */
 313                         pm8001_ha->memoryMap.region[OB+i].num_elements =
 314                                                 PM8001_MPI_QUEUE;
 315                         pm8001_ha->memoryMap.region[OB+i].element_size = 128;
 316                         pm8001_ha->memoryMap.region[OB+i].total_len =
 317                                                 PM8001_MPI_QUEUE * 128;
 318                         pm8001_ha->memoryMap.region[OB+i].alignment = 128;
 319                 } else {
 320                         /* MPI Memory region 6 Outbound queues */
 321                         pm8001_ha->memoryMap.region[OB+i].num_elements =
 322                                                 PM8001_MPI_QUEUE;
 323                         pm8001_ha->memoryMap.region[OB+i].element_size = 64;
 324                         pm8001_ha->memoryMap.region[OB+i].total_len =
 325                                                 PM8001_MPI_QUEUE * 64;
 326                         pm8001_ha->memoryMap.region[OB+i].alignment = 64;
 327                 }
 328
 329         }
 330         /* Memory region write DMA*/
 331         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
 332         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
 333         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
 334         /* Memory region for devices*/
 335         pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
 336         pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
 337                 sizeof(struct pm8001_device);
 338         pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
 339                 sizeof(struct pm8001_device);
 340
 341         /* Memory region for ccb_info*/
 342         pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
 343         pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
 344                 sizeof(struct pm8001_ccb_info);
 345         pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
 346                 sizeof(struct pm8001_ccb_info);
 347
 348         /* Memory region for fw flash */
 349         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
 350
 351         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
 352         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
 353         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
 354         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
 355         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 356                 if (pm8001_mem_alloc(pm8001_ha->pdev,
 357                         &pm8001_ha->memoryMap.region[i].virt_ptr,
 358                         &pm8001_ha->memoryMap.region[i].phys_addr,
 359                         &pm8001_ha->memoryMap.region[i].phys_addr_hi,
 360                         &pm8001_ha->memoryMap.region[i].phys_addr_lo,
 361                         pm8001_ha->memoryMap.region[i].total_len,
 362                         pm8001_ha->memoryMap.region[i].alignment) != 0) {
 363                                 PM8001_FAIL_DBG(pm8001_ha,
 364                                         pm8001_printk("Mem%d alloc failed\n",
 365                                         i));
 366                                 goto err_out;
 367                 }
 368         }
 369
 370         pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
 371         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
 372                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
 373                 pm8001_ha->devices[i].id = i;
 374                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
 375                 pm8001_ha->devices[i].running_req = 0;
 376         }
 377         pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
 378         for (i = 0; i < PM8001_MAX_CCB; i++) {
 379                 pm8001_ha->ccb_info[i].ccb_dma_handle =
 380                         pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
 381                         i * sizeof(struct pm8001_ccb_info);
 382                 pm8001_ha->ccb_info[i].task = NULL;
 383                 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
 384                 pm8001_ha->ccb_info[i].device = NULL;
 385                 ++pm8001_ha->tags_num;
 386         }
 387         pm8001_ha->flags = PM8001F_INIT_TIME;
 388         /* Initialize tags */
 389         pm8001_tag_init(pm8001_ha);
 390         return 0;
 391 err_out:
 392         return 1;
 393 }
 394
 395 /**
 396  * pm8001_ioremap - remap the pci high physical address to kernal virtual
 397  * address so that we can access them.
 398  * @pm8001_ha:our hba structure.
 399  */
 400 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
 401 {
 402         u32 bar;
 403         u32 logicalBar = 0;
 404         struct pci_dev *pdev;
 405
 406         pdev = pm8001_ha->pdev;
 407         /* map pci mem (PMC pci base 0-3)*/
 408         for (bar = 0; bar < 6; bar++) {
 409                 /*
 410                 ** logical BARs for SPC:
 411                 ** bar 0 and 1 - logical BAR0
 412                 ** bar 2 and 3 - logical BAR1
 413                 ** bar4 - logical BAR2
 414                 ** bar5 - logical BAR3
 415                 ** Skip the appropriate assignments:
 416                 */
 417                 if ((bar == 1) || (bar == 3))
 418                         continue;
 419                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
 420                         pm8001_ha->io_mem[logicalBar].membase =
 421                                 pci_resource_start(pdev, bar);
 422                         pm8001_ha->io_mem[logicalBar].membase &=
 423                                 (u32)PCI_BASE_ADDRESS_MEM_MASK;
 424                         pm8001_ha->io_mem[logicalBar].memsize =
 425                                 pci_resource_len(pdev, bar);
 426                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
 427                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
 428                                 pm8001_ha->io_mem[logicalBar].memsize);
 429                         PM8001_INIT_DBG(pm8001_ha,
 430                                 pm8001_printk("PCI: bar %d, logicalBar %d ",
 431                                 bar, logicalBar));
 432                         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 433                                 "base addr %llx virt_addr=%llx len=%d\n",
 434                                 (u64)pm8001_ha->io_mem[logicalBar].membase,
 435                                 (u64)(unsigned long)
 436                                 pm8001_ha->io_mem[logicalBar].memvirtaddr,
 437                                 pm8001_ha->io_mem[logicalBar].memsize));
 438                 } else {
 439                         pm8001_ha->io_mem[logicalBar].membase   = 0;
 440                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
 441                         pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
 442                 }
 443                 logicalBar++;
 444         }
 445         return 0;
 446 }
 447
 448 /**
 449  * pm8001_pci_alloc - initialize our ha card structure
 450  * @pdev: pci device.
 451  * @ent: ent
 452  * @shost: scsi host struct which has been initialized before.
 453  */
 454 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
 455                                  const struct pci_device_id *ent,
 456                                 struct Scsi_Host *shost)
 457
 458 {
 459         struct pm8001_hba_info *pm8001_ha;
 460         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 461         int j;
 462
 463         pm8001_ha = sha->lldd_ha;
 464         if (!pm8001_ha)
 465                 return NULL;
 466
 467         pm8001_ha->pdev = pdev;
 468         pm8001_ha->dev = &pdev->dev;
 469         pm8001_ha->chip_id = ent->driver_data;
 470         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
 471         pm8001_ha->irq = pdev->irq;
 472         pm8001_ha->sas = sha;
 473         pm8001_ha->shost = shost;
 474         pm8001_ha->id = pm8001_id++;
 475         pm8001_ha->logging_level = 0x01;
 476         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
 477         /* IOMB size is 128 for 8088/89 controllers */
 478         if (pm8001_ha->chip_id != chip_8001)
 479                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
 480         else
 481                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
 482
 483 #ifdef PM8001_USE_TASKLET
 484         /* Tasklet for non msi-x interrupt handler */
 485         if ((!pdev->msix_cap || !pci_msi_enabled())
 486             || (pm8001_ha->chip_id == chip_8001))
 487                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
 488                         (unsigned long)&(pm8001_ha->irq_vector[0]));
 489         else
 490                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
 491                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
 492                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
 493 #endif
 494         pm8001_ioremap(pm8001_ha);
 495         if (!pm8001_alloc(pm8001_ha, ent))
 496                 return pm8001_ha;
 497         pm8001_free(pm8001_ha);
 498         return NULL;
 499 }
 500
 501 /**
 502  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
 503  * @pdev: pci device.
 504  */
 505 static int pci_go_44(struct pci_dev *pdev)
 506 {
 507         int rc;
 508
 509         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
 510                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
 511                 if (rc) {
 512                         rc = pci_set_consistent_dma_mask(pdev,
 513                                 DMA_BIT_MASK(32));
 514                         if (rc) {
 515                                 dev_printk(KERN_ERR, &pdev->dev,
 516                                         "44-bit DMA enable failed\n");
 517                                 return rc;
 518                         }
 519                 }
 520         } else {
 521                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 522                 if (rc) {
 523                         dev_printk(KERN_ERR, &pdev->dev,
 524                                 "32-bit DMA enable failed\n");
 525                         return rc;
 526                 }
 527                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 528                 if (rc) {
 529                         dev_printk(KERN_ERR, &pdev->dev,
 530                                 "32-bit consistent DMA enable failed\n");
 531                         return rc;
 532                 }
 533         }
 534         return rc;
 535 }
 536
 537 /**
 538  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
 539  * @shost: scsi host which has been allocated outside.
 540  * @chip_info: our ha struct.
 541  */
 542 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
 543                                    const struct pm8001_chip_info *chip_info)
 544 {
 545         int phy_nr, port_nr;
 546         struct asd_sas_phy **arr_phy;
 547         struct asd_sas_port **arr_port;
 548         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 549
 550         phy_nr = chip_info->n_phy;
 551         port_nr = phy_nr;
 552         memset(sha, 0x00, sizeof(*sha));
 553         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 554         if (!arr_phy)
 555                 goto exit;
 556         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 557         if (!arr_port)
 558                 goto exit_free2;
 559
 560         sha->sas_phy = arr_phy;
 561         sha->sas_port = arr_port;
 562         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
 563         if (!sha->lldd_ha)
 564                 goto exit_free1;
 565
 566         shost->transportt = pm8001_stt;
 567         shost->max_id = PM8001_MAX_DEVICES;
 568         shost->max_lun = 8;
 569         shost->max_channel = 0;
 570         shost->unique_id = pm8001_id;
 571         shost->max_cmd_len = 16;
 572         shost->can_queue = PM8001_CAN_QUEUE;
 573         shost->cmd_per_lun = 32;
 574         return 0;
 575 exit_free1:
 576         kfree(arr_port);
 577 exit_free2:
 578         kfree(arr_phy);
 579 exit:
 580         return -1;
 581 }
 582
 583 /**
 584  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
 585  * @shost: scsi host which has been allocated outside
 586  * @chip_info: our ha struct.
 587  */
 588 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
 589                                      const struct pm8001_chip_info *chip_info)
 590 {
 591         int i = 0;
 592         struct pm8001_hba_info *pm8001_ha;
 593         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 594
 595         pm8001_ha = sha->lldd_ha;
 596         for (i = 0; i < chip_info->n_phy; i++) {
 597                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
 598                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
 599         }
 600         sha->sas_ha_name = DRV_NAME;
 601         sha->dev = pm8001_ha->dev;
 602
 603         sha->lldd_module = THIS_MODULE;
 604         sha->sas_addr = &pm8001_ha->sas_addr[0];
 605         sha->num_phys = chip_info->n_phy;
 606         sha->core.shost = shost;
 607 }
 608
 609 /**
 610  * pm8001_init_sas_add - initialize sas address
 611  * @chip_info: our ha struct.
 612  *
 613  * Currently we just set the fixed SAS address to our HBA,for manufacture,
 614  * it should read from the EEPROM
 615  */
 616 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
 617 {
 618         u8 i, j;
 619 #ifdef PM8001_READ_VPD
 620         /* For new SPC controllers WWN is stored in flash vpd
 621         *  For SPC/SPCve controllers WWN is stored in EEPROM
 622         *  For Older SPC WWN is stored in NVMD
 623         */
 624         DECLARE_COMPLETION_ONSTACK(completion);
 625         struct pm8001_ioctl_payload payload;
 626         u16 deviceid;
 627         int rc;
 628
 629         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 630         pm8001_ha->nvmd_completion = &completion;
 631
 632         if (pm8001_ha->chip_id == chip_8001) {
 633                 if (deviceid == 0x8081 || deviceid == 0x0042) {
 634                         payload.minor_function = 4;
 635                         payload.length = 4096;
 636                 } else {
 637                         payload.minor_function = 0;
 638                         payload.length = 128;
 639                 }
 640         } else if ((pm8001_ha->chip_id == chip_8070 ||
 641                         pm8001_ha->chip_id == chip_8072) &&
 642                         pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 643                 payload.minor_function = 4;
 644                 payload.length = 4096;
 645         } else {
 646                 payload.minor_function = 1;
 647                 payload.length = 4096;
 648         }
 649         payload.offset = 0;
 650         payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
 651         if (!payload.func_specific) {
 652                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
 653                 return;
 654         }
 655         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 656         if (rc) {
 657                 kfree(payload.func_specific);
 658                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
 659                 return;
 660         }
 661         wait_for_completion(&completion);
 662
 663         for (i = 0, j = 0; i <= 7; i++, j++) {
 664                 if (pm8001_ha->chip_id == chip_8001) {
 665                         if (deviceid == 0x8081)
 666                                 pm8001_ha->sas_addr[j] =
 667                                         payload.func_specific[0x704 + i];
 668                         else if (deviceid == 0x0042)
 669                                 pm8001_ha->sas_addr[j] =
 670                                         payload.func_specific[0x010 + i];
 671                 } else if ((pm8001_ha->chip_id == chip_8070 ||
 672                                 pm8001_ha->chip_id == chip_8072) &&
 673                                 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 674                         pm8001_ha->sas_addr[j] =
 675                                         payload.func_specific[0x010 + i];
 676                 } else
 677                         pm8001_ha->sas_addr[j] =
 678                                         payload.func_specific[0x804 + i];
 679         }
 680
 681         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 682                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
 683                         pm8001_ha->sas_addr, SAS_ADDR_SIZE);
 684                 PM8001_INIT_DBG(pm8001_ha,
 685                         pm8001_printk("phy %d sas_addr = %016llx\n", i,
 686                         pm8001_ha->phy[i].dev_sas_addr));
 687         }
 688         kfree(payload.func_specific);
 689 #else
 690         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 691                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
 692                 pm8001_ha->phy[i].dev_sas_addr =
 693                         cpu_to_be64((u64)
 694                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
 695         }
 696         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
 697                 SAS_ADDR_SIZE);
 698 #endif
 699 }
 700
 701 /*
 702  * pm8001_get_phy_settings_info : Read phy setting values.
 703  * @pm8001_ha : our hba.
 704  */
 705 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
 706 {
 707
 708 #ifdef PM8001_READ_VPD
 709         /*OPTION ROM FLASH read for the SPC cards */
 710         DECLARE_COMPLETION_ONSTACK(completion);
 711         struct pm8001_ioctl_payload payload;
 712         int rc;
 713
 714         pm8001_ha->nvmd_completion = &completion;
 715         /* SAS ADDRESS read from flash / EEPROM */
 716         payload.minor_function = 6;
 717         payload.offset = 0;
 718         payload.length = 4096;
 719         payload.func_specific = kzalloc(4096, GFP_KERNEL);
 720         if (!payload.func_specific)
 721                 return -ENOMEM;
 722         /* Read phy setting values from flash */
 723         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 724         if (rc) {
 725                 kfree(payload.func_specific);
 726                 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
 727                 return -ENOMEM;
 728         }
 729         wait_for_completion(&completion);
 730         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
 731         kfree(payload.func_specific);
 732 #endif
 733         return 0;
 734 }
 735
 736 struct pm8001_mpi3_phy_pg_trx_config {
 737         u32 LaneLosCfg;
 738         u32 LanePgaCfg1;
 739         u32 LanePisoCfg1;
 740         u32 LanePisoCfg2;
 741         u32 LanePisoCfg3;
 742         u32 LanePisoCfg4;
 743         u32 LanePisoCfg5;
 744         u32 LanePisoCfg6;
 745         u32 LaneBctCtrl;
 746 };
 747
 748 /**
 749  * pm8001_get_internal_phy_settings : Retrieves the internal PHY settings
 750  * @pm8001_ha : our adapter
 751  * @phycfg : PHY config page to populate
 752  */
 753 static
 754 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
 755                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 756 {
 757         phycfg->LaneLosCfg   = 0x00000132;
 758         phycfg->LanePgaCfg1  = 0x00203949;
 759         phycfg->LanePisoCfg1 = 0x000000FF;
 760         phycfg->LanePisoCfg2 = 0xFF000001;
 761         phycfg->LanePisoCfg3 = 0xE7011300;
 762         phycfg->LanePisoCfg4 = 0x631C40C0;
 763         phycfg->LanePisoCfg5 = 0xF8102036;
 764         phycfg->LanePisoCfg6 = 0xF74A1000;
 765         phycfg->LaneBctCtrl  = 0x00FB33F8;
 766 }
 767
 768 /**
 769  * pm8001_get_external_phy_settings : Retrieves the external PHY settings
 770  * @pm8001_ha : our adapter
 771  * @phycfg : PHY config page to populate
 772  */
 773 static
 774 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
 775                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 776 {
 777         phycfg->LaneLosCfg   = 0x00000132;
 778         phycfg->LanePgaCfg1  = 0x00203949;
 779         phycfg->LanePisoCfg1 = 0x000000FF;
 780         phycfg->LanePisoCfg2 = 0xFF000001;
 781         phycfg->LanePisoCfg3 = 0xE7011300;
 782         phycfg->LanePisoCfg4 = 0x63349140;
 783         phycfg->LanePisoCfg5 = 0xF8102036;
 784         phycfg->LanePisoCfg6 = 0xF80D9300;
 785         phycfg->LaneBctCtrl  = 0x00FB33F8;
 786 }
 787
 788 /**
 789  * pm8001_get_phy_mask : Retrieves the mask that denotes if a PHY is int/ext
 790  * @pm8001_ha : our adapter
 791  * @phymask : The PHY mask
 792  */
 793 static
 794 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
 795 {
 796         switch (pm8001_ha->pdev->subsystem_device) {
 797         case 0x0070: /* H1280 - 8 external 0 internal */
 798         case 0x0072: /* H12F0 - 16 external 0 internal */
 799                 *phymask = 0x0000;
 800                 break;
 801
 802         case 0x0071: /* H1208 - 0 external 8 internal */
 803         case 0x0073: /* H120F - 0 external 16 internal */
 804                 *phymask = 0xFFFF;
 805                 break;
 806
 807         case 0x0080: /* H1244 - 4 external 4 internal */
 808                 *phymask = 0x00F0;
 809                 break;
 810
 811         case 0x0081: /* H1248 - 4 external 8 internal */
 812                 *phymask = 0x0FF0;
 813                 break;
 814
 815         case 0x0082: /* H1288 - 8 external 8 internal */
 816                 *phymask = 0xFF00;
 817                 break;
 818
 819         default:
 820                 PM8001_INIT_DBG(pm8001_ha,
 821                         pm8001_printk("Unknown subsystem device=0x%.04x",
 822                                 pm8001_ha->pdev->subsystem_device));
 823         }
 824 }
 825
 826 /**
 827  * pm8001_set_phy_settings_ven_117c_12Gb : Configure ATTO 12Gb PHY settings
 828  * @pm8001_ha : our adapter
 829  */
 830 static
 831 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
 832 {
 833         struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
 834         struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
 835         int phymask = 0;
 836         int i = 0;
 837
 838         memset(&phycfg_int, 0, sizeof(phycfg_int));
 839         memset(&phycfg_ext, 0, sizeof(phycfg_ext));
 840
 841         pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
 842         pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
 843         pm8001_get_phy_mask(pm8001_ha, &phymask);
 844
 845         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 846                 if (phymask & (1 << i)) {/* Internal PHY */
 847                         pm8001_set_phy_profile_single(pm8001_ha, i,
 848                                         sizeof(phycfg_int) / sizeof(u32),
 849                                         (u32 *)&phycfg_int);
 850
 851                 } else { /* External PHY */
 852                         pm8001_set_phy_profile_single(pm8001_ha, i,
 853                                         sizeof(phycfg_ext) / sizeof(u32),
 854                                         (u32 *)&phycfg_ext);
 855                 }
 856         }
 857
 858         return 0;
 859 }
 860
 861 /**
 862  * pm8001_configure_phy_settings : Configures PHY settings based on vendor ID.
 863  * @pm8001_ha : our hba.
 864  */
 865 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
 866 {
 867         switch (pm8001_ha->pdev->subsystem_vendor) {
 868         case PCI_VENDOR_ID_ATTO:
 869                 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
 870                         return 0;
 871                 else
 872                         return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
 873
 874         case PCI_VENDOR_ID_ADAPTEC2:
 875         case 0:
 876                 return 0;
 877
 878         default:
 879                 return pm8001_get_phy_settings_info(pm8001_ha);
 880         }
 881 }
 882
 883 #ifdef PM8001_USE_MSIX
 884 /**
 885  * pm8001_setup_msix - enable MSI-X interrupt
 886  * @chip_info: our ha struct.
 887  * @irq_handler: irq_handler
 888  */
 889 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
 890 {
 891         u32 i = 0, j = 0;
 892         u32 number_of_intr;
 893         int flag = 0;
 894         u32 max_entry;
 895         int rc;
 896         static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
 897
 898         /* SPCv controllers supports 64 msi-x */
 899         if (pm8001_ha->chip_id == chip_8001) {
 900                 number_of_intr = 1;
 901         } else {
 902                 number_of_intr = PM8001_MAX_MSIX_VEC;
 903                 flag &= ~IRQF_SHARED;
 904         }
 905
 906         max_entry = sizeof(pm8001_ha->msix_entries) /
 907                 sizeof(pm8001_ha->msix_entries[0]);
 908         for (i = 0; i < max_entry ; i++)
 909                 pm8001_ha->msix_entries[i].entry = i;
 910         rc = pci_enable_msix_exact(pm8001_ha->pdev, pm8001_ha->msix_entries,
 911                 number_of_intr);
 912         pm8001_ha->number_of_intr = number_of_intr;
 913         if (rc)
 914                 return rc;
 915
 916         PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
 917                 "pci_enable_msix_exact request ret:%d no of intr %d\n",
 918                                 rc, pm8001_ha->number_of_intr));
 919
 920         for (i = 0; i < number_of_intr; i++) {
 921                 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
 922                                 DRV_NAME"%d", i);
 923                 pm8001_ha->irq_vector[i].irq_id = i;
 924                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
 925
 926                 rc = request_irq(pm8001_ha->msix_entries[i].vector,
 927                         pm8001_interrupt_handler_msix, flag,
 928                         intr_drvname[i], &(pm8001_ha->irq_vector[i]));
 929                 if (rc) {
 930                         for (j = 0; j < i; j++) {
 931                                 free_irq(pm8001_ha->msix_entries[j].vector,
 932                                         &(pm8001_ha->irq_vector[i]));
 933                         }
 934                         pci_disable_msix(pm8001_ha->pdev);
 935                         break;
 936                 }
 937         }
 938
 939         return rc;
 940 }
 941 #endif
 942
 943 /**
 944  * pm8001_request_irq - register interrupt
 945  * @chip_info: our ha struct.
 946  */
 947 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
 948 {
 949         struct pci_dev *pdev;
 950         int rc;
 951
 952         pdev = pm8001_ha->pdev;
 953
 954 #ifdef PM8001_USE_MSIX
 955         if (pdev->msix_cap && pci_msi_enabled())
 956                 return pm8001_setup_msix(pm8001_ha);
 957         else {
 958                 PM8001_INIT_DBG(pm8001_ha,
 959                         pm8001_printk("MSIX not supported!!!\n"));
 960                 goto intx;
 961         }
 962 #endif
 963
 964 intx:
 965         /* initialize the INT-X interrupt */
 966         pm8001_ha->irq_vector[0].irq_id = 0;
 967         pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
 968         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
 969                 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
 970         return rc;
 971 }
 972
 973 /**
 974  * pm8001_pci_probe - probe supported device
 975  * @pdev: pci device which kernel has been prepared for.
 976  * @ent: pci device id
 977  *
 978  * This function is the main initialization function, when register a new
 979  * pci driver it is invoked, all struct an hardware initilization should be done
 980  * here, also, register interrupt
 981  */
 982 static int pm8001_pci_probe(struct pci_dev *pdev,
 983                             const struct pci_device_id *ent)
 984 {
 985         unsigned int rc;
 986         u32     pci_reg;
 987         u8      i = 0;
 988         struct pm8001_hba_info *pm8001_ha;
 989         struct Scsi_Host *shost = NULL;
 990         const struct pm8001_chip_info *chip;
 991
 992         dev_printk(KERN_INFO, &pdev->dev,
 993                 "pm80xx: driver version %s\n", DRV_VERSION);
 994         rc = pci_enable_device(pdev);
 995         if (rc)
 996                 goto err_out_enable;
 997         pci_set_master(pdev);
 998         /*
 999          * Enable pci slot busmaster by setting pci command register.
1000          * This is required by FW for Cyclone card.
1001          */
1002
1003         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1004         pci_reg |= 0x157;
1005         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1006         rc = pci_request_regions(pdev, DRV_NAME);
1007         if (rc)
1008                 goto err_out_disable;
1009         rc = pci_go_44(pdev);
1010         if (rc)
1011                 goto err_out_regions;
1012
1013         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1014         if (!shost) {
1015                 rc = -ENOMEM;
1016                 goto err_out_regions;
1017         }
1018         chip = &pm8001_chips[ent->driver_data];
1019         SHOST_TO_SAS_HA(shost) =
1020                 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1021         if (!SHOST_TO_SAS_HA(shost)) {
1022                 rc = -ENOMEM;
1023                 goto err_out_free_host;
1024         }
1025
1026         rc = pm8001_prep_sas_ha_init(shost, chip);
1027         if (rc) {
1028                 rc = -ENOMEM;
1029                 goto err_out_free;
1030         }
1031         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1032         /* ent->driver variable is used to differentiate between controllers */
1033         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1034         if (!pm8001_ha) {
1035                 rc = -ENOMEM;
1036                 goto err_out_free;
1037         }
1038         list_add_tail(&pm8001_ha->list, &hba_list);
1039         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1040         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1041         if (rc) {
1042                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1043                         "chip_init failed [ret: %d]\n", rc));
1044                 goto err_out_ha_free;
1045         }
1046
1047         rc = scsi_add_host(shost, &pdev->dev);
1048         if (rc)
1049                 goto err_out_ha_free;
1050         rc = pm8001_request_irq(pm8001_ha);
1051         if (rc) {
1052                 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1053                         "pm8001_request_irq failed [ret: %d]\n", rc));
1054                 goto err_out_shost;
1055         }
1056
1057         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1058         if (pm8001_ha->chip_id != chip_8001) {
1059                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1060                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1061                 /* setup thermal configuration. */
1062                 pm80xx_set_thermal_config(pm8001_ha);
1063         }
1064
1065         pm8001_init_sas_add(pm8001_ha);
1066         /* phy setting support for motherboard controller */
1067         if (pm8001_configure_phy_settings(pm8001_ha))
1068                 goto err_out_shost;
1069
1070         pm8001_post_sas_ha_init(shost, chip);
1071         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1072         if (rc)
1073                 goto err_out_shost;
1074         scsi_scan_host(pm8001_ha->shost);
1075         return 0;
1076
1077 err_out_shost:
1078         scsi_remove_host(pm8001_ha->shost);
1079 err_out_ha_free:
1080         pm8001_free(pm8001_ha);
1081 err_out_free:
1082         kfree(SHOST_TO_SAS_HA(shost));
1083 err_out_free_host:
1084         kfree(shost);
1085 err_out_regions:
1086         pci_release_regions(pdev);
1087 err_out_disable:
1088         pci_disable_device(pdev);
1089 err_out_enable:
1090         return rc;
1091 }
1092
1093 static void pm8001_pci_remove(struct pci_dev *pdev)
1094 {
1095         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1096         struct pm8001_hba_info *pm8001_ha;
1097         int i, j;
1098         pm8001_ha = sha->lldd_ha;
1099         sas_unregister_ha(sha);
1100         sas_remove_host(pm8001_ha->shost);
1101         list_del(&pm8001_ha->list);
1102         scsi_remove_host(pm8001_ha->shost);
1103         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1104         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1105
1106 #ifdef PM8001_USE_MSIX
1107         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1108                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
1109         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1110                 free_irq(pm8001_ha->msix_entries[i].vector,
1111                                 &(pm8001_ha->irq_vector[i]));
1112         pci_disable_msix(pdev);
1113 #else
1114         free_irq(pm8001_ha->irq, sha);
1115 #endif
1116 #ifdef PM8001_USE_TASKLET
1117         /* For non-msix and msix interrupts */
1118         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1119             (pm8001_ha->chip_id == chip_8001))
1120                 tasklet_kill(&pm8001_ha->tasklet[0]);
1121         else
1122                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1123                         tasklet_kill(&pm8001_ha->tasklet[j]);
1124 #endif
1125         pm8001_free(pm8001_ha);
1126         kfree(sha->sas_phy);
1127         kfree(sha->sas_port);
1128         kfree(sha);
1129         pci_release_regions(pdev);
1130         pci_disable_device(pdev);
1131 }
1132
1133 /**
1134  * pm8001_pci_suspend - power management suspend main entry point
1135  * @pdev: PCI device struct
1136  * @state: PM state change to (usually PCI_D3)
1137  *
1138  * Returns 0 success, anything else error.
1139  */
1140 static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1141 {
1142         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1143         struct pm8001_hba_info *pm8001_ha;
1144         int  i, j;
1145         u32 device_state;
1146         pm8001_ha = sha->lldd_ha;
1147         sas_suspend_ha(sha);
1148         flush_workqueue(pm8001_wq);
1149         scsi_block_requests(pm8001_ha->shost);
1150         if (!pdev->pm_cap) {
1151                 dev_err(&pdev->dev, " PCI PM not supported\n");
1152                 return -ENODEV;
1153         }
1154         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1155         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1156 #ifdef PM8001_USE_MSIX
1157         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1158                 synchronize_irq(pm8001_ha->msix_entries[i].vector);
1159         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1160                 free_irq(pm8001_ha->msix_entries[i].vector,
1161                                 &(pm8001_ha->irq_vector[i]));
1162         pci_disable_msix(pdev);
1163 #else
1164         free_irq(pm8001_ha->irq, sha);
1165 #endif
1166 #ifdef PM8001_USE_TASKLET
1167         /* For non-msix and msix interrupts */
1168         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1169             (pm8001_ha->chip_id == chip_8001))
1170                 tasklet_kill(&pm8001_ha->tasklet[0]);
1171         else
1172                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1173                         tasklet_kill(&pm8001_ha->tasklet[j]);
1174 #endif
1175         device_state = pci_choose_state(pdev, state);
1176         pm8001_printk("pdev=0x%p, slot=%s, entering "
1177                       "operating state [D%d]\n", pdev,
1178                       pm8001_ha->name, device_state);
1179         pci_save_state(pdev);
1180         pci_disable_device(pdev);
1181         pci_set_power_state(pdev, device_state);
1182         return 0;
1183 }
1184
1185 /**
1186  * pm8001_pci_resume - power management resume main entry point
1187  * @pdev: PCI device struct
1188  *
1189  * Returns 0 success, anything else error.
1190  */
1191 static int pm8001_pci_resume(struct pci_dev *pdev)
1192 {
1193         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1194         struct pm8001_hba_info *pm8001_ha;
1195         int rc;
1196         u8 i = 0, j;
1197         u32 device_state;
1198         DECLARE_COMPLETION_ONSTACK(completion);
1199         pm8001_ha = sha->lldd_ha;
1200         device_state = pdev->current_state;
1201
1202         pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1203                 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1204
1205         pci_set_power_state(pdev, PCI_D0);
1206         pci_enable_wake(pdev, PCI_D0, 0);
1207         pci_restore_state(pdev);
1208         rc = pci_enable_device(pdev);
1209         if (rc) {
1210                 pm8001_printk("slot=%s Enable device failed during resume\n",
1211                               pm8001_ha->name);
1212                 goto err_out_enable;
1213         }
1214
1215         pci_set_master(pdev);
1216         rc = pci_go_44(pdev);
1217         if (rc)
1218                 goto err_out_disable;
1219         sas_prep_resume_ha(sha);
1220         /* chip soft rst only for spc */
1221         if (pm8001_ha->chip_id == chip_8001) {
1222                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1223                 PM8001_INIT_DBG(pm8001_ha,
1224                         pm8001_printk("chip soft reset successful\n"));
1225         }
1226         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1227         if (rc)
1228                 goto err_out_disable;
1229
1230         /* disable all the interrupt bits */
1231         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1232
1233         rc = pm8001_request_irq(pm8001_ha);
1234         if (rc)
1235                 goto err_out_disable;
1236 #ifdef PM8001_USE_TASKLET
1237         /*  Tasklet for non msi-x interrupt handler */
1238         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1239             (pm8001_ha->chip_id == chip_8001))
1240                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1241                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1242         else
1243                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1244                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1245                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1246 #endif
1247         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1248         if (pm8001_ha->chip_id != chip_8001) {
1249                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1250                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1251         }
1252
1253         /* Chip documentation for the 8070 and 8072 SPCv    */
1254         /* states that a 500ms minimum delay is required    */
1255         /* before issuing commands.  Otherwise, the firmare */
1256         /* will enter an unrecoverable state.               */
1257
1258         if (pm8001_ha->chip_id == chip_8070 ||
1259                 pm8001_ha->chip_id == chip_8072) {
1260                 mdelay(500);
1261         }
1262
1263         /* Spin up the PHYs */
1264
1265         pm8001_ha->flags = PM8001F_RUN_TIME;
1266         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1267                 pm8001_ha->phy[i].enable_completion = &completion;
1268                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1269                 wait_for_completion(&completion);
1270         }
1271         sas_resume_ha(sha);
1272         return 0;
1273
1274 err_out_disable:
1275         scsi_remove_host(pm8001_ha->shost);
1276         pci_disable_device(pdev);
1277 err_out_enable:
1278         return rc;
1279 }
1280
1281 /* update of pci device, vendor id and driver data with
1282  * unique value for each of the controller
1283  */
1284 static struct pci_device_id pm8001_pci_table[] = {
1285         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1286         { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1287         { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1288         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1289         /* Support for SPC/SPCv/SPCve controllers */
1290         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1291         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1292         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1293         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1294         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1295         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1296         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1297         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1298         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1299         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1300         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1301         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1302         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1303         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1304         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1305         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1306                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1307         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1308                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1309         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1310                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1311         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1312                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1313         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1314                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1315         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1316                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1317         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1318                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1319         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1320                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1321         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1322                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1323         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1324                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1325         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1326                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1327         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1328                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1329         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1330                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1331         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1332                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1333         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1334                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1335         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1336                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1337         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1338                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1339         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1340                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1341         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1342                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1343         { PCI_VENDOR_ID_ATTO, 0x8070,
1344                 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1345         { PCI_VENDOR_ID_ATTO, 0x8070,
1346                 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1347         { PCI_VENDOR_ID_ATTO, 0x8072,
1348                 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1349         { PCI_VENDOR_ID_ATTO, 0x8072,
1350                 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1351         { PCI_VENDOR_ID_ATTO, 0x8070,
1352                 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1353         { PCI_VENDOR_ID_ATTO, 0x8072,
1354                 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1355         { PCI_VENDOR_ID_ATTO, 0x8072,
1356                 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1357         {} /* terminate list */
1358 };
1359
1360 static struct pci_driver pm8001_pci_driver = {
1361         .name           = DRV_NAME,
1362         .id_table       = pm8001_pci_table,
1363         .probe          = pm8001_pci_probe,
1364         .remove         = pm8001_pci_remove,
1365         .suspend        = pm8001_pci_suspend,
1366         .resume         = pm8001_pci_resume,
1367 };
1368
1369 /**
1370  *      pm8001_init - initialize scsi transport template
1371  */
1372 static int __init pm8001_init(void)
1373 {
1374         int rc = -ENOMEM;
1375
1376         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1377         if (!pm8001_wq)
1378                 goto err;
1379
1380         pm8001_id = 0;
1381         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1382         if (!pm8001_stt)
1383                 goto err_wq;
1384         rc = pci_register_driver(&pm8001_pci_driver);
1385         if (rc)
1386                 goto err_tp;
1387         return 0;
1388
1389 err_tp:
1390         sas_release_transport(pm8001_stt);
1391 err_wq:
1392         destroy_workqueue(pm8001_wq);
1393 err:
1394         return rc;
1395 }
1396
1397 static void __exit pm8001_exit(void)
1398 {
1399         pci_unregister_driver(&pm8001_pci_driver);
1400         sas_release_transport(pm8001_stt);
1401         destroy_workqueue(pm8001_wq);
1402 }
1403
1404 module_init(pm8001_init);
1405 module_exit(pm8001_exit);
1406
1407 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1408 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1409 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1410 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1411 MODULE_DESCRIPTION(
1412                 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1413                 "SAS/SATA controller driver");
1414 MODULE_VERSION(DRV_VERSION);
1415 MODULE_LICENSE("GPL");
1416 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1417