2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 * Table for showing the current message id in use for particular level
10 * Change this table for addition of log/debug messages.
11 * ----------------------------------------------------------------------
12 * | Level | Last Value Used | Holes |
13 * ----------------------------------------------------------------------
14 * | Module Init and Probe | 0x014f | 0x4b,0xba,0xfa |
15 * | Mailbox commands | 0x1179 | 0x111a-0x111b |
16 * | | | 0x1155-0x1158 |
17 * | Device Discovery | 0x2095 | 0x2020-0x2022, |
19 * | Queue Command and IO tracing | 0x3058 | 0x3006-0x300b |
20 * | | | 0x3027-0x3028 |
21 * | | | 0x303d-0x3041 |
22 * | | | 0x302d,0x3033 |
23 * | | | 0x3036,0x3038 |
25 * | DPC Thread | 0x4022 | 0x4002,0x4013 |
26 * | Async Events | 0x5081 | 0x502b-0x502f |
27 * | | | 0x5047,0x5052 |
28 * | | | 0x5040,0x5075 |
29 * | Timer Routines | 0x6011 | |
30 * | User Space Interactions | 0x70dd | 0x7018,0x702e, |
31 * | | | 0x7020,0x7024, |
32 * | | | 0x7039,0x7045, |
33 * | | | 0x7073-0x7075, |
34 * | | | 0x707b,0x708c, |
35 * | | | 0x70a5,0x70a6, |
36 * | | | 0x70a8,0x70ab, |
37 * | | | 0x70ad-0x70ae, |
38 * | | | 0x70d1-0x70da |
39 * | Task Management | 0x803c | 0x8025-0x8026 |
40 * | | | 0x800b,0x8039 |
41 * | AER/EEH | 0x9011 | |
42 * | Virtual Port | 0xa007 | |
43 * | ISP82XX Specific | 0xb086 | 0xb002,0xb024 |
44 * | MultiQ | 0xc00c | |
46 * | Target Mode | 0xe070 | |
47 * | Target Mode Management | 0xf072 | |
48 * | Target Mode Task Management | 0x1000b | |
49 * ----------------------------------------------------------------------
54 #include <linux/delay.h>
56 static uint32_t ql_dbg_offset = 0x800;
59 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump)
61 fw_dump->fw_major_version = htonl(ha->fw_major_version);
62 fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
63 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
64 fw_dump->fw_attributes = htonl(ha->fw_attributes);
66 fw_dump->vendor = htonl(ha->pdev->vendor);
67 fw_dump->device = htonl(ha->pdev->device);
68 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
69 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
73 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr)
75 struct req_que *req = ha->req_q_map[0];
76 struct rsp_que *rsp = ha->rsp_q_map[0];
78 memcpy(ptr, req->ring, req->length *
82 ptr += req->length * sizeof(request_t);
83 memcpy(ptr, rsp->ring, rsp->length *
86 return ptr + (rsp->length * sizeof(response_t));
90 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram,
91 uint32_t ram_dwords, void **nxt)
94 uint32_t cnt, stat, timer, dwords, idx;
96 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
97 dma_addr_t dump_dma = ha->gid_list_dma;
98 uint32_t *dump = (uint32_t *)ha->gid_list;
103 WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
104 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
106 dwords = qla2x00_gid_list_size(ha) / 4;
107 for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
108 cnt += dwords, addr += dwords) {
109 if (cnt + dwords > ram_dwords)
110 dwords = ram_dwords - cnt;
112 WRT_REG_WORD(®->mailbox1, LSW(addr));
113 WRT_REG_WORD(®->mailbox8, MSW(addr));
115 WRT_REG_WORD(®->mailbox2, MSW(dump_dma));
116 WRT_REG_WORD(®->mailbox3, LSW(dump_dma));
117 WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma)));
118 WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma)));
120 WRT_REG_WORD(®->mailbox4, MSW(dwords));
121 WRT_REG_WORD(®->mailbox5, LSW(dwords));
122 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
124 for (timer = 6000000; timer; timer--) {
125 /* Check for pending interrupts. */
126 stat = RD_REG_DWORD(®->host_status);
127 if (stat & HSRX_RISC_INT) {
130 if (stat == 0x1 || stat == 0x2 ||
131 stat == 0x10 || stat == 0x11) {
132 set_bit(MBX_INTERRUPT,
135 mb0 = RD_REG_WORD(®->mailbox0);
137 WRT_REG_DWORD(®->hccr,
139 RD_REG_DWORD(®->hccr);
143 /* Clear this intr; it wasn't a mailbox intr */
144 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT);
145 RD_REG_DWORD(®->hccr);
150 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
151 rval = mb0 & MBS_MASK;
152 for (idx = 0; idx < dwords; idx++)
153 ram[cnt + idx] = swab32(dump[idx]);
155 rval = QLA_FUNCTION_FAILED;
159 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
164 qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram,
165 uint32_t cram_size, void **nxt)
170 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
171 if (rval != QLA_SUCCESS)
174 /* External Memory. */
175 return qla24xx_dump_ram(ha, 0x100000, *nxt,
176 ha->fw_memory_size - 0x100000 + 1, nxt);
180 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
181 uint32_t count, uint32_t *buf)
183 uint32_t __iomem *dmp_reg;
185 WRT_REG_DWORD(®->iobase_addr, iobase);
186 dmp_reg = ®->iobase_window;
188 *buf++ = htonl(RD_REG_DWORD(dmp_reg++));
194 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
196 int rval = QLA_SUCCESS;
199 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
201 ((RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) == 0) &&
202 rval == QLA_SUCCESS; cnt--) {
206 rval = QLA_FUNCTION_TIMEOUT;
213 qla24xx_soft_reset(struct qla_hw_data *ha)
215 int rval = QLA_SUCCESS;
218 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
221 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
222 for (cnt = 0; cnt < 30000; cnt++) {
223 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
229 WRT_REG_DWORD(®->ctrl_status,
230 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
231 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
234 /* Wait for firmware to complete NVRAM accesses. */
235 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
236 for (cnt = 10000 ; cnt && mb0; cnt--) {
238 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0);
242 /* Wait for soft-reset to complete. */
243 for (cnt = 0; cnt < 30000; cnt++) {
244 if ((RD_REG_DWORD(®->ctrl_status) &
245 CSRX_ISP_SOFT_RESET) == 0)
250 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
251 RD_REG_DWORD(®->hccr); /* PCI Posting. */
253 for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 &&
254 rval == QLA_SUCCESS; cnt--) {
258 rval = QLA_FUNCTION_TIMEOUT;
265 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram,
266 uint32_t ram_words, void **nxt)
269 uint32_t cnt, stat, timer, words, idx;
271 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
272 dma_addr_t dump_dma = ha->gid_list_dma;
273 uint16_t *dump = (uint16_t *)ha->gid_list;
278 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
279 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
281 words = qla2x00_gid_list_size(ha) / 2;
282 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
283 cnt += words, addr += words) {
284 if (cnt + words > ram_words)
285 words = ram_words - cnt;
287 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
288 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
290 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
291 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
292 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
293 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
295 WRT_MAILBOX_REG(ha, reg, 4, words);
296 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
298 for (timer = 6000000; timer; timer--) {
299 /* Check for pending interrupts. */
300 stat = RD_REG_DWORD(®->u.isp2300.host_status);
301 if (stat & HSR_RISC_INT) {
304 if (stat == 0x1 || stat == 0x2) {
305 set_bit(MBX_INTERRUPT,
308 mb0 = RD_MAILBOX_REG(ha, reg, 0);
310 /* Release mailbox registers. */
311 WRT_REG_WORD(®->semaphore, 0);
312 WRT_REG_WORD(®->hccr,
314 RD_REG_WORD(®->hccr);
316 } else if (stat == 0x10 || stat == 0x11) {
317 set_bit(MBX_INTERRUPT,
320 mb0 = RD_MAILBOX_REG(ha, reg, 0);
322 WRT_REG_WORD(®->hccr,
324 RD_REG_WORD(®->hccr);
328 /* clear this intr; it wasn't a mailbox intr */
329 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
330 RD_REG_WORD(®->hccr);
335 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
336 rval = mb0 & MBS_MASK;
337 for (idx = 0; idx < words; idx++)
338 ram[cnt + idx] = swab16(dump[idx]);
340 rval = QLA_FUNCTION_FAILED;
344 *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
349 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
352 uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd;
355 *buf++ = htons(RD_REG_WORD(dmp_reg++));
359 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr)
364 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
365 return ptr + ntohl(ha->fw_dump->eft_size);
369 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
373 struct qla2xxx_fce_chain *fcec = ptr;
378 *last_chain = &fcec->type;
379 fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
380 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
381 fce_calc_size(ha->fce_bufs));
382 fcec->size = htonl(fce_calc_size(ha->fce_bufs));
383 fcec->addr_l = htonl(LSD(ha->fce_dma));
384 fcec->addr_h = htonl(MSD(ha->fce_dma));
386 iter_reg = fcec->eregs;
387 for (cnt = 0; cnt < 8; cnt++)
388 *iter_reg++ = htonl(ha->fce_mb[cnt]);
390 memcpy(iter_reg, ha->fce, ntohl(fcec->size));
392 return (char *)iter_reg + ntohl(fcec->size);
396 qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr,
397 uint32_t **last_chain)
399 struct qla2xxx_mqueue_chain *q;
400 struct qla2xxx_mqueue_header *qh;
408 if (!ha->tgt.atio_ring)
413 aqp->length = ha->tgt.atio_q_length;
414 aqp->ring = ha->tgt.atio_ring;
416 for (que = 0; que < num_queues; que++) {
417 /* aqp = ha->atio_q_map[que]; */
419 *last_chain = &q->type;
420 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
421 q->chain_size = htonl(
422 sizeof(struct qla2xxx_mqueue_chain) +
423 sizeof(struct qla2xxx_mqueue_header) +
424 (aqp->length * sizeof(request_t)));
425 ptr += sizeof(struct qla2xxx_mqueue_chain);
429 qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
430 qh->number = htonl(que);
431 qh->size = htonl(aqp->length * sizeof(request_t));
432 ptr += sizeof(struct qla2xxx_mqueue_header);
435 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
437 ptr += aqp->length * sizeof(request_t);
444 qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
446 struct qla2xxx_mqueue_chain *q;
447 struct qla2xxx_mqueue_header *qh;
456 for (que = 1; que < ha->max_req_queues; que++) {
457 req = ha->req_q_map[que];
463 *last_chain = &q->type;
464 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
465 q->chain_size = htonl(
466 sizeof(struct qla2xxx_mqueue_chain) +
467 sizeof(struct qla2xxx_mqueue_header) +
468 (req->length * sizeof(request_t)));
469 ptr += sizeof(struct qla2xxx_mqueue_chain);
473 qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
474 qh->number = htonl(que);
475 qh->size = htonl(req->length * sizeof(request_t));
476 ptr += sizeof(struct qla2xxx_mqueue_header);
479 memcpy(ptr, req->ring, req->length * sizeof(request_t));
480 ptr += req->length * sizeof(request_t);
483 /* Response queues */
484 for (que = 1; que < ha->max_rsp_queues; que++) {
485 rsp = ha->rsp_q_map[que];
491 *last_chain = &q->type;
492 q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
493 q->chain_size = htonl(
494 sizeof(struct qla2xxx_mqueue_chain) +
495 sizeof(struct qla2xxx_mqueue_header) +
496 (rsp->length * sizeof(response_t)));
497 ptr += sizeof(struct qla2xxx_mqueue_chain);
501 qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
502 qh->number = htonl(que);
503 qh->size = htonl(rsp->length * sizeof(response_t));
504 ptr += sizeof(struct qla2xxx_mqueue_header);
507 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
508 ptr += rsp->length * sizeof(response_t);
515 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain)
517 uint32_t cnt, que_idx;
519 struct qla2xxx_mq_chain *mq = ptr;
520 struct device_reg_25xxmq __iomem *reg;
522 if (!ha->mqenable || IS_QLA83XX(ha))
526 *last_chain = &mq->type;
527 mq->type = __constant_htonl(DUMP_CHAIN_MQ);
528 mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
530 que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
531 ha->max_req_queues : ha->max_rsp_queues;
532 mq->count = htonl(que_cnt);
533 for (cnt = 0; cnt < que_cnt; cnt++) {
534 reg = (struct device_reg_25xxmq __iomem *)
535 (ha->mqiobase + cnt * QLA_QUE_PAGE);
537 mq->qregs[que_idx] = htonl(RD_REG_DWORD(®->req_q_in));
538 mq->qregs[que_idx+1] = htonl(RD_REG_DWORD(®->req_q_out));
539 mq->qregs[que_idx+2] = htonl(RD_REG_DWORD(®->rsp_q_in));
540 mq->qregs[que_idx+3] = htonl(RD_REG_DWORD(®->rsp_q_out));
543 return ptr + sizeof(struct qla2xxx_mq_chain);
547 qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
549 struct qla_hw_data *ha = vha->hw;
551 if (rval != QLA_SUCCESS) {
552 ql_log(ql_log_warn, vha, 0xd000,
553 "Failed to dump firmware (%x).\n", rval);
556 ql_log(ql_log_info, vha, 0xd001,
557 "Firmware dump saved to temp buffer (%ld/%p).\n",
558 vha->host_no, ha->fw_dump);
560 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
565 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
567 * @hardware_locked: Called with the hardware_lock
570 qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
574 struct qla_hw_data *ha = vha->hw;
575 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
576 uint16_t __iomem *dmp_reg;
578 struct qla2300_fw_dump *fw;
580 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
584 if (!hardware_locked)
585 spin_lock_irqsave(&ha->hardware_lock, flags);
588 ql_log(ql_log_warn, vha, 0xd002,
589 "No buffer available for dump.\n");
590 goto qla2300_fw_dump_failed;
594 ql_log(ql_log_warn, vha, 0xd003,
595 "Firmware has been previously dumped (%p) "
596 "-- ignoring request.\n",
598 goto qla2300_fw_dump_failed;
600 fw = &ha->fw_dump->isp.isp23;
601 qla2xxx_prep_dump(ha, ha->fw_dump);
604 fw->hccr = htons(RD_REG_WORD(®->hccr));
607 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
608 if (IS_QLA2300(ha)) {
610 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
611 rval == QLA_SUCCESS; cnt--) {
615 rval = QLA_FUNCTION_TIMEOUT;
618 RD_REG_WORD(®->hccr); /* PCI Posting. */
622 if (rval == QLA_SUCCESS) {
623 dmp_reg = ®->flash_address;
624 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
625 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
627 dmp_reg = ®->u.isp2300.req_q_in;
628 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
629 fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
631 dmp_reg = ®->u.isp2300.mailbox0;
632 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
633 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
635 WRT_REG_WORD(®->ctrl_status, 0x40);
636 qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
638 WRT_REG_WORD(®->ctrl_status, 0x50);
639 qla2xxx_read_window(reg, 48, fw->dma_reg);
641 WRT_REG_WORD(®->ctrl_status, 0x00);
642 dmp_reg = ®->risc_hw;
643 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
644 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
646 WRT_REG_WORD(®->pcr, 0x2000);
647 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
649 WRT_REG_WORD(®->pcr, 0x2200);
650 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
652 WRT_REG_WORD(®->pcr, 0x2400);
653 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
655 WRT_REG_WORD(®->pcr, 0x2600);
656 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
658 WRT_REG_WORD(®->pcr, 0x2800);
659 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
661 WRT_REG_WORD(®->pcr, 0x2A00);
662 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
664 WRT_REG_WORD(®->pcr, 0x2C00);
665 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
667 WRT_REG_WORD(®->pcr, 0x2E00);
668 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
670 WRT_REG_WORD(®->ctrl_status, 0x10);
671 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
673 WRT_REG_WORD(®->ctrl_status, 0x20);
674 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
676 WRT_REG_WORD(®->ctrl_status, 0x30);
677 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
680 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
681 for (cnt = 0; cnt < 30000; cnt++) {
682 if ((RD_REG_WORD(®->ctrl_status) &
683 CSR_ISP_SOFT_RESET) == 0)
690 if (!IS_QLA2300(ha)) {
691 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
692 rval == QLA_SUCCESS; cnt--) {
696 rval = QLA_FUNCTION_TIMEOUT;
701 if (rval == QLA_SUCCESS)
702 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
703 sizeof(fw->risc_ram) / 2, &nxt);
705 /* Get stack SRAM. */
706 if (rval == QLA_SUCCESS)
707 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
708 sizeof(fw->stack_ram) / 2, &nxt);
711 if (rval == QLA_SUCCESS)
712 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
713 ha->fw_memory_size - 0x11000 + 1, &nxt);
715 if (rval == QLA_SUCCESS)
716 qla2xxx_copy_queues(ha, nxt);
718 qla2xxx_dump_post_process(base_vha, rval);
720 qla2300_fw_dump_failed:
721 if (!hardware_locked)
722 spin_unlock_irqrestore(&ha->hardware_lock, flags);
726 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
728 * @hardware_locked: Called with the hardware_lock
731 qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
735 uint16_t risc_address;
737 struct qla_hw_data *ha = vha->hw;
738 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
739 uint16_t __iomem *dmp_reg;
741 struct qla2100_fw_dump *fw;
742 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
748 if (!hardware_locked)
749 spin_lock_irqsave(&ha->hardware_lock, flags);
752 ql_log(ql_log_warn, vha, 0xd004,
753 "No buffer available for dump.\n");
754 goto qla2100_fw_dump_failed;
758 ql_log(ql_log_warn, vha, 0xd005,
759 "Firmware has been previously dumped (%p) "
760 "-- ignoring request.\n",
762 goto qla2100_fw_dump_failed;
764 fw = &ha->fw_dump->isp.isp21;
765 qla2xxx_prep_dump(ha, ha->fw_dump);
768 fw->hccr = htons(RD_REG_WORD(®->hccr));
771 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
772 for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
773 rval == QLA_SUCCESS; cnt--) {
777 rval = QLA_FUNCTION_TIMEOUT;
779 if (rval == QLA_SUCCESS) {
780 dmp_reg = ®->flash_address;
781 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
782 fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
784 dmp_reg = ®->u.isp2100.mailbox0;
785 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
787 dmp_reg = ®->u_end.isp2200.mailbox8;
789 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
792 dmp_reg = ®->u.isp2100.unused_2[0];
793 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
794 fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
796 WRT_REG_WORD(®->ctrl_status, 0x00);
797 dmp_reg = ®->risc_hw;
798 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
799 fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
801 WRT_REG_WORD(®->pcr, 0x2000);
802 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
804 WRT_REG_WORD(®->pcr, 0x2100);
805 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
807 WRT_REG_WORD(®->pcr, 0x2200);
808 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
810 WRT_REG_WORD(®->pcr, 0x2300);
811 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
813 WRT_REG_WORD(®->pcr, 0x2400);
814 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
816 WRT_REG_WORD(®->pcr, 0x2500);
817 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
819 WRT_REG_WORD(®->pcr, 0x2600);
820 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
822 WRT_REG_WORD(®->pcr, 0x2700);
823 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
825 WRT_REG_WORD(®->ctrl_status, 0x10);
826 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
828 WRT_REG_WORD(®->ctrl_status, 0x20);
829 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
831 WRT_REG_WORD(®->ctrl_status, 0x30);
832 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
835 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
838 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
839 rval == QLA_SUCCESS; cnt--) {
843 rval = QLA_FUNCTION_TIMEOUT;
847 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
848 (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) {
850 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
852 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 &&
853 rval == QLA_SUCCESS; cnt--) {
857 rval = QLA_FUNCTION_TIMEOUT;
859 if (rval == QLA_SUCCESS) {
860 /* Set memory configuration and timing. */
862 WRT_REG_WORD(®->mctr, 0xf1);
864 WRT_REG_WORD(®->mctr, 0xf2);
865 RD_REG_WORD(®->mctr); /* PCI Posting. */
868 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
872 if (rval == QLA_SUCCESS) {
874 risc_address = 0x1000;
875 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
876 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
878 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
879 cnt++, risc_address++) {
880 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
881 WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT);
883 for (timer = 6000000; timer != 0; timer--) {
884 /* Check for pending interrupts. */
885 if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) {
886 if (RD_REG_WORD(®->semaphore) & BIT_0) {
887 set_bit(MBX_INTERRUPT,
890 mb0 = RD_MAILBOX_REG(ha, reg, 0);
891 mb2 = RD_MAILBOX_REG(ha, reg, 2);
893 WRT_REG_WORD(®->semaphore, 0);
894 WRT_REG_WORD(®->hccr,
896 RD_REG_WORD(®->hccr);
899 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
900 RD_REG_WORD(®->hccr);
905 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
906 rval = mb0 & MBS_MASK;
907 fw->risc_ram[cnt] = htons(mb2);
909 rval = QLA_FUNCTION_FAILED;
913 if (rval == QLA_SUCCESS)
914 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
916 qla2xxx_dump_post_process(base_vha, rval);
918 qla2100_fw_dump_failed:
919 if (!hardware_locked)
920 spin_unlock_irqrestore(&ha->hardware_lock, flags);
924 qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
928 uint32_t risc_address;
929 struct qla_hw_data *ha = vha->hw;
930 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
931 uint32_t __iomem *dmp_reg;
933 uint16_t __iomem *mbx_reg;
935 struct qla24xx_fw_dump *fw;
936 uint32_t ext_mem_cnt;
939 uint32_t *last_chain = NULL;
940 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
945 risc_address = ext_mem_cnt = 0;
948 if (!hardware_locked)
949 spin_lock_irqsave(&ha->hardware_lock, flags);
952 ql_log(ql_log_warn, vha, 0xd006,
953 "No buffer available for dump.\n");
954 goto qla24xx_fw_dump_failed;
958 ql_log(ql_log_warn, vha, 0xd007,
959 "Firmware has been previously dumped (%p) "
960 "-- ignoring request.\n",
962 goto qla24xx_fw_dump_failed;
964 fw = &ha->fw_dump->isp.isp24;
965 qla2xxx_prep_dump(ha, ha->fw_dump);
967 fw->host_status = htonl(RD_REG_DWORD(®->host_status));
970 rval = qla24xx_pause_risc(reg);
971 if (rval != QLA_SUCCESS)
972 goto qla24xx_fw_dump_failed_0;
974 /* Host interface registers. */
975 dmp_reg = ®->flash_addr;
976 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
977 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
979 /* Disable interrupts. */
980 WRT_REG_DWORD(®->ictrl, 0);
981 RD_REG_DWORD(®->ictrl);
983 /* Shadow registers. */
984 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
985 RD_REG_DWORD(®->iobase_addr);
986 WRT_REG_DWORD(®->iobase_select, 0xB0000000);
987 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
989 WRT_REG_DWORD(®->iobase_select, 0xB0100000);
990 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
992 WRT_REG_DWORD(®->iobase_select, 0xB0200000);
993 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
995 WRT_REG_DWORD(®->iobase_select, 0xB0300000);
996 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
998 WRT_REG_DWORD(®->iobase_select, 0xB0400000);
999 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
1001 WRT_REG_DWORD(®->iobase_select, 0xB0500000);
1002 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
1004 WRT_REG_DWORD(®->iobase_select, 0xB0600000);
1005 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
1007 /* Mailbox registers. */
1008 mbx_reg = ®->mailbox0;
1009 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1010 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1012 /* Transfer sequence registers. */
1013 iter_reg = fw->xseq_gp_reg;
1014 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1015 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1016 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1017 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1018 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1019 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1020 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1021 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1023 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
1024 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1026 /* Receive sequence registers. */
1027 iter_reg = fw->rseq_gp_reg;
1028 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1029 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1030 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1031 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1032 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1033 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1034 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1035 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1037 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
1038 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1039 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1041 /* Command DMA registers. */
1042 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1045 iter_reg = fw->req0_dma_reg;
1046 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1047 dmp_reg = ®->iobase_q;
1048 for (cnt = 0; cnt < 7; cnt++)
1049 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1051 iter_reg = fw->resp0_dma_reg;
1052 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1053 dmp_reg = ®->iobase_q;
1054 for (cnt = 0; cnt < 7; cnt++)
1055 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1057 iter_reg = fw->req1_dma_reg;
1058 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1059 dmp_reg = ®->iobase_q;
1060 for (cnt = 0; cnt < 7; cnt++)
1061 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1063 /* Transmit DMA registers. */
1064 iter_reg = fw->xmt0_dma_reg;
1065 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1066 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1068 iter_reg = fw->xmt1_dma_reg;
1069 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1070 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1072 iter_reg = fw->xmt2_dma_reg;
1073 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1074 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1076 iter_reg = fw->xmt3_dma_reg;
1077 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1078 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1080 iter_reg = fw->xmt4_dma_reg;
1081 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1082 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1084 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1086 /* Receive DMA registers. */
1087 iter_reg = fw->rcvt0_data_dma_reg;
1088 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1089 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1091 iter_reg = fw->rcvt1_data_dma_reg;
1092 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1093 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1095 /* RISC registers. */
1096 iter_reg = fw->risc_gp_reg;
1097 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1098 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1099 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1100 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1101 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1102 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1103 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1104 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1106 /* Local memory controller registers. */
1107 iter_reg = fw->lmc_reg;
1108 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1109 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1110 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1111 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1112 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1113 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1114 qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1116 /* Fibre Protocol Module registers. */
1117 iter_reg = fw->fpm_hdw_reg;
1118 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1119 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1120 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1121 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1122 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1123 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1124 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1125 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1126 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1127 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1128 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1129 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1131 /* Frame Buffer registers. */
1132 iter_reg = fw->fb_hdw_reg;
1133 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1134 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1135 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1136 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1137 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1138 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1139 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1140 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1141 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1142 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1143 qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1145 rval = qla24xx_soft_reset(ha);
1146 if (rval != QLA_SUCCESS)
1147 goto qla24xx_fw_dump_failed_0;
1149 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1151 if (rval != QLA_SUCCESS)
1152 goto qla24xx_fw_dump_failed_0;
1154 nxt = qla2xxx_copy_queues(ha, nxt);
1156 qla24xx_copy_eft(ha, nxt);
1158 nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
1159 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1161 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1162 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1165 /* Adjust valid length. */
1166 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1168 qla24xx_fw_dump_failed_0:
1169 qla2xxx_dump_post_process(base_vha, rval);
1171 qla24xx_fw_dump_failed:
1172 if (!hardware_locked)
1173 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1177 qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1181 uint32_t risc_address;
1182 struct qla_hw_data *ha = vha->hw;
1183 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1184 uint32_t __iomem *dmp_reg;
1186 uint16_t __iomem *mbx_reg;
1187 unsigned long flags;
1188 struct qla25xx_fw_dump *fw;
1189 uint32_t ext_mem_cnt;
1190 void *nxt, *nxt_chain;
1191 uint32_t *last_chain = NULL;
1192 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1194 risc_address = ext_mem_cnt = 0;
1197 if (!hardware_locked)
1198 spin_lock_irqsave(&ha->hardware_lock, flags);
1201 ql_log(ql_log_warn, vha, 0xd008,
1202 "No buffer available for dump.\n");
1203 goto qla25xx_fw_dump_failed;
1206 if (ha->fw_dumped) {
1207 ql_log(ql_log_warn, vha, 0xd009,
1208 "Firmware has been previously dumped (%p) "
1209 "-- ignoring request.\n",
1211 goto qla25xx_fw_dump_failed;
1213 fw = &ha->fw_dump->isp.isp25;
1214 qla2xxx_prep_dump(ha, ha->fw_dump);
1215 ha->fw_dump->version = __constant_htonl(2);
1217 fw->host_status = htonl(RD_REG_DWORD(®->host_status));
1220 rval = qla24xx_pause_risc(reg);
1221 if (rval != QLA_SUCCESS)
1222 goto qla25xx_fw_dump_failed_0;
1224 /* Host/Risc registers. */
1225 iter_reg = fw->host_risc_reg;
1226 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1227 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1229 /* PCIe registers. */
1230 WRT_REG_DWORD(®->iobase_addr, 0x7C00);
1231 RD_REG_DWORD(®->iobase_addr);
1232 WRT_REG_DWORD(®->iobase_window, 0x01);
1233 dmp_reg = ®->iobase_c4;
1234 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1235 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1236 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1237 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window));
1239 WRT_REG_DWORD(®->iobase_window, 0x00);
1240 RD_REG_DWORD(®->iobase_window);
1242 /* Host interface registers. */
1243 dmp_reg = ®->flash_addr;
1244 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1245 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1247 /* Disable interrupts. */
1248 WRT_REG_DWORD(®->ictrl, 0);
1249 RD_REG_DWORD(®->ictrl);
1251 /* Shadow registers. */
1252 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
1253 RD_REG_DWORD(®->iobase_addr);
1254 WRT_REG_DWORD(®->iobase_select, 0xB0000000);
1255 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
1257 WRT_REG_DWORD(®->iobase_select, 0xB0100000);
1258 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
1260 WRT_REG_DWORD(®->iobase_select, 0xB0200000);
1261 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
1263 WRT_REG_DWORD(®->iobase_select, 0xB0300000);
1264 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
1266 WRT_REG_DWORD(®->iobase_select, 0xB0400000);
1267 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
1269 WRT_REG_DWORD(®->iobase_select, 0xB0500000);
1270 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
1272 WRT_REG_DWORD(®->iobase_select, 0xB0600000);
1273 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
1275 WRT_REG_DWORD(®->iobase_select, 0xB0700000);
1276 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata));
1278 WRT_REG_DWORD(®->iobase_select, 0xB0800000);
1279 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata));
1281 WRT_REG_DWORD(®->iobase_select, 0xB0900000);
1282 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata));
1284 WRT_REG_DWORD(®->iobase_select, 0xB0A00000);
1285 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata));
1287 /* RISC I/O register. */
1288 WRT_REG_DWORD(®->iobase_addr, 0x0010);
1289 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window));
1291 /* Mailbox registers. */
1292 mbx_reg = ®->mailbox0;
1293 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1294 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1296 /* Transfer sequence registers. */
1297 iter_reg = fw->xseq_gp_reg;
1298 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1299 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1300 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1301 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1302 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1303 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1304 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1305 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1307 iter_reg = fw->xseq_0_reg;
1308 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1309 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1310 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1312 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1314 /* Receive sequence registers. */
1315 iter_reg = fw->rseq_gp_reg;
1316 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1317 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1318 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1319 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1320 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1321 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1322 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1323 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1325 iter_reg = fw->rseq_0_reg;
1326 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1327 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1329 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1330 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1332 /* Auxiliary sequence registers. */
1333 iter_reg = fw->aseq_gp_reg;
1334 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1335 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1336 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1337 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1338 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1339 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1340 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1341 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1343 iter_reg = fw->aseq_0_reg;
1344 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1345 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1347 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1348 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1350 /* Command DMA registers. */
1351 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1354 iter_reg = fw->req0_dma_reg;
1355 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1356 dmp_reg = ®->iobase_q;
1357 for (cnt = 0; cnt < 7; cnt++)
1358 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1360 iter_reg = fw->resp0_dma_reg;
1361 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1362 dmp_reg = ®->iobase_q;
1363 for (cnt = 0; cnt < 7; cnt++)
1364 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1366 iter_reg = fw->req1_dma_reg;
1367 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1368 dmp_reg = ®->iobase_q;
1369 for (cnt = 0; cnt < 7; cnt++)
1370 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1372 /* Transmit DMA registers. */
1373 iter_reg = fw->xmt0_dma_reg;
1374 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1375 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1377 iter_reg = fw->xmt1_dma_reg;
1378 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1379 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1381 iter_reg = fw->xmt2_dma_reg;
1382 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1383 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1385 iter_reg = fw->xmt3_dma_reg;
1386 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1387 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1389 iter_reg = fw->xmt4_dma_reg;
1390 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1391 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1393 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1395 /* Receive DMA registers. */
1396 iter_reg = fw->rcvt0_data_dma_reg;
1397 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1398 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1400 iter_reg = fw->rcvt1_data_dma_reg;
1401 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1402 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1404 /* RISC registers. */
1405 iter_reg = fw->risc_gp_reg;
1406 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1407 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1408 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1409 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1410 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1411 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1412 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1413 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1415 /* Local memory controller registers. */
1416 iter_reg = fw->lmc_reg;
1417 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1418 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1419 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1420 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1421 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1422 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1423 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1424 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1426 /* Fibre Protocol Module registers. */
1427 iter_reg = fw->fpm_hdw_reg;
1428 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1429 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1430 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1431 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1432 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1433 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1434 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1435 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1436 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1437 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1438 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1439 qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1441 /* Frame Buffer registers. */
1442 iter_reg = fw->fb_hdw_reg;
1443 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1444 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1445 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1446 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1447 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1448 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1449 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1450 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1451 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1452 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1453 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1454 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1456 /* Multi queue registers */
1457 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1460 rval = qla24xx_soft_reset(ha);
1461 if (rval != QLA_SUCCESS)
1462 goto qla25xx_fw_dump_failed_0;
1464 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1466 if (rval != QLA_SUCCESS)
1467 goto qla25xx_fw_dump_failed_0;
1469 nxt = qla2xxx_copy_queues(ha, nxt);
1471 nxt = qla24xx_copy_eft(ha, nxt);
1473 /* Chain entries -- started with MQ. */
1474 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1475 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1476 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1478 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1479 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1482 /* Adjust valid length. */
1483 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1485 qla25xx_fw_dump_failed_0:
1486 qla2xxx_dump_post_process(base_vha, rval);
1488 qla25xx_fw_dump_failed:
1489 if (!hardware_locked)
1490 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1494 qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1498 uint32_t risc_address;
1499 struct qla_hw_data *ha = vha->hw;
1500 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1501 uint32_t __iomem *dmp_reg;
1503 uint16_t __iomem *mbx_reg;
1504 unsigned long flags;
1505 struct qla81xx_fw_dump *fw;
1506 uint32_t ext_mem_cnt;
1507 void *nxt, *nxt_chain;
1508 uint32_t *last_chain = NULL;
1509 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1511 risc_address = ext_mem_cnt = 0;
1514 if (!hardware_locked)
1515 spin_lock_irqsave(&ha->hardware_lock, flags);
1518 ql_log(ql_log_warn, vha, 0xd00a,
1519 "No buffer available for dump.\n");
1520 goto qla81xx_fw_dump_failed;
1523 if (ha->fw_dumped) {
1524 ql_log(ql_log_warn, vha, 0xd00b,
1525 "Firmware has been previously dumped (%p) "
1526 "-- ignoring request.\n",
1528 goto qla81xx_fw_dump_failed;
1530 fw = &ha->fw_dump->isp.isp81;
1531 qla2xxx_prep_dump(ha, ha->fw_dump);
1533 fw->host_status = htonl(RD_REG_DWORD(®->host_status));
1536 rval = qla24xx_pause_risc(reg);
1537 if (rval != QLA_SUCCESS)
1538 goto qla81xx_fw_dump_failed_0;
1540 /* Host/Risc registers. */
1541 iter_reg = fw->host_risc_reg;
1542 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1543 qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1545 /* PCIe registers. */
1546 WRT_REG_DWORD(®->iobase_addr, 0x7C00);
1547 RD_REG_DWORD(®->iobase_addr);
1548 WRT_REG_DWORD(®->iobase_window, 0x01);
1549 dmp_reg = ®->iobase_c4;
1550 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1551 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1552 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1553 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window));
1555 WRT_REG_DWORD(®->iobase_window, 0x00);
1556 RD_REG_DWORD(®->iobase_window);
1558 /* Host interface registers. */
1559 dmp_reg = ®->flash_addr;
1560 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1561 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1563 /* Disable interrupts. */
1564 WRT_REG_DWORD(®->ictrl, 0);
1565 RD_REG_DWORD(®->ictrl);
1567 /* Shadow registers. */
1568 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
1569 RD_REG_DWORD(®->iobase_addr);
1570 WRT_REG_DWORD(®->iobase_select, 0xB0000000);
1571 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
1573 WRT_REG_DWORD(®->iobase_select, 0xB0100000);
1574 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
1576 WRT_REG_DWORD(®->iobase_select, 0xB0200000);
1577 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
1579 WRT_REG_DWORD(®->iobase_select, 0xB0300000);
1580 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
1582 WRT_REG_DWORD(®->iobase_select, 0xB0400000);
1583 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
1585 WRT_REG_DWORD(®->iobase_select, 0xB0500000);
1586 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
1588 WRT_REG_DWORD(®->iobase_select, 0xB0600000);
1589 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
1591 WRT_REG_DWORD(®->iobase_select, 0xB0700000);
1592 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata));
1594 WRT_REG_DWORD(®->iobase_select, 0xB0800000);
1595 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata));
1597 WRT_REG_DWORD(®->iobase_select, 0xB0900000);
1598 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata));
1600 WRT_REG_DWORD(®->iobase_select, 0xB0A00000);
1601 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata));
1603 /* RISC I/O register. */
1604 WRT_REG_DWORD(®->iobase_addr, 0x0010);
1605 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window));
1607 /* Mailbox registers. */
1608 mbx_reg = ®->mailbox0;
1609 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1610 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1612 /* Transfer sequence registers. */
1613 iter_reg = fw->xseq_gp_reg;
1614 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1615 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1616 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1617 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1618 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1619 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1620 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1621 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1623 iter_reg = fw->xseq_0_reg;
1624 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1625 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1626 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1628 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1630 /* Receive sequence registers. */
1631 iter_reg = fw->rseq_gp_reg;
1632 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1633 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1634 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1635 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1636 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1637 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1638 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1639 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1641 iter_reg = fw->rseq_0_reg;
1642 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1643 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
1645 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
1646 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
1648 /* Auxiliary sequence registers. */
1649 iter_reg = fw->aseq_gp_reg;
1650 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
1651 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
1652 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
1653 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
1654 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
1655 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
1656 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
1657 qla24xx_read_window(reg, 0xB070, 16, iter_reg);
1659 iter_reg = fw->aseq_0_reg;
1660 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
1661 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
1663 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
1664 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
1666 /* Command DMA registers. */
1667 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
1670 iter_reg = fw->req0_dma_reg;
1671 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
1672 dmp_reg = ®->iobase_q;
1673 for (cnt = 0; cnt < 7; cnt++)
1674 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1676 iter_reg = fw->resp0_dma_reg;
1677 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
1678 dmp_reg = ®->iobase_q;
1679 for (cnt = 0; cnt < 7; cnt++)
1680 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1682 iter_reg = fw->req1_dma_reg;
1683 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
1684 dmp_reg = ®->iobase_q;
1685 for (cnt = 0; cnt < 7; cnt++)
1686 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
1688 /* Transmit DMA registers. */
1689 iter_reg = fw->xmt0_dma_reg;
1690 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
1691 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
1693 iter_reg = fw->xmt1_dma_reg;
1694 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
1695 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
1697 iter_reg = fw->xmt2_dma_reg;
1698 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
1699 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
1701 iter_reg = fw->xmt3_dma_reg;
1702 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
1703 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
1705 iter_reg = fw->xmt4_dma_reg;
1706 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
1707 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
1709 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
1711 /* Receive DMA registers. */
1712 iter_reg = fw->rcvt0_data_dma_reg;
1713 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
1714 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
1716 iter_reg = fw->rcvt1_data_dma_reg;
1717 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
1718 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
1720 /* RISC registers. */
1721 iter_reg = fw->risc_gp_reg;
1722 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
1723 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
1724 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
1725 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
1726 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
1727 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
1728 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
1729 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
1731 /* Local memory controller registers. */
1732 iter_reg = fw->lmc_reg;
1733 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
1734 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
1735 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
1736 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
1737 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
1738 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
1739 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
1740 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
1742 /* Fibre Protocol Module registers. */
1743 iter_reg = fw->fpm_hdw_reg;
1744 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
1745 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
1746 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
1747 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
1748 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
1749 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
1750 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
1751 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
1752 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
1753 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
1754 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
1755 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
1756 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
1757 qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
1759 /* Frame Buffer registers. */
1760 iter_reg = fw->fb_hdw_reg;
1761 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
1762 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
1763 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
1764 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
1765 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
1766 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
1767 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
1768 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
1769 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
1770 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
1771 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
1772 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
1773 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
1775 /* Multi queue registers */
1776 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
1779 rval = qla24xx_soft_reset(ha);
1780 if (rval != QLA_SUCCESS)
1781 goto qla81xx_fw_dump_failed_0;
1783 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
1785 if (rval != QLA_SUCCESS)
1786 goto qla81xx_fw_dump_failed_0;
1788 nxt = qla2xxx_copy_queues(ha, nxt);
1790 nxt = qla24xx_copy_eft(ha, nxt);
1792 /* Chain entries -- started with MQ. */
1793 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
1794 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
1795 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
1797 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
1798 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
1801 /* Adjust valid length. */
1802 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
1804 qla81xx_fw_dump_failed_0:
1805 qla2xxx_dump_post_process(base_vha, rval);
1807 qla81xx_fw_dump_failed:
1808 if (!hardware_locked)
1809 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1813 qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
1816 uint32_t cnt, reg_data;
1817 uint32_t risc_address;
1818 struct qla_hw_data *ha = vha->hw;
1819 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1820 uint32_t __iomem *dmp_reg;
1822 uint16_t __iomem *mbx_reg;
1823 unsigned long flags;
1824 struct qla83xx_fw_dump *fw;
1825 uint32_t ext_mem_cnt;
1826 void *nxt, *nxt_chain;
1827 uint32_t *last_chain = NULL;
1828 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
1830 risc_address = ext_mem_cnt = 0;
1833 if (!hardware_locked)
1834 spin_lock_irqsave(&ha->hardware_lock, flags);
1837 ql_log(ql_log_warn, vha, 0xd00c,
1838 "No buffer available for dump!!!\n");
1839 goto qla83xx_fw_dump_failed;
1842 if (ha->fw_dumped) {
1843 ql_log(ql_log_warn, vha, 0xd00d,
1844 "Firmware has been previously dumped (%p) -- ignoring "
1845 "request...\n", ha->fw_dump);
1846 goto qla83xx_fw_dump_failed;
1848 fw = &ha->fw_dump->isp.isp83;
1849 qla2xxx_prep_dump(ha, ha->fw_dump);
1851 fw->host_status = htonl(RD_REG_DWORD(®->host_status));
1854 rval = qla24xx_pause_risc(reg);
1855 if (rval != QLA_SUCCESS)
1856 goto qla83xx_fw_dump_failed_0;
1858 WRT_REG_DWORD(®->iobase_addr, 0x6000);
1859 dmp_reg = ®->iobase_window;
1860 reg_data = RD_REG_DWORD(dmp_reg);
1861 WRT_REG_DWORD(dmp_reg, 0);
1863 dmp_reg = ®->unused_4_1[0];
1864 reg_data = RD_REG_DWORD(dmp_reg);
1865 WRT_REG_DWORD(dmp_reg, 0);
1867 WRT_REG_DWORD(®->iobase_addr, 0x6010);
1868 dmp_reg = ®->unused_4_1[2];
1869 reg_data = RD_REG_DWORD(dmp_reg);
1870 WRT_REG_DWORD(dmp_reg, 0);
1872 /* select PCR and disable ecc checking and correction */
1873 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
1874 RD_REG_DWORD(®->iobase_addr);
1875 WRT_REG_DWORD(®->iobase_select, 0x60000000); /* write to F0h = PCR */
1877 /* Host/Risc registers. */
1878 iter_reg = fw->host_risc_reg;
1879 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
1880 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
1881 qla24xx_read_window(reg, 0x7040, 16, iter_reg);
1883 /* PCIe registers. */
1884 WRT_REG_DWORD(®->iobase_addr, 0x7C00);
1885 RD_REG_DWORD(®->iobase_addr);
1886 WRT_REG_DWORD(®->iobase_window, 0x01);
1887 dmp_reg = ®->iobase_c4;
1888 fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
1889 fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
1890 fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
1891 fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window));
1893 WRT_REG_DWORD(®->iobase_window, 0x00);
1894 RD_REG_DWORD(®->iobase_window);
1896 /* Host interface registers. */
1897 dmp_reg = ®->flash_addr;
1898 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1899 fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
1901 /* Disable interrupts. */
1902 WRT_REG_DWORD(®->ictrl, 0);
1903 RD_REG_DWORD(®->ictrl);
1905 /* Shadow registers. */
1906 WRT_REG_DWORD(®->iobase_addr, 0x0F70);
1907 RD_REG_DWORD(®->iobase_addr);
1908 WRT_REG_DWORD(®->iobase_select, 0xB0000000);
1909 fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata));
1911 WRT_REG_DWORD(®->iobase_select, 0xB0100000);
1912 fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata));
1914 WRT_REG_DWORD(®->iobase_select, 0xB0200000);
1915 fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata));
1917 WRT_REG_DWORD(®->iobase_select, 0xB0300000);
1918 fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata));
1920 WRT_REG_DWORD(®->iobase_select, 0xB0400000);
1921 fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata));
1923 WRT_REG_DWORD(®->iobase_select, 0xB0500000);
1924 fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata));
1926 WRT_REG_DWORD(®->iobase_select, 0xB0600000);
1927 fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata));
1929 WRT_REG_DWORD(®->iobase_select, 0xB0700000);
1930 fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata));
1932 WRT_REG_DWORD(®->iobase_select, 0xB0800000);
1933 fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata));
1935 WRT_REG_DWORD(®->iobase_select, 0xB0900000);
1936 fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata));
1938 WRT_REG_DWORD(®->iobase_select, 0xB0A00000);
1939 fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata));
1941 /* RISC I/O register. */
1942 WRT_REG_DWORD(®->iobase_addr, 0x0010);
1943 fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window));
1945 /* Mailbox registers. */
1946 mbx_reg = ®->mailbox0;
1947 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1948 fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
1950 /* Transfer sequence registers. */
1951 iter_reg = fw->xseq_gp_reg;
1952 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
1953 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
1954 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
1955 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
1956 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
1957 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
1958 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
1959 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
1960 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
1961 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
1962 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
1963 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
1964 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
1965 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
1966 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
1967 qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
1969 iter_reg = fw->xseq_0_reg;
1970 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
1971 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
1972 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
1974 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
1976 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
1978 /* Receive sequence registers. */
1979 iter_reg = fw->rseq_gp_reg;
1980 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
1981 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
1982 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
1983 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
1984 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
1985 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
1986 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
1987 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
1988 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
1989 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
1990 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
1991 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
1992 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
1993 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
1994 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
1995 qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
1997 iter_reg = fw->rseq_0_reg;
1998 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
1999 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
2001 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
2002 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
2003 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
2005 /* Auxiliary sequence registers. */
2006 iter_reg = fw->aseq_gp_reg;
2007 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
2008 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
2009 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
2010 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
2011 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
2012 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
2013 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
2014 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
2015 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
2016 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
2017 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
2018 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
2019 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
2020 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
2021 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
2022 qla24xx_read_window(reg, 0xB170, 16, iter_reg);
2024 iter_reg = fw->aseq_0_reg;
2025 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
2026 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
2028 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
2029 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
2030 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
2032 /* Command DMA registers. */
2033 iter_reg = fw->cmd_dma_reg;
2034 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
2035 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
2036 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
2037 qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
2040 iter_reg = fw->req0_dma_reg;
2041 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
2042 dmp_reg = ®->iobase_q;
2043 for (cnt = 0; cnt < 7; cnt++)
2044 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2046 iter_reg = fw->resp0_dma_reg;
2047 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
2048 dmp_reg = ®->iobase_q;
2049 for (cnt = 0; cnt < 7; cnt++)
2050 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2052 iter_reg = fw->req1_dma_reg;
2053 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
2054 dmp_reg = ®->iobase_q;
2055 for (cnt = 0; cnt < 7; cnt++)
2056 *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
2058 /* Transmit DMA registers. */
2059 iter_reg = fw->xmt0_dma_reg;
2060 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
2061 qla24xx_read_window(reg, 0x7610, 16, iter_reg);
2063 iter_reg = fw->xmt1_dma_reg;
2064 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
2065 qla24xx_read_window(reg, 0x7630, 16, iter_reg);
2067 iter_reg = fw->xmt2_dma_reg;
2068 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
2069 qla24xx_read_window(reg, 0x7650, 16, iter_reg);
2071 iter_reg = fw->xmt3_dma_reg;
2072 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
2073 qla24xx_read_window(reg, 0x7670, 16, iter_reg);
2075 iter_reg = fw->xmt4_dma_reg;
2076 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
2077 qla24xx_read_window(reg, 0x7690, 16, iter_reg);
2079 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
2081 /* Receive DMA registers. */
2082 iter_reg = fw->rcvt0_data_dma_reg;
2083 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
2084 qla24xx_read_window(reg, 0x7710, 16, iter_reg);
2086 iter_reg = fw->rcvt1_data_dma_reg;
2087 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
2088 qla24xx_read_window(reg, 0x7730, 16, iter_reg);
2090 /* RISC registers. */
2091 iter_reg = fw->risc_gp_reg;
2092 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
2093 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
2094 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
2095 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
2096 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
2097 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
2098 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
2099 qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
2101 /* Local memory controller registers. */
2102 iter_reg = fw->lmc_reg;
2103 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
2104 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
2105 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
2106 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
2107 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
2108 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
2109 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
2110 qla24xx_read_window(reg, 0x3070, 16, iter_reg);
2112 /* Fibre Protocol Module registers. */
2113 iter_reg = fw->fpm_hdw_reg;
2114 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
2115 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
2116 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
2117 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
2118 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
2119 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
2120 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
2121 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
2122 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
2123 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
2124 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
2125 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
2126 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
2127 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
2128 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
2129 qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
2131 /* RQ0 Array registers. */
2132 iter_reg = fw->rq0_array_reg;
2133 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
2134 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
2135 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
2136 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
2137 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
2138 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
2139 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
2140 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
2141 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
2142 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
2143 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
2144 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
2145 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
2146 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
2147 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
2148 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
2150 /* RQ1 Array registers. */
2151 iter_reg = fw->rq1_array_reg;
2152 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
2153 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
2154 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
2155 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
2156 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
2157 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
2158 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
2159 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
2160 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
2161 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
2162 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
2163 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
2164 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
2165 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
2166 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
2167 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
2169 /* RP0 Array registers. */
2170 iter_reg = fw->rp0_array_reg;
2171 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
2172 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
2173 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
2174 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
2175 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
2176 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
2177 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
2178 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
2179 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
2180 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
2181 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
2182 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
2183 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
2184 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
2185 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
2186 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
2188 /* RP1 Array registers. */
2189 iter_reg = fw->rp1_array_reg;
2190 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
2191 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
2192 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
2193 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
2194 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
2195 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
2196 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
2197 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
2198 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
2199 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
2200 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
2201 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
2202 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
2203 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
2204 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
2205 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
2207 iter_reg = fw->at0_array_reg;
2208 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
2209 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
2210 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
2211 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
2212 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
2213 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
2214 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
2215 qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
2217 /* I/O Queue Control registers. */
2218 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
2220 /* Frame Buffer registers. */
2221 iter_reg = fw->fb_hdw_reg;
2222 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
2223 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
2224 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
2225 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
2226 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
2227 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
2228 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
2229 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
2230 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
2231 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
2232 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
2233 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
2234 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
2235 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
2236 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
2237 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
2238 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
2239 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
2240 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
2241 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
2242 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
2243 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
2244 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
2245 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
2246 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
2247 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
2248 qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
2250 /* Multi queue registers */
2251 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
2254 rval = qla24xx_soft_reset(ha);
2255 if (rval != QLA_SUCCESS) {
2256 ql_log(ql_log_warn, vha, 0xd00e,
2257 "SOFT RESET FAILED, forcing continuation of dump!!!\n");
2260 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
2262 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET);
2263 RD_REG_DWORD(®->hccr);
2265 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE);
2266 RD_REG_DWORD(®->hccr);
2268 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
2269 RD_REG_DWORD(®->hccr);
2271 for (cnt = 30000; cnt && (RD_REG_WORD(®->mailbox0)); cnt--)
2276 nxt += sizeof(fw->code_ram);
2277 nxt += (ha->fw_memory_size - 0x100000 + 1);
2280 ql_log(ql_log_warn, vha, 0xd010,
2281 "bigger hammer success?\n");
2284 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
2286 if (rval != QLA_SUCCESS)
2287 goto qla83xx_fw_dump_failed_0;
2290 nxt = qla2xxx_copy_queues(ha, nxt);
2292 nxt = qla24xx_copy_eft(ha, nxt);
2294 /* Chain entries -- started with MQ. */
2295 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
2296 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
2297 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
2299 ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);
2300 *last_chain |= __constant_htonl(DUMP_CHAIN_LAST);
2303 /* Adjust valid length. */
2304 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
2306 qla83xx_fw_dump_failed_0:
2307 qla2xxx_dump_post_process(base_vha, rval);
2309 qla83xx_fw_dump_failed:
2310 if (!hardware_locked)
2311 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2314 /****************************************************************************/
2315 /* Driver Debug Functions. */
2316 /****************************************************************************/
2319 ql_mask_match(uint32_t level)
2321 if (ql2xextended_error_logging == 1)
2322 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2323 return (level & ql2xextended_error_logging) == level;
2327 * This function is for formatting and logging debug information.
2328 * It is to be used when vha is available. It formats the message
2329 * and logs it to the messages file.
2331 * level: The level of the debug messages to be printed.
2332 * If ql2xextended_error_logging value is correctly set,
2333 * this message will appear in the messages file.
2334 * vha: Pointer to the scsi_qla_host_t.
2335 * id: This is a unique identifier for the level. It identifies the
2336 * part of the code from where the message originated.
2337 * msg: The message to be displayed.
2340 ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2343 struct va_format vaf;
2345 if (!ql_mask_match(level))
2354 const struct pci_dev *pdev = vha->hw->pdev;
2355 /* <module-name> <pci-name> <msg-id>:<host> Message */
2356 pr_warn("%s [%s]-%04x:%ld: %pV",
2357 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
2358 vha->host_no, &vaf);
2360 pr_warn("%s [%s]-%04x: : %pV",
2361 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
2369 * This function is for formatting and logging debug information.
2370 * It is to be used when vha is not available and pci is available,
2371 * i.e., before host allocation. It formats the message and logs it
2372 * to the messages file.
2374 * level: The level of the debug messages to be printed.
2375 * If ql2xextended_error_logging value is correctly set,
2376 * this message will appear in the messages file.
2377 * pdev: Pointer to the struct pci_dev.
2378 * id: This is a unique id for the level. It identifies the part
2379 * of the code from where the message originated.
2380 * msg: The message to be displayed.
2383 ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2384 const char *fmt, ...)
2387 struct va_format vaf;
2391 if (!ql_mask_match(level))
2399 /* <module-name> <dev-name>:<msg-id> Message */
2400 pr_warn("%s [%s]-%04x: : %pV",
2401 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
2407 * This function is for formatting and logging log messages.
2408 * It is to be used when vha is available. It formats the message
2409 * and logs it to the messages file. All the messages will be logged
2410 * irrespective of value of ql2xextended_error_logging.
2412 * level: The level of the log messages to be printed in the
2414 * vha: Pointer to the scsi_qla_host_t
2415 * id: This is a unique id for the level. It identifies the
2416 * part of the code from where the message originated.
2417 * msg: The message to be displayed.
2420 ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...)
2423 struct va_format vaf;
2426 if (level > ql_errlev)
2430 const struct pci_dev *pdev = vha->hw->pdev;
2431 /* <module-name> <msg-id>:<host> Message */
2432 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
2433 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
2435 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2436 QL_MSGHDR, "0000:00:00.0", id);
2438 pbuf[sizeof(pbuf) - 1] = 0;
2446 case ql_log_fatal: /* FATAL LOG */
2447 pr_crit("%s%pV", pbuf, &vaf);
2450 pr_err("%s%pV", pbuf, &vaf);
2453 pr_warn("%s%pV", pbuf, &vaf);
2456 pr_info("%s%pV", pbuf, &vaf);
2464 * This function is for formatting and logging log messages.
2465 * It is to be used when vha is not available and pci is available,
2466 * i.e., before host allocation. It formats the message and logs
2467 * it to the messages file. All the messages are logged irrespective
2468 * of the value of ql2xextended_error_logging.
2470 * level: The level of the log messages to be printed in the
2472 * pdev: Pointer to the struct pci_dev.
2473 * id: This is a unique id for the level. It identifies the
2474 * part of the code from where the message originated.
2475 * msg: The message to be displayed.
2478 ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
2479 const char *fmt, ...)
2482 struct va_format vaf;
2487 if (level > ql_errlev)
2490 /* <module-name> <dev-name>:<msg-id> Message */
2491 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
2492 QL_MSGHDR, dev_name(&(pdev->dev)), id);
2493 pbuf[sizeof(pbuf) - 1] = 0;
2501 case ql_log_fatal: /* FATAL LOG */
2502 pr_crit("%s%pV", pbuf, &vaf);
2505 pr_err("%s%pV", pbuf, &vaf);
2508 pr_warn("%s%pV", pbuf, &vaf);
2511 pr_info("%s%pV", pbuf, &vaf);
2519 ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
2522 struct qla_hw_data *ha = vha->hw;
2523 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2524 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
2525 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
2526 uint16_t __iomem *mbx_reg;
2528 if (!ql_mask_match(level))
2532 mbx_reg = ®82->mailbox_in[0];
2533 else if (IS_FWI2_CAPABLE(ha))
2534 mbx_reg = ®24->mailbox0;
2536 mbx_reg = MAILBOX_REG(ha, reg, 0);
2538 ql_dbg(level, vha, id, "Mailbox registers:\n");
2539 for (i = 0; i < 6; i++)
2540 ql_dbg(level, vha, id,
2541 "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
2546 ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
2547 uint8_t *b, uint32_t size)
2552 if (!ql_mask_match(level))
2555 ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
2556 "9 Ah Bh Ch Dh Eh Fh\n");
2557 ql_dbg(level, vha, id, "----------------------------------"
2558 "----------------------------\n");
2560 ql_dbg(level, vha, id, " ");
2561 for (cnt = 0; cnt < size;) {
2563 printk("%02x", (uint32_t) c);
2571 ql_dbg(level, vha, id, "\n");