2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
8 #include <linux/delay.h>
10 #include <linux/ratelimit.h>
11 #include <linux/vmalloc.h>
12 #include <scsi/scsi_tcq.h>
14 #define MASK(n) ((1ULL<<(n))-1)
15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
25 #define BLOCK_PROTECT_BITS 0x0F
27 /* CRB window related */
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35 #define CRB_INDIRECT_2M (0x1e0000UL)
37 #define MAX_CRB_XFORM 60
38 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
39 static int qla82xx_crb_table_initialized;
41 #define qla82xx_crb_addr_transform(name) \
42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
45 static void qla82xx_crb_addr_transform_setup(void)
47 qla82xx_crb_addr_transform(XDMA);
48 qla82xx_crb_addr_transform(TIMR);
49 qla82xx_crb_addr_transform(SRE);
50 qla82xx_crb_addr_transform(SQN3);
51 qla82xx_crb_addr_transform(SQN2);
52 qla82xx_crb_addr_transform(SQN1);
53 qla82xx_crb_addr_transform(SQN0);
54 qla82xx_crb_addr_transform(SQS3);
55 qla82xx_crb_addr_transform(SQS2);
56 qla82xx_crb_addr_transform(SQS1);
57 qla82xx_crb_addr_transform(SQS0);
58 qla82xx_crb_addr_transform(RPMX7);
59 qla82xx_crb_addr_transform(RPMX6);
60 qla82xx_crb_addr_transform(RPMX5);
61 qla82xx_crb_addr_transform(RPMX4);
62 qla82xx_crb_addr_transform(RPMX3);
63 qla82xx_crb_addr_transform(RPMX2);
64 qla82xx_crb_addr_transform(RPMX1);
65 qla82xx_crb_addr_transform(RPMX0);
66 qla82xx_crb_addr_transform(ROMUSB);
67 qla82xx_crb_addr_transform(SN);
68 qla82xx_crb_addr_transform(QMN);
69 qla82xx_crb_addr_transform(QMS);
70 qla82xx_crb_addr_transform(PGNI);
71 qla82xx_crb_addr_transform(PGND);
72 qla82xx_crb_addr_transform(PGN3);
73 qla82xx_crb_addr_transform(PGN2);
74 qla82xx_crb_addr_transform(PGN1);
75 qla82xx_crb_addr_transform(PGN0);
76 qla82xx_crb_addr_transform(PGSI);
77 qla82xx_crb_addr_transform(PGSD);
78 qla82xx_crb_addr_transform(PGS3);
79 qla82xx_crb_addr_transform(PGS2);
80 qla82xx_crb_addr_transform(PGS1);
81 qla82xx_crb_addr_transform(PGS0);
82 qla82xx_crb_addr_transform(PS);
83 qla82xx_crb_addr_transform(PH);
84 qla82xx_crb_addr_transform(NIU);
85 qla82xx_crb_addr_transform(I2Q);
86 qla82xx_crb_addr_transform(EG);
87 qla82xx_crb_addr_transform(MN);
88 qla82xx_crb_addr_transform(MS);
89 qla82xx_crb_addr_transform(CAS2);
90 qla82xx_crb_addr_transform(CAS1);
91 qla82xx_crb_addr_transform(CAS0);
92 qla82xx_crb_addr_transform(CAM);
93 qla82xx_crb_addr_transform(C2C1);
94 qla82xx_crb_addr_transform(C2C0);
95 qla82xx_crb_addr_transform(SMB);
96 qla82xx_crb_addr_transform(OCM0);
98 * Used only in P3 just define it for P2 also.
100 qla82xx_crb_addr_transform(I2C0);
102 qla82xx_crb_table_initialized = 1;
105 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
107 {{{1, 0x0100000, 0x0102000, 0x120000},
108 {1, 0x0110000, 0x0120000, 0x130000},
109 {1, 0x0120000, 0x0122000, 0x124000},
110 {1, 0x0130000, 0x0132000, 0x126000},
111 {1, 0x0140000, 0x0142000, 0x128000},
112 {1, 0x0150000, 0x0152000, 0x12a000},
113 {1, 0x0160000, 0x0170000, 0x110000},
114 {1, 0x0170000, 0x0172000, 0x12e000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {1, 0x01e0000, 0x01e0800, 0x122000},
122 {0, 0x0000000, 0x0000000, 0x000000} } } ,
123 {{{1, 0x0200000, 0x0210000, 0x180000} } },
125 {{{1, 0x0400000, 0x0401000, 0x169000} } },
126 {{{1, 0x0500000, 0x0510000, 0x140000} } },
127 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
128 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
129 {{{1, 0x0800000, 0x0802000, 0x170000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {1, 0x08f0000, 0x08f2000, 0x172000} } },
145 {{{1, 0x0900000, 0x0902000, 0x174000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {1, 0x09f0000, 0x09f2000, 0x176000} } },
161 {{{0, 0x0a00000, 0x0a02000, 0x178000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
177 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {0, 0x0000000, 0x0000000, 0x000000},
182 {0, 0x0000000, 0x0000000, 0x000000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
193 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
194 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
195 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
196 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
197 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
198 {{{1, 0x1100000, 0x1101000, 0x160000} } },
199 {{{1, 0x1200000, 0x1201000, 0x161000} } },
200 {{{1, 0x1300000, 0x1301000, 0x162000} } },
201 {{{1, 0x1400000, 0x1401000, 0x163000} } },
202 {{{1, 0x1500000, 0x1501000, 0x165000} } },
203 {{{1, 0x1600000, 0x1601000, 0x166000} } },
210 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
211 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
212 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
214 {{{1, 0x2100000, 0x2102000, 0x120000},
215 {1, 0x2110000, 0x2120000, 0x130000},
216 {1, 0x2120000, 0x2122000, 0x124000},
217 {1, 0x2130000, 0x2132000, 0x126000},
218 {1, 0x2140000, 0x2142000, 0x128000},
219 {1, 0x2150000, 0x2152000, 0x12a000},
220 {1, 0x2160000, 0x2170000, 0x110000},
221 {1, 0x2170000, 0x2172000, 0x12e000},
222 {0, 0x0000000, 0x0000000, 0x000000},
223 {0, 0x0000000, 0x0000000, 0x000000},
224 {0, 0x0000000, 0x0000000, 0x000000},
225 {0, 0x0000000, 0x0000000, 0x000000},
226 {0, 0x0000000, 0x0000000, 0x000000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000} } },
230 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
236 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
237 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
238 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
239 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
240 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
241 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
242 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
243 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
244 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
245 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
246 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
247 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
249 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
250 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
251 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
252 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
253 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
254 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
257 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
258 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
259 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
263 * top 12 bits of crb internal address (hub, agent)
265 static unsigned qla82xx_crb_hub_agt[64] = {
267 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
268 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
269 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
271 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
275 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
306 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
308 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
309 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
310 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
312 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
328 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
333 static char *q_dev_state[] = {
344 char *qdev_state(uint32_t dev_state)
346 return q_dev_state[dev_state];
350 * In: 'off_in' is offset from CRB space in 128M pci map
351 * Out: 'off_out' is 2M pci map addr
352 * side effect: lock crb window
355 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in,
356 void __iomem **off_out)
359 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
361 ha->crb_win = CRB_HI(off_in);
362 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase);
364 /* Read back value to make sure write has gone through before trying
367 win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
368 if (win_read != ha->crb_win) {
369 ql_dbg(ql_dbg_p3p, vha, 0xb000,
370 "%s: Written crbwin (0x%x) "
371 "!= Read crbwin (0x%x), off=0x%lx.\n",
372 __func__, ha->crb_win, win_read, off_in);
374 *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
377 static inline unsigned long
378 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
380 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
381 /* See if we are currently pointing to the region we want to use next */
382 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
383 /* No need to change window. PCIX and PCIEregs are in both
384 * regs are in both windows.
389 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
390 /* We are in first CRB window */
391 if (ha->curr_window != 0)
396 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
397 /* We are in second CRB window */
398 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
400 if (ha->curr_window != 1)
403 /* We are in the QM or direct access
404 * register region - do nothing
406 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
407 (off < QLA82XX_PCI_CAMQM_MAX))
410 /* strange address given */
411 ql_dbg(ql_dbg_p3p, vha, 0xb001,
412 "%s: Warning: unm_nic_pci_set_crbwindow "
413 "called with an unknown address(%llx).\n",
414 QLA2XXX_DRIVER_NAME, off);
419 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in,
420 void __iomem **off_out)
422 struct crb_128M_2M_sub_block_map *m;
424 if (off_in >= QLA82XX_CRB_MAX)
427 if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) {
428 *off_out = (off_in - QLA82XX_PCI_CAMQM) +
429 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
433 if (off_in < QLA82XX_PCI_CRBSPACE)
436 *off_out = (void __iomem *)(off_in - QLA82XX_PCI_CRBSPACE);
439 m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)];
441 if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) {
442 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase;
445 /* Not in direct map, use crb window */
449 #define CRB_WIN_LOCK_TIMEOUT 100000000
450 static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
452 int done = 0, timeout = 0;
455 /* acquire semaphore3 from PCI HW block */
456 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
459 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
463 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
468 qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data)
471 unsigned long flags = 0;
474 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
480 write_lock_irqsave(&ha->hw_lock, flags);
482 qla82xx_crb_win_lock(ha);
483 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
486 writel(data, (void __iomem *)off);
489 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
491 write_unlock_irqrestore(&ha->hw_lock, flags);
498 qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in)
501 unsigned long flags = 0;
505 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
511 write_lock_irqsave(&ha->hw_lock, flags);
513 qla82xx_crb_win_lock(ha);
514 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
516 data = RD_REG_DWORD(off);
519 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
521 write_unlock_irqrestore(&ha->hw_lock, flags);
527 #define IDC_LOCK_TIMEOUT 100000000
528 int qla82xx_idc_lock(struct qla_hw_data *ha)
531 int done = 0, timeout = 0;
534 /* acquire semaphore5 from PCI HW block */
535 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
538 if (timeout >= IDC_LOCK_TIMEOUT)
547 for (i = 0; i < 20; i++)
555 void qla82xx_idc_unlock(struct qla_hw_data *ha)
557 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
561 * check memory access boundary.
562 * used by test agent. support ddr access only for now
565 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
566 unsigned long long addr, int size)
568 if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
569 QLA82XX_ADDR_DDR_NET_MAX) ||
570 !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET,
571 QLA82XX_ADDR_DDR_NET_MAX) ||
572 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
578 static int qla82xx_pci_set_window_warning_count;
581 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
585 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
587 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
588 QLA82XX_ADDR_DDR_NET_MAX)) {
589 /* DDR network side */
590 window = MN_WIN(addr);
591 ha->ddr_mn_window = window;
593 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
594 win_read = qla82xx_rd_32(ha,
595 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
596 if ((win_read << 17) != window) {
597 ql_dbg(ql_dbg_p3p, vha, 0xb003,
598 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
599 __func__, window, win_read);
601 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
602 } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
603 QLA82XX_ADDR_OCM0_MAX)) {
605 if ((addr & 0x00ff800) == 0xff800) {
606 ql_log(ql_log_warn, vha, 0xb004,
607 "%s: QM access not handled.\n", __func__);
610 window = OCM_WIN(addr);
611 ha->ddr_mn_window = window;
613 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
614 win_read = qla82xx_rd_32(ha,
615 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
616 temp1 = ((window & 0x1FF) << 7) |
617 ((window & 0x0FFFE0000) >> 17);
618 if (win_read != temp1) {
619 ql_log(ql_log_warn, vha, 0xb005,
620 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
621 __func__, temp1, win_read);
623 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
625 } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET,
626 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
627 /* QDR network side */
628 window = MS_WIN(addr);
629 ha->qdr_sn_window = window;
631 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
632 win_read = qla82xx_rd_32(ha,
633 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
634 if (win_read != window) {
635 ql_log(ql_log_warn, vha, 0xb006,
636 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
637 __func__, window, win_read);
639 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
642 * peg gdb frequently accesses memory that doesn't exist,
643 * this limits the chit chat so debugging isn't slowed down.
645 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
646 (qla82xx_pci_set_window_warning_count%64 == 0)) {
647 ql_log(ql_log_warn, vha, 0xb007,
648 "%s: Warning:%s Unknown address range!.\n",
649 __func__, QLA2XXX_DRIVER_NAME);
656 /* check if address is in the same windows as the previous access */
657 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
658 unsigned long long addr)
661 unsigned long long qdr_max;
663 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
665 /* DDR network side */
666 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
667 QLA82XX_ADDR_DDR_NET_MAX))
669 else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
670 QLA82XX_ADDR_OCM0_MAX))
672 else if (addr_in_range(addr, QLA82XX_ADDR_OCM1,
673 QLA82XX_ADDR_OCM1_MAX))
675 else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
676 /* QDR network side */
677 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
678 if (ha->qdr_sn_window == window)
684 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
685 u64 off, void *data, int size)
688 void __iomem *addr = NULL;
691 uint8_t __iomem *mem_ptr = NULL;
692 unsigned long mem_base;
693 unsigned long mem_page;
694 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
696 write_lock_irqsave(&ha->hw_lock, flags);
699 * If attempting to access unknown address or straddle hw windows,
702 start = qla82xx_pci_set_window(ha, off);
703 if ((start == -1UL) ||
704 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
705 write_unlock_irqrestore(&ha->hw_lock, flags);
706 ql_log(ql_log_fatal, vha, 0xb008,
707 "%s out of bound pci memory "
708 "access, offset is 0x%llx.\n",
709 QLA2XXX_DRIVER_NAME, off);
713 write_unlock_irqrestore(&ha->hw_lock, flags);
714 mem_base = pci_resource_start(ha->pdev, 0);
715 mem_page = start & PAGE_MASK;
716 /* Map two pages whenever user tries to access addresses in two
719 if (mem_page != ((start + size - 1) & PAGE_MASK))
720 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
722 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
723 if (mem_ptr == NULL) {
728 addr += start & (PAGE_SIZE - 1);
729 write_lock_irqsave(&ha->hw_lock, flags);
733 *(u8 *)data = readb(addr);
736 *(u16 *)data = readw(addr);
739 *(u32 *)data = readl(addr);
742 *(u64 *)data = readq(addr);
748 write_unlock_irqrestore(&ha->hw_lock, flags);
756 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
757 u64 off, void *data, int size)
760 void __iomem *addr = NULL;
763 uint8_t __iomem *mem_ptr = NULL;
764 unsigned long mem_base;
765 unsigned long mem_page;
766 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
768 write_lock_irqsave(&ha->hw_lock, flags);
771 * If attempting to access unknown address or straddle hw windows,
774 start = qla82xx_pci_set_window(ha, off);
775 if ((start == -1UL) ||
776 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
777 write_unlock_irqrestore(&ha->hw_lock, flags);
778 ql_log(ql_log_fatal, vha, 0xb009,
779 "%s out of bount memory "
780 "access, offset is 0x%llx.\n",
781 QLA2XXX_DRIVER_NAME, off);
785 write_unlock_irqrestore(&ha->hw_lock, flags);
786 mem_base = pci_resource_start(ha->pdev, 0);
787 mem_page = start & PAGE_MASK;
788 /* Map two pages whenever user tries to access addresses in two
791 if (mem_page != ((start + size - 1) & PAGE_MASK))
792 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
794 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
799 addr += start & (PAGE_SIZE - 1);
800 write_lock_irqsave(&ha->hw_lock, flags);
804 writeb(*(u8 *)data, addr);
807 writew(*(u16 *)data, addr);
810 writel(*(u32 *)data, addr);
813 writeq(*(u64 *)data, addr);
819 write_unlock_irqrestore(&ha->hw_lock, flags);
825 #define MTU_FUDGE_FACTOR 100
827 qla82xx_decode_crb_addr(unsigned long addr)
830 unsigned long base_addr, offset, pci_base;
832 if (!qla82xx_crb_table_initialized)
833 qla82xx_crb_addr_transform_setup();
835 pci_base = ADDR_ERROR;
836 base_addr = addr & 0xfff00000;
837 offset = addr & 0x000fffff;
839 for (i = 0; i < MAX_CRB_XFORM; i++) {
840 if (crb_addr_xform[i] == base_addr) {
845 if (pci_base == ADDR_ERROR)
847 return pci_base + offset;
850 static long rom_max_timeout = 100;
851 static long qla82xx_rom_lock_timeout = 100;
854 qla82xx_rom_lock(struct qla_hw_data *ha)
856 int done = 0, timeout = 0;
857 uint32_t lock_owner = 0;
858 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
861 /* acquire semaphore2 from PCI HW block */
862 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
865 if (timeout >= qla82xx_rom_lock_timeout) {
866 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
867 ql_dbg(ql_dbg_p3p, vha, 0xb157,
868 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
869 __func__, ha->portnum, lock_owner);
874 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum);
879 qla82xx_rom_unlock(struct qla_hw_data *ha)
881 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff);
882 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
886 qla82xx_wait_rom_busy(struct qla_hw_data *ha)
890 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
893 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
896 if (timeout >= rom_max_timeout) {
897 ql_dbg(ql_dbg_p3p, vha, 0xb00a,
898 "%s: Timeout reached waiting for rom busy.\n",
899 QLA2XXX_DRIVER_NAME);
907 qla82xx_wait_rom_done(struct qla_hw_data *ha)
911 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
914 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
917 if (timeout >= rom_max_timeout) {
918 ql_dbg(ql_dbg_p3p, vha, 0xb00b,
919 "%s: Timeout reached waiting for rom done.\n",
920 QLA2XXX_DRIVER_NAME);
928 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
930 uint32_t off_value, rval = 0;
932 WRT_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
934 /* Read back value to make sure write has gone through */
935 RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
936 off_value = (off & 0x0000FFFF);
939 WRT_REG_DWORD(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
942 rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M +
949 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
951 /* Dword reads to flash. */
952 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
953 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
954 (addr & 0x0000FFFF), 0, 0);
960 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
963 uint32_t lock_owner = 0;
964 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
966 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
971 if (loops >= 50000) {
972 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
973 ql_log(ql_log_fatal, vha, 0x00b9,
974 "Failed to acquire SEM2 lock, Lock Owner %u.\n",
978 ret = qla82xx_do_rom_fast_read(ha, addr, valp);
979 qla82xx_rom_unlock(ha);
984 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
986 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
987 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
988 qla82xx_wait_rom_busy(ha);
989 if (qla82xx_wait_rom_done(ha)) {
990 ql_log(ql_log_warn, vha, 0xb00c,
991 "Error waiting for rom done.\n");
994 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
999 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
1005 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1007 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1008 while ((done != 0) && (ret == 0)) {
1009 ret = qla82xx_read_status_reg(ha, &val);
1014 if (timeout >= 50000) {
1015 ql_log(ql_log_warn, vha, 0xb00d,
1016 "Timeout reached waiting for write finish.\n");
1024 qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1027 qla82xx_wait_rom_busy(ha);
1028 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1029 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1030 qla82xx_wait_rom_busy(ha);
1031 if (qla82xx_wait_rom_done(ha))
1033 if (qla82xx_read_status_reg(ha, &val) != 0)
1041 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1043 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1044 if (qla82xx_flash_set_write_enable(ha))
1046 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1047 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1048 if (qla82xx_wait_rom_done(ha)) {
1049 ql_log(ql_log_warn, vha, 0xb00e,
1050 "Error waiting for rom done.\n");
1053 return qla82xx_flash_wait_write_finish(ha);
1057 qla82xx_write_disable_flash(struct qla_hw_data *ha)
1059 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1060 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1061 if (qla82xx_wait_rom_done(ha)) {
1062 ql_log(ql_log_warn, vha, 0xb00f,
1063 "Error waiting for rom done.\n");
1070 ql82xx_rom_lock_d(struct qla_hw_data *ha)
1073 uint32_t lock_owner = 0;
1074 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1076 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1081 if (loops >= 50000) {
1082 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
1083 ql_log(ql_log_warn, vha, 0xb010,
1084 "ROM lock failed, Lock Owner %u.\n", lock_owner);
1091 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1095 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1097 ret = ql82xx_rom_lock_d(ha);
1099 ql_log(ql_log_warn, vha, 0xb011,
1100 "ROM lock failed.\n");
1104 if (qla82xx_flash_set_write_enable(ha))
1107 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1108 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1109 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1110 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1111 qla82xx_wait_rom_busy(ha);
1112 if (qla82xx_wait_rom_done(ha)) {
1113 ql_log(ql_log_warn, vha, 0xb012,
1114 "Error waiting for rom done.\n");
1119 ret = qla82xx_flash_wait_write_finish(ha);
1122 qla82xx_rom_unlock(ha);
1126 /* This routine does CRB initialize sequence
1127 * to put the ISP into operational state
1130 qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1134 struct crb_addr_pair *buf;
1137 struct qla_hw_data *ha = vha->hw;
1139 struct crb_addr_pair {
1144 /* Halt all the individual PEGs and other blocks of the ISP */
1145 qla82xx_rom_lock(ha);
1147 /* disable all I2Q */
1148 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1149 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1150 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1151 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1152 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1153 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1155 /* disable all niu interrupts */
1156 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1157 /* disable xge rx/tx */
1158 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1159 /* disable xg1 rx/tx */
1160 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1161 /* disable sideband mac */
1162 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1163 /* disable ap0 mac */
1164 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1165 /* disable ap1 mac */
1166 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1169 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1170 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1173 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1176 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1177 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1178 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1179 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1180 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1181 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1184 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1185 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1186 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1187 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1188 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1192 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1193 /* don't reset CAM block on reset */
1194 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1196 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1197 qla82xx_rom_unlock(ha);
1199 /* Read the signature value from the flash.
1200 * Offset 0: Contain signature (0xcafecafe)
1201 * Offset 4: Offset and number of addr/value pairs
1202 * that present in CRB initialize sequence
1204 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1205 qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1206 ql_log(ql_log_fatal, vha, 0x006e,
1207 "Error Reading crb_init area: n: %08x.\n", n);
1211 /* Offset in flash = lower 16 bits
1212 * Number of entries = upper 16 bits
1214 offset = n & 0xffffU;
1215 n = (n >> 16) & 0xffffU;
1217 /* number of addr/value pair should not exceed 1024 entries */
1219 ql_log(ql_log_fatal, vha, 0x0071,
1220 "Card flash not initialized:n=0x%x.\n", n);
1224 ql_log(ql_log_info, vha, 0x0072,
1225 "%d CRB init values found in ROM.\n", n);
1227 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1229 ql_log(ql_log_fatal, vha, 0x010c,
1230 "Unable to allocate memory.\n");
1234 for (i = 0; i < n; i++) {
1235 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1236 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1245 for (i = 0; i < n; i++) {
1246 /* Translate internal CRB initialization
1247 * address to PCI bus address
1249 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1250 QLA82XX_PCI_CRBSPACE;
1251 /* Not all CRB addr/value pair to be written,
1252 * some of them are skipped
1255 /* skipping cold reboot MAGIC */
1256 if (off == QLA82XX_CAM_RAM(0x1fc))
1259 /* do not reset PCI */
1260 if (off == (ROMUSB_GLB + 0xbc))
1263 /* skip core clock, so that firmware can increase the clock */
1264 if (off == (ROMUSB_GLB + 0xc8))
1267 /* skip the function enable register */
1268 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1271 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1274 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1277 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1280 if (off == ADDR_ERROR) {
1281 ql_log(ql_log_fatal, vha, 0x0116,
1282 "Unknown addr: 0x%08lx.\n", buf[i].addr);
1286 qla82xx_wr_32(ha, off, buf[i].data);
1288 /* ISP requires much bigger delay to settle down,
1289 * else crb_window returns 0xffffffff
1291 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1294 /* ISP requires millisec delay between
1295 * successive CRB register updation
1302 /* Resetting the data and instruction cache */
1303 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1304 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1305 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1307 /* Clear all protocol processing engines */
1308 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1309 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1310 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1311 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1312 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1313 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1314 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1315 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1320 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1321 u64 off, void *data, int size)
1323 int i, j, ret = 0, loop, sz[2], off0;
1324 int scale, shift_amount, startword;
1326 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1329 * If not MN, go check for MS or invalid.
1331 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1332 mem_crb = QLA82XX_CRB_QDR_NET;
1334 mem_crb = QLA82XX_CRB_DDR_NET;
1335 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1336 return qla82xx_pci_mem_write_direct(ha,
1341 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1342 sz[1] = size - sz[0];
1344 off8 = off & 0xfffffff0;
1345 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1348 startword = (off & 0xf)/8;
1350 for (i = 0; i < loop; i++) {
1351 if (qla82xx_pci_mem_read_2M(ha, off8 +
1352 (i << shift_amount), &word[i * scale], 8))
1358 tmpw = *((uint8_t *)data);
1361 tmpw = *((uint16_t *)data);
1364 tmpw = *((uint32_t *)data);
1368 tmpw = *((uint64_t *)data);
1373 word[startword] = tmpw;
1376 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1377 word[startword] |= tmpw << (off0 * 8);
1380 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1381 word[startword+1] |= tmpw >> (sz[0] * 8);
1384 for (i = 0; i < loop; i++) {
1385 temp = off8 + (i << shift_amount);
1386 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1388 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1389 temp = word[i * scale] & 0xffffffff;
1390 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1391 temp = (word[i * scale] >> 32) & 0xffffffff;
1392 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1393 temp = word[i*scale + 1] & 0xffffffff;
1394 qla82xx_wr_32(ha, mem_crb +
1395 MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1396 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1397 qla82xx_wr_32(ha, mem_crb +
1398 MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1400 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1401 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1402 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1403 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1405 for (j = 0; j < MAX_CTL_CHECK; j++) {
1406 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1407 if ((temp & MIU_TA_CTL_BUSY) == 0)
1411 if (j >= MAX_CTL_CHECK) {
1412 if (printk_ratelimit())
1413 dev_err(&ha->pdev->dev,
1414 "failed to write through agent.\n");
1424 qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1428 long flashaddr = ha->flt_region_bootload << 2;
1429 long memaddr = BOOTLD_START;
1432 size = (IMAGE_START - BOOTLD_START) / 8;
1434 for (i = 0; i < size; i++) {
1435 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1436 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1439 data = ((u64)high << 32) | low ;
1440 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1444 if (i % 0x1000 == 0)
1448 read_lock(&ha->hw_lock);
1449 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1450 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1451 read_unlock(&ha->hw_lock);
1456 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1457 u64 off, void *data, int size)
1459 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1462 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1465 * If not MN, go check for MS or invalid.
1468 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1469 mem_crb = QLA82XX_CRB_QDR_NET;
1471 mem_crb = QLA82XX_CRB_DDR_NET;
1472 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1473 return qla82xx_pci_mem_read_direct(ha,
1477 off8 = off & 0xfffffff0;
1478 off0[0] = off & 0xf;
1479 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1481 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1483 sz[1] = size - sz[0];
1485 for (i = 0; i < loop; i++) {
1486 temp = off8 + (i << shift_amount);
1487 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1489 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1490 temp = MIU_TA_CTL_ENABLE;
1491 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1492 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1493 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1495 for (j = 0; j < MAX_CTL_CHECK; j++) {
1496 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1497 if ((temp & MIU_TA_CTL_BUSY) == 0)
1501 if (j >= MAX_CTL_CHECK) {
1502 if (printk_ratelimit())
1503 dev_err(&ha->pdev->dev,
1504 "failed to read through agent.\n");
1508 start = off0[i] >> 2;
1509 end = (off0[i] + sz[i] - 1) >> 2;
1510 for (k = start; k <= end; k++) {
1511 temp = qla82xx_rd_32(ha,
1512 mem_crb + MIU_TEST_AGT_RDDATA(k));
1513 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1517 if (j >= MAX_CTL_CHECK)
1520 if ((off0[0] & 7) == 0) {
1523 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1524 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1529 *(uint8_t *)data = val;
1532 *(uint16_t *)data = val;
1535 *(uint32_t *)data = val;
1538 *(uint64_t *)data = val;
1545 static struct qla82xx_uri_table_desc *
1546 qla82xx_get_table_desc(const u8 *unirom, int section)
1549 struct qla82xx_uri_table_desc *directory =
1550 (struct qla82xx_uri_table_desc *)&unirom[0];
1553 __le32 entries = cpu_to_le32(directory->num_entries);
1555 for (i = 0; i < entries; i++) {
1556 offset = cpu_to_le32(directory->findex) +
1557 (i * cpu_to_le32(directory->entry_size));
1558 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1560 if (tab_type == section)
1561 return (struct qla82xx_uri_table_desc *)&unirom[offset];
1567 static struct qla82xx_uri_data_desc *
1568 qla82xx_get_data_desc(struct qla_hw_data *ha,
1569 u32 section, u32 idx_offset)
1571 const u8 *unirom = ha->hablob->fw->data;
1572 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1573 struct qla82xx_uri_table_desc *tab_desc = NULL;
1576 tab_desc = qla82xx_get_table_desc(unirom, section);
1580 offset = cpu_to_le32(tab_desc->findex) +
1581 (cpu_to_le32(tab_desc->entry_size) * idx);
1583 return (struct qla82xx_uri_data_desc *)&unirom[offset];
1587 qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1589 u32 offset = BOOTLD_START;
1590 struct qla82xx_uri_data_desc *uri_desc = NULL;
1592 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1593 uri_desc = qla82xx_get_data_desc(ha,
1594 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1596 offset = cpu_to_le32(uri_desc->findex);
1599 return (u8 *)&ha->hablob->fw->data[offset];
1603 qla82xx_get_fw_size(struct qla_hw_data *ha)
1605 struct qla82xx_uri_data_desc *uri_desc = NULL;
1607 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1608 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1609 QLA82XX_URI_FIRMWARE_IDX_OFF);
1611 return cpu_to_le32(uri_desc->size);
1614 return cpu_to_le32(*(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1618 qla82xx_get_fw_offs(struct qla_hw_data *ha)
1620 u32 offset = IMAGE_START;
1621 struct qla82xx_uri_data_desc *uri_desc = NULL;
1623 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1624 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1625 QLA82XX_URI_FIRMWARE_IDX_OFF);
1627 offset = cpu_to_le32(uri_desc->findex);
1630 return (u8 *)&ha->hablob->fw->data[offset];
1633 /* PCI related functions */
1634 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1636 unsigned long val = 0;
1644 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1645 val = control + QLA82XX_MSIX_TBL_SPACE;
1653 qla82xx_iospace_config(struct qla_hw_data *ha)
1657 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1658 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1659 "Failed to reserver selected regions.\n");
1660 goto iospace_error_exit;
1663 /* Use MMIO operations for all accesses. */
1664 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1665 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1666 "Region #0 not an MMIO resource, aborting.\n");
1667 goto iospace_error_exit;
1670 len = pci_resource_len(ha->pdev, 0);
1671 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len);
1672 if (!ha->nx_pcibase) {
1673 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1674 "Cannot remap pcibase MMIO, aborting.\n");
1675 goto iospace_error_exit;
1678 /* Mapping of IO base pointer */
1679 if (IS_QLA8044(ha)) {
1680 ha->iobase = ha->nx_pcibase;
1681 } else if (IS_QLA82XX(ha)) {
1682 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11);
1686 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) +
1687 (ha->pdev->devfn << 12)), 4);
1688 if (!ha->nxdb_wr_ptr) {
1689 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1690 "Cannot remap MMIO, aborting.\n");
1691 goto iospace_error_exit;
1694 /* Mapping of IO base pointer,
1695 * door bell read and write pointer
1697 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) +
1698 (ha->pdev->devfn * 8);
1700 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ?
1701 QLA82XX_CAMRAM_DB1 :
1702 QLA82XX_CAMRAM_DB2);
1705 ha->max_req_queues = ha->max_rsp_queues = 1;
1706 ha->msix_count = ha->max_rsp_queues + 1;
1707 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1708 "nx_pci_base=%p iobase=%p "
1709 "max_req_queues=%d msix_count=%d.\n",
1710 ha->nx_pcibase, ha->iobase,
1711 ha->max_req_queues, ha->msix_count);
1712 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1713 "nx_pci_base=%p iobase=%p "
1714 "max_req_queues=%d msix_count=%d.\n",
1715 ha->nx_pcibase, ha->iobase,
1716 ha->max_req_queues, ha->msix_count);
1723 /* GS related functions */
1725 /* Initialization related functions */
1728 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1731 * Returns 0 on success.
1734 qla82xx_pci_config(scsi_qla_host_t *vha)
1736 struct qla_hw_data *ha = vha->hw;
1739 pci_set_master(ha->pdev);
1740 ret = pci_set_mwi(ha->pdev);
1741 ha->chip_revision = ha->pdev->revision;
1742 ql_dbg(ql_dbg_init, vha, 0x0043,
1743 "Chip revision:%d; pci_set_mwi() returned %d.\n",
1744 ha->chip_revision, ret);
1749 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1752 * Returns 0 on success.
1755 qla82xx_reset_chip(scsi_qla_host_t *vha)
1757 struct qla_hw_data *ha = vha->hw;
1758 ha->isp_ops->disable_intrs(ha);
1761 void qla82xx_config_rings(struct scsi_qla_host *vha)
1763 struct qla_hw_data *ha = vha->hw;
1764 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1765 struct init_cb_81xx *icb;
1766 struct req_que *req = ha->req_q_map[0];
1767 struct rsp_que *rsp = ha->rsp_q_map[0];
1769 /* Setup ring parameters in initialization control block. */
1770 icb = (struct init_cb_81xx *)ha->init_cb;
1771 icb->request_q_outpointer = cpu_to_le16(0);
1772 icb->response_q_inpointer = cpu_to_le16(0);
1773 icb->request_q_length = cpu_to_le16(req->length);
1774 icb->response_q_length = cpu_to_le16(rsp->length);
1775 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1776 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1777 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1778 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1780 WRT_REG_DWORD(®->req_q_out[0], 0);
1781 WRT_REG_DWORD(®->rsp_q_in[0], 0);
1782 WRT_REG_DWORD(®->rsp_q_out[0], 0);
1786 qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1789 u32 i, flashaddr, size;
1792 size = (IMAGE_START - BOOTLD_START) / 8;
1794 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
1795 flashaddr = BOOTLD_START;
1797 for (i = 0; i < size; i++) {
1798 data = cpu_to_le64(ptr64[i]);
1799 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1804 flashaddr = FLASH_ADDR_START;
1805 size = (__force u32)qla82xx_get_fw_size(ha) / 8;
1806 ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
1808 for (i = 0; i < size; i++) {
1809 data = cpu_to_le64(ptr64[i]);
1811 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1817 /* Write a magic value to CAMRAM register
1818 * at a specified offset to indicate
1819 * that all data is written and
1820 * ready for firmware to initialize.
1822 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
1824 read_lock(&ha->hw_lock);
1825 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1826 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1827 read_unlock(&ha->hw_lock);
1832 qla82xx_set_product_offset(struct qla_hw_data *ha)
1834 struct qla82xx_uri_table_desc *ptab_desc = NULL;
1835 const uint8_t *unirom = ha->hablob->fw->data;
1838 __le32 flags, file_chiprev, offset;
1839 uint8_t chiprev = ha->chip_revision;
1840 /* Hardcoding mn_present flag for P3P */
1844 ptab_desc = qla82xx_get_table_desc(unirom,
1845 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1849 entries = cpu_to_le32(ptab_desc->num_entries);
1851 for (i = 0; i < entries; i++) {
1852 offset = cpu_to_le32(ptab_desc->findex) +
1853 (i * cpu_to_le32(ptab_desc->entry_size));
1854 flags = cpu_to_le32(*((int *)&unirom[offset] +
1855 QLA82XX_URI_FLAGS_OFF));
1856 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1857 QLA82XX_URI_CHIP_REV_OFF));
1859 flagbit = mn_present ? 1 : 2;
1861 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1862 ha->file_prd_off = offset;
1870 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1874 struct qla_hw_data *ha = vha->hw;
1875 const struct firmware *fw = ha->hablob->fw;
1877 ha->fw_type = fw_type;
1879 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1880 if (qla82xx_set_product_offset(ha))
1883 min_size = QLA82XX_URI_FW_MIN_SIZE;
1885 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1886 if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
1889 min_size = QLA82XX_FW_MIN_SIZE;
1892 if (fw->size < min_size)
1898 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
1902 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1905 read_lock(&ha->hw_lock);
1906 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1907 read_unlock(&ha->hw_lock);
1910 case PHAN_INITIALIZE_COMPLETE:
1911 case PHAN_INITIALIZE_ACK:
1913 case PHAN_INITIALIZE_FAILED:
1918 ql_log(ql_log_info, vha, 0x00a8,
1919 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1924 } while (--retries);
1926 ql_log(ql_log_fatal, vha, 0x00a9,
1927 "Cmd Peg initialization failed: 0x%x.\n", val);
1929 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1930 read_lock(&ha->hw_lock);
1931 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1932 read_unlock(&ha->hw_lock);
1933 return QLA_FUNCTION_FAILED;
1937 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1941 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1944 read_lock(&ha->hw_lock);
1945 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1946 read_unlock(&ha->hw_lock);
1949 case PHAN_INITIALIZE_COMPLETE:
1950 case PHAN_INITIALIZE_ACK:
1952 case PHAN_INITIALIZE_FAILED:
1957 ql_log(ql_log_info, vha, 0x00ab,
1958 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1963 } while (--retries);
1965 ql_log(ql_log_fatal, vha, 0x00ac,
1966 "Rcv Peg initializatin failed: 0x%x.\n", val);
1967 read_lock(&ha->hw_lock);
1968 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1969 read_unlock(&ha->hw_lock);
1970 return QLA_FUNCTION_FAILED;
1973 /* ISR related functions */
1974 static struct qla82xx_legacy_intr_set legacy_intr[] = \
1975 QLA82XX_LEGACY_INTR_CONFIG;
1978 * qla82xx_mbx_completion() - Process mailbox command completions.
1979 * @ha: SCSI driver HA context
1980 * @mb0: Mailbox0 register
1983 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1986 uint16_t __iomem *wptr;
1987 struct qla_hw_data *ha = vha->hw;
1988 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1989 wptr = (uint16_t __iomem *)®->mailbox_out[1];
1991 /* Load return mailbox registers. */
1992 ha->flags.mbox_int = 1;
1993 ha->mailbox_out[0] = mb0;
1995 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
1996 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
2001 ql_dbg(ql_dbg_async, vha, 0x5053,
2002 "MBX pointer ERROR.\n");
2006 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2008 * @dev_id: SCSI driver HA context
2011 * Called by system whenever the host adapter generates an interrupt.
2013 * Returns handled flag.
2016 qla82xx_intr_handler(int irq, void *dev_id)
2018 scsi_qla_host_t *vha;
2019 struct qla_hw_data *ha;
2020 struct rsp_que *rsp;
2021 struct device_reg_82xx __iomem *reg;
2022 int status = 0, status1 = 0;
2023 unsigned long flags;
2028 rsp = (struct rsp_que *) dev_id;
2030 ql_log(ql_log_info, NULL, 0xb053,
2031 "%s: NULL response queue pointer.\n", __func__);
2036 if (!ha->flags.msi_enabled) {
2037 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2038 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2041 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2042 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2046 /* clear the interrupt */
2047 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2049 /* read twice to ensure write is flushed */
2050 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2051 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2053 reg = &ha->iobase->isp82;
2055 spin_lock_irqsave(&ha->hardware_lock, flags);
2056 vha = pci_get_drvdata(ha->pdev);
2057 for (iter = 1; iter--; ) {
2059 if (RD_REG_DWORD(®->host_int)) {
2060 stat = RD_REG_DWORD(®->host_status);
2062 switch (stat & 0xff) {
2067 qla82xx_mbx_completion(vha, MSW(stat));
2068 status |= MBX_INTERRUPT;
2072 mb[1] = RD_REG_WORD(®->mailbox_out[1]);
2073 mb[2] = RD_REG_WORD(®->mailbox_out[2]);
2074 mb[3] = RD_REG_WORD(®->mailbox_out[3]);
2075 qla2x00_async_event(vha, rsp, mb);
2078 qla24xx_process_response_queue(vha, rsp);
2081 ql_dbg(ql_dbg_async, vha, 0x5054,
2082 "Unrecognized interrupt type (%d).\n",
2087 WRT_REG_DWORD(®->host_int, 0);
2090 qla2x00_handle_mbx_completion(ha, status);
2091 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2093 if (!ha->flags.msi_enabled)
2094 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2100 qla82xx_msix_default(int irq, void *dev_id)
2102 scsi_qla_host_t *vha;
2103 struct qla_hw_data *ha;
2104 struct rsp_que *rsp;
2105 struct device_reg_82xx __iomem *reg;
2107 unsigned long flags;
2109 uint32_t host_int = 0;
2112 rsp = (struct rsp_que *) dev_id;
2115 "%s(): NULL response queue pointer.\n", __func__);
2120 reg = &ha->iobase->isp82;
2122 spin_lock_irqsave(&ha->hardware_lock, flags);
2123 vha = pci_get_drvdata(ha->pdev);
2125 host_int = RD_REG_DWORD(®->host_int);
2126 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2129 stat = RD_REG_DWORD(®->host_status);
2131 switch (stat & 0xff) {
2136 qla82xx_mbx_completion(vha, MSW(stat));
2137 status |= MBX_INTERRUPT;
2141 mb[1] = RD_REG_WORD(®->mailbox_out[1]);
2142 mb[2] = RD_REG_WORD(®->mailbox_out[2]);
2143 mb[3] = RD_REG_WORD(®->mailbox_out[3]);
2144 qla2x00_async_event(vha, rsp, mb);
2147 qla24xx_process_response_queue(vha, rsp);
2150 ql_dbg(ql_dbg_async, vha, 0x5041,
2151 "Unrecognized interrupt type (%d).\n",
2156 WRT_REG_DWORD(®->host_int, 0);
2159 qla2x00_handle_mbx_completion(ha, status);
2160 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2166 qla82xx_msix_rsp_q(int irq, void *dev_id)
2168 scsi_qla_host_t *vha;
2169 struct qla_hw_data *ha;
2170 struct rsp_que *rsp;
2171 struct device_reg_82xx __iomem *reg;
2172 unsigned long flags;
2173 uint32_t host_int = 0;
2175 rsp = (struct rsp_que *) dev_id;
2178 "%s(): NULL response queue pointer.\n", __func__);
2183 reg = &ha->iobase->isp82;
2184 spin_lock_irqsave(&ha->hardware_lock, flags);
2185 vha = pci_get_drvdata(ha->pdev);
2186 host_int = RD_REG_DWORD(®->host_int);
2187 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2189 qla24xx_process_response_queue(vha, rsp);
2190 WRT_REG_DWORD(®->host_int, 0);
2192 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2197 qla82xx_poll(int irq, void *dev_id)
2199 scsi_qla_host_t *vha;
2200 struct qla_hw_data *ha;
2201 struct rsp_que *rsp;
2202 struct device_reg_82xx __iomem *reg;
2205 uint32_t host_int = 0;
2207 unsigned long flags;
2209 rsp = (struct rsp_que *) dev_id;
2212 "%s(): NULL response queue pointer.\n", __func__);
2217 reg = &ha->iobase->isp82;
2218 spin_lock_irqsave(&ha->hardware_lock, flags);
2219 vha = pci_get_drvdata(ha->pdev);
2221 host_int = RD_REG_DWORD(®->host_int);
2222 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2225 stat = RD_REG_DWORD(®->host_status);
2226 switch (stat & 0xff) {
2231 qla82xx_mbx_completion(vha, MSW(stat));
2232 status |= MBX_INTERRUPT;
2236 mb[1] = RD_REG_WORD(®->mailbox_out[1]);
2237 mb[2] = RD_REG_WORD(®->mailbox_out[2]);
2238 mb[3] = RD_REG_WORD(®->mailbox_out[3]);
2239 qla2x00_async_event(vha, rsp, mb);
2242 qla24xx_process_response_queue(vha, rsp);
2245 ql_dbg(ql_dbg_p3p, vha, 0xb013,
2246 "Unrecognized interrupt type (%d).\n",
2250 WRT_REG_DWORD(®->host_int, 0);
2253 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2257 qla82xx_enable_intrs(struct qla_hw_data *ha)
2259 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2260 qla82xx_mbx_intr_enable(vha);
2261 spin_lock_irq(&ha->hardware_lock);
2263 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0);
2265 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2266 spin_unlock_irq(&ha->hardware_lock);
2267 ha->interrupts_on = 1;
2271 qla82xx_disable_intrs(struct qla_hw_data *ha)
2273 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2274 qla82xx_mbx_intr_disable(vha);
2275 spin_lock_irq(&ha->hardware_lock);
2277 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1);
2279 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2280 spin_unlock_irq(&ha->hardware_lock);
2281 ha->interrupts_on = 0;
2284 void qla82xx_init_flags(struct qla_hw_data *ha)
2286 struct qla82xx_legacy_intr_set *nx_legacy_intr;
2288 /* ISP 8021 initializations */
2289 rwlock_init(&ha->hw_lock);
2290 ha->qdr_sn_window = -1;
2291 ha->ddr_mn_window = -1;
2292 ha->curr_window = 255;
2293 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2294 nx_legacy_intr = &legacy_intr[ha->portnum];
2295 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2296 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2297 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2298 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2302 qla82xx_set_idc_version(scsi_qla_host_t *vha)
2305 uint32_t drv_active;
2306 struct qla_hw_data *ha = vha->hw;
2308 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2309 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) {
2310 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
2311 QLA82XX_IDC_VERSION);
2312 ql_log(ql_log_info, vha, 0xb082,
2313 "IDC version updated to %d\n", QLA82XX_IDC_VERSION);
2315 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION);
2316 if (idc_ver != QLA82XX_IDC_VERSION)
2317 ql_log(ql_log_info, vha, 0xb083,
2318 "qla2xxx driver IDC version %d is not compatible "
2319 "with IDC version %d of the other drivers\n",
2320 QLA82XX_IDC_VERSION, idc_ver);
2325 qla82xx_set_drv_active(scsi_qla_host_t *vha)
2327 uint32_t drv_active;
2328 struct qla_hw_data *ha = vha->hw;
2330 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2332 /* If reset value is all FF's, initialize DRV_ACTIVE */
2333 if (drv_active == 0xffffffff) {
2334 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2335 QLA82XX_DRV_NOT_ACTIVE);
2336 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2338 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2339 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2343 qla82xx_clear_drv_active(struct qla_hw_data *ha)
2345 uint32_t drv_active;
2347 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2348 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2349 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2353 qla82xx_need_reset(struct qla_hw_data *ha)
2358 if (ha->flags.nic_core_reset_owner)
2361 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2362 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2368 qla82xx_set_rst_ready(struct qla_hw_data *ha)
2371 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2373 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2375 /* If reset value is all FF's, initialize DRV_STATE */
2376 if (drv_state == 0xffffffff) {
2377 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
2378 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2380 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2381 ql_dbg(ql_dbg_init, vha, 0x00bb,
2382 "drv_state = 0x%08x.\n", drv_state);
2383 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2387 qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2391 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2392 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2393 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2397 qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2399 uint32_t qsnt_state;
2401 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2402 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2403 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2407 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2409 struct qla_hw_data *ha = vha->hw;
2410 uint32_t qsnt_state;
2412 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2413 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2414 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2418 qla82xx_load_fw(scsi_qla_host_t *vha)
2421 struct fw_blob *blob;
2422 struct qla_hw_data *ha = vha->hw;
2424 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2425 ql_log(ql_log_fatal, vha, 0x009f,
2426 "Error during CRB initialization.\n");
2427 return QLA_FUNCTION_FAILED;
2431 /* Bring QM and CAMRAM out of reset */
2432 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2433 rst &= ~((1 << 28) | (1 << 24));
2434 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2438 * 1) Operational firmware residing in flash.
2439 * 2) Firmware via request-firmware interface (.bin file).
2441 if (ql2xfwloadbin == 2)
2444 ql_log(ql_log_info, vha, 0x00a0,
2445 "Attempting to load firmware from flash.\n");
2447 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2448 ql_log(ql_log_info, vha, 0x00a1,
2449 "Firmware loaded successfully from flash.\n");
2452 ql_log(ql_log_warn, vha, 0x0108,
2453 "Firmware load from flash failed.\n");
2457 ql_log(ql_log_info, vha, 0x00a2,
2458 "Attempting to load firmware from blob.\n");
2460 /* Load firmware blob. */
2461 blob = ha->hablob = qla2x00_request_firmware(vha);
2463 ql_log(ql_log_fatal, vha, 0x00a3,
2464 "Firmware image not present.\n");
2465 goto fw_load_failed;
2468 /* Validating firmware blob */
2469 if (qla82xx_validate_firmware_blob(vha,
2470 QLA82XX_FLASH_ROMIMAGE)) {
2471 /* Fallback to URI format */
2472 if (qla82xx_validate_firmware_blob(vha,
2473 QLA82XX_UNIFIED_ROMIMAGE)) {
2474 ql_log(ql_log_fatal, vha, 0x00a4,
2475 "No valid firmware image found.\n");
2476 return QLA_FUNCTION_FAILED;
2480 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2481 ql_log(ql_log_info, vha, 0x00a5,
2482 "Firmware loaded successfully from binary blob.\n");
2486 ql_log(ql_log_fatal, vha, 0x00a6,
2487 "Firmware load failed for binary blob.\n");
2492 return QLA_FUNCTION_FAILED;
2496 qla82xx_start_firmware(scsi_qla_host_t *vha)
2499 struct qla_hw_data *ha = vha->hw;
2501 /* scrub dma mask expansion register */
2502 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
2504 /* Put both the PEG CMD and RCV PEG to default state
2505 * of 0 before resetting the hardware
2507 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2508 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2510 /* Overwrite stale initialization register values */
2511 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2512 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2514 if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2515 ql_log(ql_log_fatal, vha, 0x00a7,
2516 "Error trying to start fw.\n");
2517 return QLA_FUNCTION_FAILED;
2520 /* Handshake with the card before we register the devices. */
2521 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2522 ql_log(ql_log_fatal, vha, 0x00aa,
2523 "Error during card handshake.\n");
2524 return QLA_FUNCTION_FAILED;
2527 /* Negotiated Link width */
2528 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
2529 ha->link_width = (lnk >> 4) & 0x3f;
2531 /* Synchronize with Receive peg */
2532 return qla82xx_check_rcvpeg_state(ha);
2536 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2541 struct qla_hw_data *ha = vha->hw;
2543 /* Dword reads to flash. */
2544 for (i = 0; i < length/4; i++, faddr += 4) {
2545 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2546 ql_log(ql_log_warn, vha, 0x0106,
2547 "Do ROM fast read failed.\n");
2550 dwptr[i] = cpu_to_le32(val);
2557 qla82xx_unprotect_flash(struct qla_hw_data *ha)
2561 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2563 ret = ql82xx_rom_lock_d(ha);
2565 ql_log(ql_log_warn, vha, 0xb014,
2566 "ROM Lock failed.\n");
2570 ret = qla82xx_read_status_reg(ha, &val);
2572 goto done_unprotect;
2574 val &= ~(BLOCK_PROTECT_BITS << 2);
2575 ret = qla82xx_write_status_reg(ha, val);
2577 val |= (BLOCK_PROTECT_BITS << 2);
2578 qla82xx_write_status_reg(ha, val);
2581 if (qla82xx_write_disable_flash(ha) != 0)
2582 ql_log(ql_log_warn, vha, 0xb015,
2583 "Write disable failed.\n");
2586 qla82xx_rom_unlock(ha);
2591 qla82xx_protect_flash(struct qla_hw_data *ha)
2595 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2597 ret = ql82xx_rom_lock_d(ha);
2599 ql_log(ql_log_warn, vha, 0xb016,
2600 "ROM Lock failed.\n");
2604 ret = qla82xx_read_status_reg(ha, &val);
2608 val |= (BLOCK_PROTECT_BITS << 2);
2609 /* LOCK all sectors */
2610 ret = qla82xx_write_status_reg(ha, val);
2612 ql_log(ql_log_warn, vha, 0xb017,
2613 "Write status register failed.\n");
2615 if (qla82xx_write_disable_flash(ha) != 0)
2616 ql_log(ql_log_warn, vha, 0xb018,
2617 "Write disable failed.\n");
2619 qla82xx_rom_unlock(ha);
2624 qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2627 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2629 ret = ql82xx_rom_lock_d(ha);
2631 ql_log(ql_log_warn, vha, 0xb019,
2632 "ROM Lock failed.\n");
2636 qla82xx_flash_set_write_enable(ha);
2637 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2638 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2639 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2641 if (qla82xx_wait_rom_done(ha)) {
2642 ql_log(ql_log_warn, vha, 0xb01a,
2643 "Error waiting for rom done.\n");
2647 ret = qla82xx_flash_wait_write_finish(ha);
2649 qla82xx_rom_unlock(ha);
2654 * Address and length are byte address
2657 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2658 uint32_t offset, uint32_t length)
2660 scsi_block_requests(vha->host);
2661 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
2662 scsi_unblock_requests(vha->host);
2667 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
2668 uint32_t faddr, uint32_t dwords)
2673 dma_addr_t optrom_dma;
2674 void *optrom = NULL;
2676 struct qla_hw_data *ha = vha->hw;
2680 /* Prepare burst-capable write on supported ISPs. */
2681 if (page_mode && !(faddr & 0xfff) &&
2682 dwords > OPTROM_BURST_DWORDS) {
2683 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2684 &optrom_dma, GFP_KERNEL);
2686 ql_log(ql_log_warn, vha, 0xb01b,
2687 "Unable to allocate memory "
2688 "for optrom burst write (%x KB).\n",
2689 OPTROM_BURST_SIZE / 1024);
2693 rest_addr = ha->fdt_block_size - 1;
2695 ret = qla82xx_unprotect_flash(ha);
2697 ql_log(ql_log_warn, vha, 0xb01c,
2698 "Unable to unprotect flash for update.\n");
2702 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2703 /* Are we at the beginning of a sector? */
2704 if ((faddr & rest_addr) == 0) {
2706 ret = qla82xx_erase_sector(ha, faddr);
2708 ql_log(ql_log_warn, vha, 0xb01d,
2709 "Unable to erase sector: address=%x.\n",
2715 /* Go with burst-write. */
2716 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2717 /* Copy data to DMA'ble buffer. */
2718 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2720 ret = qla2x00_load_ram(vha, optrom_dma,
2721 (ha->flash_data_off | faddr),
2722 OPTROM_BURST_DWORDS);
2723 if (ret != QLA_SUCCESS) {
2724 ql_log(ql_log_warn, vha, 0xb01e,
2725 "Unable to burst-write optrom segment "
2726 "(%x/%x/%llx).\n", ret,
2727 (ha->flash_data_off | faddr),
2728 (unsigned long long)optrom_dma);
2729 ql_log(ql_log_warn, vha, 0xb01f,
2730 "Reverting to slow-write.\n");
2732 dma_free_coherent(&ha->pdev->dev,
2733 OPTROM_BURST_SIZE, optrom, optrom_dma);
2736 liter += OPTROM_BURST_DWORDS - 1;
2737 faddr += OPTROM_BURST_DWORDS - 1;
2738 dwptr += OPTROM_BURST_DWORDS - 1;
2743 ret = qla82xx_write_flash_dword(ha, faddr,
2744 cpu_to_le32(*dwptr));
2746 ql_dbg(ql_dbg_p3p, vha, 0xb020,
2747 "Unable to program flash address=%x data=%x.\n",
2753 ret = qla82xx_protect_flash(ha);
2755 ql_log(ql_log_warn, vha, 0xb021,
2756 "Unable to protect flash after update.\n");
2759 dma_free_coherent(&ha->pdev->dev,
2760 OPTROM_BURST_SIZE, optrom, optrom_dma);
2765 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2766 uint32_t offset, uint32_t length)
2771 scsi_block_requests(vha->host);
2772 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
2774 scsi_unblock_requests(vha->host);
2776 /* Convert return ISP82xx to generic */
2778 rval = QLA_FUNCTION_FAILED;
2785 qla82xx_start_iocbs(scsi_qla_host_t *vha)
2787 struct qla_hw_data *ha = vha->hw;
2788 struct req_que *req = ha->req_q_map[0];
2791 /* Adjust ring index. */
2793 if (req->ring_index == req->length) {
2794 req->ring_index = 0;
2795 req->ring_ptr = req->ring;
2799 dbval = 0x04 | (ha->portnum << 5);
2801 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2803 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval);
2805 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2807 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
2808 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2815 qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
2817 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2818 uint32_t lock_owner = 0;
2820 if (qla82xx_rom_lock(ha)) {
2821 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
2822 /* Someone else is holding the lock. */
2823 ql_log(ql_log_info, vha, 0xb022,
2824 "Resetting rom_lock, Lock Owner %u.\n", lock_owner);
2827 * Either we got the lock, or someone
2828 * else died while holding it.
2829 * In either case, unlock.
2831 qla82xx_rom_unlock(ha);
2835 * qla82xx_device_bootstrap
2836 * Initialize device, set DEV_READY, start fw
2839 * IDC lock must be held upon entry
2846 qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2848 int rval = QLA_SUCCESS;
2850 uint32_t old_count, count;
2851 struct qla_hw_data *ha = vha->hw;
2854 need_reset = qla82xx_need_reset(ha);
2857 /* We are trying to perform a recovery here. */
2858 if (ha->flags.isp82xx_fw_hung)
2859 qla82xx_rom_lock_recovery(ha);
2861 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2862 for (i = 0; i < 10; i++) {
2864 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2865 if (count != old_count) {
2870 qla82xx_rom_lock_recovery(ha);
2873 /* set to DEV_INITIALIZING */
2874 ql_log(ql_log_info, vha, 0x009e,
2875 "HW State: INITIALIZING.\n");
2876 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
2878 qla82xx_idc_unlock(ha);
2879 rval = qla82xx_start_firmware(vha);
2880 qla82xx_idc_lock(ha);
2882 if (rval != QLA_SUCCESS) {
2883 ql_log(ql_log_fatal, vha, 0x00ad,
2884 "HW State: FAILED.\n");
2885 qla82xx_clear_drv_active(ha);
2886 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
2891 ql_log(ql_log_info, vha, 0x00ae,
2892 "HW State: READY.\n");
2893 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2899 * qla82xx_need_qsnt_handler
2900 * Code to start quiescence sequence
2903 * IDC lock must be held upon entry
2909 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2911 struct qla_hw_data *ha = vha->hw;
2912 uint32_t dev_state, drv_state, drv_active;
2913 unsigned long reset_timeout;
2915 if (vha->flags.online) {
2916 /*Block any further I/O and wait for pending cmnds to complete*/
2917 qla2x00_quiesce_io(vha);
2920 /* Set the quiescence ready bit */
2921 qla82xx_set_qsnt_ready(ha);
2923 /*wait for 30 secs for other functions to ack */
2924 reset_timeout = jiffies + (30 * HZ);
2926 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2927 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2928 /* Its 2 that is written when qsnt is acked, moving one bit */
2929 drv_active = drv_active << 0x01;
2931 while (drv_state != drv_active) {
2933 if (time_after_eq(jiffies, reset_timeout)) {
2934 /* quiescence timeout, other functions didn't ack
2935 * changing the state to DEV_READY
2937 ql_log(ql_log_info, vha, 0xb023,
2938 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2939 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
2940 drv_active, drv_state);
2941 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2943 ql_log(ql_log_info, vha, 0xb025,
2944 "HW State: DEV_READY.\n");
2945 qla82xx_idc_unlock(ha);
2946 qla2x00_perform_loop_resync(vha);
2947 qla82xx_idc_lock(ha);
2949 qla82xx_clear_qsnt_ready(vha);
2953 qla82xx_idc_unlock(ha);
2955 qla82xx_idc_lock(ha);
2957 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2958 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2959 drv_active = drv_active << 0x01;
2961 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2962 /* everyone acked so set the state to DEV_QUIESCENCE */
2963 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
2964 ql_log(ql_log_info, vha, 0xb026,
2965 "HW State: DEV_QUIESCENT.\n");
2966 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
2971 * qla82xx_wait_for_state_change
2972 * Wait for device state to change from given current state
2975 * IDC lock must not be held upon entry
2978 * Changed device state.
2981 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
2983 struct qla_hw_data *ha = vha->hw;
2988 qla82xx_idc_lock(ha);
2989 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2990 qla82xx_idc_unlock(ha);
2991 } while (dev_state == curr_state);
2997 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
2999 struct qla_hw_data *ha = vha->hw;
3001 /* Disable the board */
3002 ql_log(ql_log_fatal, vha, 0x00b8,
3003 "Disabling the board.\n");
3005 if (IS_QLA82XX(ha)) {
3006 qla82xx_clear_drv_active(ha);
3007 qla82xx_idc_unlock(ha);
3008 } else if (IS_QLA8044(ha)) {
3009 qla8044_clear_drv_active(ha);
3010 qla8044_idc_unlock(ha);
3013 /* Set DEV_FAILED flag to disable timer */
3014 vha->device_flags |= DFLG_DEV_FAILED;
3015 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3016 qla2x00_mark_all_devices_lost(vha, 0);
3017 vha->flags.online = 0;
3018 vha->flags.init_done = 0;
3022 * qla82xx_need_reset_handler
3023 * Code to start reset sequence
3026 * IDC lock must be held upon entry
3033 qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3035 uint32_t dev_state, drv_state, drv_active;
3036 uint32_t active_mask = 0;
3037 unsigned long reset_timeout;
3038 struct qla_hw_data *ha = vha->hw;
3039 struct req_que *req = ha->req_q_map[0];
3041 if (vha->flags.online) {
3042 qla82xx_idc_unlock(ha);
3043 qla2x00_abort_isp_cleanup(vha);
3044 ha->isp_ops->get_flash_version(vha, req->ring);
3045 ha->isp_ops->nvram_config(vha);
3046 qla82xx_idc_lock(ha);
3049 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3050 if (!ha->flags.nic_core_reset_owner) {
3051 ql_dbg(ql_dbg_p3p, vha, 0xb028,
3052 "reset_acknowledged by 0x%x\n", ha->portnum);
3053 qla82xx_set_rst_ready(ha);
3055 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
3056 drv_active &= active_mask;
3057 ql_dbg(ql_dbg_p3p, vha, 0xb029,
3058 "active_mask: 0x%08x\n", active_mask);
3061 /* wait for 10 seconds for reset ack from all functions */
3062 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
3064 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3065 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3066 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3068 ql_dbg(ql_dbg_p3p, vha, 0xb02a,
3069 "drv_state: 0x%08x, drv_active: 0x%08x, "
3070 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3071 drv_state, drv_active, dev_state, active_mask);
3073 while (drv_state != drv_active &&
3074 dev_state != QLA8XXX_DEV_INITIALIZING) {
3075 if (time_after_eq(jiffies, reset_timeout)) {
3076 ql_log(ql_log_warn, vha, 0x00b5,
3077 "Reset timeout.\n");
3080 qla82xx_idc_unlock(ha);
3082 qla82xx_idc_lock(ha);
3083 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3084 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3085 if (ha->flags.nic_core_reset_owner)
3086 drv_active &= active_mask;
3087 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3090 ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3091 "drv_state: 0x%08x, drv_active: 0x%08x, "
3092 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3093 drv_state, drv_active, dev_state, active_mask);
3095 ql_log(ql_log_info, vha, 0x00b6,
3096 "Device state is 0x%x = %s.\n",
3098 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3100 /* Force to DEV_COLD unless someone else is starting a reset */
3101 if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3102 dev_state != QLA8XXX_DEV_COLD) {
3103 ql_log(ql_log_info, vha, 0x00b7,
3104 "HW State: COLD/RE-INIT.\n");
3105 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
3106 qla82xx_set_rst_ready(ha);
3108 if (qla82xx_md_collect(vha))
3109 ql_log(ql_log_warn, vha, 0xb02c,
3110 "Minidump not collected.\n");
3112 ql_log(ql_log_warn, vha, 0xb04f,
3113 "Minidump disabled.\n");
3118 qla82xx_check_md_needed(scsi_qla_host_t *vha)
3120 struct qla_hw_data *ha = vha->hw;
3121 uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3122 int rval = QLA_SUCCESS;
3124 fw_major_version = ha->fw_major_version;
3125 fw_minor_version = ha->fw_minor_version;
3126 fw_subminor_version = ha->fw_subminor_version;
3128 rval = qla2x00_get_fw_version(vha);
3129 if (rval != QLA_SUCCESS)
3133 if (!ha->fw_dumped) {
3134 if ((fw_major_version != ha->fw_major_version ||
3135 fw_minor_version != ha->fw_minor_version ||
3136 fw_subminor_version != ha->fw_subminor_version) ||
3137 (ha->prev_minidump_failed)) {
3138 ql_dbg(ql_dbg_p3p, vha, 0xb02d,
3139 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n",
3140 fw_major_version, fw_minor_version,
3141 fw_subminor_version,
3142 ha->fw_major_version,
3143 ha->fw_minor_version,
3144 ha->fw_subminor_version,
3145 ha->prev_minidump_failed);
3146 /* Release MiniDump resources */
3147 qla82xx_md_free(vha);
3148 /* ALlocate MiniDump resources */
3149 qla82xx_md_prep(vha);
3152 ql_log(ql_log_info, vha, 0xb02e,
3153 "Firmware dump available to retrieve\n");
3160 qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3162 uint32_t fw_heartbeat_counter;
3165 fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3166 QLA82XX_PEG_ALIVE_COUNTER);
3167 /* all 0xff, assume AER/EEH in progress, ignore */
3168 if (fw_heartbeat_counter == 0xffffffff) {
3169 ql_dbg(ql_dbg_timer, vha, 0x6003,
3170 "FW heartbeat counter is 0xffffffff, "
3171 "returning status=%d.\n", status);
3174 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3175 vha->seconds_since_last_heartbeat++;
3176 /* FW not alive after 2 seconds */
3177 if (vha->seconds_since_last_heartbeat == 2) {
3178 vha->seconds_since_last_heartbeat = 0;
3182 vha->seconds_since_last_heartbeat = 0;
3183 vha->fw_heartbeat_counter = fw_heartbeat_counter;
3185 ql_dbg(ql_dbg_timer, vha, 0x6004,
3186 "Returning status=%d.\n", status);
3191 * qla82xx_device_state_handler
3192 * Main state handler
3195 * IDC lock must be held upon entry
3202 qla82xx_device_state_handler(scsi_qla_host_t *vha)
3205 uint32_t old_dev_state;
3206 int rval = QLA_SUCCESS;
3207 unsigned long dev_init_timeout;
3208 struct qla_hw_data *ha = vha->hw;
3211 qla82xx_idc_lock(ha);
3212 if (!vha->flags.init_done) {
3213 qla82xx_set_drv_active(vha);
3214 qla82xx_set_idc_version(vha);
3217 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3218 old_dev_state = dev_state;
3219 ql_log(ql_log_info, vha, 0x009b,
3220 "Device state is 0x%x = %s.\n",
3222 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3224 /* wait for 30 seconds for device to go ready */
3225 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
3229 if (time_after_eq(jiffies, dev_init_timeout)) {
3230 ql_log(ql_log_fatal, vha, 0x009c,
3231 "Device init failed.\n");
3232 rval = QLA_FUNCTION_FAILED;
3235 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3236 if (old_dev_state != dev_state) {
3238 old_dev_state = dev_state;
3240 if (loopcount < 5) {
3241 ql_log(ql_log_info, vha, 0x009d,
3242 "Device state is 0x%x = %s.\n",
3244 dev_state < MAX_STATES ? qdev_state(dev_state) :
3248 switch (dev_state) {
3249 case QLA8XXX_DEV_READY:
3250 ha->flags.nic_core_reset_owner = 0;
3252 case QLA8XXX_DEV_COLD:
3253 rval = qla82xx_device_bootstrap(vha);
3255 case QLA8XXX_DEV_INITIALIZING:
3256 qla82xx_idc_unlock(ha);
3258 qla82xx_idc_lock(ha);
3260 case QLA8XXX_DEV_NEED_RESET:
3261 if (!ql2xdontresethba)
3262 qla82xx_need_reset_handler(vha);
3264 qla82xx_idc_unlock(ha);
3266 qla82xx_idc_lock(ha);
3268 dev_init_timeout = jiffies +
3269 (ha->fcoe_dev_init_timeout * HZ);
3271 case QLA8XXX_DEV_NEED_QUIESCENT:
3272 qla82xx_need_qsnt_handler(vha);
3273 /* Reset timeout value after quiescence handler */
3274 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
3277 case QLA8XXX_DEV_QUIESCENT:
3278 /* Owner will exit and other will wait for the state
3281 if (ha->flags.quiesce_owner)
3284 qla82xx_idc_unlock(ha);
3286 qla82xx_idc_lock(ha);
3288 /* Reset timeout value after quiescence handler */
3289 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
3292 case QLA8XXX_DEV_FAILED:
3293 qla8xxx_dev_failed_handler(vha);
3294 rval = QLA_FUNCTION_FAILED;
3297 qla82xx_idc_unlock(ha);
3299 qla82xx_idc_lock(ha);
3304 qla82xx_idc_unlock(ha);
3309 static int qla82xx_check_temp(scsi_qla_host_t *vha)
3311 uint32_t temp, temp_state, temp_val;
3312 struct qla_hw_data *ha = vha->hw;
3314 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3315 temp_state = qla82xx_get_temp_state(temp);
3316 temp_val = qla82xx_get_temp_val(temp);
3318 if (temp_state == QLA82XX_TEMP_PANIC) {
3319 ql_log(ql_log_warn, vha, 0x600e,
3320 "Device temperature %d degrees C exceeds "
3321 " maximum allowed. Hardware has been shut down.\n",
3324 } else if (temp_state == QLA82XX_TEMP_WARN) {
3325 ql_log(ql_log_warn, vha, 0x600f,
3326 "Device temperature %d degrees C exceeds "
3327 "operating range. Immediate action needed.\n",
3333 int qla82xx_read_temperature(scsi_qla_host_t *vha)
3337 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE);
3338 return qla82xx_get_temp_val(temp);
3341 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3343 struct qla_hw_data *ha = vha->hw;
3345 if (ha->flags.mbox_busy) {
3346 ha->flags.mbox_int = 1;
3347 ha->flags.mbox_busy = 0;
3348 ql_log(ql_log_warn, vha, 0x6010,
3349 "Doing premature completion of mbx command.\n");
3350 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
3351 complete(&ha->mbx_intr_comp);
3355 void qla82xx_watchdog(scsi_qla_host_t *vha)
3357 uint32_t dev_state, halt_status;
3358 struct qla_hw_data *ha = vha->hw;
3360 /* don't poll if reset is going on */
3361 if (!ha->flags.nic_core_reset_hdlr_active) {
3362 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3363 if (qla82xx_check_temp(vha)) {
3364 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3365 ha->flags.isp82xx_fw_hung = 1;
3366 qla82xx_clear_pending_mbx(vha);
3367 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
3368 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
3369 ql_log(ql_log_warn, vha, 0x6001,
3370 "Adapter reset needed.\n");
3371 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3372 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
3373 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
3374 ql_log(ql_log_warn, vha, 0x6002,
3375 "Quiescent needed.\n");
3376 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
3377 } else if (dev_state == QLA8XXX_DEV_FAILED &&
3378 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
3379 vha->flags.online == 1) {
3380 ql_log(ql_log_warn, vha, 0xb055,
3381 "Adapter state is failed. Offlining.\n");
3382 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3383 ha->flags.isp82xx_fw_hung = 1;
3384 qla82xx_clear_pending_mbx(vha);
3386 if (qla82xx_check_fw_alive(vha)) {
3387 ql_dbg(ql_dbg_timer, vha, 0x6011,
3388 "disabling pause transmit on port 0 & 1.\n");
3389 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3390 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
3391 halt_status = qla82xx_rd_32(ha,
3392 QLA82XX_PEG_HALT_STATUS1);
3393 ql_log(ql_log_info, vha, 0x6005,
3394 "dumping hw/fw registers:.\n "
3395 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3396 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3397 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3398 " PEG_NET_4_PC: 0x%x.\n", halt_status,
3399 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3401 QLA82XX_CRB_PEG_NET_0 + 0x3c),
3403 QLA82XX_CRB_PEG_NET_1 + 0x3c),
3405 QLA82XX_CRB_PEG_NET_2 + 0x3c),
3407 QLA82XX_CRB_PEG_NET_3 + 0x3c),
3409 QLA82XX_CRB_PEG_NET_4 + 0x3c));
3410 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
3411 ql_log(ql_log_warn, vha, 0xb052,
3412 "Firmware aborted with "
3413 "error code 0x00006700. Device is "
3415 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3416 set_bit(ISP_UNRECOVERABLE,
3419 ql_log(ql_log_info, vha, 0x6006,
3420 "Detect abort needed.\n");
3421 set_bit(ISP_ABORT_NEEDED,
3424 ha->flags.isp82xx_fw_hung = 1;
3425 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3426 qla82xx_clear_pending_mbx(vha);
3432 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3435 struct qla_hw_data *ha = vha->hw;
3438 rval = qla82xx_device_state_handler(vha);
3439 else if (IS_QLA8044(ha)) {
3440 qla8044_idc_lock(ha);
3441 /* Decide the reset ownership */
3442 qla83xx_reset_ownership(vha);
3443 qla8044_idc_unlock(ha);
3444 rval = qla8044_device_state_handler(vha);
3450 qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3452 struct qla_hw_data *ha = vha->hw;
3453 uint32_t dev_state = 0;
3456 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3457 else if (IS_QLA8044(ha))
3458 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
3460 if (dev_state == QLA8XXX_DEV_READY) {
3461 ql_log(ql_log_info, vha, 0xb02f,
3462 "HW State: NEED RESET\n");
3463 if (IS_QLA82XX(ha)) {
3464 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3465 QLA8XXX_DEV_NEED_RESET);
3466 ha->flags.nic_core_reset_owner = 1;
3467 ql_dbg(ql_dbg_p3p, vha, 0xb030,
3468 "reset_owner is 0x%x\n", ha->portnum);
3469 } else if (IS_QLA8044(ha))
3470 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
3471 QLA8XXX_DEV_NEED_RESET);
3473 ql_log(ql_log_info, vha, 0xb031,
3474 "Device state is 0x%x = %s.\n",
3476 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3481 * Resets ISP and aborts all outstanding commands.
3484 * ha = adapter block pointer.
3490 qla82xx_abort_isp(scsi_qla_host_t *vha)
3493 struct qla_hw_data *ha = vha->hw;
3495 if (vha->device_flags & DFLG_DEV_FAILED) {
3496 ql_log(ql_log_warn, vha, 0x8024,
3497 "Device in failed state, exiting.\n");
3500 ha->flags.nic_core_reset_hdlr_active = 1;
3502 qla82xx_idc_lock(ha);
3503 qla82xx_set_reset_owner(vha);
3504 qla82xx_idc_unlock(ha);
3507 rval = qla82xx_device_state_handler(vha);
3508 else if (IS_QLA8044(ha)) {
3509 qla8044_idc_lock(ha);
3510 /* Decide the reset ownership */
3511 qla83xx_reset_ownership(vha);
3512 qla8044_idc_unlock(ha);
3513 rval = qla8044_device_state_handler(vha);
3516 qla82xx_idc_lock(ha);
3517 qla82xx_clear_rst_ready(ha);
3518 qla82xx_idc_unlock(ha);
3520 if (rval == QLA_SUCCESS) {
3521 ha->flags.isp82xx_fw_hung = 0;
3522 ha->flags.nic_core_reset_hdlr_active = 0;
3523 qla82xx_restart_isp(vha);
3527 vha->flags.online = 1;
3528 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3529 if (ha->isp_abort_cnt == 0) {
3530 ql_log(ql_log_warn, vha, 0x8027,
3531 "ISP error recover failed - board "
3534 * The next call disables the board
3537 ha->isp_ops->reset_adapter(vha);
3538 vha->flags.online = 0;
3539 clear_bit(ISP_ABORT_RETRY,
3542 } else { /* schedule another ISP abort */
3543 ha->isp_abort_cnt--;
3544 ql_log(ql_log_warn, vha, 0x8036,
3545 "ISP abort - retry remaining %d.\n",
3547 rval = QLA_FUNCTION_FAILED;
3550 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3551 ql_dbg(ql_dbg_taskm, vha, 0x8029,
3552 "ISP error recovery - retrying (%d) more times.\n",
3554 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3555 rval = QLA_FUNCTION_FAILED;
3562 * qla82xx_fcoe_ctx_reset
3563 * Perform a quick reset and aborts all outstanding commands.
3564 * This will only perform an FCoE context reset and avoids a full blown
3568 * ha = adapter block pointer.
3569 * is_reset_path = flag for identifying the reset path.
3574 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3576 int rval = QLA_FUNCTION_FAILED;
3578 if (vha->flags.online) {
3579 /* Abort all outstanding commands, so as to be requeued later */
3580 qla2x00_abort_isp_cleanup(vha);
3583 /* Stop currently executing firmware.
3584 * This will destroy existing FCoE context at the F/W end.
3586 qla2x00_try_to_stop_firmware(vha);
3588 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3589 rval = qla82xx_restart_isp(vha);
3595 * qla2x00_wait_for_fcoe_ctx_reset
3596 * Wait till the FCoE context is reset.
3599 * Does context switching here.
3600 * Release SPIN_LOCK (if any) before calling this routine.
3603 * Success (fcoe_ctx reset is done) : 0
3604 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3606 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3608 int status = QLA_FUNCTION_FAILED;
3609 unsigned long wait_reset;
3611 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3612 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3613 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3614 && time_before(jiffies, wait_reset)) {
3616 set_current_state(TASK_UNINTERRUPTIBLE);
3617 schedule_timeout(HZ);
3619 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3620 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3621 status = QLA_SUCCESS;
3625 ql_dbg(ql_dbg_p3p, vha, 0xb027,
3626 "%s: status=%d.\n", __func__, status);
3632 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3634 int i, fw_state = 0;
3635 unsigned long flags;
3636 struct qla_hw_data *ha = vha->hw;
3638 /* Check if 82XX firmware is alive or not
3639 * We may have arrived here from NEED_RESET
3642 if (!ha->flags.isp82xx_fw_hung) {
3643 for (i = 0; i < 2; i++) {
3646 fw_state = qla82xx_check_fw_alive(vha);
3647 else if (IS_QLA8044(ha))
3648 fw_state = qla8044_check_fw_alive(vha);
3650 ha->flags.isp82xx_fw_hung = 1;
3651 qla82xx_clear_pending_mbx(vha);
3656 ql_dbg(ql_dbg_init, vha, 0x00b0,
3657 "Entered %s fw_hung=%d.\n",
3658 __func__, ha->flags.isp82xx_fw_hung);
3660 /* Abort all commands gracefully if fw NOT hung */
3661 if (!ha->flags.isp82xx_fw_hung) {
3664 struct req_que *req;
3666 spin_lock_irqsave(&ha->hardware_lock, flags);
3667 for (que = 0; que < ha->max_req_queues; que++) {
3668 req = ha->req_q_map[que];
3671 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
3672 sp = req->outstanding_cmds[cnt];
3674 if ((!sp->u.scmd.ctx ||
3676 SRB_FCP_CMND_DMA_VALID)) &&
3677 !ha->flags.isp82xx_fw_hung) {
3678 spin_unlock_irqrestore(
3679 &ha->hardware_lock, flags);
3680 if (ha->isp_ops->abort_command(sp)) {
3681 ql_log(ql_log_info, vha,
3683 "mbx abort failed.\n");
3685 ql_log(ql_log_info, vha,
3687 "mbx abort success.\n");
3689 spin_lock_irqsave(&ha->hardware_lock, flags);
3694 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3696 /* Wait for pending cmds (physical and virtual) to complete */
3697 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3698 WAIT_HOST) == QLA_SUCCESS) {
3699 ql_dbg(ql_dbg_init, vha, 0x00b3,
3701 "pending commands.\n");
3706 /* Minidump related functions */
3708 qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3709 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3711 struct qla_hw_data *ha = vha->hw;
3712 struct qla82xx_md_entry_crb *crb_entry;
3713 uint32_t read_value, opcode, poll_time;
3714 uint32_t addr, index, crb_addr;
3715 unsigned long wtime;
3716 struct qla82xx_md_template_hdr *tmplt_hdr;
3717 uint32_t rval = QLA_SUCCESS;
3720 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3721 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3722 crb_addr = crb_entry->addr;
3724 for (i = 0; i < crb_entry->op_count; i++) {
3725 opcode = crb_entry->crb_ctrl.opcode;
3726 if (opcode & QLA82XX_DBG_OPCODE_WR) {
3727 qla82xx_md_rw_32(ha, crb_addr,
3728 crb_entry->value_1, 1);
3729 opcode &= ~QLA82XX_DBG_OPCODE_WR;
3732 if (opcode & QLA82XX_DBG_OPCODE_RW) {
3733 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3734 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3735 opcode &= ~QLA82XX_DBG_OPCODE_RW;
3738 if (opcode & QLA82XX_DBG_OPCODE_AND) {
3739 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3740 read_value &= crb_entry->value_2;
3741 opcode &= ~QLA82XX_DBG_OPCODE_AND;
3742 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3743 read_value |= crb_entry->value_3;
3744 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3746 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3749 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3750 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3751 read_value |= crb_entry->value_3;
3752 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3753 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3756 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3757 poll_time = crb_entry->crb_strd.poll_timeout;
3758 wtime = jiffies + poll_time;
3759 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3762 if ((read_value & crb_entry->value_2)
3763 == crb_entry->value_1)
3765 else if (time_after_eq(jiffies, wtime)) {
3766 /* capturing dump failed */
3767 rval = QLA_FUNCTION_FAILED;
3770 read_value = qla82xx_md_rw_32(ha,
3773 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3776 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3777 if (crb_entry->crb_strd.state_index_a) {
3778 index = crb_entry->crb_strd.state_index_a;
3779 addr = tmplt_hdr->saved_state_array[index];
3783 read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3784 index = crb_entry->crb_ctrl.state_index_v;
3785 tmplt_hdr->saved_state_array[index] = read_value;
3786 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3789 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3790 if (crb_entry->crb_strd.state_index_a) {
3791 index = crb_entry->crb_strd.state_index_a;
3792 addr = tmplt_hdr->saved_state_array[index];
3796 if (crb_entry->crb_ctrl.state_index_v) {
3797 index = crb_entry->crb_ctrl.state_index_v;
3799 tmplt_hdr->saved_state_array[index];
3801 read_value = crb_entry->value_1;
3803 qla82xx_md_rw_32(ha, addr, read_value, 1);
3804 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3807 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3808 index = crb_entry->crb_ctrl.state_index_v;
3809 read_value = tmplt_hdr->saved_state_array[index];
3810 read_value <<= crb_entry->crb_ctrl.shl;
3811 read_value >>= crb_entry->crb_ctrl.shr;
3812 if (crb_entry->value_2)
3813 read_value &= crb_entry->value_2;
3814 read_value |= crb_entry->value_3;
3815 read_value += crb_entry->value_1;
3816 tmplt_hdr->saved_state_array[index] = read_value;
3817 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3819 crb_addr += crb_entry->crb_strd.addr_stride;
3825 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3826 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3828 struct qla_hw_data *ha = vha->hw;
3829 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3830 struct qla82xx_md_entry_rdocm *ocm_hdr;
3831 uint32_t *data_ptr = *d_ptr;
3833 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3834 r_addr = ocm_hdr->read_addr;
3835 r_stride = ocm_hdr->read_addr_stride;
3836 loop_cnt = ocm_hdr->op_count;
3838 for (i = 0; i < loop_cnt; i++) {
3839 r_value = RD_REG_DWORD(r_addr + ha->nx_pcibase);
3840 *data_ptr++ = cpu_to_le32(r_value);
3847 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3848 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3850 struct qla_hw_data *ha = vha->hw;
3851 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3852 struct qla82xx_md_entry_mux *mux_hdr;
3853 uint32_t *data_ptr = *d_ptr;
3855 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3856 r_addr = mux_hdr->read_addr;
3857 s_addr = mux_hdr->select_addr;
3858 s_stride = mux_hdr->select_value_stride;
3859 s_value = mux_hdr->select_value;
3860 loop_cnt = mux_hdr->op_count;
3862 for (i = 0; i < loop_cnt; i++) {
3863 qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3864 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3865 *data_ptr++ = cpu_to_le32(s_value);
3866 *data_ptr++ = cpu_to_le32(r_value);
3867 s_value += s_stride;
3873 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3874 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3876 struct qla_hw_data *ha = vha->hw;
3877 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3878 struct qla82xx_md_entry_crb *crb_hdr;
3879 uint32_t *data_ptr = *d_ptr;
3881 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3882 r_addr = crb_hdr->addr;
3883 r_stride = crb_hdr->crb_strd.addr_stride;
3884 loop_cnt = crb_hdr->op_count;
3886 for (i = 0; i < loop_cnt; i++) {
3887 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3888 *data_ptr++ = cpu_to_le32(r_addr);
3889 *data_ptr++ = cpu_to_le32(r_value);
3896 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3897 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3899 struct qla_hw_data *ha = vha->hw;
3900 uint32_t addr, r_addr, c_addr, t_r_addr;
3901 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3902 unsigned long p_wait, w_time, p_mask;
3903 uint32_t c_value_w, c_value_r;
3904 struct qla82xx_md_entry_cache *cache_hdr;
3905 int rval = QLA_FUNCTION_FAILED;
3906 uint32_t *data_ptr = *d_ptr;
3908 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3909 loop_count = cache_hdr->op_count;
3910 r_addr = cache_hdr->read_addr;
3911 c_addr = cache_hdr->control_addr;
3912 c_value_w = cache_hdr->cache_ctrl.write_value;
3914 t_r_addr = cache_hdr->tag_reg_addr;
3915 t_value = cache_hdr->addr_ctrl.init_tag_value;
3916 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3917 p_wait = cache_hdr->cache_ctrl.poll_wait;
3918 p_mask = cache_hdr->cache_ctrl.poll_mask;
3920 for (i = 0; i < loop_count; i++) {
3921 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3923 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3926 w_time = jiffies + p_wait;
3928 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3929 if ((c_value_r & p_mask) == 0)
3931 else if (time_after_eq(jiffies, w_time)) {
3932 /* capturing dump failed */
3933 ql_dbg(ql_dbg_p3p, vha, 0xb032,
3934 "c_value_r: 0x%x, poll_mask: 0x%lx, "
3936 c_value_r, p_mask, w_time);
3943 for (k = 0; k < r_cnt; k++) {
3944 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3945 *data_ptr++ = cpu_to_le32(r_value);
3946 addr += cache_hdr->read_ctrl.read_addr_stride;
3948 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3955 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3956 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3958 struct qla_hw_data *ha = vha->hw;
3959 uint32_t addr, r_addr, c_addr, t_r_addr;
3960 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3962 struct qla82xx_md_entry_cache *cache_hdr;
3963 uint32_t *data_ptr = *d_ptr;
3965 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3966 loop_count = cache_hdr->op_count;
3967 r_addr = cache_hdr->read_addr;
3968 c_addr = cache_hdr->control_addr;
3969 c_value_w = cache_hdr->cache_ctrl.write_value;
3971 t_r_addr = cache_hdr->tag_reg_addr;
3972 t_value = cache_hdr->addr_ctrl.init_tag_value;
3973 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3975 for (i = 0; i < loop_count; i++) {
3976 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3977 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3979 for (k = 0; k < r_cnt; k++) {
3980 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3981 *data_ptr++ = cpu_to_le32(r_value);
3982 addr += cache_hdr->read_ctrl.read_addr_stride;
3984 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3990 qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
3991 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3993 struct qla_hw_data *ha = vha->hw;
3994 uint32_t s_addr, r_addr;
3995 uint32_t r_stride, r_value, r_cnt, qid = 0;
3996 uint32_t i, k, loop_cnt;
3997 struct qla82xx_md_entry_queue *q_hdr;
3998 uint32_t *data_ptr = *d_ptr;
4000 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
4001 s_addr = q_hdr->select_addr;
4002 r_cnt = q_hdr->rd_strd.read_addr_cnt;
4003 r_stride = q_hdr->rd_strd.read_addr_stride;
4004 loop_cnt = q_hdr->op_count;
4006 for (i = 0; i < loop_cnt; i++) {
4007 qla82xx_md_rw_32(ha, s_addr, qid, 1);
4008 r_addr = q_hdr->read_addr;
4009 for (k = 0; k < r_cnt; k++) {
4010 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
4011 *data_ptr++ = cpu_to_le32(r_value);
4014 qid += q_hdr->q_strd.queue_id_stride;
4020 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
4021 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4023 struct qla_hw_data *ha = vha->hw;
4024 uint32_t r_addr, r_value;
4025 uint32_t i, loop_cnt;
4026 struct qla82xx_md_entry_rdrom *rom_hdr;
4027 uint32_t *data_ptr = *d_ptr;
4029 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
4030 r_addr = rom_hdr->read_addr;
4031 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
4033 for (i = 0; i < loop_cnt; i++) {
4034 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
4035 (r_addr & 0xFFFF0000), 1);
4036 r_value = qla82xx_md_rw_32(ha,
4037 MD_DIRECT_ROM_READ_BASE +
4038 (r_addr & 0x0000FFFF), 0, 0);
4039 *data_ptr++ = cpu_to_le32(r_value);
4040 r_addr += sizeof(uint32_t);
4046 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4047 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4049 struct qla_hw_data *ha = vha->hw;
4050 uint32_t r_addr, r_value, r_data;
4051 uint32_t i, j, loop_cnt;
4052 struct qla82xx_md_entry_rdmem *m_hdr;
4053 unsigned long flags;
4054 int rval = QLA_FUNCTION_FAILED;
4055 uint32_t *data_ptr = *d_ptr;
4057 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
4058 r_addr = m_hdr->read_addr;
4059 loop_cnt = m_hdr->read_data_size/16;
4062 ql_log(ql_log_warn, vha, 0xb033,
4063 "Read addr 0x%x not 16 bytes aligned\n", r_addr);
4067 if (m_hdr->read_data_size % 16) {
4068 ql_log(ql_log_warn, vha, 0xb034,
4069 "Read data[0x%x] not multiple of 16 bytes\n",
4070 m_hdr->read_data_size);
4074 ql_dbg(ql_dbg_p3p, vha, 0xb035,
4075 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4076 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4078 write_lock_irqsave(&ha->hw_lock, flags);
4079 for (i = 0; i < loop_cnt; i++) {
4080 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4082 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4083 r_value = MIU_TA_CTL_ENABLE;
4084 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4085 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4086 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4088 for (j = 0; j < MAX_CTL_CHECK; j++) {
4089 r_value = qla82xx_md_rw_32(ha,
4090 MD_MIU_TEST_AGT_CTRL, 0, 0);
4091 if ((r_value & MIU_TA_CTL_BUSY) == 0)
4095 if (j >= MAX_CTL_CHECK) {
4096 printk_ratelimited(KERN_ERR
4097 "failed to read through agent\n");
4098 write_unlock_irqrestore(&ha->hw_lock, flags);
4102 for (j = 0; j < 4; j++) {
4103 r_data = qla82xx_md_rw_32(ha,
4104 MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4105 *data_ptr++ = cpu_to_le32(r_data);
4109 write_unlock_irqrestore(&ha->hw_lock, flags);
4115 qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4117 struct qla_hw_data *ha = vha->hw;
4118 uint64_t chksum = 0;
4119 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4120 int count = ha->md_template_size/sizeof(uint32_t);
4124 while (chksum >> 32)
4125 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4130 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4131 qla82xx_md_entry_hdr_t *entry_hdr, int index)
4133 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4134 ql_dbg(ql_dbg_p3p, vha, 0xb036,
4135 "Skipping entry[%d]: "
4136 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4137 index, entry_hdr->entry_type,
4138 entry_hdr->d_ctrl.entry_capture_mask);
4142 qla82xx_md_collect(scsi_qla_host_t *vha)
4144 struct qla_hw_data *ha = vha->hw;
4145 int no_entry_hdr = 0;
4146 qla82xx_md_entry_hdr_t *entry_hdr;
4147 struct qla82xx_md_template_hdr *tmplt_hdr;
4149 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4150 int i = 0, rval = QLA_FUNCTION_FAILED;
4152 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4153 data_ptr = (uint32_t *)ha->md_dump;
4155 if (ha->fw_dumped) {
4156 ql_log(ql_log_warn, vha, 0xb037,
4157 "Firmware has been previously dumped (%p) "
4158 "-- ignoring request.\n", ha->fw_dump);
4164 if (!ha->md_tmplt_hdr || !ha->md_dump) {
4165 ql_log(ql_log_warn, vha, 0xb038,
4166 "Memory not allocated for minidump capture\n");
4170 if (ha->flags.isp82xx_no_md_cap) {
4171 ql_log(ql_log_warn, vha, 0xb054,
4172 "Forced reset from application, "
4173 "ignore minidump capture\n");
4174 ha->flags.isp82xx_no_md_cap = 0;
4178 if (qla82xx_validate_template_chksum(vha)) {
4179 ql_log(ql_log_info, vha, 0xb039,
4180 "Template checksum validation error\n");
4184 no_entry_hdr = tmplt_hdr->num_of_entries;
4185 ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4186 "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4188 ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4189 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4191 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4193 /* Validate whether required debug level is set */
4194 if ((f_capture_mask & 0x3) != 0x3) {
4195 ql_log(ql_log_warn, vha, 0xb03c,
4196 "Minimum required capture mask[0x%x] level not set\n",
4200 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4202 tmplt_hdr->driver_info[0] = vha->host_no;
4203 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4204 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4205 QLA_DRIVER_BETA_VER;
4207 total_data_size = ha->md_dump_size;
4209 ql_dbg(ql_dbg_p3p, vha, 0xb03d,
4210 "Total minidump data_size 0x%x to be captured\n", total_data_size);
4212 /* Check whether template obtained is valid */
4213 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4214 ql_log(ql_log_warn, vha, 0xb04e,
4215 "Bad template header entry type: 0x%x obtained\n",
4216 tmplt_hdr->entry_type);
4220 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4221 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4223 /* Walk through the entry headers */
4224 for (i = 0; i < no_entry_hdr; i++) {
4226 if (data_collected > total_data_size) {
4227 ql_log(ql_log_warn, vha, 0xb03e,
4228 "More MiniDump data collected: [0x%x]\n",
4233 if (!(entry_hdr->d_ctrl.entry_capture_mask &
4235 entry_hdr->d_ctrl.driver_flags |=
4236 QLA82XX_DBG_SKIPPED_FLAG;
4237 ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4238 "Skipping entry[%d]: "
4239 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4240 i, entry_hdr->entry_type,
4241 entry_hdr->d_ctrl.entry_capture_mask);
4242 goto skip_nxt_entry;
4245 ql_dbg(ql_dbg_p3p, vha, 0xb040,
4246 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4247 "entry_type: 0x%x, captrue_mask: 0x%x\n",
4248 __func__, i, data_ptr, entry_hdr,
4249 entry_hdr->entry_type,
4250 entry_hdr->d_ctrl.entry_capture_mask);
4252 ql_dbg(ql_dbg_p3p, vha, 0xb041,
4253 "Data collected: [0x%x], Dump size left:[0x%x]\n",
4254 data_collected, (ha->md_dump_size - data_collected));
4256 /* Decode the entry type and take
4257 * required action to capture debug data */
4258 switch (entry_hdr->entry_type) {
4260 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4263 rval = qla82xx_minidump_process_control(vha,
4264 entry_hdr, &data_ptr);
4265 if (rval != QLA_SUCCESS) {
4266 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4271 qla82xx_minidump_process_rdcrb(vha,
4272 entry_hdr, &data_ptr);
4275 rval = qla82xx_minidump_process_rdmem(vha,
4276 entry_hdr, &data_ptr);
4277 if (rval != QLA_SUCCESS) {
4278 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4284 qla82xx_minidump_process_rdrom(vha,
4285 entry_hdr, &data_ptr);
4291 rval = qla82xx_minidump_process_l2tag(vha,
4292 entry_hdr, &data_ptr);
4293 if (rval != QLA_SUCCESS) {
4294 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4300 qla82xx_minidump_process_l1cache(vha,
4301 entry_hdr, &data_ptr);
4304 qla82xx_minidump_process_rdocm(vha,
4305 entry_hdr, &data_ptr);
4308 qla82xx_minidump_process_rdmux(vha,
4309 entry_hdr, &data_ptr);
4312 qla82xx_minidump_process_queue(vha,
4313 entry_hdr, &data_ptr);
4317 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4321 ql_dbg(ql_dbg_p3p, vha, 0xb042,
4322 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4324 data_collected = (uint8_t *)data_ptr -
4325 (uint8_t *)ha->md_dump;
4327 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4328 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
4331 if (data_collected != total_data_size) {
4332 ql_dbg(ql_dbg_p3p, vha, 0xb043,
4333 "MiniDump data mismatch: Data collected: [0x%x],"
4334 "total_data_size:[0x%x]\n",
4335 data_collected, total_data_size);
4339 ql_log(ql_log_info, vha, 0xb044,
4340 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4341 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4343 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
4350 qla82xx_md_alloc(scsi_qla_host_t *vha)
4352 struct qla_hw_data *ha = vha->hw;
4354 struct qla82xx_md_template_hdr *tmplt_hdr;
4356 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4358 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4359 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
4360 ql_log(ql_log_info, vha, 0xb045,
4361 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4365 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
4366 if (i & ql2xmdcapmask)
4367 ha->md_dump_size += tmplt_hdr->capture_size_array[k];
4371 ql_log(ql_log_warn, vha, 0xb046,
4372 "Firmware dump previously allocated.\n");
4376 ha->md_dump = vmalloc(ha->md_dump_size);
4377 if (ha->md_dump == NULL) {
4378 ql_log(ql_log_warn, vha, 0xb047,
4379 "Unable to allocate memory for Minidump size "
4380 "(0x%x).\n", ha->md_dump_size);
4387 qla82xx_md_free(scsi_qla_host_t *vha)
4389 struct qla_hw_data *ha = vha->hw;
4391 /* Release the template header allocated */
4392 if (ha->md_tmplt_hdr) {
4393 ql_log(ql_log_info, vha, 0xb048,
4394 "Free MiniDump template: %p, size (%d KB)\n",
4395 ha->md_tmplt_hdr, ha->md_template_size / 1024);
4396 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4397 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4398 ha->md_tmplt_hdr = NULL;
4401 /* Release the template data buffer allocated */
4403 ql_log(ql_log_info, vha, 0xb049,
4404 "Free MiniDump memory: %p, size (%d KB)\n",
4405 ha->md_dump, ha->md_dump_size / 1024);
4407 ha->md_dump_size = 0;
4413 qla82xx_md_prep(scsi_qla_host_t *vha)
4415 struct qla_hw_data *ha = vha->hw;
4418 /* Get Minidump template size */
4419 rval = qla82xx_md_get_template_size(vha);
4420 if (rval == QLA_SUCCESS) {
4421 ql_log(ql_log_info, vha, 0xb04a,
4422 "MiniDump Template size obtained (%d KB)\n",
4423 ha->md_template_size / 1024);
4425 /* Get Minidump template */
4427 rval = qla8044_md_get_template(vha);
4429 rval = qla82xx_md_get_template(vha);
4431 if (rval == QLA_SUCCESS) {
4432 ql_dbg(ql_dbg_p3p, vha, 0xb04b,
4433 "MiniDump Template obtained\n");
4435 /* Allocate memory for minidump */
4436 rval = qla82xx_md_alloc(vha);
4437 if (rval == QLA_SUCCESS)
4438 ql_log(ql_log_info, vha, 0xb04c,
4439 "MiniDump memory allocated (%d KB)\n",
4440 ha->md_dump_size / 1024);
4442 ql_log(ql_log_info, vha, 0xb04d,
4443 "Free MiniDump template: %p, size: (%d KB)\n",
4445 ha->md_template_size / 1024);
4446 dma_free_coherent(&ha->pdev->dev,
4447 ha->md_template_size,
4448 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4449 ha->md_tmplt_hdr = NULL;
4457 qla82xx_beacon_on(struct scsi_qla_host *vha)
4461 struct qla_hw_data *ha = vha->hw;
4462 qla82xx_idc_lock(ha);
4463 rval = qla82xx_mbx_beacon_ctl(vha, 1);
4466 ql_log(ql_log_warn, vha, 0xb050,
4467 "mbx set led config failed in %s\n", __func__);
4470 ha->beacon_blink_led = 1;
4472 qla82xx_idc_unlock(ha);
4477 qla82xx_beacon_off(struct scsi_qla_host *vha)
4481 struct qla_hw_data *ha = vha->hw;
4482 qla82xx_idc_lock(ha);
4483 rval = qla82xx_mbx_beacon_ctl(vha, 0);
4486 ql_log(ql_log_warn, vha, 0xb051,
4487 "mbx set led config failed in %s\n", __func__);
4490 ha->beacon_blink_led = 0;
4492 qla82xx_idc_unlock(ha);
4497 qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
4499 struct qla_hw_data *ha = vha->hw;
4501 if (!ha->allow_cna_fw_dump)
4504 scsi_block_requests(vha->host);
4505 ha->flags.isp82xx_no_md_cap = 1;
4506 qla82xx_idc_lock(ha);
4507 qla82xx_set_reset_owner(vha);
4508 qla82xx_idc_unlock(ha);
4509 qla2x00_wait_for_chip_reset(vha);
4510 scsi_unblock_requests(vha->host);