2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <scsi/scsi_tcq.h>
17 #include <scsi/scsicam.h>
18 #include <scsi/scsi_transport.h>
19 #include <scsi/scsi_transport_fc.h>
21 #include "qla_target.h"
26 char qla2x00_version_str[40];
28 static int apidev_major;
31 * SRB allocation cache
33 static struct kmem_cache *srb_cachep;
36 * CT6 CTX allocation cache
38 static struct kmem_cache *ctx_cachep;
40 * error level for logging
42 int ql_errlev = ql_log_all;
44 static int ql2xenableclass2;
45 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46 MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
51 int ql2xlogintimeout = 20;
52 module_param(ql2xlogintimeout, int, S_IRUGO);
53 MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
56 int qlport_down_retry;
57 module_param(qlport_down_retry, int, S_IRUGO);
58 MODULE_PARM_DESC(qlport_down_retry,
59 "Maximum number of command retries to a port that returns "
60 "a PORT-DOWN status.");
62 int ql2xplogiabsentdevice;
63 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64 MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
66 "a Fabric scan. This is needed for several broken switches. "
67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69 int ql2xloginretrycount = 0;
70 module_param(ql2xloginretrycount, int, S_IRUGO);
71 MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
74 int ql2xallocfwdump = 1;
75 module_param(ql2xallocfwdump, int, S_IRUGO);
76 MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
81 int ql2xextended_error_logging;
82 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
83 MODULE_PARM_DESC(ql2xextended_error_logging,
84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
99 "\t\tDo LOGICAL OR of the value to enable more than one level");
101 int ql2xshiftctondsd = 6;
102 module_param(ql2xshiftctondsd, int, S_IRUGO);
103 MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
107 int ql2xfdmienable=1;
108 module_param(ql2xfdmienable, int, S_IRUGO);
109 MODULE_PARM_DESC(ql2xfdmienable,
110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
113 int ql2xmaxqdepth = MAX_Q_DEPTH;
114 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
115 MODULE_PARM_DESC(ql2xmaxqdepth,
116 "Maximum queue depth to set for each LUN. "
119 int ql2xenabledif = 2;
120 module_param(ql2xenabledif, int, S_IRUGO);
121 MODULE_PARM_DESC(ql2xenabledif,
122 " Enable T10-CRC-DIF "
123 " Default is 0 - No DIF Support. 1 - Enable it"
124 ", 2 - Enable DIF for all types, except Type 0.");
126 int ql2xenablehba_err_chk = 2;
127 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
128 MODULE_PARM_DESC(ql2xenablehba_err_chk,
129 " Enable T10-CRC-DIF Error isolation by HBA:\n"
131 " 0 -- Error isolation disabled\n"
132 " 1 -- Error isolation enabled only for DIX Type 0\n"
133 " 2 -- Error isolation enabled for all Types\n");
135 int ql2xiidmaenable=1;
136 module_param(ql2xiidmaenable, int, S_IRUGO);
137 MODULE_PARM_DESC(ql2xiidmaenable,
138 "Enables iIDMA settings "
139 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
141 int ql2xmaxqueues = 1;
142 module_param(ql2xmaxqueues, int, S_IRUGO);
143 MODULE_PARM_DESC(ql2xmaxqueues,
144 "Enables MQ settings "
145 "Default is 1 for single queue. Set it to number "
146 "of queues in MQ mode.");
148 int ql2xmultique_tag;
149 module_param(ql2xmultique_tag, int, S_IRUGO);
150 MODULE_PARM_DESC(ql2xmultique_tag,
151 "Enables CPU affinity settings for the driver "
152 "Default is 0 for no affinity of request and response IO. "
153 "Set it to 1 to turn on the cpu affinity.");
156 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
157 MODULE_PARM_DESC(ql2xfwloadbin,
158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
165 module_param(ql2xetsenable, int, S_IRUGO);
166 MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
171 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
172 MODULE_PARM_DESC(ql2xdbwr,
173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
177 int ql2xtargetreset = 1;
178 module_param(ql2xtargetreset, int, S_IRUGO);
179 MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
184 module_param(ql2xgffidenable, int, S_IRUGO);
185 MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
189 int ql2xasynctmfenable;
190 module_param(ql2xasynctmfenable, int, S_IRUGO);
191 MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
195 int ql2xdontresethba;
196 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
197 MODULE_PARM_DESC(ql2xdontresethba,
198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
202 uint ql2xmaxlun = MAX_LUNS;
203 module_param(ql2xmaxlun, uint, S_IRUGO);
204 MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
208 int ql2xmdcapmask = 0x1F;
209 module_param(ql2xmdcapmask, int, S_IRUGO);
210 MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
214 int ql2xmdenable = 1;
215 module_param(ql2xmdenable, int, S_IRUGO);
216 MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
222 * SCSI host template entry points
224 static int qla2xxx_slave_configure(struct scsi_device * device);
225 static int qla2xxx_slave_alloc(struct scsi_device *);
226 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
227 static void qla2xxx_scan_start(struct Scsi_Host *);
228 static void qla2xxx_slave_destroy(struct scsi_device *);
229 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
230 static int qla2xxx_eh_abort(struct scsi_cmnd *);
231 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
232 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
233 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
234 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
236 static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
237 static int qla2x00_change_queue_type(struct scsi_device *, int);
238 static void qla2x00_free_device(scsi_qla_host_t *);
240 struct scsi_host_template qla2xxx_driver_template = {
241 .module = THIS_MODULE,
242 .name = QLA2XXX_DRIVER_NAME,
243 .queuecommand = qla2xxx_queuecommand,
245 .eh_abort_handler = qla2xxx_eh_abort,
246 .eh_device_reset_handler = qla2xxx_eh_device_reset,
247 .eh_target_reset_handler = qla2xxx_eh_target_reset,
248 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
249 .eh_host_reset_handler = qla2xxx_eh_host_reset,
251 .slave_configure = qla2xxx_slave_configure,
253 .slave_alloc = qla2xxx_slave_alloc,
254 .slave_destroy = qla2xxx_slave_destroy,
255 .scan_finished = qla2xxx_scan_finished,
256 .scan_start = qla2xxx_scan_start,
257 .change_queue_depth = qla2x00_change_queue_depth,
258 .change_queue_type = qla2x00_change_queue_type,
261 .use_clustering = ENABLE_CLUSTERING,
262 .sg_tablesize = SG_ALL,
264 .max_sectors = 0xFFFF,
265 .shost_attrs = qla2x00_host_attrs,
267 .supported_mode = MODE_INITIATOR,
270 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
271 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
273 /* TODO Convert to inlines
279 qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
281 init_timer(&vha->timer);
282 vha->timer.expires = jiffies + interval * HZ;
283 vha->timer.data = (unsigned long)vha;
284 vha->timer.function = (void (*)(unsigned long))func;
285 add_timer(&vha->timer);
286 vha->timer_active = 1;
290 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
292 /* Currently used for 82XX only. */
293 if (vha->device_flags & DFLG_DEV_FAILED) {
294 ql_dbg(ql_dbg_timer, vha, 0x600d,
295 "Device in a failed state, returning.\n");
299 mod_timer(&vha->timer, jiffies + interval * HZ);
302 static __inline__ void
303 qla2x00_stop_timer(scsi_qla_host_t *vha)
305 del_timer_sync(&vha->timer);
306 vha->timer_active = 0;
309 static int qla2x00_do_dpc(void *data);
311 static void qla2x00_rst_aen(scsi_qla_host_t *);
313 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
314 struct req_que **, struct rsp_que **);
315 static void qla2x00_free_fw_dump(struct qla_hw_data *);
316 static void qla2x00_mem_free(struct qla_hw_data *);
318 /* -------------------------------------------------------------------------- */
319 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
322 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
323 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
325 if (!ha->req_q_map) {
326 ql_log(ql_log_fatal, vha, 0x003b,
327 "Unable to allocate memory for request queue ptrs.\n");
331 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
333 if (!ha->rsp_q_map) {
334 ql_log(ql_log_fatal, vha, 0x003c,
335 "Unable to allocate memory for response queue ptrs.\n");
339 * Make sure we record at least the request and response queue zero in
340 * case we need to free them if part of the probe fails.
342 ha->rsp_q_map[0] = rsp;
343 ha->req_q_map[0] = req;
344 set_bit(0, ha->rsp_qid_map);
345 set_bit(0, ha->req_qid_map);
349 kfree(ha->req_q_map);
350 ha->req_q_map = NULL;
355 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
357 if (IS_QLAFX00(ha)) {
358 if (req && req->ring_fx00)
359 dma_free_coherent(&ha->pdev->dev,
360 (req->length_fx00 + 1) * sizeof(request_t),
361 req->ring_fx00, req->dma_fx00);
362 } else if (req && req->ring)
363 dma_free_coherent(&ha->pdev->dev,
364 (req->length + 1) * sizeof(request_t),
365 req->ring, req->dma);
368 kfree(req->outstanding_cmds);
374 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
376 if (IS_QLAFX00(ha)) {
377 if (rsp && rsp->ring)
378 dma_free_coherent(&ha->pdev->dev,
379 (rsp->length_fx00 + 1) * sizeof(request_t),
380 rsp->ring_fx00, rsp->dma_fx00);
381 } else if (rsp && rsp->ring) {
382 dma_free_coherent(&ha->pdev->dev,
383 (rsp->length + 1) * sizeof(response_t),
384 rsp->ring, rsp->dma);
390 static void qla2x00_free_queues(struct qla_hw_data *ha)
396 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
397 req = ha->req_q_map[cnt];
398 qla2x00_free_req_que(ha, req);
400 kfree(ha->req_q_map);
401 ha->req_q_map = NULL;
403 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
404 rsp = ha->rsp_q_map[cnt];
405 qla2x00_free_rsp_que(ha, rsp);
407 kfree(ha->rsp_q_map);
408 ha->rsp_q_map = NULL;
411 static int qla25xx_setup_mode(struct scsi_qla_host *vha)
413 uint16_t options = 0;
415 struct qla_hw_data *ha = vha->hw;
417 if (!(ha->fw_attributes & BIT_6)) {
418 ql_log(ql_log_warn, vha, 0x00d8,
419 "Firmware is not multi-queue capable.\n");
422 if (ql2xmultique_tag) {
423 /* create a request queue for IO */
425 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
426 QLA_DEFAULT_QUE_QOS);
428 ql_log(ql_log_warn, vha, 0x00e0,
429 "Failed to create request queue.\n");
432 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
433 vha->req = ha->req_q_map[req];
435 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
436 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
438 ql_log(ql_log_warn, vha, 0x00e8,
439 "Failed to create response queue.\n");
443 ha->flags.cpu_affinity_enabled = 1;
444 ql_dbg(ql_dbg_multiq, vha, 0xc007,
445 "CPU affinity mode enalbed, "
446 "no. of response queues:%d no. of request queues:%d.\n",
447 ha->max_rsp_queues, ha->max_req_queues);
448 ql_dbg(ql_dbg_init, vha, 0x00e9,
449 "CPU affinity mode enalbed, "
450 "no. of response queues:%d no. of request queues:%d.\n",
451 ha->max_rsp_queues, ha->max_req_queues);
455 qla25xx_delete_queues(vha);
456 destroy_workqueue(ha->wq);
458 vha->req = ha->req_q_map[0];
461 kfree(ha->req_q_map);
462 kfree(ha->rsp_q_map);
463 ha->max_req_queues = ha->max_rsp_queues = 1;
468 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
470 struct qla_hw_data *ha = vha->hw;
471 static char *pci_bus_modes[] = {
472 "33", "66", "100", "133",
477 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
480 strcat(str, pci_bus_modes[pci_bus]);
482 pci_bus = (ha->pci_attr & BIT_8) >> 8;
484 strcat(str, pci_bus_modes[pci_bus]);
486 strcat(str, " MHz)");
492 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
494 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
495 struct qla_hw_data *ha = vha->hw;
499 pcie_reg = pci_pcie_cap(ha->pdev);
502 uint16_t pcie_lstat, lspeed, lwidth;
504 pcie_reg += PCI_EXP_LNKCAP;
505 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
506 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
507 lwidth = (pcie_lstat &
508 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
510 strcpy(str, "PCIe (");
513 strcat(str, "2.5GT/s ");
516 strcat(str, "5.0GT/s ");
519 strcat(str, "8.0GT/s ");
522 strcat(str, "<unknown> ");
525 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
532 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
533 if (pci_bus == 0 || pci_bus == 8) {
535 strcat(str, pci_bus_modes[pci_bus >> 3]);
539 strcat(str, "Mode 2");
541 strcat(str, "Mode 1");
543 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
545 strcat(str, " MHz)");
551 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
554 struct qla_hw_data *ha = vha->hw;
556 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
557 ha->fw_minor_version,
558 ha->fw_subminor_version);
560 if (ha->fw_attributes & BIT_9) {
565 switch (ha->fw_attributes & 0xFF) {
579 sprintf(un_str, "(%x)", ha->fw_attributes);
583 if (ha->fw_attributes & 0x100)
590 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
592 struct qla_hw_data *ha = vha->hw;
594 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
595 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
600 qla2x00_sp_free_dma(void *vha, void *ptr)
602 srb_t *sp = (srb_t *)ptr;
603 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
604 struct qla_hw_data *ha = sp->fcport->vha->hw;
605 void *ctx = GET_CMD_CTX_SP(sp);
607 if (sp->flags & SRB_DMA_VALID) {
609 sp->flags &= ~SRB_DMA_VALID;
612 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
613 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
614 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
615 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
618 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
619 /* List assured to be having elements */
620 qla2x00_clean_dsd_pool(ha, sp);
621 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
624 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
625 dma_pool_free(ha->dl_dma_pool, ctx,
626 ((struct crc_context *)ctx)->crc_ctx_dma);
627 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
630 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
631 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
633 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
635 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
636 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
637 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
638 mempool_free(ctx1, ha->ctx_mempool);
643 qla2x00_rel_sp(sp->fcport->vha, sp);
647 qla2x00_sp_compl(void *data, void *ptr, int res)
649 struct qla_hw_data *ha = (struct qla_hw_data *)data;
650 srb_t *sp = (srb_t *)ptr;
651 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
655 if (atomic_read(&sp->ref_count) == 0) {
656 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
657 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
659 if (ql2xextended_error_logging & ql_dbg_io)
663 if (!atomic_dec_and_test(&sp->ref_count))
666 qla2x00_sp_free_dma(ha, sp);
670 /* If we are SP1 here, we need to still take and release the host_lock as SP1
671 * does not have the changes necessary to avoid taking host->host_lock.
674 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
676 scsi_qla_host_t *vha = shost_priv(host);
677 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
678 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
679 struct qla_hw_data *ha = vha->hw;
680 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
684 if (ha->flags.eeh_busy) {
685 if (ha->flags.pci_channel_io_perm_failure) {
686 ql_dbg(ql_dbg_aer, vha, 0x9010,
687 "PCI Channel IO permanent failure, exiting "
689 cmd->result = DID_NO_CONNECT << 16;
691 ql_dbg(ql_dbg_aer, vha, 0x9011,
692 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
693 cmd->result = DID_REQUEUE << 16;
695 goto qc24_fail_command;
698 rval = fc_remote_port_chkready(rport);
701 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
702 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
704 goto qc24_fail_command;
707 if (!vha->flags.difdix_supported &&
708 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
709 ql_dbg(ql_dbg_io, vha, 0x3004,
710 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
712 cmd->result = DID_NO_CONNECT << 16;
713 goto qc24_fail_command;
717 cmd->result = DID_NO_CONNECT << 16;
718 goto qc24_fail_command;
721 if (atomic_read(&fcport->state) != FCS_ONLINE) {
722 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
723 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
724 ql_dbg(ql_dbg_io, vha, 0x3005,
725 "Returning DNC, fcport_state=%d loop_state=%d.\n",
726 atomic_read(&fcport->state),
727 atomic_read(&base_vha->loop_state));
728 cmd->result = DID_NO_CONNECT << 16;
729 goto qc24_fail_command;
731 goto qc24_target_busy;
734 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
736 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
740 sp->u.scmd.cmd = cmd;
741 sp->type = SRB_SCSI_CMD;
742 atomic_set(&sp->ref_count, 1);
743 CMD_SP(cmd) = (void *)sp;
744 sp->free = qla2x00_sp_free_dma;
745 sp->done = qla2x00_sp_compl;
747 rval = ha->isp_ops->start_scsi(sp);
748 if (rval != QLA_SUCCESS) {
749 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
750 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
751 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
752 goto qc24_host_busy_free_sp;
757 qc24_host_busy_free_sp:
758 qla2x00_sp_free_dma(ha, sp);
761 return SCSI_MLQUEUE_HOST_BUSY;
764 return SCSI_MLQUEUE_TARGET_BUSY;
773 * qla2x00_eh_wait_on_command
774 * Waits for the command to be returned by the Firmware for some
778 * cmd = Scsi Command to wait on.
785 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
787 #define ABORT_POLLING_PERIOD 1000
788 #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
789 unsigned long wait_iter = ABORT_WAIT_ITER;
790 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
791 struct qla_hw_data *ha = vha->hw;
792 int ret = QLA_SUCCESS;
794 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
795 ql_dbg(ql_dbg_taskm, vha, 0x8005,
796 "Return:eh_wait.\n");
800 while (CMD_SP(cmd) && wait_iter--) {
801 msleep(ABORT_POLLING_PERIOD);
804 ret = QLA_FUNCTION_FAILED;
810 * qla2x00_wait_for_hba_online
811 * Wait till the HBA is online after going through
812 * <= MAX_RETRIES_OF_ISP_ABORT or
813 * finally HBA is disabled ie marked offline
816 * ha - pointer to host adapter structure
819 * Does context switching-Release SPIN_LOCK
820 * (if any) before calling this routine.
823 * Success (Adapter is online) : 0
824 * Failed (Adapter is offline/disabled) : 1
827 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
830 unsigned long wait_online;
831 struct qla_hw_data *ha = vha->hw;
832 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
834 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
835 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
836 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
837 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
838 ha->dpc_active) && time_before(jiffies, wait_online)) {
842 if (base_vha->flags.online)
843 return_status = QLA_SUCCESS;
845 return_status = QLA_FUNCTION_FAILED;
847 return (return_status);
851 * qla2x00_wait_for_reset_ready
852 * Wait till the HBA is online after going through
853 * <= MAX_RETRIES_OF_ISP_ABORT or
854 * finally HBA is disabled ie marked offline or flash
855 * operations are in progress.
858 * ha - pointer to host adapter structure
861 * Does context switching-Release SPIN_LOCK
862 * (if any) before calling this routine.
865 * Success (Adapter is online/no flash ops) : 0
866 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
869 qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
872 unsigned long wait_online;
873 struct qla_hw_data *ha = vha->hw;
874 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
876 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
877 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
878 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
879 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
880 ha->optrom_state != QLA_SWAITING ||
881 ha->dpc_active) && time_before(jiffies, wait_online))
884 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
885 return_status = QLA_SUCCESS;
887 return_status = QLA_FUNCTION_FAILED;
889 ql_dbg(ql_dbg_taskm, vha, 0x8019,
890 "%s return status=%d.\n", __func__, return_status);
892 return return_status;
896 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
899 unsigned long wait_reset;
900 struct qla_hw_data *ha = vha->hw;
901 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
903 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
904 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
905 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
906 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
907 ha->dpc_active) && time_before(jiffies, wait_reset)) {
911 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
912 ha->flags.chip_reset_done)
915 if (ha->flags.chip_reset_done)
916 return_status = QLA_SUCCESS;
918 return_status = QLA_FUNCTION_FAILED;
920 return return_status;
924 sp_get(struct srb *sp)
926 atomic_inc(&sp->ref_count);
929 /**************************************************************************
933 * The abort function will abort the specified command.
936 * cmd = Linux SCSI command packet to be aborted.
939 * Either SUCCESS or FAILED.
942 * Only return FAILED if command not returned by firmware.
943 **************************************************************************/
945 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
947 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
950 unsigned int id, lun;
953 struct qla_hw_data *ha = vha->hw;
958 ret = fc_block_scsi_eh(cmd);
963 id = cmd->device->id;
964 lun = cmd->device->lun;
966 spin_lock_irqsave(&ha->hardware_lock, flags);
967 sp = (srb_t *) CMD_SP(cmd);
969 spin_unlock_irqrestore(&ha->hardware_lock, flags);
973 ql_dbg(ql_dbg_taskm, vha, 0x8002,
974 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
975 vha->host_no, id, lun, sp, cmd);
977 /* Get a reference to the sp and drop the lock.*/
980 spin_unlock_irqrestore(&ha->hardware_lock, flags);
981 if (ha->isp_ops->abort_command(sp)) {
983 ql_dbg(ql_dbg_taskm, vha, 0x8003,
984 "Abort command mbx failed cmd=%p.\n", cmd);
986 ql_dbg(ql_dbg_taskm, vha, 0x8004,
987 "Abort command mbx success cmd=%p.\n", cmd);
991 spin_lock_irqsave(&ha->hardware_lock, flags);
993 spin_unlock_irqrestore(&ha->hardware_lock, flags);
995 /* Did the command return during mailbox execution? */
996 if (ret == FAILED && !CMD_SP(cmd))
999 /* Wait for the command to be returned. */
1001 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
1002 ql_log(ql_log_warn, vha, 0x8006,
1003 "Abort handler timed out cmd=%p.\n", cmd);
1008 ql_log(ql_log_info, vha, 0x801c,
1009 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
1010 vha->host_no, id, lun, wait, ret);
1016 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1017 unsigned int l, enum nexus_wait_type type)
1019 int cnt, match, status;
1020 unsigned long flags;
1021 struct qla_hw_data *ha = vha->hw;
1022 struct req_que *req;
1024 struct scsi_cmnd *cmd;
1026 status = QLA_SUCCESS;
1028 spin_lock_irqsave(&ha->hardware_lock, flags);
1030 for (cnt = 1; status == QLA_SUCCESS &&
1031 cnt < req->num_outstanding_cmds; cnt++) {
1032 sp = req->outstanding_cmds[cnt];
1035 if (sp->type != SRB_SCSI_CMD)
1037 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1040 cmd = GET_CMD_SP(sp);
1046 match = cmd->device->id == t;
1049 match = (cmd->device->id == t &&
1050 cmd->device->lun == l);
1056 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1057 status = qla2x00_eh_wait_on_command(cmd);
1058 spin_lock_irqsave(&ha->hardware_lock, flags);
1060 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1065 static char *reset_errors[] = {
1068 "Task management failed",
1069 "Waiting for command completions",
1073 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1074 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1076 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1077 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1084 err = fc_block_scsi_eh(cmd);
1088 ql_log(ql_log_info, vha, 0x8009,
1089 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
1090 cmd->device->id, cmd->device->lun, cmd);
1093 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1094 ql_log(ql_log_warn, vha, 0x800a,
1095 "Wait for hba online failed for cmd=%p.\n", cmd);
1096 goto eh_reset_failed;
1099 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1101 ql_log(ql_log_warn, vha, 0x800c,
1102 "do_reset failed for cmd=%p.\n", cmd);
1103 goto eh_reset_failed;
1106 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1107 cmd->device->lun, type) != QLA_SUCCESS) {
1108 ql_log(ql_log_warn, vha, 0x800d,
1109 "wait for pending cmds failed for cmd=%p.\n", cmd);
1110 goto eh_reset_failed;
1113 ql_log(ql_log_info, vha, 0x800e,
1114 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1115 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1120 ql_log(ql_log_info, vha, 0x800f,
1121 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1122 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1128 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1130 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1131 struct qla_hw_data *ha = vha->hw;
1133 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1134 ha->isp_ops->lun_reset);
1138 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1140 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1141 struct qla_hw_data *ha = vha->hw;
1143 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1144 ha->isp_ops->target_reset);
1147 /**************************************************************************
1148 * qla2xxx_eh_bus_reset
1151 * The bus reset function will reset the bus and abort any executing
1155 * cmd = Linux SCSI command packet of the command that cause the
1159 * SUCCESS/FAILURE (defined as macro in scsi.h).
1161 **************************************************************************/
1163 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1165 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1166 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1168 unsigned int id, lun;
1170 id = cmd->device->id;
1171 lun = cmd->device->lun;
1177 ret = fc_block_scsi_eh(cmd);
1182 ql_log(ql_log_info, vha, 0x8012,
1183 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1185 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1186 ql_log(ql_log_fatal, vha, 0x8013,
1187 "Wait for hba online failed board disabled.\n");
1188 goto eh_bus_reset_done;
1191 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1195 goto eh_bus_reset_done;
1197 /* Flush outstanding commands. */
1198 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1200 ql_log(ql_log_warn, vha, 0x8014,
1201 "Wait for pending commands failed.\n");
1206 ql_log(ql_log_warn, vha, 0x802b,
1207 "BUS RESET %s nexus=%ld:%d:%d.\n",
1208 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1213 /**************************************************************************
1214 * qla2xxx_eh_host_reset
1217 * The reset function will reset the Adapter.
1220 * cmd = Linux SCSI command packet of the command that cause the
1224 * Either SUCCESS or FAILED.
1227 **************************************************************************/
1229 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1231 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1232 struct qla_hw_data *ha = vha->hw;
1234 unsigned int id, lun;
1235 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1237 id = cmd->device->id;
1238 lun = cmd->device->lun;
1240 ql_log(ql_log_info, vha, 0x8018,
1241 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1243 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
1244 goto eh_host_reset_lock;
1246 if (vha != base_vha) {
1247 if (qla2x00_vp_abort_isp(vha))
1248 goto eh_host_reset_lock;
1250 if (IS_QLA82XX(vha->hw)) {
1251 if (!qla82xx_fcoe_ctx_reset(vha)) {
1252 /* Ctx reset success */
1254 goto eh_host_reset_lock;
1256 /* fall thru if ctx reset failed */
1259 flush_workqueue(ha->wq);
1261 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1262 if (ha->isp_ops->abort_isp(base_vha)) {
1263 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1264 /* failed. schedule dpc to try */
1265 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1267 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1268 ql_log(ql_log_warn, vha, 0x802a,
1269 "wait for hba online failed.\n");
1270 goto eh_host_reset_lock;
1273 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1276 /* Waiting for command to be returned to OS.*/
1277 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1282 ql_log(ql_log_info, vha, 0x8017,
1283 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1284 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1290 * qla2x00_loop_reset
1294 * ha = adapter block pointer.
1300 qla2x00_loop_reset(scsi_qla_host_t *vha)
1303 struct fc_port *fcport;
1304 struct qla_hw_data *ha = vha->hw;
1306 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1307 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1308 if (fcport->port_type != FCT_TARGET)
1311 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1312 if (ret != QLA_SUCCESS) {
1313 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1314 "Bus Reset failed: Target Reset=%d "
1315 "d_id=%x.\n", ret, fcport->d_id.b24);
1323 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1324 atomic_set(&vha->loop_state, LOOP_DOWN);
1325 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1326 qla2x00_mark_all_devices_lost(vha, 0);
1327 ret = qla2x00_full_login_lip(vha);
1328 if (ret != QLA_SUCCESS) {
1329 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1330 "full_login_lip=%d.\n", ret);
1334 if (ha->flags.enable_lip_reset) {
1335 ret = qla2x00_lip_reset(vha);
1336 if (ret != QLA_SUCCESS)
1337 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1338 "lip_reset failed (%d).\n", ret);
1341 /* Issue marker command only when we are going to start the I/O */
1342 vha->marker_needed = 1;
1348 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1351 unsigned long flags;
1353 struct qla_hw_data *ha = vha->hw;
1354 struct req_que *req;
1356 spin_lock_irqsave(&ha->hardware_lock, flags);
1357 for (que = 0; que < ha->max_req_queues; que++) {
1358 req = ha->req_q_map[que];
1361 if (!req->outstanding_cmds)
1363 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1364 sp = req->outstanding_cmds[cnt];
1366 req->outstanding_cmds[cnt] = NULL;
1367 sp->done(vha, sp, res);
1371 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1375 qla2xxx_slave_alloc(struct scsi_device *sdev)
1377 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1379 if (!rport || fc_remote_port_chkready(rport))
1382 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1388 qla2xxx_slave_configure(struct scsi_device *sdev)
1390 scsi_qla_host_t *vha = shost_priv(sdev->host);
1391 struct req_que *req = vha->req;
1393 if (IS_T10_PI_CAPABLE(vha->hw))
1394 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1396 if (sdev->tagged_supported)
1397 scsi_activate_tcq(sdev, req->max_q_depth);
1399 scsi_deactivate_tcq(sdev, req->max_q_depth);
1404 qla2xxx_slave_destroy(struct scsi_device *sdev)
1406 sdev->hostdata = NULL;
1409 static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1411 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1413 if (!scsi_track_queue_full(sdev, qdepth))
1416 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1417 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1418 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1421 static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1423 fc_port_t *fcport = sdev->hostdata;
1424 struct scsi_qla_host *vha = fcport->vha;
1425 struct req_que *req = NULL;
1431 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1434 if (sdev->ordered_tags)
1435 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1437 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1439 ql_dbg(ql_dbg_io, vha, 0x302a,
1440 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1441 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
1445 qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
1448 case SCSI_QDEPTH_DEFAULT:
1449 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1451 case SCSI_QDEPTH_QFULL:
1452 qla2x00_handle_queue_full(sdev, qdepth);
1454 case SCSI_QDEPTH_RAMP_UP:
1455 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1461 return sdev->queue_depth;
1465 qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1467 if (sdev->tagged_supported) {
1468 scsi_set_tag_type(sdev, tag_type);
1470 scsi_activate_tcq(sdev, sdev->queue_depth);
1472 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1480 qla2x00_host_ramp_down_queuedepth(scsi_qla_host_t *vha)
1482 scsi_qla_host_t *vp;
1483 struct Scsi_Host *shost;
1484 struct scsi_device *sdev;
1485 struct qla_hw_data *ha = vha->hw;
1486 unsigned long flags;
1488 ha->host_last_rampdown_time = jiffies;
1490 if (ha->cfg_lun_q_depth <= vha->host->cmd_per_lun)
1493 if ((ha->cfg_lun_q_depth / 2) < vha->host->cmd_per_lun)
1494 ha->cfg_lun_q_depth = vha->host->cmd_per_lun;
1496 ha->cfg_lun_q_depth = ha->cfg_lun_q_depth / 2;
1499 * Geometrically ramp down the queue depth for all devices on this
1502 spin_lock_irqsave(&ha->vport_slock, flags);
1503 list_for_each_entry(vp, &ha->vp_list, list) {
1505 shost_for_each_device(sdev, shost) {
1506 if (sdev->queue_depth > shost->cmd_per_lun) {
1507 if (sdev->queue_depth < ha->cfg_lun_q_depth)
1509 ql_log(ql_log_warn, vp, 0x3031,
1510 "%ld:%d:%d: Ramping down queue depth to %d",
1511 vp->host_no, sdev->id, sdev->lun,
1512 ha->cfg_lun_q_depth);
1513 qla2x00_change_queue_depth(sdev,
1514 ha->cfg_lun_q_depth, SCSI_QDEPTH_DEFAULT);
1518 spin_unlock_irqrestore(&ha->vport_slock, flags);
1524 qla2x00_host_ramp_up_queuedepth(scsi_qla_host_t *vha)
1526 scsi_qla_host_t *vp;
1527 struct Scsi_Host *shost;
1528 struct scsi_device *sdev;
1529 struct qla_hw_data *ha = vha->hw;
1530 unsigned long flags;
1532 ha->host_last_rampup_time = jiffies;
1533 ha->cfg_lun_q_depth++;
1536 * Linearly ramp up the queue depth for all devices on this
1539 spin_lock_irqsave(&ha->vport_slock, flags);
1540 list_for_each_entry(vp, &ha->vp_list, list) {
1542 shost_for_each_device(sdev, shost) {
1543 if (sdev->queue_depth > ha->cfg_lun_q_depth)
1545 qla2x00_change_queue_depth(sdev, ha->cfg_lun_q_depth,
1546 SCSI_QDEPTH_RAMP_UP);
1549 spin_unlock_irqrestore(&ha->vport_slock, flags);
1555 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1558 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1559 * supported addressing method.
1562 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1564 /* Assume a 32bit DMA mask. */
1565 ha->flags.enable_64bit_addressing = 0;
1567 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1568 /* Any upper-dword bits set? */
1569 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1570 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1571 /* Ok, a 64bit DMA mask is applicable. */
1572 ha->flags.enable_64bit_addressing = 1;
1573 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1574 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1579 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1580 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1584 qla2x00_enable_intrs(struct qla_hw_data *ha)
1586 unsigned long flags = 0;
1587 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1589 spin_lock_irqsave(&ha->hardware_lock, flags);
1590 ha->interrupts_on = 1;
1591 /* enable risc and host interrupts */
1592 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
1593 RD_REG_WORD(®->ictrl);
1594 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1599 qla2x00_disable_intrs(struct qla_hw_data *ha)
1601 unsigned long flags = 0;
1602 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1604 spin_lock_irqsave(&ha->hardware_lock, flags);
1605 ha->interrupts_on = 0;
1606 /* disable risc and host interrupts */
1607 WRT_REG_WORD(®->ictrl, 0);
1608 RD_REG_WORD(®->ictrl);
1609 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1613 qla24xx_enable_intrs(struct qla_hw_data *ha)
1615 unsigned long flags = 0;
1616 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1618 spin_lock_irqsave(&ha->hardware_lock, flags);
1619 ha->interrupts_on = 1;
1620 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT);
1621 RD_REG_DWORD(®->ictrl);
1622 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1626 qla24xx_disable_intrs(struct qla_hw_data *ha)
1628 unsigned long flags = 0;
1629 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1631 if (IS_NOPOLLING_TYPE(ha))
1633 spin_lock_irqsave(&ha->hardware_lock, flags);
1634 ha->interrupts_on = 0;
1635 WRT_REG_DWORD(®->ictrl, 0);
1636 RD_REG_DWORD(®->ictrl);
1637 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1641 qla2x00_iospace_config(struct qla_hw_data *ha)
1643 resource_size_t pio;
1647 if (pci_request_selected_regions(ha->pdev, ha->bars,
1648 QLA2XXX_DRIVER_NAME)) {
1649 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1650 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1651 pci_name(ha->pdev));
1652 goto iospace_error_exit;
1654 if (!(ha->bars & 1))
1657 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1658 pio = pci_resource_start(ha->pdev, 0);
1659 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1660 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1661 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1662 "Invalid pci I/O region size (%s).\n",
1663 pci_name(ha->pdev));
1667 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1668 "Region #0 no a PIO resource (%s).\n",
1669 pci_name(ha->pdev));
1672 ha->pio_address = pio;
1673 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1674 "PIO address=%llu.\n",
1675 (unsigned long long)ha->pio_address);
1678 /* Use MMIO operations for all accesses. */
1679 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1680 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1681 "Region #1 not an MMIO resource (%s), aborting.\n",
1682 pci_name(ha->pdev));
1683 goto iospace_error_exit;
1685 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1686 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1687 "Invalid PCI mem region size (%s), aborting.\n",
1688 pci_name(ha->pdev));
1689 goto iospace_error_exit;
1692 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1694 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1695 "Cannot remap MMIO (%s), aborting.\n",
1696 pci_name(ha->pdev));
1697 goto iospace_error_exit;
1700 /* Determine queue resources */
1701 ha->max_req_queues = ha->max_rsp_queues = 1;
1702 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1703 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1704 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1707 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1708 pci_resource_len(ha->pdev, 3));
1710 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1711 "MQIO Base=%p.\n", ha->mqiobase);
1712 /* Read MSIX vector size of the board */
1713 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1714 ha->msix_count = msix;
1715 /* Max queues are bounded by available msix vectors */
1716 /* queue 0 uses two msix vectors */
1717 if (ql2xmultique_tag) {
1718 cpus = num_online_cpus();
1719 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1720 (cpus + 1) : (ha->msix_count - 1);
1721 ha->max_req_queues = 2;
1722 } else if (ql2xmaxqueues > 1) {
1723 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1724 QLA_MQ_SIZE : ql2xmaxqueues;
1725 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1726 "QoS mode set, max no of request queues:%d.\n",
1727 ha->max_req_queues);
1728 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1729 "QoS mode set, max no of request queues:%d.\n",
1730 ha->max_req_queues);
1732 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1733 "MSI-X vector count: %d.\n", msix);
1735 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1736 "BAR 3 not enabled.\n");
1739 ha->msix_count = ha->max_rsp_queues + 1;
1740 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1741 "MSIX Count:%d.\n", ha->msix_count);
1750 qla83xx_iospace_config(struct qla_hw_data *ha)
1755 if (pci_request_selected_regions(ha->pdev, ha->bars,
1756 QLA2XXX_DRIVER_NAME)) {
1757 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1758 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1759 pci_name(ha->pdev));
1761 goto iospace_error_exit;
1764 /* Use MMIO operations for all accesses. */
1765 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1766 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1767 "Invalid pci I/O region size (%s).\n",
1768 pci_name(ha->pdev));
1769 goto iospace_error_exit;
1771 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1772 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1773 "Invalid PCI mem region size (%s), aborting\n",
1774 pci_name(ha->pdev));
1775 goto iospace_error_exit;
1778 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1780 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1781 "Cannot remap MMIO (%s), aborting.\n",
1782 pci_name(ha->pdev));
1783 goto iospace_error_exit;
1786 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1787 /* 83XX 26XX always use MQ type access for queues
1788 * - mbar 2, a.k.a region 4 */
1789 ha->max_req_queues = ha->max_rsp_queues = 1;
1790 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1791 pci_resource_len(ha->pdev, 4));
1793 if (!ha->mqiobase) {
1794 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1795 "BAR2/region4 not enabled\n");
1799 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1800 pci_resource_len(ha->pdev, 2));
1802 /* Read MSIX vector size of the board */
1803 pci_read_config_word(ha->pdev,
1804 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1805 ha->msix_count = msix;
1806 /* Max queues are bounded by available msix vectors */
1807 /* queue 0 uses two msix vectors */
1808 if (ql2xmultique_tag) {
1809 cpus = num_online_cpus();
1810 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1811 (cpus + 1) : (ha->msix_count - 1);
1812 ha->max_req_queues = 2;
1813 } else if (ql2xmaxqueues > 1) {
1814 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1815 QLA_MQ_SIZE : ql2xmaxqueues;
1816 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1817 "QoS mode set, max no of request queues:%d.\n",
1818 ha->max_req_queues);
1819 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1820 "QoS mode set, max no of request queues:%d.\n",
1821 ha->max_req_queues);
1823 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1824 "MSI-X vector count: %d.\n", msix);
1826 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1827 "BAR 1 not enabled.\n");
1830 ha->msix_count = ha->max_rsp_queues + 1;
1832 qlt_83xx_iospace_config(ha);
1834 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1835 "MSIX Count:%d.\n", ha->msix_count);
1842 static struct isp_operations qla2100_isp_ops = {
1843 .pci_config = qla2100_pci_config,
1844 .reset_chip = qla2x00_reset_chip,
1845 .chip_diag = qla2x00_chip_diag,
1846 .config_rings = qla2x00_config_rings,
1847 .reset_adapter = qla2x00_reset_adapter,
1848 .nvram_config = qla2x00_nvram_config,
1849 .update_fw_options = qla2x00_update_fw_options,
1850 .load_risc = qla2x00_load_risc,
1851 .pci_info_str = qla2x00_pci_info_str,
1852 .fw_version_str = qla2x00_fw_version_str,
1853 .intr_handler = qla2100_intr_handler,
1854 .enable_intrs = qla2x00_enable_intrs,
1855 .disable_intrs = qla2x00_disable_intrs,
1856 .abort_command = qla2x00_abort_command,
1857 .target_reset = qla2x00_abort_target,
1858 .lun_reset = qla2x00_lun_reset,
1859 .fabric_login = qla2x00_login_fabric,
1860 .fabric_logout = qla2x00_fabric_logout,
1861 .calc_req_entries = qla2x00_calc_iocbs_32,
1862 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1863 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1864 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1865 .read_nvram = qla2x00_read_nvram_data,
1866 .write_nvram = qla2x00_write_nvram_data,
1867 .fw_dump = qla2100_fw_dump,
1870 .beacon_blink = NULL,
1871 .read_optrom = qla2x00_read_optrom_data,
1872 .write_optrom = qla2x00_write_optrom_data,
1873 .get_flash_version = qla2x00_get_flash_version,
1874 .start_scsi = qla2x00_start_scsi,
1875 .abort_isp = qla2x00_abort_isp,
1876 .iospace_config = qla2x00_iospace_config,
1877 .initialize_adapter = qla2x00_initialize_adapter,
1880 static struct isp_operations qla2300_isp_ops = {
1881 .pci_config = qla2300_pci_config,
1882 .reset_chip = qla2x00_reset_chip,
1883 .chip_diag = qla2x00_chip_diag,
1884 .config_rings = qla2x00_config_rings,
1885 .reset_adapter = qla2x00_reset_adapter,
1886 .nvram_config = qla2x00_nvram_config,
1887 .update_fw_options = qla2x00_update_fw_options,
1888 .load_risc = qla2x00_load_risc,
1889 .pci_info_str = qla2x00_pci_info_str,
1890 .fw_version_str = qla2x00_fw_version_str,
1891 .intr_handler = qla2300_intr_handler,
1892 .enable_intrs = qla2x00_enable_intrs,
1893 .disable_intrs = qla2x00_disable_intrs,
1894 .abort_command = qla2x00_abort_command,
1895 .target_reset = qla2x00_abort_target,
1896 .lun_reset = qla2x00_lun_reset,
1897 .fabric_login = qla2x00_login_fabric,
1898 .fabric_logout = qla2x00_fabric_logout,
1899 .calc_req_entries = qla2x00_calc_iocbs_32,
1900 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1901 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1902 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1903 .read_nvram = qla2x00_read_nvram_data,
1904 .write_nvram = qla2x00_write_nvram_data,
1905 .fw_dump = qla2300_fw_dump,
1906 .beacon_on = qla2x00_beacon_on,
1907 .beacon_off = qla2x00_beacon_off,
1908 .beacon_blink = qla2x00_beacon_blink,
1909 .read_optrom = qla2x00_read_optrom_data,
1910 .write_optrom = qla2x00_write_optrom_data,
1911 .get_flash_version = qla2x00_get_flash_version,
1912 .start_scsi = qla2x00_start_scsi,
1913 .abort_isp = qla2x00_abort_isp,
1914 .iospace_config = qla2x00_iospace_config,
1915 .initialize_adapter = qla2x00_initialize_adapter,
1918 static struct isp_operations qla24xx_isp_ops = {
1919 .pci_config = qla24xx_pci_config,
1920 .reset_chip = qla24xx_reset_chip,
1921 .chip_diag = qla24xx_chip_diag,
1922 .config_rings = qla24xx_config_rings,
1923 .reset_adapter = qla24xx_reset_adapter,
1924 .nvram_config = qla24xx_nvram_config,
1925 .update_fw_options = qla24xx_update_fw_options,
1926 .load_risc = qla24xx_load_risc,
1927 .pci_info_str = qla24xx_pci_info_str,
1928 .fw_version_str = qla24xx_fw_version_str,
1929 .intr_handler = qla24xx_intr_handler,
1930 .enable_intrs = qla24xx_enable_intrs,
1931 .disable_intrs = qla24xx_disable_intrs,
1932 .abort_command = qla24xx_abort_command,
1933 .target_reset = qla24xx_abort_target,
1934 .lun_reset = qla24xx_lun_reset,
1935 .fabric_login = qla24xx_login_fabric,
1936 .fabric_logout = qla24xx_fabric_logout,
1937 .calc_req_entries = NULL,
1938 .build_iocbs = NULL,
1939 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1940 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1941 .read_nvram = qla24xx_read_nvram_data,
1942 .write_nvram = qla24xx_write_nvram_data,
1943 .fw_dump = qla24xx_fw_dump,
1944 .beacon_on = qla24xx_beacon_on,
1945 .beacon_off = qla24xx_beacon_off,
1946 .beacon_blink = qla24xx_beacon_blink,
1947 .read_optrom = qla24xx_read_optrom_data,
1948 .write_optrom = qla24xx_write_optrom_data,
1949 .get_flash_version = qla24xx_get_flash_version,
1950 .start_scsi = qla24xx_start_scsi,
1951 .abort_isp = qla2x00_abort_isp,
1952 .iospace_config = qla2x00_iospace_config,
1953 .initialize_adapter = qla2x00_initialize_adapter,
1956 static struct isp_operations qla25xx_isp_ops = {
1957 .pci_config = qla25xx_pci_config,
1958 .reset_chip = qla24xx_reset_chip,
1959 .chip_diag = qla24xx_chip_diag,
1960 .config_rings = qla24xx_config_rings,
1961 .reset_adapter = qla24xx_reset_adapter,
1962 .nvram_config = qla24xx_nvram_config,
1963 .update_fw_options = qla24xx_update_fw_options,
1964 .load_risc = qla24xx_load_risc,
1965 .pci_info_str = qla24xx_pci_info_str,
1966 .fw_version_str = qla24xx_fw_version_str,
1967 .intr_handler = qla24xx_intr_handler,
1968 .enable_intrs = qla24xx_enable_intrs,
1969 .disable_intrs = qla24xx_disable_intrs,
1970 .abort_command = qla24xx_abort_command,
1971 .target_reset = qla24xx_abort_target,
1972 .lun_reset = qla24xx_lun_reset,
1973 .fabric_login = qla24xx_login_fabric,
1974 .fabric_logout = qla24xx_fabric_logout,
1975 .calc_req_entries = NULL,
1976 .build_iocbs = NULL,
1977 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1978 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1979 .read_nvram = qla25xx_read_nvram_data,
1980 .write_nvram = qla25xx_write_nvram_data,
1981 .fw_dump = qla25xx_fw_dump,
1982 .beacon_on = qla24xx_beacon_on,
1983 .beacon_off = qla24xx_beacon_off,
1984 .beacon_blink = qla24xx_beacon_blink,
1985 .read_optrom = qla25xx_read_optrom_data,
1986 .write_optrom = qla24xx_write_optrom_data,
1987 .get_flash_version = qla24xx_get_flash_version,
1988 .start_scsi = qla24xx_dif_start_scsi,
1989 .abort_isp = qla2x00_abort_isp,
1990 .iospace_config = qla2x00_iospace_config,
1991 .initialize_adapter = qla2x00_initialize_adapter,
1994 static struct isp_operations qla81xx_isp_ops = {
1995 .pci_config = qla25xx_pci_config,
1996 .reset_chip = qla24xx_reset_chip,
1997 .chip_diag = qla24xx_chip_diag,
1998 .config_rings = qla24xx_config_rings,
1999 .reset_adapter = qla24xx_reset_adapter,
2000 .nvram_config = qla81xx_nvram_config,
2001 .update_fw_options = qla81xx_update_fw_options,
2002 .load_risc = qla81xx_load_risc,
2003 .pci_info_str = qla24xx_pci_info_str,
2004 .fw_version_str = qla24xx_fw_version_str,
2005 .intr_handler = qla24xx_intr_handler,
2006 .enable_intrs = qla24xx_enable_intrs,
2007 .disable_intrs = qla24xx_disable_intrs,
2008 .abort_command = qla24xx_abort_command,
2009 .target_reset = qla24xx_abort_target,
2010 .lun_reset = qla24xx_lun_reset,
2011 .fabric_login = qla24xx_login_fabric,
2012 .fabric_logout = qla24xx_fabric_logout,
2013 .calc_req_entries = NULL,
2014 .build_iocbs = NULL,
2015 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2016 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2018 .write_nvram = NULL,
2019 .fw_dump = qla81xx_fw_dump,
2020 .beacon_on = qla24xx_beacon_on,
2021 .beacon_off = qla24xx_beacon_off,
2022 .beacon_blink = qla83xx_beacon_blink,
2023 .read_optrom = qla25xx_read_optrom_data,
2024 .write_optrom = qla24xx_write_optrom_data,
2025 .get_flash_version = qla24xx_get_flash_version,
2026 .start_scsi = qla24xx_dif_start_scsi,
2027 .abort_isp = qla2x00_abort_isp,
2028 .iospace_config = qla2x00_iospace_config,
2029 .initialize_adapter = qla2x00_initialize_adapter,
2032 static struct isp_operations qla82xx_isp_ops = {
2033 .pci_config = qla82xx_pci_config,
2034 .reset_chip = qla82xx_reset_chip,
2035 .chip_diag = qla24xx_chip_diag,
2036 .config_rings = qla82xx_config_rings,
2037 .reset_adapter = qla24xx_reset_adapter,
2038 .nvram_config = qla81xx_nvram_config,
2039 .update_fw_options = qla24xx_update_fw_options,
2040 .load_risc = qla82xx_load_risc,
2041 .pci_info_str = qla24xx_pci_info_str,
2042 .fw_version_str = qla24xx_fw_version_str,
2043 .intr_handler = qla82xx_intr_handler,
2044 .enable_intrs = qla82xx_enable_intrs,
2045 .disable_intrs = qla82xx_disable_intrs,
2046 .abort_command = qla24xx_abort_command,
2047 .target_reset = qla24xx_abort_target,
2048 .lun_reset = qla24xx_lun_reset,
2049 .fabric_login = qla24xx_login_fabric,
2050 .fabric_logout = qla24xx_fabric_logout,
2051 .calc_req_entries = NULL,
2052 .build_iocbs = NULL,
2053 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2054 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2055 .read_nvram = qla24xx_read_nvram_data,
2056 .write_nvram = qla24xx_write_nvram_data,
2057 .fw_dump = qla24xx_fw_dump,
2058 .beacon_on = qla82xx_beacon_on,
2059 .beacon_off = qla82xx_beacon_off,
2060 .beacon_blink = NULL,
2061 .read_optrom = qla82xx_read_optrom_data,
2062 .write_optrom = qla82xx_write_optrom_data,
2063 .get_flash_version = qla24xx_get_flash_version,
2064 .start_scsi = qla82xx_start_scsi,
2065 .abort_isp = qla82xx_abort_isp,
2066 .iospace_config = qla82xx_iospace_config,
2067 .initialize_adapter = qla2x00_initialize_adapter,
2070 static struct isp_operations qla83xx_isp_ops = {
2071 .pci_config = qla25xx_pci_config,
2072 .reset_chip = qla24xx_reset_chip,
2073 .chip_diag = qla24xx_chip_diag,
2074 .config_rings = qla24xx_config_rings,
2075 .reset_adapter = qla24xx_reset_adapter,
2076 .nvram_config = qla81xx_nvram_config,
2077 .update_fw_options = qla81xx_update_fw_options,
2078 .load_risc = qla81xx_load_risc,
2079 .pci_info_str = qla24xx_pci_info_str,
2080 .fw_version_str = qla24xx_fw_version_str,
2081 .intr_handler = qla24xx_intr_handler,
2082 .enable_intrs = qla24xx_enable_intrs,
2083 .disable_intrs = qla24xx_disable_intrs,
2084 .abort_command = qla24xx_abort_command,
2085 .target_reset = qla24xx_abort_target,
2086 .lun_reset = qla24xx_lun_reset,
2087 .fabric_login = qla24xx_login_fabric,
2088 .fabric_logout = qla24xx_fabric_logout,
2089 .calc_req_entries = NULL,
2090 .build_iocbs = NULL,
2091 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2092 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2094 .write_nvram = NULL,
2095 .fw_dump = qla83xx_fw_dump,
2096 .beacon_on = qla24xx_beacon_on,
2097 .beacon_off = qla24xx_beacon_off,
2098 .beacon_blink = qla83xx_beacon_blink,
2099 .read_optrom = qla25xx_read_optrom_data,
2100 .write_optrom = qla24xx_write_optrom_data,
2101 .get_flash_version = qla24xx_get_flash_version,
2102 .start_scsi = qla24xx_dif_start_scsi,
2103 .abort_isp = qla2x00_abort_isp,
2104 .iospace_config = qla83xx_iospace_config,
2105 .initialize_adapter = qla2x00_initialize_adapter,
2108 static struct isp_operations qlafx00_isp_ops = {
2109 .pci_config = qlafx00_pci_config,
2110 .reset_chip = qlafx00_soft_reset,
2111 .chip_diag = qlafx00_chip_diag,
2112 .config_rings = qlafx00_config_rings,
2113 .reset_adapter = qlafx00_soft_reset,
2114 .nvram_config = NULL,
2115 .update_fw_options = NULL,
2117 .pci_info_str = qlafx00_pci_info_str,
2118 .fw_version_str = qlafx00_fw_version_str,
2119 .intr_handler = qlafx00_intr_handler,
2120 .enable_intrs = qlafx00_enable_intrs,
2121 .disable_intrs = qlafx00_disable_intrs,
2122 .abort_command = qlafx00_abort_command,
2123 .target_reset = qlafx00_abort_target,
2124 .lun_reset = qlafx00_lun_reset,
2125 .fabric_login = NULL,
2126 .fabric_logout = NULL,
2127 .calc_req_entries = NULL,
2128 .build_iocbs = NULL,
2129 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2130 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2131 .read_nvram = qla24xx_read_nvram_data,
2132 .write_nvram = qla24xx_write_nvram_data,
2134 .beacon_on = qla24xx_beacon_on,
2135 .beacon_off = qla24xx_beacon_off,
2136 .beacon_blink = NULL,
2137 .read_optrom = qla24xx_read_optrom_data,
2138 .write_optrom = qla24xx_write_optrom_data,
2139 .get_flash_version = qla24xx_get_flash_version,
2140 .start_scsi = qlafx00_start_scsi,
2141 .abort_isp = qlafx00_abort_isp,
2142 .iospace_config = qlafx00_iospace_config,
2143 .initialize_adapter = qlafx00_initialize_adapter,
2147 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2149 ha->device_type = DT_EXTENDED_IDS;
2150 switch (ha->pdev->device) {
2151 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2152 ha->device_type |= DT_ISP2100;
2153 ha->device_type &= ~DT_EXTENDED_IDS;
2154 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2156 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2157 ha->device_type |= DT_ISP2200;
2158 ha->device_type &= ~DT_EXTENDED_IDS;
2159 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2161 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2162 ha->device_type |= DT_ISP2300;
2163 ha->device_type |= DT_ZIO_SUPPORTED;
2164 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2166 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2167 ha->device_type |= DT_ISP2312;
2168 ha->device_type |= DT_ZIO_SUPPORTED;
2169 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2171 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2172 ha->device_type |= DT_ISP2322;
2173 ha->device_type |= DT_ZIO_SUPPORTED;
2174 if (ha->pdev->subsystem_vendor == 0x1028 &&
2175 ha->pdev->subsystem_device == 0x0170)
2176 ha->device_type |= DT_OEM_001;
2177 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2179 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2180 ha->device_type |= DT_ISP6312;
2181 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2183 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2184 ha->device_type |= DT_ISP6322;
2185 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2187 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2188 ha->device_type |= DT_ISP2422;
2189 ha->device_type |= DT_ZIO_SUPPORTED;
2190 ha->device_type |= DT_FWI2;
2191 ha->device_type |= DT_IIDMA;
2192 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2194 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2195 ha->device_type |= DT_ISP2432;
2196 ha->device_type |= DT_ZIO_SUPPORTED;
2197 ha->device_type |= DT_FWI2;
2198 ha->device_type |= DT_IIDMA;
2199 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2201 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2202 ha->device_type |= DT_ISP8432;
2203 ha->device_type |= DT_ZIO_SUPPORTED;
2204 ha->device_type |= DT_FWI2;
2205 ha->device_type |= DT_IIDMA;
2206 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2208 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2209 ha->device_type |= DT_ISP5422;
2210 ha->device_type |= DT_FWI2;
2211 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2213 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2214 ha->device_type |= DT_ISP5432;
2215 ha->device_type |= DT_FWI2;
2216 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2218 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2219 ha->device_type |= DT_ISP2532;
2220 ha->device_type |= DT_ZIO_SUPPORTED;
2221 ha->device_type |= DT_FWI2;
2222 ha->device_type |= DT_IIDMA;
2223 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2225 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2226 ha->device_type |= DT_ISP8001;
2227 ha->device_type |= DT_ZIO_SUPPORTED;
2228 ha->device_type |= DT_FWI2;
2229 ha->device_type |= DT_IIDMA;
2230 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2232 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2233 ha->device_type |= DT_ISP8021;
2234 ha->device_type |= DT_ZIO_SUPPORTED;
2235 ha->device_type |= DT_FWI2;
2236 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2237 /* Initialize 82XX ISP flags */
2238 qla82xx_init_flags(ha);
2240 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2241 ha->device_type |= DT_ISP2031;
2242 ha->device_type |= DT_ZIO_SUPPORTED;
2243 ha->device_type |= DT_FWI2;
2244 ha->device_type |= DT_IIDMA;
2245 ha->device_type |= DT_T10_PI;
2246 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2248 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2249 ha->device_type |= DT_ISP8031;
2250 ha->device_type |= DT_ZIO_SUPPORTED;
2251 ha->device_type |= DT_FWI2;
2252 ha->device_type |= DT_IIDMA;
2253 ha->device_type |= DT_T10_PI;
2254 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2256 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2257 ha->device_type |= DT_ISPFX00;
2262 ha->port_no = !(ha->portnum & 1);
2264 /* Get adapter physical port no from interrupt pin register. */
2265 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2267 if (ha->port_no & 1)
2268 ha->flags.port0 = 1;
2270 ha->flags.port0 = 0;
2271 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2272 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2273 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
2277 qla2xxx_scan_start(struct Scsi_Host *shost)
2279 scsi_qla_host_t *vha = shost_priv(shost);
2281 if (vha->hw->flags.running_gold_fw)
2284 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2285 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2286 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2287 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2291 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2293 scsi_qla_host_t *vha = shost_priv(shost);
2297 if (time > vha->hw->loop_reset_delay * HZ)
2300 return atomic_read(&vha->loop_state) == LOOP_READY;
2304 * PCI driver interface
2307 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2310 struct Scsi_Host *host;
2311 scsi_qla_host_t *base_vha = NULL;
2312 struct qla_hw_data *ha;
2314 char fw_str[30], wq_name[30];
2315 struct scsi_host_template *sht;
2316 int bars, mem_only = 0;
2317 uint16_t req_length = 0, rsp_length = 0;
2318 struct req_que *req = NULL;
2319 struct rsp_que *rsp = NULL;
2321 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2322 sht = &qla2xxx_driver_template;
2323 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2324 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2325 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2326 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2327 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2328 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2329 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2330 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2331 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2332 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2333 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001) {
2334 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2336 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2337 "Mem only adapter.\n");
2339 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2340 "Bars=%d.\n", bars);
2343 if (pci_enable_device_mem(pdev))
2346 if (pci_enable_device(pdev))
2350 /* This may fail but that's ok */
2351 pci_enable_pcie_error_reporting(pdev);
2353 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2355 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2356 "Unable to allocate memory for ha.\n");
2359 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2360 "Memory allocated for ha=%p.\n", ha);
2362 ha->tgt.enable_class_2 = ql2xenableclass2;
2364 /* Clear our data area */
2366 ha->mem_only = mem_only;
2367 spin_lock_init(&ha->hardware_lock);
2368 spin_lock_init(&ha->vport_slock);
2369 mutex_init(&ha->selflogin_lock);
2371 /* Set ISP-type information. */
2372 qla2x00_set_isp_flags(ha);
2374 /* Set EEH reset type to fundamental if required by hba */
2375 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2377 pdev->needs_freset = 1;
2379 ha->prev_topology = 0;
2380 ha->init_cb_size = sizeof(init_cb_t);
2381 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2382 ha->optrom_size = OPTROM_SIZE_2300;
2383 ha->cfg_lun_q_depth = ql2xmaxqdepth;
2385 /* Assign ISP specific operations. */
2386 if (IS_QLA2100(ha)) {
2387 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2388 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2389 req_length = REQUEST_ENTRY_CNT_2100;
2390 rsp_length = RESPONSE_ENTRY_CNT_2100;
2391 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2392 ha->gid_list_info_size = 4;
2393 ha->flash_conf_off = ~0;
2394 ha->flash_data_off = ~0;
2395 ha->nvram_conf_off = ~0;
2396 ha->nvram_data_off = ~0;
2397 ha->isp_ops = &qla2100_isp_ops;
2398 } else if (IS_QLA2200(ha)) {
2399 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2400 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2401 req_length = REQUEST_ENTRY_CNT_2200;
2402 rsp_length = RESPONSE_ENTRY_CNT_2100;
2403 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2404 ha->gid_list_info_size = 4;
2405 ha->flash_conf_off = ~0;
2406 ha->flash_data_off = ~0;
2407 ha->nvram_conf_off = ~0;
2408 ha->nvram_data_off = ~0;
2409 ha->isp_ops = &qla2100_isp_ops;
2410 } else if (IS_QLA23XX(ha)) {
2411 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2412 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2413 req_length = REQUEST_ENTRY_CNT_2200;
2414 rsp_length = RESPONSE_ENTRY_CNT_2300;
2415 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2416 ha->gid_list_info_size = 6;
2417 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2418 ha->optrom_size = OPTROM_SIZE_2322;
2419 ha->flash_conf_off = ~0;
2420 ha->flash_data_off = ~0;
2421 ha->nvram_conf_off = ~0;
2422 ha->nvram_data_off = ~0;
2423 ha->isp_ops = &qla2300_isp_ops;
2424 } else if (IS_QLA24XX_TYPE(ha)) {
2425 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2426 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2427 req_length = REQUEST_ENTRY_CNT_24XX;
2428 rsp_length = RESPONSE_ENTRY_CNT_2300;
2429 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2430 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2431 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2432 ha->gid_list_info_size = 8;
2433 ha->optrom_size = OPTROM_SIZE_24XX;
2434 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2435 ha->isp_ops = &qla24xx_isp_ops;
2436 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2437 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2438 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2439 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2440 } else if (IS_QLA25XX(ha)) {
2441 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2442 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2443 req_length = REQUEST_ENTRY_CNT_24XX;
2444 rsp_length = RESPONSE_ENTRY_CNT_2300;
2445 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2446 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2447 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2448 ha->gid_list_info_size = 8;
2449 ha->optrom_size = OPTROM_SIZE_25XX;
2450 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2451 ha->isp_ops = &qla25xx_isp_ops;
2452 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2453 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2454 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2455 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2456 } else if (IS_QLA81XX(ha)) {
2457 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2458 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2459 req_length = REQUEST_ENTRY_CNT_24XX;
2460 rsp_length = RESPONSE_ENTRY_CNT_2300;
2461 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2462 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2463 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2464 ha->gid_list_info_size = 8;
2465 ha->optrom_size = OPTROM_SIZE_81XX;
2466 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2467 ha->isp_ops = &qla81xx_isp_ops;
2468 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2469 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2470 ha->nvram_conf_off = ~0;
2471 ha->nvram_data_off = ~0;
2472 } else if (IS_QLA82XX(ha)) {
2473 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2474 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2475 req_length = REQUEST_ENTRY_CNT_82XX;
2476 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2477 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2478 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2479 ha->gid_list_info_size = 8;
2480 ha->optrom_size = OPTROM_SIZE_82XX;
2481 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2482 ha->isp_ops = &qla82xx_isp_ops;
2483 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2484 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2485 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2486 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2487 } else if (IS_QLA83XX(ha)) {
2488 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2489 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2490 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2491 req_length = REQUEST_ENTRY_CNT_24XX;
2492 rsp_length = RESPONSE_ENTRY_CNT_2300;
2493 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2494 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2495 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2496 ha->gid_list_info_size = 8;
2497 ha->optrom_size = OPTROM_SIZE_83XX;
2498 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2499 ha->isp_ops = &qla83xx_isp_ops;
2500 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2501 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2502 ha->nvram_conf_off = ~0;
2503 ha->nvram_data_off = ~0;
2504 } else if (IS_QLAFX00(ha)) {
2505 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2506 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2507 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2508 req_length = REQUEST_ENTRY_CNT_FX00;
2509 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2510 ha->init_cb_size = sizeof(struct init_cb_fx);
2511 ha->isp_ops = &qlafx00_isp_ops;
2512 ha->port_down_retry_count = 30; /* default value */
2513 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2514 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2515 ha->mr.fw_hbt_en = 1;
2518 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2519 "mbx_count=%d, req_length=%d, "
2520 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2521 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2522 "max_fibre_devices=%d.\n",
2523 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2524 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2525 ha->nvram_npiv_size, ha->max_fibre_devices);
2526 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2527 "isp_ops=%p, flash_conf_off=%d, "
2528 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2529 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2530 ha->nvram_conf_off, ha->nvram_data_off);
2532 /* Configure PCI I/O space */
2533 ret = ha->isp_ops->iospace_config(ha);
2535 goto iospace_config_failed;
2537 ql_log_pci(ql_log_info, pdev, 0x001d,
2538 "Found an ISP%04X irq %d iobase 0x%p.\n",
2539 pdev->device, pdev->irq, ha->iobase);
2540 mutex_init(&ha->vport_lock);
2541 init_completion(&ha->mbx_cmd_comp);
2542 complete(&ha->mbx_cmd_comp);
2543 init_completion(&ha->mbx_intr_comp);
2544 init_completion(&ha->dcbx_comp);
2545 init_completion(&ha->lb_portup_comp);
2547 set_bit(0, (unsigned long *) ha->vp_idx_map);
2549 qla2x00_config_dma_addressing(ha);
2550 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2551 "64 Bit addressing is %s.\n",
2552 ha->flags.enable_64bit_addressing ? "enable" :
2554 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
2556 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2557 "Failed to allocate memory for adapter, aborting.\n");
2559 goto probe_hw_failed;
2562 req->max_q_depth = MAX_Q_DEPTH;
2563 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
2564 req->max_q_depth = ql2xmaxqdepth;
2567 base_vha = qla2x00_create_host(sht, ha);
2570 qla2x00_mem_free(ha);
2571 qla2x00_free_req_que(ha, req);
2572 qla2x00_free_rsp_que(ha, rsp);
2573 goto probe_hw_failed;
2576 pci_set_drvdata(pdev, base_vha);
2578 host = base_vha->host;
2579 base_vha->req = req;
2581 host->can_queue = 1024;
2583 host->can_queue = req->length + 128;
2584 if (IS_QLA2XXX_MIDTYPE(ha))
2585 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
2587 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2590 /* Setup fcport template structure. */
2591 ha->mr.fcport.vha = base_vha;
2592 ha->mr.fcport.port_type = FCT_UNKNOWN;
2593 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2594 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2595 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2596 ha->mr.fcport.scan_state = 1;
2598 /* Set the SG table size based on ISP type */
2599 if (!IS_FWI2_CAPABLE(ha)) {
2601 host->sg_tablesize = 32;
2603 if (!IS_QLA82XX(ha))
2604 host->sg_tablesize = QLA_SG_ALL;
2606 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2607 "can_queue=%d, req=%p, "
2608 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2609 host->can_queue, base_vha->req,
2610 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2611 host->max_id = ha->max_fibre_devices;
2612 host->cmd_per_lun = 3;
2613 host->unique_id = host->host_no;
2614 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
2615 host->max_cmd_len = 32;
2617 host->max_cmd_len = MAX_CMDSZ;
2618 host->max_channel = MAX_BUSES - 1;
2619 host->max_lun = ql2xmaxlun;
2620 host->transportt = qla2xxx_transport_template;
2621 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
2623 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2624 "max_id=%d this_id=%d "
2625 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2626 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
2627 host->this_id, host->cmd_per_lun, host->unique_id,
2628 host->max_cmd_len, host->max_channel, host->max_lun,
2629 host->transportt, sht->vendor_id);
2632 /* Alloc arrays of request and response ring ptrs */
2633 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2634 ql_log(ql_log_fatal, base_vha, 0x003d,
2635 "Failed to allocate memory for queue pointers..."
2637 goto probe_init_failed;
2640 qlt_probe_one_stage1(base_vha, ha);
2642 /* Set up the irqs */
2643 ret = qla2x00_request_irqs(ha, rsp);
2645 goto probe_init_failed;
2647 pci_save_state(pdev);
2649 /* Assign back pointers */
2653 if (IS_QLAFX00(ha)) {
2654 ha->rsp_q_map[0] = rsp;
2655 ha->req_q_map[0] = req;
2656 set_bit(0, ha->req_qid_map);
2657 set_bit(0, ha->rsp_qid_map);
2660 /* FWI2-capable only. */
2661 req->req_q_in = &ha->iobase->isp24.req_q_in;
2662 req->req_q_out = &ha->iobase->isp24.req_q_out;
2663 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2664 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
2665 if (ha->mqenable || IS_QLA83XX(ha)) {
2666 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2667 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2668 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2669 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
2672 if (IS_QLAFX00(ha)) {
2673 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2674 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2675 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2676 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2679 if (IS_QLA82XX(ha)) {
2680 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2681 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2682 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2685 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2686 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2687 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2688 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2689 "req->req_q_in=%p req->req_q_out=%p "
2690 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2691 req->req_q_in, req->req_q_out,
2692 rsp->rsp_q_in, rsp->rsp_q_out);
2693 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2694 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2695 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2696 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2697 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2698 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
2700 if (ha->isp_ops->initialize_adapter(base_vha)) {
2701 ql_log(ql_log_fatal, base_vha, 0x00d6,
2702 "Failed to initialize adapter - Adapter flags %x.\n",
2703 base_vha->device_flags);
2705 if (IS_QLA82XX(ha)) {
2706 qla82xx_idc_lock(ha);
2707 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2708 QLA8XXX_DEV_FAILED);
2709 qla82xx_idc_unlock(ha);
2710 ql_log(ql_log_fatal, base_vha, 0x00d7,
2711 "HW State: FAILED.\n");
2719 if (qla25xx_setup_mode(base_vha)) {
2720 ql_log(ql_log_warn, base_vha, 0x00ec,
2721 "Failed to create queues, falling back to single queue mode.\n");
2726 if (ha->flags.running_gold_fw)
2730 * Startup the kernel thread for this host adapter
2732 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
2733 "%s_dpc", base_vha->host_str);
2734 if (IS_ERR(ha->dpc_thread)) {
2735 ql_log(ql_log_fatal, base_vha, 0x00ed,
2736 "Failed to start DPC thread.\n");
2737 ret = PTR_ERR(ha->dpc_thread);
2740 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2741 "DPC thread started successfully.\n");
2744 * If we're not coming up in initiator mode, we might sit for
2745 * a while without waking up the dpc thread, which leads to a
2746 * stuck process warning. So just kick the dpc once here and
2747 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2749 qla2xxx_wake_dpc(base_vha);
2751 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2752 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2753 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2754 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2756 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2757 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2758 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2759 INIT_WORK(&ha->idc_state_handler,
2760 qla83xx_idc_state_handler_work);
2761 INIT_WORK(&ha->nic_core_unrecoverable,
2762 qla83xx_nic_core_unrecoverable_work);
2766 list_add_tail(&base_vha->list, &ha->vp_list);
2767 base_vha->host->irq = ha->pdev->irq;
2769 /* Initialized the timer */
2770 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
2771 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2772 "Started qla2x00_timer with "
2773 "interval=%d.\n", WATCH_INTERVAL);
2774 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2775 "Detected hba at address=%p.\n",
2778 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
2779 if (ha->fw_attributes & BIT_4) {
2780 int prot = 0, guard;
2781 base_vha->flags.difdix_supported = 1;
2782 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2783 "Registering for DIF/DIX type 1 and 3 protection.\n");
2784 if (ql2xenabledif == 1)
2785 prot = SHOST_DIX_TYPE0_PROTECTION;
2786 scsi_host_set_prot(host,
2787 prot | SHOST_DIF_TYPE1_PROTECTION
2788 | SHOST_DIF_TYPE2_PROTECTION
2789 | SHOST_DIF_TYPE3_PROTECTION
2790 | SHOST_DIX_TYPE1_PROTECTION
2791 | SHOST_DIX_TYPE2_PROTECTION
2792 | SHOST_DIX_TYPE3_PROTECTION);
2794 guard = SHOST_DIX_GUARD_CRC;
2796 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2797 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2798 guard |= SHOST_DIX_GUARD_IP;
2800 scsi_host_set_guard(host, guard);
2802 base_vha->flags.difdix_supported = 0;
2805 ha->isp_ops->enable_intrs(ha);
2807 ret = scsi_add_host(host, &pdev->dev);
2811 base_vha->flags.init_done = 1;
2812 base_vha->flags.online = 1;
2814 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2815 "Init done and hba is online.\n");
2817 if (qla_ini_mode_enabled(base_vha))
2818 scsi_scan_host(host);
2820 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2821 "skipping scsi_scan_host() for non-initiator port\n");
2823 qla2x00_alloc_sysfs_attr(base_vha);
2825 if (IS_QLAFX00(ha)) {
2826 ret = qlafx00_fx_disc(base_vha,
2827 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2829 ret = qlafx00_fx_disc(base_vha,
2830 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2832 /* Register system information */
2833 ret = qlafx00_fx_disc(base_vha,
2834 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2837 qla2x00_init_host_attr(base_vha);
2839 qla2x00_dfs_setup(base_vha);
2841 ql_log(ql_log_info, base_vha, 0x00fb,
2842 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
2843 ql_log(ql_log_info, base_vha, 0x00fc,
2844 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2845 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2846 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2848 ha->isp_ops->fw_version_str(base_vha, fw_str));
2850 qlt_add_target(ha, base_vha);
2855 qla2x00_free_req_que(ha, req);
2856 ha->req_q_map[0] = NULL;
2857 clear_bit(0, ha->req_qid_map);
2858 qla2x00_free_rsp_que(ha, rsp);
2859 ha->rsp_q_map[0] = NULL;
2860 clear_bit(0, ha->rsp_qid_map);
2861 ha->max_req_queues = ha->max_rsp_queues = 0;
2864 if (base_vha->timer_active)
2865 qla2x00_stop_timer(base_vha);
2866 base_vha->flags.online = 0;
2867 if (ha->dpc_thread) {
2868 struct task_struct *t = ha->dpc_thread;
2870 ha->dpc_thread = NULL;
2874 qla2x00_free_device(base_vha);
2876 scsi_host_put(base_vha->host);
2879 if (IS_QLA82XX(ha)) {
2880 qla82xx_idc_lock(ha);
2881 qla82xx_clear_drv_active(ha);
2882 qla82xx_idc_unlock(ha);
2884 iospace_config_failed:
2885 if (IS_QLA82XX(ha)) {
2886 if (!ha->nx_pcibase)
2887 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2889 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2892 iounmap(ha->iobase);
2894 iounmap(ha->cregbase);
2896 pci_release_selected_regions(ha->pdev, ha->bars);
2901 pci_disable_device(pdev);
2906 qla2x00_stop_dpc_thread(scsi_qla_host_t *vha)
2908 struct qla_hw_data *ha = vha->hw;
2909 struct task_struct *t = ha->dpc_thread;
2911 if (ha->dpc_thread == NULL)
2914 * qla2xxx_wake_dpc checks for ->dpc_thread
2915 * so we need to zero it out.
2917 ha->dpc_thread = NULL;
2922 qla2x00_shutdown(struct pci_dev *pdev)
2924 scsi_qla_host_t *vha;
2925 struct qla_hw_data *ha;
2927 if (!atomic_read(&pdev->enable_cnt))
2930 vha = pci_get_drvdata(pdev);
2933 /* Turn-off FCE trace */
2934 if (ha->flags.fce_enabled) {
2935 qla2x00_disable_fce_trace(vha, NULL, NULL);
2936 ha->flags.fce_enabled = 0;
2939 /* Turn-off EFT trace */
2941 qla2x00_disable_eft_trace(vha);
2943 /* Stop currently executing firmware. */
2944 qla2x00_try_to_stop_firmware(vha);
2946 /* Turn adapter off line */
2947 vha->flags.online = 0;
2949 /* turn-off interrupts on the card */
2950 if (ha->interrupts_on) {
2951 vha->flags.init_done = 0;
2952 ha->isp_ops->disable_intrs(ha);
2955 qla2x00_free_irqs(vha);
2957 qla2x00_free_fw_dump(ha);
2961 qla2x00_remove_one(struct pci_dev *pdev)
2963 scsi_qla_host_t *base_vha, *vha;
2964 struct qla_hw_data *ha;
2965 unsigned long flags;
2968 * If the PCI device is disabled that means that probe failed and any
2969 * resources should be have cleaned up on probe exit.
2971 if (!atomic_read(&pdev->enable_cnt))
2974 base_vha = pci_get_drvdata(pdev);
2977 ha->flags.host_shutting_down = 1;
2979 set_bit(UNLOADING, &base_vha->dpc_flags);
2980 mutex_lock(&ha->vport_lock);
2981 while (ha->cur_vport_count) {
2982 spin_lock_irqsave(&ha->vport_slock, flags);
2984 BUG_ON(base_vha->list.next == &ha->vp_list);
2985 /* This assumes first entry in ha->vp_list is always base vha */
2986 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2987 scsi_host_get(vha->host);
2989 spin_unlock_irqrestore(&ha->vport_slock, flags);
2990 mutex_unlock(&ha->vport_lock);
2992 fc_vport_terminate(vha->fc_vport);
2993 scsi_host_put(vha->host);
2995 mutex_lock(&ha->vport_lock);
2997 mutex_unlock(&ha->vport_lock);
2999 if (IS_QLA8031(ha)) {
3000 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3001 "Clearing fcoe driver presence.\n");
3002 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3003 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3004 "Error while clearing DRV-Presence.\n");
3007 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3009 qla2x00_dfs_remove(base_vha);
3011 qla84xx_put_chip(base_vha);
3014 if (base_vha->timer_active)
3015 qla2x00_stop_timer(base_vha);
3017 base_vha->flags.online = 0;
3019 /* Flush the work queue and remove it */
3021 flush_workqueue(ha->wq);
3022 destroy_workqueue(ha->wq);
3026 /* Cancel all work and destroy DPC workqueues */
3027 if (ha->dpc_lp_wq) {
3028 cancel_work_sync(&ha->idc_aen);
3029 destroy_workqueue(ha->dpc_lp_wq);
3030 ha->dpc_lp_wq = NULL;
3033 if (ha->dpc_hp_wq) {
3034 cancel_work_sync(&ha->nic_core_reset);
3035 cancel_work_sync(&ha->idc_state_handler);
3036 cancel_work_sync(&ha->nic_core_unrecoverable);
3037 destroy_workqueue(ha->dpc_hp_wq);
3038 ha->dpc_hp_wq = NULL;
3041 /* Kill the kernel thread for this host */
3042 if (ha->dpc_thread) {
3043 struct task_struct *t = ha->dpc_thread;
3046 * qla2xxx_wake_dpc checks for ->dpc_thread
3047 * so we need to zero it out.
3049 ha->dpc_thread = NULL;
3052 qlt_remove_target(ha, base_vha);
3054 qla2x00_free_sysfs_attr(base_vha);
3056 fc_remove_host(base_vha->host);
3058 scsi_remove_host(base_vha->host);
3060 qla2x00_free_device(base_vha);
3062 scsi_host_put(base_vha->host);
3064 if (IS_QLA82XX(ha)) {
3065 qla82xx_idc_lock(ha);
3066 qla82xx_clear_drv_active(ha);
3067 qla82xx_idc_unlock(ha);
3069 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
3071 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
3074 iounmap(ha->iobase);
3077 iounmap(ha->cregbase);
3080 iounmap(ha->mqiobase);
3082 if (IS_QLA83XX(ha) && ha->msixbase)
3083 iounmap(ha->msixbase);
3086 pci_release_selected_regions(ha->pdev, ha->bars);
3090 pci_disable_pcie_error_reporting(pdev);
3092 pci_disable_device(pdev);
3093 pci_set_drvdata(pdev, NULL);
3097 qla2x00_free_device(scsi_qla_host_t *vha)
3099 struct qla_hw_data *ha = vha->hw;
3101 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3104 if (vha->timer_active)
3105 qla2x00_stop_timer(vha);
3107 qla2x00_stop_dpc_thread(vha);
3109 qla25xx_delete_queues(vha);
3110 if (ha->flags.fce_enabled)
3111 qla2x00_disable_fce_trace(vha, NULL, NULL);
3114 qla2x00_disable_eft_trace(vha);
3116 /* Stop currently executing firmware. */
3117 qla2x00_try_to_stop_firmware(vha);
3119 vha->flags.online = 0;
3121 /* turn-off interrupts on the card */
3122 if (ha->interrupts_on) {
3123 vha->flags.init_done = 0;
3124 ha->isp_ops->disable_intrs(ha);
3127 qla2x00_free_irqs(vha);
3129 qla2x00_free_fcports(vha);
3131 qla2x00_mem_free(ha);
3133 qla82xx_md_free(vha);
3135 qla2x00_free_queues(ha);
3138 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3140 fc_port_t *fcport, *tfcport;
3142 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3143 list_del(&fcport->list);
3144 qla2x00_clear_loop_id(fcport);
3151 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3154 struct fc_rport *rport;
3155 scsi_qla_host_t *base_vha;
3156 unsigned long flags;
3161 rport = fcport->rport;
3163 base_vha = pci_get_drvdata(vha->hw->pdev);
3164 spin_lock_irqsave(vha->host->host_lock, flags);
3165 fcport->drport = rport;
3166 spin_unlock_irqrestore(vha->host->host_lock, flags);
3167 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3168 qla2xxx_wake_dpc(base_vha);
3170 fc_remote_port_delete(rport);
3171 qlt_fc_port_deleted(vha, fcport);
3176 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3178 * Input: ha = adapter block pointer. fcport = port structure pointer.
3184 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3185 int do_login, int defer)
3187 if (IS_QLAFX00(vha->hw)) {
3188 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3189 qla2x00_schedule_rport_del(vha, fcport, defer);
3193 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3194 vha->vp_idx == fcport->vha->vp_idx) {
3195 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3196 qla2x00_schedule_rport_del(vha, fcport, defer);
3199 * We may need to retry the login, so don't change the state of the
3200 * port but do the retries.
3202 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3203 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3208 if (fcport->login_retry == 0) {
3209 fcport->login_retry = vha->hw->login_retry_count;
3210 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3212 ql_dbg(ql_dbg_disc, vha, 0x2067,
3214 "%02x%02x%02x%02x%02x%02x%02x%02x, "
3215 "id = 0x%04x retry cnt=%d.\n",
3216 fcport->port_name[0], fcport->port_name[1],
3217 fcport->port_name[2], fcport->port_name[3],
3218 fcport->port_name[4], fcport->port_name[5],
3219 fcport->port_name[6], fcport->port_name[7],
3220 fcport->loop_id, fcport->login_retry);
3225 * qla2x00_mark_all_devices_lost
3226 * Updates fcport state when device goes offline.
3229 * ha = adapter block pointer.
3230 * fcport = port structure pointer.
3238 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3242 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3243 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3247 * No point in marking the device as lost, if the device is
3250 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3252 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3253 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3255 qla2x00_schedule_rport_del(vha, fcport, defer);
3256 else if (vha->vp_idx == fcport->vha->vp_idx)
3257 qla2x00_schedule_rport_del(vha, fcport, defer);
3264 * Allocates adapter memory.
3271 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3272 struct req_que **req, struct rsp_que **rsp)
3276 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3277 &ha->init_cb_dma, GFP_KERNEL);
3281 if (qlt_mem_alloc(ha) < 0)
3282 goto fail_free_init_cb;
3284 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3285 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3287 goto fail_free_tgt_mem;
3289 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3290 if (!ha->srb_mempool)
3291 goto fail_free_gid_list;
3293 if (IS_QLA82XX(ha)) {
3294 /* Allocate cache for CT6 Ctx. */
3296 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3297 sizeof(struct ct6_dsd), 0,
3298 SLAB_HWCACHE_ALIGN, NULL);
3300 goto fail_free_gid_list;
3302 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3304 if (!ha->ctx_mempool)
3305 goto fail_free_srb_mempool;
3306 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3307 "ctx_cachep=%p ctx_mempool=%p.\n",
3308 ctx_cachep, ha->ctx_mempool);
3311 /* Get memory for cached NVRAM */
3312 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3314 goto fail_free_ctx_mempool;
3316 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3318 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3319 DMA_POOL_SIZE, 8, 0);
3320 if (!ha->s_dma_pool)
3321 goto fail_free_nvram;
3323 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3324 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3325 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3327 if (IS_QLA82XX(ha) || ql2xenabledif) {
3328 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3329 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3330 if (!ha->dl_dma_pool) {
3331 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3332 "Failed to allocate memory for dl_dma_pool.\n");
3333 goto fail_s_dma_pool;
3336 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3337 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3338 if (!ha->fcp_cmnd_dma_pool) {
3339 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3340 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
3341 goto fail_dl_dma_pool;
3343 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3344 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3345 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
3348 /* Allocate memory for SNS commands */
3349 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3350 /* Get consistent memory allocated for SNS commands */
3351 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
3352 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
3355 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
3356 "sns_cmd: %p.\n", ha->sns_cmd);
3358 /* Get consistent memory allocated for MS IOCB */
3359 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3363 /* Get consistent memory allocated for CT SNS commands */
3364 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
3365 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
3367 goto fail_free_ms_iocb;
3368 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3369 "ms_iocb=%p ct_sns=%p.\n",
3370 ha->ms_iocb, ha->ct_sns);
3373 /* Allocate memory for request ring */
3374 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3376 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3377 "Failed to allocate memory for req.\n");
3380 (*req)->length = req_len;
3381 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3382 ((*req)->length + 1) * sizeof(request_t),
3383 &(*req)->dma, GFP_KERNEL);
3384 if (!(*req)->ring) {
3385 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3386 "Failed to allocate memory for req_ring.\n");
3389 /* Allocate memory for response ring */
3390 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3392 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3393 "Failed to allocate memory for rsp.\n");
3397 (*rsp)->length = rsp_len;
3398 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3399 ((*rsp)->length + 1) * sizeof(response_t),
3400 &(*rsp)->dma, GFP_KERNEL);
3401 if (!(*rsp)->ring) {
3402 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3403 "Failed to allocate memory for rsp_ring.\n");
3408 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3409 "req=%p req->length=%d req->ring=%p rsp=%p "
3410 "rsp->length=%d rsp->ring=%p.\n",
3411 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3413 /* Allocate memory for NVRAM data for vports */
3414 if (ha->nvram_npiv_size) {
3415 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
3416 ha->nvram_npiv_size, GFP_KERNEL);
3417 if (!ha->npiv_info) {
3418 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3419 "Failed to allocate memory for npiv_info.\n");
3420 goto fail_npiv_info;
3423 ha->npiv_info = NULL;
3425 /* Get consistent memory allocated for EX-INIT-CB. */
3426 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
3427 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3428 &ha->ex_init_cb_dma);
3429 if (!ha->ex_init_cb)
3430 goto fail_ex_init_cb;
3431 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3432 "ex_init_cb=%p.\n", ha->ex_init_cb);
3435 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3437 /* Get consistent memory allocated for Async Port-Database. */
3438 if (!IS_FWI2_CAPABLE(ha)) {
3439 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3443 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3444 "async_pd=%p.\n", ha->async_pd);
3447 INIT_LIST_HEAD(&ha->vp_list);
3449 /* Allocate memory for our loop_id bitmap */
3450 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3452 if (!ha->loop_id_map)
3455 qla2x00_set_reserved_loop_ids(ha);
3456 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3457 "loop_id_map=%p. \n", ha->loop_id_map);
3463 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
3465 kfree(ha->npiv_info);
3467 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3468 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3469 (*rsp)->ring = NULL;
3474 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3475 sizeof(request_t), (*req)->ring, (*req)->dma);
3476 (*req)->ring = NULL;
3481 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3482 ha->ct_sns, ha->ct_sns_dma);
3486 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3488 ha->ms_iocb_dma = 0;
3490 if (IS_QLA82XX(ha) || ql2xenabledif) {
3491 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3492 ha->fcp_cmnd_dma_pool = NULL;
3495 if (IS_QLA82XX(ha) || ql2xenabledif) {
3496 dma_pool_destroy(ha->dl_dma_pool);
3497 ha->dl_dma_pool = NULL;
3500 dma_pool_destroy(ha->s_dma_pool);
3501 ha->s_dma_pool = NULL;
3505 fail_free_ctx_mempool:
3506 mempool_destroy(ha->ctx_mempool);
3507 ha->ctx_mempool = NULL;
3508 fail_free_srb_mempool:
3509 mempool_destroy(ha->srb_mempool);
3510 ha->srb_mempool = NULL;
3512 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3515 ha->gid_list = NULL;
3516 ha->gid_list_dma = 0;
3520 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3523 ha->init_cb_dma = 0;
3525 ql_log(ql_log_fatal, NULL, 0x0030,
3526 "Memory allocation failure.\n");
3531 * qla2x00_free_fw_dump
3532 * Frees fw dump stuff.
3535 * ha = adapter block pointer.
3538 qla2x00_free_fw_dump(struct qla_hw_data *ha)
3541 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
3546 dma_free_coherent(&ha->pdev->dev,
3547 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
3556 ha->fw_dump_reading = 0;
3561 * Frees all adapter allocated memory.
3564 * ha = adapter block pointer.
3567 qla2x00_mem_free(struct qla_hw_data *ha)
3569 qla2x00_free_fw_dump(ha);
3572 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3575 if (ha->srb_mempool)
3576 mempool_destroy(ha->srb_mempool);
3579 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3580 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3583 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3584 ha->xgmac_data, ha->xgmac_data_dma);
3587 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3588 ha->sns_cmd, ha->sns_cmd_dma);
3591 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3592 ha->ct_sns, ha->ct_sns_dma);
3595 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3598 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3601 dma_pool_free(ha->s_dma_pool,
3602 ha->ex_init_cb, ha->ex_init_cb_dma);
3605 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3608 dma_pool_destroy(ha->s_dma_pool);
3611 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3612 ha->gid_list, ha->gid_list_dma);
3614 if (IS_QLA82XX(ha)) {
3615 if (!list_empty(&ha->gbl_dsd_list)) {
3616 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3618 /* clean up allocated prev pool */
3619 list_for_each_entry_safe(dsd_ptr,
3620 tdsd_ptr, &ha->gbl_dsd_list, list) {
3621 dma_pool_free(ha->dl_dma_pool,
3622 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3623 list_del(&dsd_ptr->list);
3629 if (ha->dl_dma_pool)
3630 dma_pool_destroy(ha->dl_dma_pool);
3632 if (ha->fcp_cmnd_dma_pool)
3633 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3635 if (ha->ctx_mempool)
3636 mempool_destroy(ha->ctx_mempool);
3641 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
3642 ha->init_cb, ha->init_cb_dma);
3643 vfree(ha->optrom_buffer);
3645 kfree(ha->npiv_info);
3647 kfree(ha->loop_id_map);
3649 ha->srb_mempool = NULL;
3650 ha->ctx_mempool = NULL;
3652 ha->sns_cmd_dma = 0;
3656 ha->ms_iocb_dma = 0;
3658 ha->init_cb_dma = 0;
3659 ha->ex_init_cb = NULL;
3660 ha->ex_init_cb_dma = 0;
3661 ha->async_pd = NULL;
3662 ha->async_pd_dma = 0;
3664 ha->s_dma_pool = NULL;
3665 ha->dl_dma_pool = NULL;
3666 ha->fcp_cmnd_dma_pool = NULL;
3668 ha->gid_list = NULL;
3669 ha->gid_list_dma = 0;
3671 ha->tgt.atio_ring = NULL;
3672 ha->tgt.atio_dma = 0;
3673 ha->tgt.tgt_vp_map = NULL;
3676 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3677 struct qla_hw_data *ha)
3679 struct Scsi_Host *host;
3680 struct scsi_qla_host *vha = NULL;
3682 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3684 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3685 "Failed to allocate host from the scsi layer, aborting.\n");
3689 /* Clear our data area */
3690 vha = shost_priv(host);
3691 memset(vha, 0, sizeof(scsi_qla_host_t));
3694 vha->host_no = host->host_no;
3697 INIT_LIST_HEAD(&vha->vp_fcports);
3698 INIT_LIST_HEAD(&vha->work_list);
3699 INIT_LIST_HEAD(&vha->list);
3701 spin_lock_init(&vha->work_lock);
3703 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
3704 ql_dbg(ql_dbg_init, vha, 0x0041,
3705 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3706 vha->host, vha->hw, vha,
3707 dev_name(&(ha->pdev->dev)));
3715 static struct qla_work_evt *
3716 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
3718 struct qla_work_evt *e;
3721 QLA_VHA_MARK_BUSY(vha, bail);
3725 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
3727 QLA_VHA_MARK_NOT_BUSY(vha);
3731 INIT_LIST_HEAD(&e->list);
3733 e->flags = QLA_EVT_FLAG_FREE;
3738 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
3740 unsigned long flags;
3742 spin_lock_irqsave(&vha->work_lock, flags);
3743 list_add_tail(&e->list, &vha->work_list);
3744 spin_unlock_irqrestore(&vha->work_lock, flags);
3745 qla2xxx_wake_dpc(vha);
3751 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
3754 struct qla_work_evt *e;
3756 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
3758 return QLA_FUNCTION_FAILED;
3760 e->u.aen.code = code;
3761 e->u.aen.data = data;
3762 return qla2x00_post_work(vha, e);
3766 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3768 struct qla_work_evt *e;
3770 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
3772 return QLA_FUNCTION_FAILED;
3774 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3775 return qla2x00_post_work(vha, e);
3778 #define qla2x00_post_async_work(name, type) \
3779 int qla2x00_post_async_##name##_work( \
3780 struct scsi_qla_host *vha, \
3781 fc_port_t *fcport, uint16_t *data) \
3783 struct qla_work_evt *e; \
3785 e = qla2x00_alloc_work(vha, type); \
3787 return QLA_FUNCTION_FAILED; \
3789 e->u.logio.fcport = fcport; \
3791 e->u.logio.data[0] = data[0]; \
3792 e->u.logio.data[1] = data[1]; \
3794 return qla2x00_post_work(vha, e); \
3797 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3798 qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3799 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3800 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
3801 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3802 qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
3805 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3807 struct qla_work_evt *e;
3809 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3811 return QLA_FUNCTION_FAILED;
3813 e->u.uevent.code = code;
3814 return qla2x00_post_work(vha, e);
3818 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3820 char event_string[40];
3821 char *envp[] = { event_string, NULL };
3824 case QLA_UEVENT_CODE_FW_DUMP:
3825 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3832 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3836 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3837 uint32_t *data, int cnt)
3839 struct qla_work_evt *e;
3841 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3843 return QLA_FUNCTION_FAILED;
3845 e->u.aenfx.evtcode = evtcode;
3846 e->u.aenfx.count = cnt;
3847 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3848 return qla2x00_post_work(vha, e);
3852 qla2x00_do_work(struct scsi_qla_host *vha)
3854 struct qla_work_evt *e, *tmp;
3855 unsigned long flags;
3858 spin_lock_irqsave(&vha->work_lock, flags);
3859 list_splice_init(&vha->work_list, &work);
3860 spin_unlock_irqrestore(&vha->work_lock, flags);
3862 list_for_each_entry_safe(e, tmp, &work, list) {
3863 list_del_init(&e->list);
3867 fc_host_post_event(vha->host, fc_get_event_number(),
3868 e->u.aen.code, e->u.aen.data);
3870 case QLA_EVT_IDC_ACK:
3871 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3873 case QLA_EVT_ASYNC_LOGIN:
3874 qla2x00_async_login(vha, e->u.logio.fcport,
3877 case QLA_EVT_ASYNC_LOGIN_DONE:
3878 qla2x00_async_login_done(vha, e->u.logio.fcport,
3881 case QLA_EVT_ASYNC_LOGOUT:
3882 qla2x00_async_logout(vha, e->u.logio.fcport);
3884 case QLA_EVT_ASYNC_LOGOUT_DONE:
3885 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3888 case QLA_EVT_ASYNC_ADISC:
3889 qla2x00_async_adisc(vha, e->u.logio.fcport,
3892 case QLA_EVT_ASYNC_ADISC_DONE:
3893 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3896 case QLA_EVT_UEVENT:
3897 qla2x00_uevent_emit(vha, e->u.uevent.code);
3900 qlafx00_process_aen(vha, e);
3903 if (e->flags & QLA_EVT_FLAG_FREE)
3906 /* For each work completed decrement vha ref count */
3907 QLA_VHA_MARK_NOT_BUSY(vha);
3911 /* Relogins all the fcports of a vport
3912 * Context: dpc thread
3914 void qla2x00_relogin(struct scsi_qla_host *vha)
3918 uint16_t next_loopid = 0;
3919 struct qla_hw_data *ha = vha->hw;
3922 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3924 * If the port is not ONLINE then try to login
3925 * to it if we haven't run out of retries.
3927 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3928 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
3929 fcport->login_retry--;
3930 if (fcport->flags & FCF_FABRIC_DEVICE) {
3931 if (fcport->flags & FCF_FCP2_DEVICE)
3932 ha->isp_ops->fabric_logout(vha,
3934 fcport->d_id.b.domain,
3935 fcport->d_id.b.area,
3936 fcport->d_id.b.al_pa);
3938 if (fcport->loop_id == FC_NO_LOOP_ID) {
3939 fcport->loop_id = next_loopid =
3940 ha->min_external_loopid;
3941 status = qla2x00_find_new_loop_id(
3943 if (status != QLA_SUCCESS) {
3944 /* Ran out of IDs to use */
3949 if (IS_ALOGIO_CAPABLE(ha)) {
3950 fcport->flags |= FCF_ASYNC_SENT;
3952 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3953 status = qla2x00_post_async_login_work(
3955 if (status == QLA_SUCCESS)
3957 /* Attempt a retry. */
3960 status = qla2x00_fabric_login(vha,
3961 fcport, &next_loopid);
3962 if (status == QLA_SUCCESS) {
3971 qla2x00_get_port_database(
3973 if (status2 != QLA_SUCCESS)
3978 status = qla2x00_local_device_login(vha,
3981 if (status == QLA_SUCCESS) {
3982 fcport->old_loop_id = fcport->loop_id;
3984 ql_dbg(ql_dbg_disc, vha, 0x2003,
3985 "Port login OK: logged in ID 0x%x.\n",
3988 qla2x00_update_fcport(vha, fcport);
3990 } else if (status == 1) {
3991 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3992 /* retry the login again */
3993 ql_dbg(ql_dbg_disc, vha, 0x2007,
3994 "Retrying %d login again loop_id 0x%x.\n",
3995 fcport->login_retry, fcport->loop_id);
3997 fcport->login_retry = 0;
4000 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
4001 qla2x00_clear_loop_id(fcport);
4003 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4008 /* Schedule work on any of the dpc-workqueues */
4010 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4012 struct qla_hw_data *ha = base_vha->hw;
4014 switch (work_code) {
4015 case MBA_IDC_AEN: /* 0x8200 */
4017 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4020 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4021 if (!ha->flags.nic_core_reset_hdlr_active) {
4023 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4025 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4026 "NIC Core reset is already active. Skip "
4027 "scheduling it again.\n");
4029 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4031 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4033 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4035 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4038 ql_log(ql_log_warn, base_vha, 0xb05f,
4039 "Unknow work-code=0x%x.\n", work_code);
4045 /* Work: Perform NIC Core Unrecoverable state handling */
4047 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4049 struct qla_hw_data *ha =
4050 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
4051 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4052 uint32_t dev_state = 0;
4054 qla83xx_idc_lock(base_vha, 0);
4055 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4056 qla83xx_reset_ownership(base_vha);
4057 if (ha->flags.nic_core_reset_owner) {
4058 ha->flags.nic_core_reset_owner = 0;
4059 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4060 QLA8XXX_DEV_FAILED);
4061 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4062 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4064 qla83xx_idc_unlock(base_vha, 0);
4067 /* Work: Execute IDC state handler */
4069 qla83xx_idc_state_handler_work(struct work_struct *work)
4071 struct qla_hw_data *ha =
4072 container_of(work, struct qla_hw_data, idc_state_handler);
4073 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4074 uint32_t dev_state = 0;
4076 qla83xx_idc_lock(base_vha, 0);
4077 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4078 if (dev_state == QLA8XXX_DEV_FAILED ||
4079 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4080 qla83xx_idc_state_handler(base_vha);
4081 qla83xx_idc_unlock(base_vha, 0);
4085 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4087 int rval = QLA_SUCCESS;
4088 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4089 uint32_t heart_beat_counter1, heart_beat_counter2;
4092 if (time_after(jiffies, heart_beat_wait)) {
4093 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4094 "Nic Core f/w is not alive.\n");
4095 rval = QLA_FUNCTION_FAILED;
4099 qla83xx_idc_lock(base_vha, 0);
4100 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4101 &heart_beat_counter1);
4102 qla83xx_idc_unlock(base_vha, 0);
4104 qla83xx_idc_lock(base_vha, 0);
4105 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4106 &heart_beat_counter2);
4107 qla83xx_idc_unlock(base_vha, 0);
4108 } while (heart_beat_counter1 == heart_beat_counter2);
4113 /* Work: Perform NIC Core Reset handling */
4115 qla83xx_nic_core_reset_work(struct work_struct *work)
4117 struct qla_hw_data *ha =
4118 container_of(work, struct qla_hw_data, nic_core_reset);
4119 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4120 uint32_t dev_state = 0;
4122 if (IS_QLA2031(ha)) {
4123 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4124 ql_log(ql_log_warn, base_vha, 0xb081,
4125 "Failed to dump mctp\n");
4129 if (!ha->flags.nic_core_reset_hdlr_active) {
4130 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4131 qla83xx_idc_lock(base_vha, 0);
4132 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4134 qla83xx_idc_unlock(base_vha, 0);
4135 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4136 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4137 "Nic Core f/w is alive.\n");
4142 ha->flags.nic_core_reset_hdlr_active = 1;
4143 if (qla83xx_nic_core_reset(base_vha)) {
4144 /* NIC Core reset failed. */
4145 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4146 "NIC Core reset failed.\n");
4148 ha->flags.nic_core_reset_hdlr_active = 0;
4152 /* Work: Handle 8200 IDC aens */
4154 qla83xx_service_idc_aen(struct work_struct *work)
4156 struct qla_hw_data *ha =
4157 container_of(work, struct qla_hw_data, idc_aen);
4158 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4159 uint32_t dev_state, idc_control;
4161 qla83xx_idc_lock(base_vha, 0);
4162 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4163 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4164 qla83xx_idc_unlock(base_vha, 0);
4165 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4166 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4167 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4168 "Application requested NIC Core Reset.\n");
4169 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4170 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4172 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4173 "Other protocol driver requested NIC Core Reset.\n");
4174 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4176 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4177 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4178 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4183 qla83xx_wait_logic(void)
4188 if (!in_interrupt()) {
4190 * Wait about 200ms before retrying again.
4191 * This controls the number of retries for single
4197 for (i = 0; i < 20; i++)
4198 cpu_relax(); /* This a nop instr on i386 */
4203 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4207 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4208 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4209 struct qla_hw_data *ha = base_vha->hw;
4210 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4211 "Trying force recovery of the IDC lock.\n");
4213 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4217 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4220 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4221 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4228 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4233 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4234 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4235 ~(idc_lck_rcvry_stage_mask));
4236 rval = qla83xx_wr_reg(base_vha,
4237 QLA83XX_IDC_LOCK_RECOVERY, data);
4241 /* Forcefully perform IDC UnLock */
4242 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4246 /* Clear lock-id by setting 0xff */
4247 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4251 /* Clear lock-recovery by setting 0x0 */
4252 rval = qla83xx_wr_reg(base_vha,
4253 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4264 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4266 int rval = QLA_SUCCESS;
4267 uint32_t o_drv_lockid, n_drv_lockid;
4268 unsigned long lock_recovery_timeout;
4270 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4272 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4276 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4277 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4278 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4281 return QLA_FUNCTION_FAILED;
4284 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4288 if (o_drv_lockid == n_drv_lockid) {
4289 qla83xx_wait_logic();
4299 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4301 uint16_t options = (requester_id << 15) | BIT_6;
4303 uint32_t lock_owner;
4304 struct qla_hw_data *ha = base_vha->hw;
4306 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4308 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4311 /* Setting lock-id to our function-number */
4312 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4315 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4317 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4318 "Failed to acquire IDC lock, acquired by %d, "
4319 "retrying...\n", lock_owner);
4321 /* Retry/Perform IDC-Lock recovery */
4322 if (qla83xx_idc_lock_recovery(base_vha)
4324 qla83xx_wait_logic();
4327 ql_log(ql_log_warn, base_vha, 0xb075,
4328 "IDC Lock recovery FAILED.\n");
4335 /* XXX: IDC-lock implementation using access-control mbx */
4337 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4338 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4339 "Failed to acquire IDC lock. retrying...\n");
4340 /* Retry/Perform IDC-Lock recovery */
4341 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4342 qla83xx_wait_logic();
4345 ql_log(ql_log_warn, base_vha, 0xb076,
4346 "IDC Lock recovery FAILED.\n");
4353 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4355 uint16_t options = (requester_id << 15) | BIT_7, retry;
4357 struct qla_hw_data *ha = base_vha->hw;
4359 /* IDC-unlock implementation using driver-unlock/lock-id
4364 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4366 if (data == ha->portnum) {
4367 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4368 /* Clearing lock-id by setting 0xff */
4369 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4370 } else if (retry < 10) {
4371 /* SV: XXX: IDC unlock retrying needed here? */
4373 /* Retry for IDC-unlock */
4374 qla83xx_wait_logic();
4376 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4377 "Failed to release IDC lock, retyring=%d\n", retry);
4380 } else if (retry < 10) {
4381 /* Retry for IDC-unlock */
4382 qla83xx_wait_logic();
4384 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4385 "Failed to read drv-lockid, retyring=%d\n", retry);
4391 /* XXX: IDC-unlock implementation using access-control mbx */
4394 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4396 /* Retry for IDC-unlock */
4397 qla83xx_wait_logic();
4399 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4400 "Failed to release IDC lock, retyring=%d\n", retry);
4409 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4411 int rval = QLA_SUCCESS;
4412 struct qla_hw_data *ha = vha->hw;
4413 uint32_t drv_presence;
4415 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4416 if (rval == QLA_SUCCESS) {
4417 drv_presence |= (1 << ha->portnum);
4418 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4426 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4428 int rval = QLA_SUCCESS;
4430 qla83xx_idc_lock(vha, 0);
4431 rval = __qla83xx_set_drv_presence(vha);
4432 qla83xx_idc_unlock(vha, 0);
4438 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4440 int rval = QLA_SUCCESS;
4441 struct qla_hw_data *ha = vha->hw;
4442 uint32_t drv_presence;
4444 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4445 if (rval == QLA_SUCCESS) {
4446 drv_presence &= ~(1 << ha->portnum);
4447 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4455 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4457 int rval = QLA_SUCCESS;
4459 qla83xx_idc_lock(vha, 0);
4460 rval = __qla83xx_clear_drv_presence(vha);
4461 qla83xx_idc_unlock(vha, 0);
4467 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4469 struct qla_hw_data *ha = vha->hw;
4470 uint32_t drv_ack, drv_presence;
4471 unsigned long ack_timeout;
4473 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4474 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4476 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4477 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4478 if ((drv_ack & drv_presence) == drv_presence)
4481 if (time_after_eq(jiffies, ack_timeout)) {
4482 ql_log(ql_log_warn, vha, 0xb067,
4483 "RESET ACK TIMEOUT! drv_presence=0x%x "
4484 "drv_ack=0x%x\n", drv_presence, drv_ack);
4486 * The function(s) which did not ack in time are forced
4487 * to withdraw any further participation in the IDC
4490 if (drv_ack != drv_presence)
4491 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4496 qla83xx_idc_unlock(vha, 0);
4498 qla83xx_idc_lock(vha, 0);
4501 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4502 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4506 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4508 int rval = QLA_SUCCESS;
4509 uint32_t idc_control;
4511 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4512 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4514 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4515 __qla83xx_get_idc_control(vha, &idc_control);
4516 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4517 __qla83xx_set_idc_control(vha, 0);
4519 qla83xx_idc_unlock(vha, 0);
4520 rval = qla83xx_restart_nic_firmware(vha);
4521 qla83xx_idc_lock(vha, 0);
4523 if (rval != QLA_SUCCESS) {
4524 ql_log(ql_log_fatal, vha, 0xb06a,
4525 "Failed to restart NIC f/w.\n");
4526 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4527 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4529 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4530 "Success in restarting nic f/w.\n");
4531 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4532 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4538 /* Assumes idc_lock always held on entry */
4540 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4542 struct qla_hw_data *ha = base_vha->hw;
4543 int rval = QLA_SUCCESS;
4544 unsigned long dev_init_timeout;
4547 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4548 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4552 if (time_after_eq(jiffies, dev_init_timeout)) {
4553 ql_log(ql_log_warn, base_vha, 0xb06e,
4554 "Initialization TIMEOUT!\n");
4555 /* Init timeout. Disable further NIC Core
4558 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4559 QLA8XXX_DEV_FAILED);
4560 ql_log(ql_log_info, base_vha, 0xb06f,
4561 "HW State: FAILED.\n");
4564 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4565 switch (dev_state) {
4566 case QLA8XXX_DEV_READY:
4567 if (ha->flags.nic_core_reset_owner)
4568 qla83xx_idc_audit(base_vha,
4569 IDC_AUDIT_COMPLETION);
4570 ha->flags.nic_core_reset_owner = 0;
4571 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4572 "Reset_owner reset by 0x%x.\n",
4575 case QLA8XXX_DEV_COLD:
4576 if (ha->flags.nic_core_reset_owner)
4577 rval = qla83xx_device_bootstrap(base_vha);
4579 /* Wait for AEN to change device-state */
4580 qla83xx_idc_unlock(base_vha, 0);
4582 qla83xx_idc_lock(base_vha, 0);
4585 case QLA8XXX_DEV_INITIALIZING:
4586 /* Wait for AEN to change device-state */
4587 qla83xx_idc_unlock(base_vha, 0);
4589 qla83xx_idc_lock(base_vha, 0);
4591 case QLA8XXX_DEV_NEED_RESET:
4592 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4593 qla83xx_need_reset_handler(base_vha);
4595 /* Wait for AEN to change device-state */
4596 qla83xx_idc_unlock(base_vha, 0);
4598 qla83xx_idc_lock(base_vha, 0);
4600 /* reset timeout value after need reset handler */
4601 dev_init_timeout = jiffies +
4602 (ha->fcoe_dev_init_timeout * HZ);
4604 case QLA8XXX_DEV_NEED_QUIESCENT:
4605 /* XXX: DEBUG for now */
4606 qla83xx_idc_unlock(base_vha, 0);
4608 qla83xx_idc_lock(base_vha, 0);
4610 case QLA8XXX_DEV_QUIESCENT:
4611 /* XXX: DEBUG for now */
4612 if (ha->flags.quiesce_owner)
4615 qla83xx_idc_unlock(base_vha, 0);
4617 qla83xx_idc_lock(base_vha, 0);
4618 dev_init_timeout = jiffies +
4619 (ha->fcoe_dev_init_timeout * HZ);
4621 case QLA8XXX_DEV_FAILED:
4622 if (ha->flags.nic_core_reset_owner)
4623 qla83xx_idc_audit(base_vha,
4624 IDC_AUDIT_COMPLETION);
4625 ha->flags.nic_core_reset_owner = 0;
4626 __qla83xx_clear_drv_presence(base_vha);
4627 qla83xx_idc_unlock(base_vha, 0);
4628 qla8xxx_dev_failed_handler(base_vha);
4629 rval = QLA_FUNCTION_FAILED;
4630 qla83xx_idc_lock(base_vha, 0);
4632 case QLA8XXX_BAD_VALUE:
4633 qla83xx_idc_unlock(base_vha, 0);
4635 qla83xx_idc_lock(base_vha, 0);
4638 ql_log(ql_log_warn, base_vha, 0xb071,
4639 "Unknow Device State: %x.\n", dev_state);
4640 qla83xx_idc_unlock(base_vha, 0);
4641 qla8xxx_dev_failed_handler(base_vha);
4642 rval = QLA_FUNCTION_FAILED;
4643 qla83xx_idc_lock(base_vha, 0);
4652 /**************************************************************************
4654 * This kernel thread is a task that is schedule by the interrupt handler
4655 * to perform the background processing for interrupts.
4658 * This task always run in the context of a kernel thread. It
4659 * is kick-off by the driver's detect code and starts up
4660 * up one per adapter. It immediately goes to sleep and waits for
4661 * some fibre event. When either the interrupt handler or
4662 * the timer routine detects a event it will one of the task
4663 * bits then wake us up.
4664 **************************************************************************/
4666 qla2x00_do_dpc(void *data)
4669 scsi_qla_host_t *base_vha;
4670 struct qla_hw_data *ha;
4672 ha = (struct qla_hw_data *)data;
4673 base_vha = pci_get_drvdata(ha->pdev);
4675 set_user_nice(current, -20);
4677 set_current_state(TASK_INTERRUPTIBLE);
4678 while (!kthread_should_stop()) {
4679 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4680 "DPC handler sleeping.\n");
4683 __set_current_state(TASK_RUNNING);
4685 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4688 if (ha->flags.eeh_busy) {
4689 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4690 "eeh_busy=%d.\n", ha->flags.eeh_busy);
4696 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4697 "DPC handler waking up, dpc_flags=0x%lx.\n",
4698 base_vha->dpc_flags);
4700 qla2x00_do_work(base_vha);
4702 if (IS_QLA82XX(ha)) {
4703 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4704 &base_vha->dpc_flags)) {
4705 qla82xx_idc_lock(ha);
4706 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4707 QLA8XXX_DEV_FAILED);
4708 qla82xx_idc_unlock(ha);
4709 ql_log(ql_log_info, base_vha, 0x4004,
4710 "HW State: FAILED.\n");
4711 qla82xx_device_state_handler(base_vha);
4715 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4716 &base_vha->dpc_flags)) {
4718 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4719 "FCoE context reset scheduled.\n");
4720 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4721 &base_vha->dpc_flags))) {
4722 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4723 /* FCoE-ctx reset failed.
4724 * Escalate to chip-reset
4726 set_bit(ISP_ABORT_NEEDED,
4727 &base_vha->dpc_flags);
4729 clear_bit(ABORT_ISP_ACTIVE,
4730 &base_vha->dpc_flags);
4733 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4734 "FCoE context reset end.\n");
4736 } else if (IS_QLAFX00(ha)) {
4737 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4738 &base_vha->dpc_flags)) {
4739 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4740 "Firmware Reset Recovery\n");
4741 if (qlafx00_reset_initialize(base_vha)) {
4742 /* Failed. Abort isp later. */
4743 if (!test_bit(UNLOADING,
4744 &base_vha->dpc_flags))
4745 set_bit(ISP_UNRECOVERABLE,
4746 &base_vha->dpc_flags);
4747 ql_dbg(ql_dbg_dpc, base_vha,
4749 "Reset Recovery Failed\n");
4753 if (test_and_clear_bit(FX00_TARGET_SCAN,
4754 &base_vha->dpc_flags)) {
4755 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4756 "ISPFx00 Target Scan scheduled\n");
4757 if (qlafx00_rescan_isp(base_vha)) {
4758 if (!test_bit(UNLOADING,
4759 &base_vha->dpc_flags))
4760 set_bit(ISP_UNRECOVERABLE,
4761 &base_vha->dpc_flags);
4762 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4763 "ISPFx00 Target Scan Failed\n");
4765 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4766 "ISPFx00 Target Scan End\n");
4770 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4771 &base_vha->dpc_flags)) {
4773 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4774 "ISP abort scheduled.\n");
4775 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4776 &base_vha->dpc_flags))) {
4778 if (ha->isp_ops->abort_isp(base_vha)) {
4779 /* failed. retry later */
4780 set_bit(ISP_ABORT_NEEDED,
4781 &base_vha->dpc_flags);
4783 clear_bit(ABORT_ISP_ACTIVE,
4784 &base_vha->dpc_flags);
4787 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4788 "ISP abort end.\n");
4791 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4792 &base_vha->dpc_flags)) {
4793 qla2x00_update_fcports(base_vha);
4796 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4798 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4799 if (ret != QLA_SUCCESS)
4800 ql_log(ql_log_warn, base_vha, 0x121,
4801 "Failed to enable receiving of RSCN "
4802 "requests: 0x%x.\n", ret);
4803 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4807 goto loop_resync_check;
4809 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
4810 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4811 "Quiescence mode scheduled.\n");
4812 if (IS_QLA82XX(ha)) {
4813 qla82xx_device_state_handler(base_vha);
4814 clear_bit(ISP_QUIESCE_NEEDED,
4815 &base_vha->dpc_flags);
4816 if (!ha->flags.quiesce_owner) {
4817 qla2x00_perform_loop_resync(base_vha);
4819 qla82xx_idc_lock(ha);
4820 qla82xx_clear_qsnt_ready(base_vha);
4821 qla82xx_idc_unlock(ha);
4824 clear_bit(ISP_QUIESCE_NEEDED,
4825 &base_vha->dpc_flags);
4826 qla2x00_quiesce_io(base_vha);
4828 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4829 "Quiescence mode end.\n");
4832 if (test_and_clear_bit(RESET_MARKER_NEEDED,
4833 &base_vha->dpc_flags) &&
4834 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
4836 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4837 "Reset marker scheduled.\n");
4838 qla2x00_rst_aen(base_vha);
4839 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
4840 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
4841 "Reset marker end.\n");
4844 /* Retry each device up to login retry count */
4845 if ((test_and_clear_bit(RELOGIN_NEEDED,
4846 &base_vha->dpc_flags)) &&
4847 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
4848 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
4850 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
4851 "Relogin scheduled.\n");
4852 qla2x00_relogin(base_vha);
4853 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
4857 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
4858 &base_vha->dpc_flags)) {
4860 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
4861 "Loop resync scheduled.\n");
4863 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
4864 &base_vha->dpc_flags))) {
4866 rval = qla2x00_loop_resync(base_vha);
4868 clear_bit(LOOP_RESYNC_ACTIVE,
4869 &base_vha->dpc_flags);
4872 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
4873 "Loop resync end.\n");
4879 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
4880 atomic_read(&base_vha->loop_state) == LOOP_READY) {
4881 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
4882 qla2xxx_flash_npiv_conf(base_vha);
4885 if (test_and_clear_bit(HOST_RAMP_DOWN_QUEUE_DEPTH,
4886 &base_vha->dpc_flags)) {
4887 /* Prevents simultaneous ramp up and down */
4888 clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
4889 &base_vha->dpc_flags);
4890 qla2x00_host_ramp_down_queuedepth(base_vha);
4893 if (test_and_clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
4894 &base_vha->dpc_flags))
4895 qla2x00_host_ramp_up_queuedepth(base_vha);
4897 if (!ha->interrupts_on)
4898 ha->isp_ops->enable_intrs(ha);
4900 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
4901 &base_vha->dpc_flags))
4902 ha->isp_ops->beacon_blink(base_vha);
4904 if (!IS_QLAFX00(ha))
4905 qla2x00_do_dpc_all_vps(base_vha);
4909 set_current_state(TASK_INTERRUPTIBLE);
4910 } /* End of while(1) */
4911 __set_current_state(TASK_RUNNING);
4913 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
4914 "DPC handler exiting.\n");
4917 * Make sure that nobody tries to wake us up again.
4921 /* Cleanup any residual CTX SRBs. */
4922 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4928 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
4930 struct qla_hw_data *ha = vha->hw;
4931 struct task_struct *t = ha->dpc_thread;
4933 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
4939 * Processes asynchronous reset.
4942 * ha = adapter block pointer.
4945 qla2x00_rst_aen(scsi_qla_host_t *vha)
4947 if (vha->flags.online && !vha->flags.reset_active &&
4948 !atomic_read(&vha->loop_down_timer) &&
4949 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
4951 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
4954 * Issue marker command only when we are going to start
4957 vha->marker_needed = 1;
4958 } while (!atomic_read(&vha->loop_down_timer) &&
4959 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
4963 /**************************************************************************
4969 * Context: Interrupt
4970 ***************************************************************************/
4972 qla2x00_timer(scsi_qla_host_t *vha)
4974 unsigned long cpu_flags = 0;
4979 struct qla_hw_data *ha = vha->hw;
4980 struct req_que *req;
4982 if (ha->flags.eeh_busy) {
4983 ql_dbg(ql_dbg_timer, vha, 0x6000,
4984 "EEH = %d, restarting timer.\n",
4985 ha->flags.eeh_busy);
4986 qla2x00_restart_timer(vha, WATCH_INTERVAL);
4990 /* Hardware read to raise pending EEH errors during mailbox waits. */
4991 if (!pci_channel_offline(ha->pdev))
4992 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
4994 /* Make sure qla82xx_watchdog is run only for physical port */
4995 if (!vha->vp_idx && IS_QLA82XX(ha)) {
4996 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
4998 qla82xx_watchdog(vha);
5001 if (!vha->vp_idx && IS_QLAFX00(ha))
5002 qlafx00_timer_routine(vha);
5004 /* Loop down handler. */
5005 if (atomic_read(&vha->loop_down_timer) > 0 &&
5006 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5007 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
5008 && vha->flags.online) {
5010 if (atomic_read(&vha->loop_down_timer) ==
5011 vha->loop_down_abort_time) {
5013 ql_log(ql_log_info, vha, 0x6008,
5014 "Loop down - aborting the queues before time expires.\n");
5016 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5017 atomic_set(&vha->loop_state, LOOP_DEAD);
5020 * Schedule an ISP abort to return any FCP2-device
5023 /* NPIV - scan physical port only */
5025 spin_lock_irqsave(&ha->hardware_lock,
5027 req = ha->req_q_map[0];
5029 index < req->num_outstanding_cmds;
5033 sp = req->outstanding_cmds[index];
5036 if (sp->type != SRB_SCSI_CMD)
5039 if (!(sfcp->flags & FCF_FCP2_DEVICE))
5043 set_bit(FCOE_CTX_RESET_NEEDED,
5046 set_bit(ISP_ABORT_NEEDED,
5050 spin_unlock_irqrestore(&ha->hardware_lock,
5056 /* if the loop has been down for 4 minutes, reinit adapter */
5057 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
5058 if (!(vha->device_flags & DFLG_NO_CABLE)) {
5059 ql_log(ql_log_warn, vha, 0x6009,
5060 "Loop down - aborting ISP.\n");
5063 set_bit(FCOE_CTX_RESET_NEEDED,
5066 set_bit(ISP_ABORT_NEEDED,
5070 ql_dbg(ql_dbg_timer, vha, 0x600a,
5071 "Loop down - seconds remaining %d.\n",
5072 atomic_read(&vha->loop_down_timer));
5075 /* Check if beacon LED needs to be blinked for physical host only */
5076 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
5077 /* There is no beacon_blink function for ISP82xx */
5078 if (!IS_QLA82XX(ha)) {
5079 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5084 /* Process any deferred work. */
5085 if (!list_empty(&vha->work_list))
5088 /* Schedule the DPC routine if needed */
5089 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5090 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5091 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
5093 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5094 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
5095 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5096 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
5097 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
5098 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
5099 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags) ||
5100 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags))) {
5101 ql_dbg(ql_dbg_timer, vha, 0x600b,
5102 "isp_abort_needed=%d loop_resync_needed=%d "
5103 "fcport_update_needed=%d start_dpc=%d "
5104 "reset_marker_needed=%d",
5105 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5106 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5107 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5109 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5110 ql_dbg(ql_dbg_timer, vha, 0x600c,
5111 "beacon_blink_needed=%d isp_unrecoverable=%d "
5112 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
5113 "relogin_needed=%d, host_ramp_down_needed=%d "
5114 "host_ramp_up_needed=%d.\n",
5115 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5116 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5117 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5118 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
5119 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
5120 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags),
5121 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags));
5122 qla2xxx_wake_dpc(vha);
5125 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5128 /* Firmware interface routines. */
5131 #define FW_ISP21XX 0
5132 #define FW_ISP22XX 1
5133 #define FW_ISP2300 2
5134 #define FW_ISP2322 3
5135 #define FW_ISP24XX 4
5136 #define FW_ISP25XX 5
5137 #define FW_ISP81XX 6
5138 #define FW_ISP82XX 7
5139 #define FW_ISP2031 8
5140 #define FW_ISP8031 9
5142 #define FW_FILE_ISP21XX "ql2100_fw.bin"
5143 #define FW_FILE_ISP22XX "ql2200_fw.bin"
5144 #define FW_FILE_ISP2300 "ql2300_fw.bin"
5145 #define FW_FILE_ISP2322 "ql2322_fw.bin"
5146 #define FW_FILE_ISP24XX "ql2400_fw.bin"
5147 #define FW_FILE_ISP25XX "ql2500_fw.bin"
5148 #define FW_FILE_ISP81XX "ql8100_fw.bin"
5149 #define FW_FILE_ISP82XX "ql8200_fw.bin"
5150 #define FW_FILE_ISP2031 "ql2600_fw.bin"
5151 #define FW_FILE_ISP8031 "ql8300_fw.bin"
5153 static DEFINE_MUTEX(qla_fw_lock);
5155 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
5156 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5157 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5158 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5159 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5160 { .name = FW_FILE_ISP24XX, },
5161 { .name = FW_FILE_ISP25XX, },
5162 { .name = FW_FILE_ISP81XX, },
5163 { .name = FW_FILE_ISP82XX, },
5164 { .name = FW_FILE_ISP2031, },
5165 { .name = FW_FILE_ISP8031, },
5169 qla2x00_request_firmware(scsi_qla_host_t *vha)
5171 struct qla_hw_data *ha = vha->hw;
5172 struct fw_blob *blob;
5174 if (IS_QLA2100(ha)) {
5175 blob = &qla_fw_blobs[FW_ISP21XX];
5176 } else if (IS_QLA2200(ha)) {
5177 blob = &qla_fw_blobs[FW_ISP22XX];
5178 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5179 blob = &qla_fw_blobs[FW_ISP2300];
5180 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5181 blob = &qla_fw_blobs[FW_ISP2322];
5182 } else if (IS_QLA24XX_TYPE(ha)) {
5183 blob = &qla_fw_blobs[FW_ISP24XX];
5184 } else if (IS_QLA25XX(ha)) {
5185 blob = &qla_fw_blobs[FW_ISP25XX];
5186 } else if (IS_QLA81XX(ha)) {
5187 blob = &qla_fw_blobs[FW_ISP81XX];
5188 } else if (IS_QLA82XX(ha)) {
5189 blob = &qla_fw_blobs[FW_ISP82XX];
5190 } else if (IS_QLA2031(ha)) {
5191 blob = &qla_fw_blobs[FW_ISP2031];
5192 } else if (IS_QLA8031(ha)) {
5193 blob = &qla_fw_blobs[FW_ISP8031];
5198 mutex_lock(&qla_fw_lock);
5202 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
5203 ql_log(ql_log_warn, vha, 0x0063,
5204 "Failed to load firmware image (%s).\n", blob->name);
5211 mutex_unlock(&qla_fw_lock);
5216 qla2x00_release_firmware(void)
5220 mutex_lock(&qla_fw_lock);
5221 for (idx = 0; idx < FW_BLOBS; idx++)
5222 release_firmware(qla_fw_blobs[idx].fw);
5223 mutex_unlock(&qla_fw_lock);
5226 static pci_ers_result_t
5227 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5229 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5230 struct qla_hw_data *ha = vha->hw;
5232 ql_dbg(ql_dbg_aer, vha, 0x9000,
5233 "PCI error detected, state %x.\n", state);
5236 case pci_channel_io_normal:
5237 ha->flags.eeh_busy = 0;
5238 return PCI_ERS_RESULT_CAN_RECOVER;
5239 case pci_channel_io_frozen:
5240 ha->flags.eeh_busy = 1;
5241 /* For ISP82XX complete any pending mailbox cmd */
5242 if (IS_QLA82XX(ha)) {
5243 ha->flags.isp82xx_fw_hung = 1;
5244 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5245 qla82xx_clear_pending_mbx(vha);
5247 qla2x00_free_irqs(vha);
5248 pci_disable_device(pdev);
5249 /* Return back all IOs */
5250 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5251 return PCI_ERS_RESULT_NEED_RESET;
5252 case pci_channel_io_perm_failure:
5253 ha->flags.pci_channel_io_perm_failure = 1;
5254 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
5255 return PCI_ERS_RESULT_DISCONNECT;
5257 return PCI_ERS_RESULT_NEED_RESET;
5260 static pci_ers_result_t
5261 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5263 int risc_paused = 0;
5265 unsigned long flags;
5266 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5267 struct qla_hw_data *ha = base_vha->hw;
5268 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5269 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5272 return PCI_ERS_RESULT_RECOVERED;
5274 spin_lock_irqsave(&ha->hardware_lock, flags);
5275 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5276 stat = RD_REG_DWORD(®->hccr);
5277 if (stat & HCCR_RISC_PAUSE)
5279 } else if (IS_QLA23XX(ha)) {
5280 stat = RD_REG_DWORD(®->u.isp2300.host_status);
5281 if (stat & HSR_RISC_PAUSED)
5283 } else if (IS_FWI2_CAPABLE(ha)) {
5284 stat = RD_REG_DWORD(®24->host_status);
5285 if (stat & HSRX_RISC_PAUSED)
5288 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5291 ql_log(ql_log_info, base_vha, 0x9003,
5292 "RISC paused -- mmio_enabled, Dumping firmware.\n");
5293 ha->isp_ops->fw_dump(base_vha, 0);
5295 return PCI_ERS_RESULT_NEED_RESET;
5297 return PCI_ERS_RESULT_RECOVERED;
5301 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
5303 uint32_t rval = QLA_FUNCTION_FAILED;
5304 uint32_t drv_active = 0;
5305 struct qla_hw_data *ha = base_vha->hw;
5307 struct pci_dev *other_pdev = NULL;
5309 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5310 "Entered %s.\n", __func__);
5312 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5314 if (base_vha->flags.online) {
5315 /* Abort all outstanding commands,
5316 * so as to be requeued later */
5317 qla2x00_abort_isp_cleanup(base_vha);
5321 fn = PCI_FUNC(ha->pdev->devfn);
5324 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5325 "Finding pci device at function = 0x%x.\n", fn);
5327 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5328 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5333 if (atomic_read(&other_pdev->enable_cnt)) {
5334 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5335 "Found PCI func available and enable at 0x%x.\n",
5337 pci_dev_put(other_pdev);
5340 pci_dev_put(other_pdev);
5345 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5346 "This devfn is reset owner = 0x%x.\n",
5348 qla82xx_idc_lock(ha);
5350 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5351 QLA8XXX_DEV_INITIALIZING);
5353 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5354 QLA82XX_IDC_VERSION);
5356 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
5357 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5358 "drv_active = 0x%x.\n", drv_active);
5360 qla82xx_idc_unlock(ha);
5361 /* Reset if device is not already reset
5362 * drv_active would be 0 if a reset has already been done
5365 rval = qla82xx_start_firmware(base_vha);
5368 qla82xx_idc_lock(ha);
5370 if (rval != QLA_SUCCESS) {
5371 ql_log(ql_log_info, base_vha, 0x900b,
5372 "HW State: FAILED.\n");
5373 qla82xx_clear_drv_active(ha);
5374 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5375 QLA8XXX_DEV_FAILED);
5377 ql_log(ql_log_info, base_vha, 0x900c,
5378 "HW State: READY.\n");
5379 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5381 qla82xx_idc_unlock(ha);
5382 ha->flags.isp82xx_fw_hung = 0;
5383 rval = qla82xx_restart_isp(base_vha);
5384 qla82xx_idc_lock(ha);
5385 /* Clear driver state register */
5386 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5387 qla82xx_set_drv_active(base_vha);
5389 qla82xx_idc_unlock(ha);
5391 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5392 "This devfn is not reset owner = 0x%x.\n",
5394 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
5395 QLA8XXX_DEV_READY)) {
5396 ha->flags.isp82xx_fw_hung = 0;
5397 rval = qla82xx_restart_isp(base_vha);
5398 qla82xx_idc_lock(ha);
5399 qla82xx_set_drv_active(base_vha);
5400 qla82xx_idc_unlock(ha);
5403 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5408 static pci_ers_result_t
5409 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5411 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
5412 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5413 struct qla_hw_data *ha = base_vha->hw;
5414 struct rsp_que *rsp;
5415 int rc, retries = 10;
5417 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5420 /* Workaround: qla2xxx driver which access hardware earlier
5421 * needs error state to be pci_channel_io_online.
5422 * Otherwise mailbox command timesout.
5424 pdev->error_state = pci_channel_io_normal;
5426 pci_restore_state(pdev);
5428 /* pci_restore_state() clears the saved_state flag of the device
5429 * save restored state which resets saved_state flag
5431 pci_save_state(pdev);
5434 rc = pci_enable_device_mem(pdev);
5436 rc = pci_enable_device(pdev);
5439 ql_log(ql_log_warn, base_vha, 0x9005,
5440 "Can't re-enable PCI device after reset.\n");
5441 goto exit_slot_reset;
5444 rsp = ha->rsp_q_map[0];
5445 if (qla2x00_request_irqs(ha, rsp))
5446 goto exit_slot_reset;
5448 if (ha->isp_ops->pci_config(base_vha))
5449 goto exit_slot_reset;
5451 if (IS_QLA82XX(ha)) {
5452 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5453 ret = PCI_ERS_RESULT_RECOVERED;
5454 goto exit_slot_reset;
5456 goto exit_slot_reset;
5459 while (ha->flags.mbox_busy && retries--)
5462 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5463 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
5464 ret = PCI_ERS_RESULT_RECOVERED;
5465 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5469 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5470 "slot_reset return %x.\n", ret);
5476 qla2xxx_pci_resume(struct pci_dev *pdev)
5478 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5479 struct qla_hw_data *ha = base_vha->hw;
5482 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5485 ret = qla2x00_wait_for_hba_online(base_vha);
5486 if (ret != QLA_SUCCESS) {
5487 ql_log(ql_log_fatal, base_vha, 0x9002,
5488 "The device failed to resume I/O from slot/link_reset.\n");
5491 pci_cleanup_aer_uncorrect_error_status(pdev);
5493 ha->flags.eeh_busy = 0;
5496 static const struct pci_error_handlers qla2xxx_err_handler = {
5497 .error_detected = qla2xxx_pci_error_detected,
5498 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5499 .slot_reset = qla2xxx_pci_slot_reset,
5500 .resume = qla2xxx_pci_resume,
5503 static struct pci_device_id qla2xxx_pci_tbl[] = {
5504 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5505 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5506 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5507 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5508 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5509 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5510 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5511 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5512 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
5513 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
5514 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5515 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
5516 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
5517 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
5518 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
5519 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5520 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5521 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
5524 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5526 static struct pci_driver qla2xxx_pci_driver = {
5527 .name = QLA2XXX_DRIVER_NAME,
5529 .owner = THIS_MODULE,
5531 .id_table = qla2xxx_pci_tbl,
5532 .probe = qla2x00_probe_one,
5533 .remove = qla2x00_remove_one,
5534 .shutdown = qla2x00_shutdown,
5535 .err_handler = &qla2xxx_err_handler,
5538 static const struct file_operations apidev_fops = {
5539 .owner = THIS_MODULE,
5540 .llseek = noop_llseek,
5544 * qla2x00_module_init - Module initialization.
5547 qla2x00_module_init(void)
5551 /* Allocate cache for SRBs. */
5552 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
5553 SLAB_HWCACHE_ALIGN, NULL);
5554 if (srb_cachep == NULL) {
5555 ql_log(ql_log_fatal, NULL, 0x0001,
5556 "Unable to allocate SRB cache...Failing load!.\n");
5560 /* Initialize target kmem_cache and mem_pools */
5563 kmem_cache_destroy(srb_cachep);
5565 } else if (ret > 0) {
5567 * If initiator mode is explictly disabled by qlt_init(),
5568 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5569 * performing scsi_scan_target() during LOOP UP event.
5571 qla2xxx_transport_functions.disable_target_scan = 1;
5572 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5575 /* Derive version string. */
5576 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
5577 if (ql2xextended_error_logging)
5578 strcat(qla2x00_version_str, "-debug");
5580 qla2xxx_transport_template =
5581 fc_attach_transport(&qla2xxx_transport_functions);
5582 if (!qla2xxx_transport_template) {
5583 kmem_cache_destroy(srb_cachep);
5584 ql_log(ql_log_fatal, NULL, 0x0002,
5585 "fc_attach_transport failed...Failing load!.\n");
5590 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5591 if (apidev_major < 0) {
5592 ql_log(ql_log_fatal, NULL, 0x0003,
5593 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
5596 qla2xxx_transport_vport_template =
5597 fc_attach_transport(&qla2xxx_transport_vport_functions);
5598 if (!qla2xxx_transport_vport_template) {
5599 kmem_cache_destroy(srb_cachep);
5601 fc_release_transport(qla2xxx_transport_template);
5602 ql_log(ql_log_fatal, NULL, 0x0004,
5603 "fc_attach_transport vport failed...Failing load!.\n");
5606 ql_log(ql_log_info, NULL, 0x0005,
5607 "QLogic Fibre Channel HBA Driver: %s.\n",
5608 qla2x00_version_str);
5609 ret = pci_register_driver(&qla2xxx_pci_driver);
5611 kmem_cache_destroy(srb_cachep);
5613 fc_release_transport(qla2xxx_transport_template);
5614 fc_release_transport(qla2xxx_transport_vport_template);
5615 ql_log(ql_log_fatal, NULL, 0x0006,
5616 "pci_register_driver failed...ret=%d Failing load!.\n",
5623 * qla2x00_module_exit - Module cleanup.
5626 qla2x00_module_exit(void)
5628 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
5629 pci_unregister_driver(&qla2xxx_pci_driver);
5630 qla2x00_release_firmware();
5631 kmem_cache_destroy(srb_cachep);
5634 kmem_cache_destroy(ctx_cachep);
5635 fc_release_transport(qla2xxx_transport_template);
5636 fc_release_transport(qla2xxx_transport_vport_template);
5639 module_init(qla2x00_module_init);
5640 module_exit(qla2x00_module_exit);
5642 MODULE_AUTHOR("QLogic Corporation");
5643 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5644 MODULE_LICENSE("GPL");
5645 MODULE_VERSION(QLA2XXX_VERSION);
5646 MODULE_FIRMWARE(FW_FILE_ISP21XX);
5647 MODULE_FIRMWARE(FW_FILE_ISP22XX);
5648 MODULE_FIRMWARE(FW_FILE_ISP2300);
5649 MODULE_FIRMWARE(FW_FILE_ISP2322);
5650 MODULE_FIRMWARE(FW_FILE_ISP24XX);
5651 MODULE_FIRMWARE(FW_FILE_ISP25XX);