2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
10 #include <linux/slab.h>
11 #include <linux/vmalloc.h>
12 #include <asm/uaccess.h>
15 * NVRAM support routines
19 * qla2x00_lock_nvram_access() -
23 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
29 data = RD_REG_WORD(®->nvram);
30 while (data & NVR_BUSY) {
32 data = RD_REG_WORD(®->nvram);
36 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
37 RD_REG_WORD(®->u.isp2300.host_semaphore);
39 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
40 while ((data & BIT_0) == 0) {
43 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
44 RD_REG_WORD(®->u.isp2300.host_semaphore);
46 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
52 * qla2x00_unlock_nvram_access() -
56 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
61 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0);
62 RD_REG_WORD(®->u.isp2300.host_semaphore);
67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
69 * @data: Serial interface selector
72 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
76 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
77 RD_REG_WORD(®->nvram); /* PCI Posting. */
79 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_CLOCK |
81 RD_REG_WORD(®->nvram); /* PCI Posting. */
83 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
84 RD_REG_WORD(®->nvram); /* PCI Posting. */
89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
92 * @nv_cmd: NVRAM command
94 * Bit definitions for NVRAM command:
99 * Bit 15-0 = write data
101 * Returns the word read from nvram @addr.
104 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
111 /* Send command to NVRAM. */
113 for (cnt = 0; cnt < 11; cnt++) {
115 qla2x00_nv_write(ha, NVR_DATA_OUT);
117 qla2x00_nv_write(ha, 0);
121 /* Read data from NVRAM. */
122 for (cnt = 0; cnt < 16; cnt++) {
123 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK);
124 RD_REG_WORD(®->nvram); /* PCI Posting. */
127 reg_data = RD_REG_WORD(®->nvram);
128 if (reg_data & NVR_DATA_IN)
130 WRT_REG_WORD(®->nvram, NVR_SELECT);
131 RD_REG_WORD(®->nvram); /* PCI Posting. */
136 WRT_REG_WORD(®->nvram, NVR_DESELECT);
137 RD_REG_WORD(®->nvram); /* PCI Posting. */
145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
146 * request routine to get the word from NVRAM.
148 * @addr: Address in NVRAM to read
150 * Returns the word read from nvram @addr.
153 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
159 nv_cmd |= NV_READ_OP;
160 data = qla2x00_nvram_request(ha, nv_cmd);
166 * qla2x00_nv_deselect() - Deselect NVRAM operations.
170 qla2x00_nv_deselect(struct qla_hw_data *ha)
172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
174 WRT_REG_WORD(®->nvram, NVR_DESELECT);
175 RD_REG_WORD(®->nvram); /* PCI Posting. */
180 * qla2x00_write_nvram_word() - Write NVRAM data.
182 * @addr: Address in NVRAM to write
183 * @data: word to program
186 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
190 uint32_t nv_cmd, wait_cnt;
191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
192 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
194 qla2x00_nv_write(ha, NVR_DATA_OUT);
195 qla2x00_nv_write(ha, 0);
196 qla2x00_nv_write(ha, 0);
198 for (word = 0; word < 8; word++)
199 qla2x00_nv_write(ha, NVR_DATA_OUT);
201 qla2x00_nv_deselect(ha);
204 nv_cmd = (addr << 16) | NV_WRITE_OP;
207 for (count = 0; count < 27; count++) {
209 qla2x00_nv_write(ha, NVR_DATA_OUT);
211 qla2x00_nv_write(ha, 0);
216 qla2x00_nv_deselect(ha);
218 /* Wait for NVRAM to become ready */
219 WRT_REG_WORD(®->nvram, NVR_SELECT);
220 RD_REG_WORD(®->nvram); /* PCI Posting. */
221 wait_cnt = NVR_WAIT_CNT;
224 ql_dbg(ql_dbg_user, vha, 0x708d,
225 "NVRAM didn't go ready...\n");
229 word = RD_REG_WORD(®->nvram);
230 } while ((word & NVR_DATA_IN) == 0);
232 qla2x00_nv_deselect(ha);
235 qla2x00_nv_write(ha, NVR_DATA_OUT);
236 for (count = 0; count < 10; count++)
237 qla2x00_nv_write(ha, 0);
239 qla2x00_nv_deselect(ha);
243 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
244 uint16_t data, uint32_t tmo)
249 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
253 qla2x00_nv_write(ha, NVR_DATA_OUT);
254 qla2x00_nv_write(ha, 0);
255 qla2x00_nv_write(ha, 0);
257 for (word = 0; word < 8; word++)
258 qla2x00_nv_write(ha, NVR_DATA_OUT);
260 qla2x00_nv_deselect(ha);
263 nv_cmd = (addr << 16) | NV_WRITE_OP;
266 for (count = 0; count < 27; count++) {
268 qla2x00_nv_write(ha, NVR_DATA_OUT);
270 qla2x00_nv_write(ha, 0);
275 qla2x00_nv_deselect(ha);
277 /* Wait for NVRAM to become ready */
278 WRT_REG_WORD(®->nvram, NVR_SELECT);
279 RD_REG_WORD(®->nvram); /* PCI Posting. */
282 word = RD_REG_WORD(®->nvram);
284 ret = QLA_FUNCTION_FAILED;
287 } while ((word & NVR_DATA_IN) == 0);
289 qla2x00_nv_deselect(ha);
292 qla2x00_nv_write(ha, NVR_DATA_OUT);
293 for (count = 0; count < 10; count++)
294 qla2x00_nv_write(ha, 0);
296 qla2x00_nv_deselect(ha);
302 * qla2x00_clear_nvram_protection() -
306 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
310 uint32_t word, wait_cnt;
311 uint16_t wprot, wprot_old;
312 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
314 /* Clear NVRAM write protection. */
315 ret = QLA_FUNCTION_FAILED;
317 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
319 __constant_cpu_to_le16(0x1234), 100000);
320 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
321 if (stat != QLA_SUCCESS || wprot != 0x1234) {
323 qla2x00_nv_write(ha, NVR_DATA_OUT);
324 qla2x00_nv_write(ha, 0);
325 qla2x00_nv_write(ha, 0);
326 for (word = 0; word < 8; word++)
327 qla2x00_nv_write(ha, NVR_DATA_OUT);
329 qla2x00_nv_deselect(ha);
331 /* Enable protection register. */
332 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
333 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334 qla2x00_nv_write(ha, NVR_PR_ENABLE);
335 for (word = 0; word < 8; word++)
336 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
338 qla2x00_nv_deselect(ha);
340 /* Clear protection register (ffff is cleared). */
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
344 for (word = 0; word < 8; word++)
345 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
347 qla2x00_nv_deselect(ha);
349 /* Wait for NVRAM to become ready. */
350 WRT_REG_WORD(®->nvram, NVR_SELECT);
351 RD_REG_WORD(®->nvram); /* PCI Posting. */
352 wait_cnt = NVR_WAIT_CNT;
355 ql_dbg(ql_dbg_user, vha, 0x708e,
356 "NVRAM didn't go ready...\n");
360 word = RD_REG_WORD(®->nvram);
361 } while ((word & NVR_DATA_IN) == 0);
366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
372 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
375 uint32_t word, wait_cnt;
376 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
378 if (stat != QLA_SUCCESS)
381 /* Set NVRAM write protection. */
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384 qla2x00_nv_write(ha, 0);
385 qla2x00_nv_write(ha, 0);
386 for (word = 0; word < 8; word++)
387 qla2x00_nv_write(ha, NVR_DATA_OUT);
389 qla2x00_nv_deselect(ha);
391 /* Enable protection register. */
392 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
393 qla2x00_nv_write(ha, NVR_PR_ENABLE);
394 qla2x00_nv_write(ha, NVR_PR_ENABLE);
395 for (word = 0; word < 8; word++)
396 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
398 qla2x00_nv_deselect(ha);
400 /* Enable protection register. */
401 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
402 qla2x00_nv_write(ha, NVR_PR_ENABLE);
403 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
404 for (word = 0; word < 8; word++)
405 qla2x00_nv_write(ha, NVR_PR_ENABLE);
407 qla2x00_nv_deselect(ha);
409 /* Wait for NVRAM to become ready. */
410 WRT_REG_WORD(®->nvram, NVR_SELECT);
411 RD_REG_WORD(®->nvram); /* PCI Posting. */
412 wait_cnt = NVR_WAIT_CNT;
415 ql_dbg(ql_dbg_user, vha, 0x708f,
416 "NVRAM didn't go ready...\n");
420 word = RD_REG_WORD(®->nvram);
421 } while ((word & NVR_DATA_IN) == 0);
425 /*****************************************************************************/
426 /* Flash Manipulation Routines */
427 /*****************************************************************************/
429 static inline uint32_t
430 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
432 return ha->flash_conf_off | faddr;
435 static inline uint32_t
436 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
438 return ha->flash_data_off | faddr;
441 static inline uint32_t
442 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
444 return ha->nvram_conf_off | naddr;
447 static inline uint32_t
448 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
450 return ha->nvram_data_off | naddr;
454 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
458 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
460 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG);
461 /* Wait for READ cycle to complete. */
464 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 &&
465 rval == QLA_SUCCESS; cnt--) {
469 rval = QLA_FUNCTION_TIMEOUT;
473 /* TODO: What happens if we time out? */
475 if (rval == QLA_SUCCESS)
476 data = RD_REG_DWORD(®->flash_data);
482 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
486 struct qla_hw_data *ha = vha->hw;
488 /* Dword reads to flash. */
489 for (i = 0; i < dwords; i++, faddr++)
490 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
491 flash_data_addr(ha, faddr)));
497 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
501 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
503 WRT_REG_DWORD(®->flash_data, data);
504 RD_REG_DWORD(®->flash_data); /* PCI Posting. */
505 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG);
506 /* Wait for Write cycle to complete. */
508 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) &&
509 rval == QLA_SUCCESS; cnt--) {
513 rval = QLA_FUNCTION_TIMEOUT;
520 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
525 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
527 *flash_id = MSB(ids);
529 /* Check if man_id and flash_id are valid. */
530 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
531 /* Read information using 0x9f opcode
532 * Device ID, Mfg ID would be read in the format:
533 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
534 * Example: ATMEL 0x00 01 45 1F
535 * Extract MFG and Dev ID from last two bytes.
537 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
539 *flash_id = MSB(ids);
544 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
546 const char *loc, *locations[] = { "DEF", "PCI" };
547 uint32_t pcihdr, pcids;
549 uint8_t *buf, *bcode, last_image;
550 uint16_t cnt, chksum, *wptr;
551 struct qla_flt_location *fltl;
552 struct qla_hw_data *ha = vha->hw;
553 struct req_que *req = ha->req_q_map[0];
556 * FLT-location structure resides after the last PCI region.
559 /* Begin with sane defaults. */
562 if (IS_QLA24XX_TYPE(ha))
563 *start = FA_FLASH_LAYOUT_ADDR_24;
564 else if (IS_QLA25XX(ha))
565 *start = FA_FLASH_LAYOUT_ADDR;
566 else if (IS_QLA81XX(ha))
567 *start = FA_FLASH_LAYOUT_ADDR_81;
568 else if (IS_QLA82XX(ha)) {
569 *start = FA_FLASH_LAYOUT_ADDR_82;
571 } else if (IS_QLA83XX(ha)) {
572 *start = FA_FLASH_LAYOUT_ADDR_83;
575 /* Begin with first PCI expansion ROM header. */
576 buf = (uint8_t *)req->ring;
577 dcode = (uint32_t *)req->ring;
581 /* Verify PCI expansion ROM header. */
582 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
583 bcode = buf + (pcihdr % 4);
584 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
587 /* Locate PCI data structure. */
588 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
589 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
590 bcode = buf + (pcihdr % 4);
592 /* Validate signature of PCI data structure. */
593 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
594 bcode[0x2] != 'I' || bcode[0x3] != 'R')
597 last_image = bcode[0x15] & BIT_7;
599 /* Locate next PCI expansion ROM. */
600 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
601 } while (!last_image);
603 /* Now verify FLT-location structure. */
604 fltl = (struct qla_flt_location *)req->ring;
605 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
606 sizeof(struct qla_flt_location) >> 2);
607 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
608 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
611 wptr = (uint16_t *)req->ring;
612 cnt = sizeof(struct qla_flt_location) >> 1;
613 for (chksum = 0; cnt; cnt--)
614 chksum += le16_to_cpu(*wptr++);
616 ql_log(ql_log_fatal, vha, 0x0045,
617 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
618 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
619 buf, sizeof(struct qla_flt_location));
620 return QLA_FUNCTION_FAILED;
623 /* Good data. Use specified location. */
625 *start = (le16_to_cpu(fltl->start_hi) << 16 |
626 le16_to_cpu(fltl->start_lo)) >> 2;
628 ql_dbg(ql_dbg_init, vha, 0x0046,
629 "FLTL[%s] = 0x%x.\n",
635 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
637 const char *loc, *locations[] = { "DEF", "FLT" };
638 const uint32_t def_fw[] =
639 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
640 const uint32_t def_boot[] =
641 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
642 const uint32_t def_vpd_nvram[] =
643 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
644 const uint32_t def_vpd0[] =
645 { 0, 0, FA_VPD0_ADDR_81 };
646 const uint32_t def_vpd1[] =
647 { 0, 0, FA_VPD1_ADDR_81 };
648 const uint32_t def_nvram0[] =
649 { 0, 0, FA_NVRAM0_ADDR_81 };
650 const uint32_t def_nvram1[] =
651 { 0, 0, FA_NVRAM1_ADDR_81 };
652 const uint32_t def_fdt[] =
653 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
654 FA_FLASH_DESCR_ADDR_81 };
655 const uint32_t def_npiv_conf0[] =
656 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
657 FA_NPIV_CONF0_ADDR_81 };
658 const uint32_t def_npiv_conf1[] =
659 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
660 FA_NPIV_CONF1_ADDR_81 };
661 const uint32_t fcp_prio_cfg0[] =
662 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
664 const uint32_t fcp_prio_cfg1[] =
665 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
669 uint16_t cnt, chksum;
671 struct qla_flt_header *flt;
672 struct qla_flt_region *region;
673 struct qla_hw_data *ha = vha->hw;
674 struct req_que *req = ha->req_q_map[0];
679 else if (IS_QLA81XX(ha))
682 /* Assign FCP prio region since older adapters may not have FLT, or
683 FCP prio region in it's FLT.
685 ha->flt_region_fcp_prio = ha->flags.port0 ?
686 fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
688 ha->flt_region_flt = flt_addr;
689 wptr = (uint16_t *)req->ring;
690 flt = (struct qla_flt_header *)req->ring;
691 region = (struct qla_flt_region *)&flt[1];
692 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
693 flt_addr << 2, OPTROM_BURST_SIZE);
694 if (*wptr == __constant_cpu_to_le16(0xffff))
696 if (flt->version != __constant_cpu_to_le16(1)) {
697 ql_log(ql_log_warn, vha, 0x0047,
698 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
699 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
700 le16_to_cpu(flt->checksum));
704 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
705 for (chksum = 0; cnt; cnt--)
706 chksum += le16_to_cpu(*wptr++);
708 ql_log(ql_log_fatal, vha, 0x0048,
709 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
710 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
711 le16_to_cpu(flt->checksum));
716 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
717 for ( ; cnt; cnt--, region++) {
718 /* Store addresses as DWORD offsets. */
719 start = le32_to_cpu(region->start) >> 2;
720 ql_dbg(ql_dbg_init, vha, 0x0049,
721 "FLT[%02x]: start=0x%x "
722 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code),
723 start, le32_to_cpu(region->end) >> 2,
724 le32_to_cpu(region->size));
726 switch (le32_to_cpu(region->code) & 0xff) {
727 case FLT_REG_FCOE_FW:
730 ha->flt_region_fw = start;
735 ha->flt_region_fw = start;
737 case FLT_REG_BOOT_CODE:
738 ha->flt_region_boot = start;
743 ha->flt_region_vpd_nvram = start;
747 ha->flt_region_vpd = start;
750 if (IS_QLA82XX(ha) || IS_QLA8031(ha))
752 if (!ha->flags.port0)
753 ha->flt_region_vpd = start;
755 case FLT_REG_NVRAM_0:
759 ha->flt_region_nvram = start;
761 case FLT_REG_NVRAM_1:
764 if (!ha->flags.port0)
765 ha->flt_region_nvram = start;
768 ha->flt_region_fdt = start;
770 case FLT_REG_NPIV_CONF_0:
772 ha->flt_region_npiv_conf = start;
774 case FLT_REG_NPIV_CONF_1:
775 if (!ha->flags.port0)
776 ha->flt_region_npiv_conf = start;
778 case FLT_REG_GOLD_FW:
779 ha->flt_region_gold_fw = start;
781 case FLT_REG_FCP_PRIO_0:
783 ha->flt_region_fcp_prio = start;
785 case FLT_REG_FCP_PRIO_1:
786 if (!ha->flags.port0)
787 ha->flt_region_fcp_prio = start;
789 case FLT_REG_BOOT_CODE_82XX:
790 ha->flt_region_boot = start;
792 case FLT_REG_FW_82XX:
793 ha->flt_region_fw = start;
795 case FLT_REG_GOLD_FW_82XX:
796 ha->flt_region_gold_fw = start;
798 case FLT_REG_BOOTLOAD_82XX:
799 ha->flt_region_bootload = start;
801 case FLT_REG_VPD_8XXX:
802 if (IS_CNA_CAPABLE(ha))
803 ha->flt_region_vpd = start;
805 case FLT_REG_FCOE_NVRAM_0:
809 ha->flt_region_nvram = start;
811 case FLT_REG_FCOE_NVRAM_1:
814 if (!ha->flags.port0)
815 ha->flt_region_nvram = start;
822 /* Use hardcoded defaults. */
824 ha->flt_region_fw = def_fw[def];
825 ha->flt_region_boot = def_boot[def];
826 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
827 ha->flt_region_vpd = ha->flags.port0 ?
828 def_vpd0[def] : def_vpd1[def];
829 ha->flt_region_nvram = ha->flags.port0 ?
830 def_nvram0[def] : def_nvram1[def];
831 ha->flt_region_fdt = def_fdt[def];
832 ha->flt_region_npiv_conf = ha->flags.port0 ?
833 def_npiv_conf0[def] : def_npiv_conf1[def];
835 ql_dbg(ql_dbg_init, vha, 0x004a,
836 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x "
837 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
838 loc, ha->flt_region_boot, ha->flt_region_fw,
839 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
840 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf,
841 ha->flt_region_fcp_prio);
845 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
847 #define FLASH_BLK_SIZE_4K 0x1000
848 #define FLASH_BLK_SIZE_32K 0x8000
849 #define FLASH_BLK_SIZE_64K 0x10000
850 const char *loc, *locations[] = { "MID", "FDT" };
851 uint16_t cnt, chksum;
853 struct qla_fdt_layout *fdt;
854 uint8_t man_id, flash_id;
855 uint16_t mid = 0, fid = 0;
856 struct qla_hw_data *ha = vha->hw;
857 struct req_que *req = ha->req_q_map[0];
859 wptr = (uint16_t *)req->ring;
860 fdt = (struct qla_fdt_layout *)req->ring;
861 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
862 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
863 if (*wptr == __constant_cpu_to_le16(0xffff))
865 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
869 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
871 chksum += le16_to_cpu(*wptr++);
873 ql_dbg(ql_dbg_init, vha, 0x004c,
874 "Inconsistent FDT detected:"
875 " checksum=0x%x id=%c version0x%x.\n", chksum,
876 fdt->sig[0], le16_to_cpu(fdt->version));
877 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
878 (uint8_t *)fdt, sizeof(*fdt));
883 mid = le16_to_cpu(fdt->man_id);
884 fid = le16_to_cpu(fdt->id);
885 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
886 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
887 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
888 if (fdt->unprotect_sec_cmd) {
889 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
890 fdt->unprotect_sec_cmd);
891 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
892 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
893 flash_conf_addr(ha, 0x0336);
898 if (IS_QLA82XX(ha)) {
899 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
902 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
905 ha->fdt_wrt_disable = 0x9c;
906 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
908 case 0xbf: /* STT flash. */
909 if (flash_id == 0x8e)
910 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
912 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
914 if (flash_id == 0x80)
915 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
917 case 0x13: /* ST M25P80. */
918 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
920 case 0x1f: /* Atmel 26DF081A. */
921 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
922 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
923 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
924 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
927 /* Default to 64 kb sector size. */
928 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
932 ql_dbg(ql_dbg_init, vha, 0x004d,
933 "FDT[%s]: (0x%x/0x%x) erase=0x%x "
934 "pr=%x wrtd=0x%x blk=0x%x.\n",
936 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
937 ha->fdt_wrt_disable, ha->fdt_block_size);
942 qla2xxx_get_idc_param(scsi_qla_host_t *vha)
944 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c
946 struct qla_hw_data *ha = vha->hw;
947 struct req_que *req = ha->req_q_map[0];
952 wptr = (uint32_t *)req->ring;
953 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
954 QLA82XX_IDC_PARAM_ADDR , 8);
956 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
957 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
958 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
960 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr++);
961 ha->fcoe_reset_timeout = le32_to_cpu(*wptr);
963 ql_dbg(ql_dbg_init, vha, 0x004e,
964 "fcoe_dev_init_timeout=%d "
965 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout,
966 ha->fcoe_reset_timeout);
971 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
975 struct qla_hw_data *ha = vha->hw;
977 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
978 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
981 ret = qla2xxx_find_flt_start(vha, &flt_addr);
982 if (ret != QLA_SUCCESS)
985 qla2xxx_get_flt_info(vha, flt_addr);
986 qla2xxx_get_fdt_info(vha);
987 qla2xxx_get_idc_param(vha);
993 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
995 #define NPIV_CONFIG_SIZE (16*1024)
998 uint16_t cnt, chksum;
1000 struct qla_npiv_header hdr;
1001 struct qla_npiv_entry *entry;
1002 struct qla_hw_data *ha = vha->hw;
1004 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1005 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
1008 if (ha->flags.nic_core_reset_hdlr_active)
1011 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
1012 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
1013 if (hdr.version == __constant_cpu_to_le16(0xffff))
1015 if (hdr.version != __constant_cpu_to_le16(1)) {
1016 ql_dbg(ql_dbg_user, vha, 0x7090,
1017 "Unsupported NPIV-Config "
1018 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1019 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1020 le16_to_cpu(hdr.checksum));
1024 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
1026 ql_log(ql_log_warn, vha, 0x7091,
1027 "Unable to allocate memory for data.\n");
1031 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
1032 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
1034 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
1035 sizeof(struct qla_npiv_entry)) >> 1;
1036 for (wptr = data, chksum = 0; cnt; cnt--)
1037 chksum += le16_to_cpu(*wptr++);
1039 ql_dbg(ql_dbg_user, vha, 0x7092,
1040 "Inconsistent NPIV-Config "
1041 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1042 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1043 le16_to_cpu(hdr.checksum));
1047 entry = data + sizeof(struct qla_npiv_header);
1048 cnt = le16_to_cpu(hdr.entries);
1049 for (i = 0; cnt; cnt--, entry++, i++) {
1051 struct fc_vport_identifiers vid;
1052 struct fc_vport *vport;
1054 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
1056 flags = le16_to_cpu(entry->flags);
1057 if (flags == 0xffff)
1059 if ((flags & BIT_0) == 0)
1062 memset(&vid, 0, sizeof(vid));
1063 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
1064 vid.vport_type = FC_PORTTYPE_NPIV;
1065 vid.disable = false;
1066 vid.port_name = wwn_to_u64(entry->port_name);
1067 vid.node_name = wwn_to_u64(entry->node_name);
1069 ql_dbg(ql_dbg_user, vha, 0x7093,
1070 "NPIV[%02x]: wwpn=%llx "
1071 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
1072 (unsigned long long)vid.port_name,
1073 (unsigned long long)vid.node_name,
1074 le16_to_cpu(entry->vf_id),
1075 entry->q_qos, entry->f_qos);
1077 if (i < QLA_PRECONFIG_VPORTS) {
1078 vport = fc_vport_create(vha->host, 0, &vid);
1080 ql_log(ql_log_warn, vha, 0x7094,
1081 "NPIV-Config Failed to create vport [%02x]: "
1082 "wwpn=%llx wwnn=%llx.\n", cnt,
1083 (unsigned long long)vid.port_name,
1084 (unsigned long long)vid.node_name);
1092 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
1094 struct qla_hw_data *ha = vha->hw;
1095 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1097 if (ha->flags.fac_supported)
1098 return qla81xx_fac_do_write_enable(vha, 1);
1100 /* Enable flash write. */
1101 WRT_REG_DWORD(®->ctrl_status,
1102 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
1103 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
1105 if (!ha->fdt_wrt_disable)
1108 /* Disable flash write-protection, first clear SR protection bit */
1109 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1110 /* Then write zero again to clear remaining SR bits.*/
1111 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1117 qla24xx_protect_flash(scsi_qla_host_t *vha)
1120 struct qla_hw_data *ha = vha->hw;
1121 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1123 if (ha->flags.fac_supported)
1124 return qla81xx_fac_do_write_enable(vha, 0);
1126 if (!ha->fdt_wrt_disable)
1127 goto skip_wrt_protect;
1129 /* Enable flash write-protection and wait for completion. */
1130 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1131 ha->fdt_wrt_disable);
1132 for (cnt = 300; cnt &&
1133 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1139 /* Disable flash write. */
1140 WRT_REG_DWORD(®->ctrl_status,
1141 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
1142 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
1148 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1150 struct qla_hw_data *ha = vha->hw;
1151 uint32_t start, finish;
1153 if (ha->flags.fac_supported) {
1155 finish = start + (ha->fdt_block_size >> 2) - 1;
1156 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1157 start), flash_data_addr(ha, finish));
1160 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1161 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1162 ((fdata >> 16) & 0xff));
1166 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1171 uint32_t sec_mask, rest_addr;
1173 dma_addr_t optrom_dma;
1174 void *optrom = NULL;
1175 struct qla_hw_data *ha = vha->hw;
1177 /* Prepare burst-capable write on supported ISPs. */
1178 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha)) &&
1179 !(faddr & 0xfff) && dwords > OPTROM_BURST_DWORDS) {
1180 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1181 &optrom_dma, GFP_KERNEL);
1183 ql_log(ql_log_warn, vha, 0x7095,
1184 "Unable to allocate "
1185 "memory for optrom burst write (%x KB).\n",
1186 OPTROM_BURST_SIZE / 1024);
1190 rest_addr = (ha->fdt_block_size >> 2) - 1;
1191 sec_mask = ~rest_addr;
1193 ret = qla24xx_unprotect_flash(vha);
1194 if (ret != QLA_SUCCESS) {
1195 ql_log(ql_log_warn, vha, 0x7096,
1196 "Unable to unprotect flash for update.\n");
1200 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1201 fdata = (faddr & sec_mask) << 2;
1203 /* Are we at the beginning of a sector? */
1204 if ((faddr & rest_addr) == 0) {
1205 /* Do sector unprotect. */
1206 if (ha->fdt_unprotect_sec_cmd)
1207 qla24xx_write_flash_dword(ha,
1208 ha->fdt_unprotect_sec_cmd,
1209 (fdata & 0xff00) | ((fdata << 16) &
1210 0xff0000) | ((fdata >> 16) & 0xff));
1211 ret = qla24xx_erase_sector(vha, fdata);
1212 if (ret != QLA_SUCCESS) {
1213 ql_dbg(ql_dbg_user, vha, 0x7007,
1214 "Unable to erase erase sector: address=%x.\n",
1220 /* Go with burst-write. */
1221 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1222 /* Copy data to DMA'ble buffer. */
1223 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1225 ret = qla2x00_load_ram(vha, optrom_dma,
1226 flash_data_addr(ha, faddr),
1227 OPTROM_BURST_DWORDS);
1228 if (ret != QLA_SUCCESS) {
1229 ql_log(ql_log_warn, vha, 0x7097,
1230 "Unable to burst-write optrom segment "
1231 "(%x/%x/%llx).\n", ret,
1232 flash_data_addr(ha, faddr),
1233 (unsigned long long)optrom_dma);
1234 ql_log(ql_log_warn, vha, 0x7098,
1235 "Reverting to slow-write.\n");
1237 dma_free_coherent(&ha->pdev->dev,
1238 OPTROM_BURST_SIZE, optrom, optrom_dma);
1241 liter += OPTROM_BURST_DWORDS - 1;
1242 faddr += OPTROM_BURST_DWORDS - 1;
1243 dwptr += OPTROM_BURST_DWORDS - 1;
1248 ret = qla24xx_write_flash_dword(ha,
1249 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1250 if (ret != QLA_SUCCESS) {
1251 ql_dbg(ql_dbg_user, vha, 0x7006,
1252 "Unable to program flash address=%x data=%x.\n",
1257 /* Do sector protect. */
1258 if (ha->fdt_unprotect_sec_cmd &&
1259 ((faddr & rest_addr) == rest_addr))
1260 qla24xx_write_flash_dword(ha,
1261 ha->fdt_protect_sec_cmd,
1262 (fdata & 0xff00) | ((fdata << 16) &
1263 0xff0000) | ((fdata >> 16) & 0xff));
1266 ret = qla24xx_protect_flash(vha);
1267 if (ret != QLA_SUCCESS)
1268 ql_log(ql_log_warn, vha, 0x7099,
1269 "Unable to protect flash after update.\n");
1272 dma_free_coherent(&ha->pdev->dev,
1273 OPTROM_BURST_SIZE, optrom, optrom_dma);
1279 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1284 struct qla_hw_data *ha = vha->hw;
1286 /* Word reads to NVRAM via registers. */
1287 wptr = (uint16_t *)buf;
1288 qla2x00_lock_nvram_access(ha);
1289 for (i = 0; i < bytes >> 1; i++, naddr++)
1290 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1292 qla2x00_unlock_nvram_access(ha);
1298 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1303 struct qla_hw_data *ha = vha->hw;
1308 /* Dword reads to flash. */
1309 dwptr = (uint32_t *)buf;
1310 for (i = 0; i < bytes >> 2; i++, naddr++)
1311 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1312 nvram_data_addr(ha, naddr)));
1318 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1324 unsigned long flags;
1325 struct qla_hw_data *ha = vha->hw;
1329 spin_lock_irqsave(&ha->hardware_lock, flags);
1330 qla2x00_lock_nvram_access(ha);
1332 /* Disable NVRAM write-protection. */
1333 stat = qla2x00_clear_nvram_protection(ha);
1335 wptr = (uint16_t *)buf;
1336 for (i = 0; i < bytes >> 1; i++, naddr++) {
1337 qla2x00_write_nvram_word(ha, naddr,
1338 cpu_to_le16(*wptr));
1342 /* Enable NVRAM write-protection. */
1343 qla2x00_set_nvram_protection(ha, stat);
1345 qla2x00_unlock_nvram_access(ha);
1346 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1352 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1358 struct qla_hw_data *ha = vha->hw;
1359 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1366 /* Enable flash write. */
1367 WRT_REG_DWORD(®->ctrl_status,
1368 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
1369 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
1371 /* Disable NVRAM write-protection. */
1372 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1373 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1375 /* Dword writes to flash. */
1376 dwptr = (uint32_t *)buf;
1377 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1378 ret = qla24xx_write_flash_dword(ha,
1379 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1380 if (ret != QLA_SUCCESS) {
1381 ql_dbg(ql_dbg_user, vha, 0x709a,
1382 "Unable to program nvram address=%x data=%x.\n",
1388 /* Enable NVRAM write-protection. */
1389 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1391 /* Disable flash write. */
1392 WRT_REG_DWORD(®->ctrl_status,
1393 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
1394 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
1400 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1405 struct qla_hw_data *ha = vha->hw;
1407 /* Dword reads to flash. */
1408 dwptr = (uint32_t *)buf;
1409 for (i = 0; i < bytes >> 2; i++, naddr++)
1410 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1411 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1417 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1420 struct qla_hw_data *ha = vha->hw;
1421 #define RMW_BUFFER_SIZE (64 * 1024)
1424 dbuf = vmalloc(RMW_BUFFER_SIZE);
1426 return QLA_MEMORY_ALLOC_FAILED;
1427 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1429 memcpy(dbuf + (naddr << 2), buf, bytes);
1430 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1438 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1440 if (IS_QLA2322(ha)) {
1441 /* Flip all colors. */
1442 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1444 ha->beacon_color_state = 0;
1445 *pflags = GPIO_LED_ALL_OFF;
1448 ha->beacon_color_state = QLA_LED_ALL_ON;
1449 *pflags = GPIO_LED_RGA_ON;
1452 /* Flip green led only. */
1453 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1455 ha->beacon_color_state = 0;
1456 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1459 ha->beacon_color_state = QLA_LED_GRN_ON;
1460 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1465 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1468 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1470 uint16_t gpio_enable;
1472 uint16_t led_color = 0;
1473 unsigned long flags;
1474 struct qla_hw_data *ha = vha->hw;
1475 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1480 spin_lock_irqsave(&ha->hardware_lock, flags);
1482 /* Save the Original GPIOE. */
1483 if (ha->pio_address) {
1484 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1485 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1487 gpio_enable = RD_REG_WORD(®->gpioe);
1488 gpio_data = RD_REG_WORD(®->gpiod);
1491 /* Set the modified gpio_enable values */
1492 gpio_enable |= GPIO_LED_MASK;
1494 if (ha->pio_address) {
1495 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1497 WRT_REG_WORD(®->gpioe, gpio_enable);
1498 RD_REG_WORD(®->gpioe);
1501 qla2x00_flip_colors(ha, &led_color);
1503 /* Clear out any previously set LED color. */
1504 gpio_data &= ~GPIO_LED_MASK;
1506 /* Set the new input LED color to GPIOD. */
1507 gpio_data |= led_color;
1509 /* Set the modified gpio_data values */
1510 if (ha->pio_address) {
1511 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1513 WRT_REG_WORD(®->gpiod, gpio_data);
1514 RD_REG_WORD(®->gpiod);
1517 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1521 qla2x00_beacon_on(struct scsi_qla_host *vha)
1523 uint16_t gpio_enable;
1525 unsigned long flags;
1526 struct qla_hw_data *ha = vha->hw;
1527 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1529 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1530 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1532 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1533 ql_log(ql_log_warn, vha, 0x709b,
1534 "Unable to update fw options (beacon on).\n");
1535 return QLA_FUNCTION_FAILED;
1538 /* Turn off LEDs. */
1539 spin_lock_irqsave(&ha->hardware_lock, flags);
1540 if (ha->pio_address) {
1541 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1542 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1544 gpio_enable = RD_REG_WORD(®->gpioe);
1545 gpio_data = RD_REG_WORD(®->gpiod);
1547 gpio_enable |= GPIO_LED_MASK;
1549 /* Set the modified gpio_enable values. */
1550 if (ha->pio_address) {
1551 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1553 WRT_REG_WORD(®->gpioe, gpio_enable);
1554 RD_REG_WORD(®->gpioe);
1557 /* Clear out previously set LED colour. */
1558 gpio_data &= ~GPIO_LED_MASK;
1559 if (ha->pio_address) {
1560 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1562 WRT_REG_WORD(®->gpiod, gpio_data);
1563 RD_REG_WORD(®->gpiod);
1565 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1568 * Let the per HBA timer kick off the blinking process based on
1569 * the following flags. No need to do anything else now.
1571 ha->beacon_blink_led = 1;
1572 ha->beacon_color_state = 0;
1578 qla2x00_beacon_off(struct scsi_qla_host *vha)
1580 int rval = QLA_SUCCESS;
1581 struct qla_hw_data *ha = vha->hw;
1583 ha->beacon_blink_led = 0;
1585 /* Set the on flag so when it gets flipped it will be off. */
1587 ha->beacon_color_state = QLA_LED_ALL_ON;
1589 ha->beacon_color_state = QLA_LED_GRN_ON;
1591 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1593 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1594 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1596 rval = qla2x00_set_fw_options(vha, ha->fw_options);
1597 if (rval != QLA_SUCCESS)
1598 ql_log(ql_log_warn, vha, 0x709c,
1599 "Unable to update fw options (beacon off).\n");
1605 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1607 /* Flip all colors. */
1608 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1610 ha->beacon_color_state = 0;
1614 ha->beacon_color_state = QLA_LED_ALL_ON;
1615 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1620 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1622 uint16_t led_color = 0;
1624 unsigned long flags;
1625 struct qla_hw_data *ha = vha->hw;
1626 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1628 /* Save the Original GPIOD. */
1629 spin_lock_irqsave(&ha->hardware_lock, flags);
1630 gpio_data = RD_REG_DWORD(®->gpiod);
1632 /* Enable the gpio_data reg for update. */
1633 gpio_data |= GPDX_LED_UPDATE_MASK;
1635 WRT_REG_DWORD(®->gpiod, gpio_data);
1636 gpio_data = RD_REG_DWORD(®->gpiod);
1638 /* Set the color bits. */
1639 qla24xx_flip_colors(ha, &led_color);
1641 /* Clear out any previously set LED color. */
1642 gpio_data &= ~GPDX_LED_COLOR_MASK;
1644 /* Set the new input LED color to GPIOD. */
1645 gpio_data |= led_color;
1647 /* Set the modified gpio_data values. */
1648 WRT_REG_DWORD(®->gpiod, gpio_data);
1649 gpio_data = RD_REG_DWORD(®->gpiod);
1650 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1654 qla83xx_select_led_port(struct qla_hw_data *ha)
1656 uint32_t led_select_value = 0;
1658 if (!IS_QLA83XX(ha))
1661 if (ha->flags.port0)
1662 led_select_value = QLA83XX_LED_PORT0;
1664 led_select_value = QLA83XX_LED_PORT1;
1667 return led_select_value;
1671 qla83xx_beacon_blink(struct scsi_qla_host *vha)
1673 uint32_t led_select_value;
1674 struct qla_hw_data *ha = vha->hw;
1675 uint16_t led_cfg[6];
1676 uint16_t orig_led_cfg[6];
1677 uint32_t led_10_value, led_43_value;
1679 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha))
1682 if (!ha->beacon_blink_led)
1685 if (IS_QLA2031(ha)) {
1686 led_select_value = qla83xx_select_led_port(ha);
1688 qla83xx_wr_reg(vha, led_select_value, 0x40002000);
1689 qla83xx_wr_reg(vha, led_select_value + 4, 0x40002000);
1691 qla83xx_wr_reg(vha, led_select_value, 0x40004000);
1692 qla83xx_wr_reg(vha, led_select_value + 4, 0x40004000);
1693 } else if (IS_QLA8031(ha)) {
1694 led_select_value = qla83xx_select_led_port(ha);
1696 qla83xx_rd_reg(vha, led_select_value, &led_10_value);
1697 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value);
1698 qla83xx_wr_reg(vha, led_select_value, 0x01f44000);
1700 qla83xx_wr_reg(vha, led_select_value, 0x400001f4);
1702 qla83xx_wr_reg(vha, led_select_value, led_10_value);
1703 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value);
1704 } else if (IS_QLA81XX(ha)) {
1708 rval = qla81xx_get_led_config(vha, orig_led_cfg);
1710 if (rval == QLA_SUCCESS) {
1711 if (IS_QLA81XX(ha)) {
1712 led_cfg[0] = 0x4000;
1713 led_cfg[1] = 0x2000;
1719 led_cfg[0] = 0x4000;
1720 led_cfg[1] = 0x4000;
1721 led_cfg[2] = 0x4000;
1722 led_cfg[3] = 0x2000;
1724 led_cfg[5] = 0x2000;
1726 rval = qla81xx_set_led_config(vha, led_cfg);
1728 if (IS_QLA81XX(ha)) {
1729 led_cfg[0] = 0x4000;
1730 led_cfg[1] = 0x2000;
1733 led_cfg[0] = 0x4000;
1734 led_cfg[1] = 0x2000;
1735 led_cfg[2] = 0x4000;
1736 led_cfg[3] = 0x4000;
1738 led_cfg[5] = 0x2000;
1740 rval = qla81xx_set_led_config(vha, led_cfg);
1742 /* On exit, restore original (presumes no status change) */
1743 qla81xx_set_led_config(vha, orig_led_cfg);
1748 qla24xx_beacon_on(struct scsi_qla_host *vha)
1751 unsigned long flags;
1752 struct qla_hw_data *ha = vha->hw;
1753 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1758 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1759 goto skip_gpio; /* let blink handle it */
1761 if (ha->beacon_blink_led == 0) {
1762 /* Enable firmware for update */
1763 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1765 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1766 return QLA_FUNCTION_FAILED;
1768 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1770 ql_log(ql_log_warn, vha, 0x7009,
1771 "Unable to update fw options (beacon on).\n");
1772 return QLA_FUNCTION_FAILED;
1778 spin_lock_irqsave(&ha->hardware_lock, flags);
1779 gpio_data = RD_REG_DWORD(®->gpiod);
1781 /* Enable the gpio_data reg for update. */
1782 gpio_data |= GPDX_LED_UPDATE_MASK;
1783 WRT_REG_DWORD(®->gpiod, gpio_data);
1784 RD_REG_DWORD(®->gpiod);
1786 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1789 /* So all colors blink together. */
1790 ha->beacon_color_state = 0;
1793 /* Let the per HBA timer kick off the blinking process. */
1794 ha->beacon_blink_led = 1;
1800 qla24xx_beacon_off(struct scsi_qla_host *vha)
1803 unsigned long flags;
1804 struct qla_hw_data *ha = vha->hw;
1805 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1810 ha->beacon_blink_led = 0;
1813 goto set_fw_options;
1815 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1818 ha->beacon_color_state = QLA_LED_ALL_ON;
1820 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1822 /* Give control back to firmware. */
1823 spin_lock_irqsave(&ha->hardware_lock, flags);
1824 gpio_data = RD_REG_DWORD(®->gpiod);
1826 /* Disable the gpio_data reg for update. */
1827 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1828 WRT_REG_DWORD(®->gpiod, gpio_data);
1829 RD_REG_DWORD(®->gpiod);
1830 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1833 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1835 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1836 ql_log(ql_log_warn, vha, 0x704d,
1837 "Unable to update fw options (beacon on).\n");
1838 return QLA_FUNCTION_FAILED;
1841 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1842 ql_log(ql_log_warn, vha, 0x704e,
1843 "Unable to update fw options (beacon on).\n");
1844 return QLA_FUNCTION_FAILED;
1852 * Flash support routines
1856 * qla2x00_flash_enable() - Setup flash for reading and writing.
1860 qla2x00_flash_enable(struct qla_hw_data *ha)
1863 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1865 data = RD_REG_WORD(®->ctrl_status);
1866 data |= CSR_FLASH_ENABLE;
1867 WRT_REG_WORD(®->ctrl_status, data);
1868 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1872 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1876 qla2x00_flash_disable(struct qla_hw_data *ha)
1879 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1881 data = RD_REG_WORD(®->ctrl_status);
1882 data &= ~(CSR_FLASH_ENABLE);
1883 WRT_REG_WORD(®->ctrl_status, data);
1884 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1888 * qla2x00_read_flash_byte() - Reads a byte from flash
1890 * @addr: Address in flash to read
1892 * A word is read from the chip, but, only the lower byte is valid.
1894 * Returns the byte read from flash @addr.
1897 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1900 uint16_t bank_select;
1901 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1903 bank_select = RD_REG_WORD(®->ctrl_status);
1905 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1906 /* Specify 64K address range: */
1907 /* clear out Module Select and Flash Address bits [19:16]. */
1908 bank_select &= ~0xf8;
1909 bank_select |= addr >> 12 & 0xf0;
1910 bank_select |= CSR_FLASH_64K_BANK;
1911 WRT_REG_WORD(®->ctrl_status, bank_select);
1912 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1914 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1915 data = RD_REG_WORD(®->flash_data);
1917 return (uint8_t)data;
1920 /* Setup bit 16 of flash address. */
1921 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1922 bank_select |= CSR_FLASH_64K_BANK;
1923 WRT_REG_WORD(®->ctrl_status, bank_select);
1924 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1925 } else if (((addr & BIT_16) == 0) &&
1926 (bank_select & CSR_FLASH_64K_BANK)) {
1927 bank_select &= ~(CSR_FLASH_64K_BANK);
1928 WRT_REG_WORD(®->ctrl_status, bank_select);
1929 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1932 /* Always perform IO mapped accesses to the FLASH registers. */
1933 if (ha->pio_address) {
1936 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1938 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1941 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1942 } while (data != data2);
1944 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1945 data = qla2x00_debounce_register(®->flash_data);
1948 return (uint8_t)data;
1952 * qla2x00_write_flash_byte() - Write a byte to flash
1954 * @addr: Address in flash to write
1955 * @data: Data to write
1958 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1960 uint16_t bank_select;
1961 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1963 bank_select = RD_REG_WORD(®->ctrl_status);
1964 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1965 /* Specify 64K address range: */
1966 /* clear out Module Select and Flash Address bits [19:16]. */
1967 bank_select &= ~0xf8;
1968 bank_select |= addr >> 12 & 0xf0;
1969 bank_select |= CSR_FLASH_64K_BANK;
1970 WRT_REG_WORD(®->ctrl_status, bank_select);
1971 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1973 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1974 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1975 WRT_REG_WORD(®->flash_data, (uint16_t)data);
1976 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1981 /* Setup bit 16 of flash address. */
1982 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1983 bank_select |= CSR_FLASH_64K_BANK;
1984 WRT_REG_WORD(®->ctrl_status, bank_select);
1985 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1986 } else if (((addr & BIT_16) == 0) &&
1987 (bank_select & CSR_FLASH_64K_BANK)) {
1988 bank_select &= ~(CSR_FLASH_64K_BANK);
1989 WRT_REG_WORD(®->ctrl_status, bank_select);
1990 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
1993 /* Always perform IO mapped accesses to the FLASH registers. */
1994 if (ha->pio_address) {
1995 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1996 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1998 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1999 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
2000 WRT_REG_WORD(®->flash_data, (uint16_t)data);
2001 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */
2006 * qla2x00_poll_flash() - Polls flash for completion.
2008 * @addr: Address in flash to poll
2009 * @poll_data: Data to be polled
2010 * @man_id: Flash manufacturer ID
2011 * @flash_id: Flash ID
2013 * This function polls the device until bit 7 of what is read matches data
2014 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
2015 * out (a fatal error). The flash book recommeds reading bit 7 again after
2016 * reading bit 5 as a 1.
2018 * Returns 0 on success, else non-zero.
2021 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
2022 uint8_t man_id, uint8_t flash_id)
2030 /* Wait for 30 seconds for command to finish. */
2032 for (cnt = 3000000; cnt; cnt--) {
2033 flash_data = qla2x00_read_flash_byte(ha, addr);
2034 if ((flash_data & BIT_7) == poll_data) {
2039 if (man_id != 0x40 && man_id != 0xda) {
2040 if ((flash_data & BIT_5) && cnt > 2)
2051 * qla2x00_program_flash_address() - Programs a flash address
2053 * @addr: Address in flash to program
2054 * @data: Data to be written in flash
2055 * @man_id: Flash manufacturer ID
2056 * @flash_id: Flash ID
2058 * Returns 0 on success, else non-zero.
2061 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
2062 uint8_t data, uint8_t man_id, uint8_t flash_id)
2064 /* Write Program Command Sequence. */
2065 if (IS_OEM_001(ha)) {
2066 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2067 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2068 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
2069 qla2x00_write_flash_byte(ha, addr, data);
2071 if (man_id == 0xda && flash_id == 0xc1) {
2072 qla2x00_write_flash_byte(ha, addr, data);
2076 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2077 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2078 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
2079 qla2x00_write_flash_byte(ha, addr, data);
2085 /* Wait for write to complete. */
2086 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
2090 * qla2x00_erase_flash() - Erase the flash.
2092 * @man_id: Flash manufacturer ID
2093 * @flash_id: Flash ID
2095 * Returns 0 on success, else non-zero.
2098 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
2100 /* Individual Sector Erase Command Sequence */
2101 if (IS_OEM_001(ha)) {
2102 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2103 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2104 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
2105 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2106 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2107 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
2109 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2110 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2111 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2112 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2113 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2114 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
2119 /* Wait for erase to complete. */
2120 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
2124 * qla2x00_erase_flash_sector() - Erase a flash sector.
2126 * @addr: Flash sector to erase
2127 * @sec_mask: Sector address mask
2128 * @man_id: Flash manufacturer ID
2129 * @flash_id: Flash ID
2131 * Returns 0 on success, else non-zero.
2134 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
2135 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
2137 /* Individual Sector Erase Command Sequence */
2138 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2139 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2140 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2141 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2142 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2143 if (man_id == 0x1f && flash_id == 0x13)
2144 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
2146 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
2150 /* Wait for erase to complete. */
2151 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
2155 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2156 * @man_id: Flash manufacturer ID
2157 * @flash_id: Flash ID
2160 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
2163 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2164 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2165 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
2166 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
2167 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
2168 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2169 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2170 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
2174 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
2175 uint32_t saddr, uint32_t length)
2177 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2178 uint32_t midpoint, ilength;
2181 midpoint = length / 2;
2183 WRT_REG_WORD(®->nvram, 0);
2184 RD_REG_WORD(®->nvram);
2185 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2186 if (ilength == midpoint) {
2187 WRT_REG_WORD(®->nvram, NVR_SELECT);
2188 RD_REG_WORD(®->nvram);
2190 data = qla2x00_read_flash_byte(ha, saddr);
2199 qla2x00_suspend_hba(struct scsi_qla_host *vha)
2202 unsigned long flags;
2203 struct qla_hw_data *ha = vha->hw;
2204 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2207 scsi_block_requests(vha->host);
2208 ha->isp_ops->disable_intrs(ha);
2209 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2212 spin_lock_irqsave(&ha->hardware_lock, flags);
2213 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
2214 RD_REG_WORD(®->hccr);
2215 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2216 for (cnt = 0; cnt < 30000; cnt++) {
2217 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0)
2224 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2228 qla2x00_resume_hba(struct scsi_qla_host *vha)
2230 struct qla_hw_data *ha = vha->hw;
2233 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2234 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2235 qla2xxx_wake_dpc(vha);
2236 qla2x00_wait_for_chip_reset(vha);
2237 scsi_unblock_requests(vha->host);
2241 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2242 uint32_t offset, uint32_t length)
2244 uint32_t addr, midpoint;
2246 struct qla_hw_data *ha = vha->hw;
2247 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2250 qla2x00_suspend_hba(vha);
2253 midpoint = ha->optrom_size / 2;
2255 qla2x00_flash_enable(ha);
2256 WRT_REG_WORD(®->nvram, 0);
2257 RD_REG_WORD(®->nvram); /* PCI Posting. */
2258 for (addr = offset, data = buf; addr < length; addr++, data++) {
2259 if (addr == midpoint) {
2260 WRT_REG_WORD(®->nvram, NVR_SELECT);
2261 RD_REG_WORD(®->nvram); /* PCI Posting. */
2264 *data = qla2x00_read_flash_byte(ha, addr);
2266 qla2x00_flash_disable(ha);
2269 qla2x00_resume_hba(vha);
2275 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2276 uint32_t offset, uint32_t length)
2280 uint8_t man_id, flash_id, sec_number, data;
2282 uint32_t addr, liter, sec_mask, rest_addr;
2283 struct qla_hw_data *ha = vha->hw;
2284 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2287 qla2x00_suspend_hba(vha);
2292 /* Reset ISP chip. */
2293 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
2294 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2296 /* Go with write. */
2297 qla2x00_flash_enable(ha);
2298 do { /* Loop once to provide quick error exit */
2299 /* Structure of flash memory based on manufacturer */
2300 if (IS_OEM_001(ha)) {
2301 /* OEM variant with special flash part. */
2302 man_id = flash_id = 0;
2307 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2309 case 0x20: /* ST flash. */
2310 if (flash_id == 0xd2 || flash_id == 0xe3) {
2312 * ST m29w008at part - 64kb sector size with
2313 * 32kb,8kb,8kb,16kb sectors at memory address
2321 * ST m29w010b part - 16kb sector size
2322 * Default to 16kb sectors
2327 case 0x40: /* Mostel flash. */
2328 /* Mostel v29c51001 part - 512 byte sector size. */
2332 case 0xbf: /* SST flash. */
2333 /* SST39sf10 part - 4kb sector size. */
2337 case 0xda: /* Winbond flash. */
2338 /* Winbond W29EE011 part - 256 byte sector size. */
2342 case 0xc2: /* Macronix flash. */
2343 /* 64k sector size. */
2344 if (flash_id == 0x38 || flash_id == 0x4f) {
2349 /* Fall through... */
2351 case 0x1f: /* Atmel flash. */
2352 /* 512k sector size. */
2353 if (flash_id == 0x13) {
2354 rest_addr = 0x7fffffff;
2355 sec_mask = 0x80000000;
2358 /* Fall through... */
2360 case 0x01: /* AMD flash. */
2361 if (flash_id == 0x38 || flash_id == 0x40 ||
2363 /* Am29LV081 part - 64kb sector size. */
2364 /* Am29LV002BT part - 64kb sector size. */
2368 } else if (flash_id == 0x3e) {
2370 * Am29LV008b part - 64kb sector size with
2371 * 32kb,8kb,8kb,16kb sector at memory address
2377 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2379 * Am29LV010 part or AM29f010 - 16kb sector
2385 } else if (flash_id == 0x6d) {
2386 /* Am29LV001 part - 8kb sector size. */
2392 /* Default to 16 kb sector size. */
2399 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2400 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2401 rval = QLA_FUNCTION_FAILED;
2406 for (addr = offset, liter = 0; liter < length; liter++,
2409 /* Are we at the beginning of a sector? */
2410 if ((addr & rest_addr) == 0) {
2411 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2412 if (addr >= 0x10000UL) {
2413 if (((addr >> 12) & 0xf0) &&
2415 flash_id == 0x3e) ||
2417 flash_id == 0xd2))) {
2419 if (sec_number == 1) {
2440 } else if (addr == ha->optrom_size / 2) {
2441 WRT_REG_WORD(®->nvram, NVR_SELECT);
2442 RD_REG_WORD(®->nvram);
2445 if (flash_id == 0xda && man_id == 0xc1) {
2446 qla2x00_write_flash_byte(ha, 0x5555,
2448 qla2x00_write_flash_byte(ha, 0x2aaa,
2450 qla2x00_write_flash_byte(ha, 0x5555,
2452 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2454 if (qla2x00_erase_flash_sector(ha,
2455 addr, sec_mask, man_id,
2457 rval = QLA_FUNCTION_FAILED;
2460 if (man_id == 0x01 && flash_id == 0x6d)
2465 if (man_id == 0x01 && flash_id == 0x6d) {
2466 if (sec_number == 1 &&
2467 addr == (rest_addr - 1)) {
2470 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2476 if (qla2x00_program_flash_address(ha, addr, data,
2477 man_id, flash_id)) {
2478 rval = QLA_FUNCTION_FAILED;
2484 qla2x00_flash_disable(ha);
2487 qla2x00_resume_hba(vha);
2493 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2494 uint32_t offset, uint32_t length)
2496 struct qla_hw_data *ha = vha->hw;
2499 scsi_block_requests(vha->host);
2500 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2503 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2506 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2507 scsi_unblock_requests(vha->host);
2513 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2514 uint32_t offset, uint32_t length)
2517 struct qla_hw_data *ha = vha->hw;
2520 scsi_block_requests(vha->host);
2521 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2523 /* Go with write. */
2524 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2527 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2528 scsi_unblock_requests(vha->host);
2534 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2535 uint32_t offset, uint32_t length)
2538 dma_addr_t optrom_dma;
2541 uint32_t faddr, left, burst;
2542 struct qla_hw_data *ha = vha->hw;
2544 if (IS_QLA25XX(ha) || IS_QLA81XX(ha))
2548 if (length < OPTROM_BURST_SIZE)
2552 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2553 &optrom_dma, GFP_KERNEL);
2555 ql_log(ql_log_warn, vha, 0x00cc,
2556 "Unable to allocate memory for optrom burst read (%x KB).\n",
2557 OPTROM_BURST_SIZE / 1024);
2562 faddr = offset >> 2;
2564 burst = OPTROM_BURST_DWORDS;
2569 rval = qla2x00_dump_ram(vha, optrom_dma,
2570 flash_data_addr(ha, faddr), burst);
2572 ql_log(ql_log_warn, vha, 0x00f5,
2573 "Unable to burst-read optrom segment (%x/%x/%llx).\n",
2574 rval, flash_data_addr(ha, faddr),
2575 (unsigned long long)optrom_dma);
2576 ql_log(ql_log_warn, vha, 0x00f6,
2577 "Reverting to slow-read.\n");
2579 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2580 optrom, optrom_dma);
2584 memcpy(pbuf, optrom, burst * 4);
2591 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2597 return qla24xx_read_optrom_data(vha, buf, offset, length);
2601 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2603 * @pcids: Pointer to the FCODE PCI data structure
2605 * The process of retrieving the FCODE version information is at best
2606 * described as interesting.
2608 * Within the first 100h bytes of the image an ASCII string is present
2609 * which contains several pieces of information including the FCODE
2610 * version. Unfortunately it seems the only reliable way to retrieve
2611 * the version is by scanning for another sentinel within the string,
2612 * the FCODE build date:
2614 * ... 2.00.02 10/17/02 ...
2616 * Returns QLA_SUCCESS on successful retrieval of version.
2619 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2621 int ret = QLA_FUNCTION_FAILED;
2622 uint32_t istart, iend, iter, vend;
2623 uint8_t do_next, rbyte, *vbyte;
2625 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2627 /* Skip the PCI data structure. */
2629 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2630 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2631 iend = istart + 0x100;
2633 /* Scan for the sentinel date string...eeewww. */
2636 while ((iter < iend) && !do_next) {
2638 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2639 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2642 else if (qla2x00_read_flash_byte(ha,
2650 /* Backtrack to previous ' ' (space). */
2652 while ((iter > istart) && !do_next) {
2654 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2661 * Mark end of version tag, and find previous ' ' (space) or
2662 * string length (recent FCODE images -- major hack ahead!!!).
2666 while ((iter > istart) && !do_next) {
2668 rbyte = qla2x00_read_flash_byte(ha, iter);
2669 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2675 /* Mark beginning of version tag, and copy data. */
2677 if ((vend - iter) &&
2678 ((vend - iter) < sizeof(ha->fcode_revision))) {
2679 vbyte = ha->fcode_revision;
2680 while (iter <= vend) {
2681 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2688 if (ret != QLA_SUCCESS)
2689 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2693 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2695 int ret = QLA_SUCCESS;
2696 uint8_t code_type, last_image;
2697 uint32_t pcihdr, pcids;
2700 struct qla_hw_data *ha = vha->hw;
2702 if (!ha->pio_address || !mbuf)
2703 return QLA_FUNCTION_FAILED;
2705 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2706 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2707 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2708 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2710 qla2x00_flash_enable(ha);
2712 /* Begin with first PCI expansion ROM header. */
2716 /* Verify PCI expansion ROM header. */
2717 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2718 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2720 ql_log(ql_log_fatal, vha, 0x0050,
2721 "No matching ROM signature.\n");
2722 ret = QLA_FUNCTION_FAILED;
2726 /* Locate PCI data structure. */
2728 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2729 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2731 /* Validate signature of PCI data structure. */
2732 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2733 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2734 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2735 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2736 /* Incorrect header. */
2737 ql_log(ql_log_fatal, vha, 0x0051,
2738 "PCI data struct not found pcir_adr=%x.\n", pcids);
2739 ret = QLA_FUNCTION_FAILED;
2744 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2745 switch (code_type) {
2746 case ROM_CODE_TYPE_BIOS:
2747 /* Intel x86, PC-AT compatible. */
2748 ha->bios_revision[0] =
2749 qla2x00_read_flash_byte(ha, pcids + 0x12);
2750 ha->bios_revision[1] =
2751 qla2x00_read_flash_byte(ha, pcids + 0x13);
2752 ql_dbg(ql_dbg_init, vha, 0x0052,
2753 "Read BIOS %d.%d.\n",
2754 ha->bios_revision[1], ha->bios_revision[0]);
2756 case ROM_CODE_TYPE_FCODE:
2757 /* Open Firmware standard for PCI (FCode). */
2759 qla2x00_get_fcode_version(ha, pcids);
2761 case ROM_CODE_TYPE_EFI:
2762 /* Extensible Firmware Interface (EFI). */
2763 ha->efi_revision[0] =
2764 qla2x00_read_flash_byte(ha, pcids + 0x12);
2765 ha->efi_revision[1] =
2766 qla2x00_read_flash_byte(ha, pcids + 0x13);
2767 ql_dbg(ql_dbg_init, vha, 0x0053,
2768 "Read EFI %d.%d.\n",
2769 ha->efi_revision[1], ha->efi_revision[0]);
2772 ql_log(ql_log_warn, vha, 0x0054,
2773 "Unrecognized code type %x at pcids %x.\n",
2778 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2780 /* Locate next PCI expansion ROM. */
2781 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2782 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2783 } while (!last_image);
2785 if (IS_QLA2322(ha)) {
2786 /* Read firmware image information. */
2787 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2789 memset(dbyte, 0, 8);
2790 dcode = (uint16_t *)dbyte;
2792 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2794 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a,
2796 "ver from flash:.\n");
2797 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
2798 (uint8_t *)dbyte, 8);
2800 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2801 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2802 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2804 ql_log(ql_log_warn, vha, 0x0057,
2805 "Unrecognized fw revision at %x.\n",
2806 ha->flt_region_fw * 4);
2808 /* values are in big endian */
2809 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2810 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2811 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2812 ql_dbg(ql_dbg_init, vha, 0x0058,
2814 "%d.%d.%d.\n", ha->fw_revision[0],
2815 ha->fw_revision[1], ha->fw_revision[2]);
2819 qla2x00_flash_disable(ha);
2825 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2827 int ret = QLA_SUCCESS;
2828 uint32_t pcihdr, pcids;
2831 uint8_t code_type, last_image;
2833 struct qla_hw_data *ha = vha->hw;
2839 return QLA_FUNCTION_FAILED;
2841 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2842 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2843 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2844 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2848 /* Begin with first PCI expansion ROM header. */
2849 pcihdr = ha->flt_region_boot << 2;
2852 /* Verify PCI expansion ROM header. */
2853 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2854 bcode = mbuf + (pcihdr % 4);
2855 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2857 ql_log(ql_log_fatal, vha, 0x0059,
2858 "No matching ROM signature.\n");
2859 ret = QLA_FUNCTION_FAILED;
2863 /* Locate PCI data structure. */
2864 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2866 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2867 bcode = mbuf + (pcihdr % 4);
2869 /* Validate signature of PCI data structure. */
2870 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2871 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2872 /* Incorrect header. */
2873 ql_log(ql_log_fatal, vha, 0x005a,
2874 "PCI data struct not found pcir_adr=%x.\n", pcids);
2875 ret = QLA_FUNCTION_FAILED;
2880 code_type = bcode[0x14];
2881 switch (code_type) {
2882 case ROM_CODE_TYPE_BIOS:
2883 /* Intel x86, PC-AT compatible. */
2884 ha->bios_revision[0] = bcode[0x12];
2885 ha->bios_revision[1] = bcode[0x13];
2886 ql_dbg(ql_dbg_init, vha, 0x005b,
2887 "Read BIOS %d.%d.\n",
2888 ha->bios_revision[1], ha->bios_revision[0]);
2890 case ROM_CODE_TYPE_FCODE:
2891 /* Open Firmware standard for PCI (FCode). */
2892 ha->fcode_revision[0] = bcode[0x12];
2893 ha->fcode_revision[1] = bcode[0x13];
2894 ql_dbg(ql_dbg_init, vha, 0x005c,
2895 "Read FCODE %d.%d.\n",
2896 ha->fcode_revision[1], ha->fcode_revision[0]);
2898 case ROM_CODE_TYPE_EFI:
2899 /* Extensible Firmware Interface (EFI). */
2900 ha->efi_revision[0] = bcode[0x12];
2901 ha->efi_revision[1] = bcode[0x13];
2902 ql_dbg(ql_dbg_init, vha, 0x005d,
2903 "Read EFI %d.%d.\n",
2904 ha->efi_revision[1], ha->efi_revision[0]);
2907 ql_log(ql_log_warn, vha, 0x005e,
2908 "Unrecognized code type %x at pcids %x.\n",
2913 last_image = bcode[0x15] & BIT_7;
2915 /* Locate next PCI expansion ROM. */
2916 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2917 } while (!last_image);
2919 /* Read firmware image information. */
2920 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2923 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2924 for (i = 0; i < 4; i++)
2925 dcode[i] = be32_to_cpu(dcode[i]);
2927 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2928 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2929 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2931 ql_log(ql_log_warn, vha, 0x005f,
2932 "Unrecognized fw revision at %x.\n",
2933 ha->flt_region_fw * 4);
2935 ha->fw_revision[0] = dcode[0];
2936 ha->fw_revision[1] = dcode[1];
2937 ha->fw_revision[2] = dcode[2];
2938 ha->fw_revision[3] = dcode[3];
2939 ql_dbg(ql_dbg_init, vha, 0x0060,
2940 "Firmware revision %d.%d.%d.%d.\n",
2941 ha->fw_revision[0], ha->fw_revision[1],
2942 ha->fw_revision[2], ha->fw_revision[3]);
2945 /* Check for golden firmware and get version if available */
2946 if (!IS_QLA81XX(ha)) {
2947 /* Golden firmware is not present in non 81XX adapters */
2951 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
2953 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode,
2954 ha->flt_region_gold_fw << 2, 32);
2956 if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF &&
2957 dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) {
2958 ql_log(ql_log_warn, vha, 0x0056,
2959 "Unrecognized golden fw at 0x%x.\n",
2960 ha->flt_region_gold_fw * 4);
2964 for (i = 4; i < 8; i++)
2965 ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]);
2971 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2973 if (pos >= end || *pos != 0x82)
2977 if (pos >= end || *pos != 0x90)
2981 if (pos >= end || *pos != 0x78)
2988 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2990 struct qla_hw_data *ha = vha->hw;
2991 uint8_t *pos = ha->vpd;
2992 uint8_t *end = pos + ha->vpd_size;
2995 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2998 while (pos < end && *pos != 0x78) {
2999 len = (*pos == 0x82) ? pos[1] : pos[2];
3001 if (!strncmp(pos, key, strlen(key)))
3004 if (*pos != 0x90 && *pos != 0x91)
3010 if (pos < end - len && *pos != 0x78)
3011 return snprintf(str, size, "%.*s", len, pos + 3);
3017 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
3020 uint32_t fcp_prio_addr;
3021 struct qla_hw_data *ha = vha->hw;
3023 if (!ha->fcp_prio_cfg) {
3024 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
3025 if (!ha->fcp_prio_cfg) {
3026 ql_log(ql_log_warn, vha, 0x00d5,
3027 "Unable to allocate memory for fcp priorty data (%x).\n",
3029 return QLA_FUNCTION_FAILED;
3032 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
3034 fcp_prio_addr = ha->flt_region_fcp_prio;
3036 /* first read the fcp priority data header from flash */
3037 ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
3038 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
3040 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
3043 /* read remaining FCP CMD config data from flash */
3044 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
3045 len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
3046 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
3048 ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
3049 fcp_prio_addr << 2, (len < max_len ? len : max_len));
3051 /* revalidate the entire FCP priority config data, including entries */
3052 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1))
3055 ha->flags.fcp_prio_enabled = 1;
3058 vfree(ha->fcp_prio_cfg);
3059 ha->fcp_prio_cfg = NULL;
3060 return QLA_FUNCTION_FAILED;