2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
5 * See LICENSE.qla4xxx for copyright and licensing details.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/module.h>
15 #include <linux/list.h>
16 #include <linux/pci.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/sched.h>
19 #include <linux/slab.h>
20 #include <linux/dmapool.h>
21 #include <linux/mempool.h>
22 #include <linux/spinlock.h>
23 #include <linux/workqueue.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/mutex.h>
27 #include <linux/aer.h>
30 #include <scsi/scsi.h>
31 #include <scsi/scsi_host.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_cmnd.h>
34 #include <scsi/scsi_transport.h>
35 #include <scsi/scsi_transport_iscsi.h>
40 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
41 #define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
44 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
45 #define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
48 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
49 #define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
52 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
53 #define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
56 #define ISP4XXX_PCI_FN_1 0x1
57 #define ISP4XXX_PCI_FN_2 0x3
63 * Data bit definitions
81 #define BIT_16 0x10000
82 #define BIT_17 0x20000
83 #define BIT_18 0x40000
84 #define BIT_19 0x80000
85 #define BIT_20 0x100000
86 #define BIT_21 0x200000
87 #define BIT_22 0x400000
88 #define BIT_23 0x800000
89 #define BIT_24 0x1000000
90 #define BIT_25 0x2000000
91 #define BIT_26 0x4000000
92 #define BIT_27 0x8000000
93 #define BIT_28 0x10000000
94 #define BIT_29 0x20000000
95 #define BIT_30 0x40000000
96 #define BIT_31 0x80000000
99 * Macros to help code, maintain, etc.
101 #define ql4_printk(level, ha, format, arg...) \
102 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
106 * Host adapter default definitions
107 ***********************************/
110 #define MAX_TARGETS MAX_DEV_DB_ENTRIES
111 #define MAX_LUNS 0xffff
112 #define MAX_AEN_ENTRIES 256 /* should be > EXT_DEF_MAX_AEN_QUEUE */
113 #define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
114 #define MAX_PDU_ENTRIES 32
115 #define INVALID_ENTRY 0xFFFF
116 #define MAX_CMDS_TO_RISC 1024
117 #define MAX_SRBS MAX_CMDS_TO_RISC
118 #define MBOX_AEN_REG_COUNT 8
119 #define MAX_INIT_RETRIES 5
124 #define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
125 #define RESPONSE_QUEUE_DEPTH 64
126 #define QUEUE_SIZE 64
127 #define DMA_BUFFER_SIZE 512
132 #define MAC_ADDR_LEN 6 /* in bytes */
133 #define IP_ADDR_LEN 4 /* in bytes */
134 #define IPv6_ADDR_LEN 16 /* IPv6 address size */
135 #define DRIVER_NAME "qla4xxx"
137 #define MAX_LINKED_CMDS_PER_LUN 3
138 #define MAX_REQS_SERVICED_PER_INTR 1
140 #define ISCSI_IPADDR_SIZE 4 /* IP address size */
141 #define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
142 #define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
144 #define QL4_SESS_RECOVERY_TMO 30 /* iSCSI session */
145 /* recovery timeout */
147 #define LSDW(x) ((u32)((u64)(x)))
148 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
151 * Retry & Timeout Values
154 #define SOFT_RESET_TOV 30
155 #define RESET_INTR_TOV 3
156 #define SEMAPHORE_TOV 10
157 #define ADAPTER_INIT_TOV 30
158 #define ADAPTER_RESET_TOV 180
159 #define EXTEND_CMD_TOV 60
160 #define WAIT_CMD_TOV 30
161 #define EH_WAIT_CMD_TOV 120
162 #define FIRMWARE_UP_TOV 60
163 #define RESET_FIRMWARE_TOV 30
164 #define LOGOUT_TOV 10
165 #define IOCB_TOV_MARGIN 10
166 #define RELOGIN_TOV 18
167 #define ISNS_DEREG_TOV 5
168 #define HBA_ONLINE_TOV 30
170 #define MAX_RESET_HA_RETRIES 2
172 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
175 * SCSI Request Block structure (srb) that is placed
176 * on cmd->SCp location of every I/O [We have 22 bytes available]
179 struct list_head list; /* (8) */
180 struct scsi_qla_host *ha; /* HA the SP is queued on */
181 struct ddb_entry *ddb;
182 uint16_t flags; /* (1) Status flags. */
184 #define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
185 #define SRB_GOT_SENSE BIT_4 /* sense data received. */
186 uint8_t state; /* (1) Status flags. */
188 #define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
189 #define SRB_FREE_STATE 1
190 #define SRB_ACTIVE_STATE 3
191 #define SRB_ACTIVE_TIMEOUT_STATE 4
192 #define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
194 struct scsi_cmnd *cmd; /* (4) SCSI command block */
195 dma_addr_t dma_handle; /* (4) for unmap of single transfers */
196 struct kref srb_ref; /* reference count for this srb */
197 uint8_t err_id; /* error id */
198 #define SRB_ERR_PORT 1 /* Request failed because "port down" */
199 #define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
200 #define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
201 #define SRB_ERR_OTHER 4
205 uint16_t iocb_cnt; /* Number of used iocbs */
208 /* Used for extended sense / status continuation */
209 uint8_t *req_sense_ptr;
210 uint16_t req_sense_len;
215 * Asynchronous Event Queue structure
218 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
223 struct aen entry[MAX_AEN_ENTRIES];
227 * Device Database (DDB) structure
230 struct list_head list; /* ddb list */
231 struct scsi_qla_host *ha;
232 struct iscsi_cls_session *sess;
233 struct iscsi_cls_conn *conn;
235 atomic_t state; /* DDB State */
237 unsigned long flags; /* DDB Flags */
239 uint16_t fw_ddb_index; /* DDB firmware index */
241 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
244 uint16_t target_session_id;
245 uint16_t connection_id;
246 uint16_t exe_throttle; /* Max mumber of cmds outstanding
248 uint16_t task_mgmt_timeout; /* Min time for task mgmt cmds to
250 uint16_t default_relogin_timeout; /* Max time to wait for
251 * relogin to complete */
252 uint16_t tcp_source_port_num;
253 uint32_t default_time2wait; /* Default Min time between
254 * relogins (+aens) */
256 atomic_t retry_relogin_timer; /* Min Time between relogins
258 atomic_t relogin_timer; /* Max Time to wait for relogin to complete */
259 atomic_t relogin_retry_count; /* Num of times relogin has been
264 uint8_t ip_addr[IP_ADDR_LEN];
265 uint8_t iscsi_name[ISCSI_NAME_SIZE]; /* 72 x48 */
266 uint8_t iscsi_alias[0x20];
268 uint16_t iscsi_max_burst_len;
269 uint16_t iscsi_max_outsnd_r2t;
270 uint16_t iscsi_first_burst_len;
271 uint16_t iscsi_max_rcv_data_seg_len;
272 uint16_t iscsi_max_snd_data_seg_len;
274 struct in6_addr remote_ipv6_addr;
275 struct in6_addr link_local_ipv6_addr;
281 #define DDB_STATE_DEAD 0 /* We can no longer talk to
283 #define DDB_STATE_ONLINE 1 /* Device ready to accept
285 #define DDB_STATE_MISSING 2 /* Device logged off, trying
291 #define DF_RELOGIN 0 /* Relogin to device */
292 #define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
293 #define DF_FO_MASKED 3
297 #include "ql4_nvram.h"
299 struct ql82xx_hw_data {
300 /* Offsets for flash/nvram access (set to ~0 if not used). */
301 uint32_t flash_conf_off;
302 uint32_t flash_data_off;
304 uint32_t fdt_wrt_disable;
305 uint32_t fdt_erase_cmd;
306 uint32_t fdt_block_size;
307 uint32_t fdt_unprotect_sec_cmd;
308 uint32_t fdt_protect_sec_cmd;
310 uint32_t flt_region_flt;
311 uint32_t flt_region_fdt;
312 uint32_t flt_region_boot;
313 uint32_t flt_region_bootload;
314 uint32_t flt_region_fw;
318 struct qla4_8xxx_legacy_intr_set {
319 uint32_t int_vec_bit;
320 uint32_t tgt_status_reg;
321 uint32_t tgt_mask_reg;
322 uint32_t pci_int_reg;
327 #define QLA_MSIX_DEFAULT 0x00
328 #define QLA_MSIX_RSP_Q 0x01
330 #define QLA_MSIX_ENTRIES 2
331 #define QLA_MIDX_DEFAULT 0
332 #define QLA_MIDX_RSP_Q 1
334 struct ql4_msix_entry {
336 uint16_t msix_vector;
343 struct isp_operations {
344 int (*iospace_config) (struct scsi_qla_host *ha);
345 void (*pci_config) (struct scsi_qla_host *);
346 void (*disable_intrs) (struct scsi_qla_host *);
347 void (*enable_intrs) (struct scsi_qla_host *);
348 int (*start_firmware) (struct scsi_qla_host *);
349 irqreturn_t (*intr_handler) (int , void *);
350 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
351 int (*reset_chip) (struct scsi_qla_host *);
352 int (*reset_firmware) (struct scsi_qla_host *);
353 void (*queue_iocb) (struct scsi_qla_host *);
354 void (*complete_iocb) (struct scsi_qla_host *);
355 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
356 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
357 int (*get_sys_info) (struct scsi_qla_host *);
360 /*qla4xxx ipaddress configuration details */
361 struct ipaddress_config {
362 uint16_t ipv4_options;
363 uint16_t tcp_options;
364 uint16_t ipv4_vlan_tag;
365 uint8_t ipv4_addr_state;
366 uint8_t ip_address[IP_ADDR_LEN];
367 uint8_t subnet_mask[IP_ADDR_LEN];
368 uint8_t gateway[IP_ADDR_LEN];
369 uint32_t ipv6_options;
370 uint32_t ipv6_addl_options;
371 uint8_t ipv6_link_local_state;
372 uint8_t ipv6_addr0_state;
373 uint8_t ipv6_addr1_state;
374 uint8_t ipv6_default_router_state;
375 uint16_t ipv6_vlan_tag;
376 struct in6_addr ipv6_link_local_addr;
377 struct in6_addr ipv6_addr0;
378 struct in6_addr ipv6_addr1;
379 struct in6_addr ipv6_default_router_addr;
383 * Linux Host Adapter structure
385 struct scsi_qla_host {
386 /* Linux adapter configuration data */
389 #define AF_ONLINE 0 /* 0x00000001 */
390 #define AF_INIT_DONE 1 /* 0x00000002 */
391 #define AF_MBOX_COMMAND 2 /* 0x00000004 */
392 #define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
393 #define AF_INTERRUPTS_ON 6 /* 0x00000040 */
394 #define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
395 #define AF_LINK_UP 8 /* 0x00000100 */
396 #define AF_IRQ_ATTACHED 10 /* 0x00000400 */
397 #define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
398 #define AF_HA_REMOVAL 12 /* 0x00001000 */
399 #define AF_INTx_ENABLED 15 /* 0x00008000 */
400 #define AF_MSI_ENABLED 16 /* 0x00010000 */
401 #define AF_MSIX_ENABLED 17 /* 0x00020000 */
402 #define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
403 #define AF_FW_RECOVERY 19 /* 0x00080000 */
404 #define AF_EEH_BUSY 20 /* 0x00100000 */
405 #define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
407 unsigned long dpc_flags;
409 #define DPC_RESET_HA 1 /* 0x00000002 */
410 #define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
411 #define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
412 #define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
413 #define DPC_RESET_HA_INTR 5 /* 0x00000020 */
414 #define DPC_ISNS_RESTART 7 /* 0x00000080 */
415 #define DPC_AEN 9 /* 0x00000200 */
416 #define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
417 #define DPC_LINK_CHANGED 18 /* 0x00040000 */
418 #define DPC_RESET_ACTIVE 20 /* 0x00040000 */
419 #define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/
420 #define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/
423 struct Scsi_Host *host; /* pointer to host data */
429 #define SRB_MIN_REQ 128
430 mempool_t *srb_mempool;
432 /* pci information */
433 struct pci_dev *pdev;
435 struct isp_reg __iomem *reg; /* Base I/O address */
436 unsigned long pio_address;
437 unsigned long pio_length;
438 #define MIN_IOBASE_LEN 0x100
440 uint16_t req_q_count;
442 unsigned long host_no;
444 /* NVRAM registers */
445 struct eeprom_data *nvram;
446 spinlock_t hardware_lock ____cacheline_aligned;
447 uint32_t eeprom_cmd_data;
449 /* Counters for general statistics */
451 uint64_t adapter_error_count;
452 uint64_t device_error_count;
453 uint64_t total_io_count;
454 uint64_t total_mbytes_xferred;
455 uint64_t link_failure_count;
456 uint64_t invalid_crc_count;
457 uint32_t bytes_xfered;
458 uint32_t spurious_int_count;
459 uint32_t aborted_io_count;
460 uint32_t io_timeout_count;
461 uint32_t mailbox_timeout_count;
462 uint32_t seconds_since_last_intr;
463 uint32_t seconds_since_last_heartbeat;
466 /* Info Needed for Management App */
467 /* --- From GetFwVersion --- */
468 uint32_t firmware_version[2];
469 uint32_t patch_number;
470 uint32_t build_number;
473 /* --- From Init_FW --- */
474 /* init_cb_t *init_cb; */
475 uint16_t firmware_options;
477 uint8_t name_string[256];
478 uint8_t heartbeat_interval;
480 /* --- From FlashSysInfo --- */
481 uint8_t my_mac[MAC_ADDR_LEN];
482 uint8_t serial_number[16];
484 /* --- From GetFwState --- */
485 uint32_t firmware_state;
486 uint32_t addl_fw_state;
488 /* Linux kernel thread */
489 struct workqueue_struct *dpc_thread;
490 struct work_struct dpc_work;
492 /* Linux timer thread */
493 struct timer_list timer;
494 uint32_t timer_active;
496 /* Recovery Timers */
497 atomic_t check_relogin_timeouts;
498 uint32_t retry_reset_ha_cnt;
499 uint32_t isp_reset_timer; /* reset test timer */
500 uint32_t nic_reset_timer; /* simulated nic reset test timer */
502 struct list_head free_srb_q;
503 uint16_t free_srb_q_count;
504 uint16_t num_srbs_allocated;
506 /* DMA Memory Block */
508 dma_addr_t queues_dma;
509 unsigned long queues_len;
511 #define MEM_ALIGN_VALUE \
512 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
513 sizeof(struct queue_entry))
514 /* request and response queue variables */
515 dma_addr_t request_dma;
516 struct queue_entry *request_ring;
517 struct queue_entry *request_ptr;
518 dma_addr_t response_dma;
519 struct queue_entry *response_ring;
520 struct queue_entry *response_ptr;
521 dma_addr_t shadow_regs_dma;
522 struct shadow_regs *shadow_regs;
523 uint16_t request_in; /* Current indexes. */
524 uint16_t request_out;
525 uint16_t response_in;
526 uint16_t response_out;
528 /* aen queue variables */
529 uint16_t aen_q_count; /* Number of available aen_q entries */
530 uint16_t aen_in; /* Current indexes */
532 struct aen aen_q[MAX_AEN_ENTRIES];
534 struct ql4_aen_log aen_log;/* tracks all aens */
536 /* This mutex protects several threads to do mailbox commands
539 struct mutex mbox_sem;
541 /* temporary mailbox status registers */
542 volatile uint8_t mbox_status_count;
543 volatile uint32_t mbox_status[MBOX_REG_COUNT];
545 /* local device database list (contains internal ddb entries) */
546 struct list_head ddb_list;
548 /* Map ddb_list entry by FW ddb index */
549 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
551 /* Saved srb for status continuation entry processing */
552 struct srb *status_srb;
556 /* qla82xx specific fields */
557 struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */
558 unsigned long nx_pcibase; /* Base I/O address */
559 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */
560 unsigned long nx_db_wr_ptr; /* Door bell write pointer */
561 unsigned long first_page_group_start;
562 unsigned long first_page_group_end;
565 uint32_t curr_window;
566 uint32_t ddr_mn_window;
567 unsigned long mn_win_crb;
568 unsigned long ms_win_crb;
574 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
578 uint32_t fw_heartbeat_counter;
580 struct isp_operations *isp_ops;
581 struct ql82xx_hw_data hw;
583 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
585 uint32_t nx_dev_init_timeout;
586 uint32_t nx_reset_timeout;
588 struct completion mbx_intr_comp;
590 struct ipaddress_config ip_config;
591 struct iscsi_iface *iface_ipv4;
592 struct iscsi_iface *iface_ipv6_0;
593 struct iscsi_iface *iface_ipv6_1;
595 /* --- From About Firmware --- */
596 uint16_t iscsi_major;
597 uint16_t iscsi_minor;
598 uint16_t bootload_major;
599 uint16_t bootload_minor;
600 uint16_t bootload_patch;
601 uint16_t bootload_build;
604 static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
606 return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
609 static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
611 return ((ha->ip_config.ipv6_options &
612 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
615 static inline int is_qla4010(struct scsi_qla_host *ha)
617 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
620 static inline int is_qla4022(struct scsi_qla_host *ha)
622 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
625 static inline int is_qla4032(struct scsi_qla_host *ha)
627 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
630 static inline int is_qla8022(struct scsi_qla_host *ha)
632 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
635 /* Note: Currently AER/EEH is now supported only for 8022 cards
636 * This function needs to be updated when AER/EEH is enabled
639 static inline int is_aer_supported(struct scsi_qla_host *ha)
641 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
644 static inline int adapter_up(struct scsi_qla_host *ha)
646 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
647 (test_bit(AF_LINK_UP, &ha->flags) != 0);
650 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
652 return (struct scsi_qla_host *)shost->hostdata;
655 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
657 return (is_qla4010(ha) ?
658 &ha->reg->u1.isp4010.nvram :
659 &ha->reg->u1.isp4022.semaphore);
662 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
664 return (is_qla4010(ha) ?
665 &ha->reg->u1.isp4010.nvram :
666 &ha->reg->u1.isp4022.nvram);
669 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
671 return (is_qla4010(ha) ?
672 &ha->reg->u2.isp4010.ext_hw_conf :
673 &ha->reg->u2.isp4022.p0.ext_hw_conf);
676 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
678 return (is_qla4010(ha) ?
679 &ha->reg->u2.isp4010.port_status :
680 &ha->reg->u2.isp4022.p0.port_status);
683 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
685 return (is_qla4010(ha) ?
686 &ha->reg->u2.isp4010.port_ctrl :
687 &ha->reg->u2.isp4022.p0.port_ctrl);
690 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
692 return (is_qla4010(ha) ?
693 &ha->reg->u2.isp4010.port_err_status :
694 &ha->reg->u2.isp4022.p0.port_err_status);
697 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
699 return (is_qla4010(ha) ?
700 &ha->reg->u2.isp4010.gp_out :
701 &ha->reg->u2.isp4022.p0.gp_out);
704 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
706 return (is_qla4010(ha) ?
707 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
708 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
711 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
712 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
713 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
715 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
718 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
719 QL4010_FLASH_SEM_BITS);
721 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
722 (QL4022_RESOURCE_BITS_BASE_CODE |
723 (a->mac_index)) << 13);
726 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
729 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
731 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
734 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
737 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
738 QL4010_NVRAM_SEM_BITS);
740 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
741 (QL4022_RESOURCE_BITS_BASE_CODE |
742 (a->mac_index)) << 10);
745 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
748 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
750 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
753 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
756 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
757 QL4010_DRVR_SEM_BITS);
759 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
760 (QL4022_RESOURCE_BITS_BASE_CODE |
761 (a->mac_index)) << 1);
764 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
767 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
769 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
772 /*---------------------------------------------------------------------------*/
774 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
775 #define PRESERVE_DDB_LIST 0
776 #define REBUILD_DDB_LIST 1
778 /* Defines for process_aen() */
779 #define PROCESS_ALL_AENS 0
780 #define FLUSH_DDB_CHANGED_AENS 1
782 #endif /*_QLA4XXX_H */