drivers/scsi/qla4xxx/ql4_nx.c

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2010 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7 #include <linux/delay.h>
   8 #include <linux/io.h>
   9 #include <linux/pci.h>
  10 #include <linux/ratelimit.h>
  11 #include "ql4_def.h"
  12 #include "ql4_glbl.h"
  13
  14 #include <asm-generic/io-64-nonatomic-lo-hi.h>
  15
  16 #define MASK(n)         DMA_BIT_MASK(n)
  17 #define MN_WIN(addr)    (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
  18 #define OCM_WIN(addr)   (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
  19 #define MS_WIN(addr)    (addr & 0x0ffc0000)
  20 #define QLA82XX_PCI_MN_2M       (0)
  21 #define QLA82XX_PCI_MS_2M       (0x80000)
  22 #define QLA82XX_PCI_OCM0_2M     (0xc0000)
  23 #define VALID_OCM_ADDR(addr)    (((addr) & 0x3f800) != 0x3f800)
  24 #define GET_MEM_OFFS_2M(addr)   (addr & MASK(18))
  25
  26 /* CRB window related */
  27 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  28 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  29 #define CRB_WINDOW_2M   (0x130060)
  30 #define CRB_HI(off)     ((qla4_8xxx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  31                         ((off) & 0xf0000))
  32 #define QLA82XX_PCI_CAMQM_2M_END        (0x04800800UL)
  33 #define QLA82XX_PCI_CAMQM_2M_BASE       (0x000ff800UL)
  34 #define CRB_INDIRECT_2M                 (0x1e0000UL)
  35
  36 static inline void __iomem *
  37 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
  38 {
  39         if ((off < ha->first_page_group_end) &&
  40             (off >= ha->first_page_group_start))
  41                 return (void __iomem *)(ha->nx_pcibase + off);
  42
  43         return NULL;
  44 }
  45
  46 #define MAX_CRB_XFORM 60
  47 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  48 static int qla4_8xxx_crb_table_initialized;
  49
  50 #define qla4_8xxx_crb_addr_transform(name) \
  51         (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  52          QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  53 static void
  54 qla4_82xx_crb_addr_transform_setup(void)
  55 {
  56         qla4_8xxx_crb_addr_transform(XDMA);
  57         qla4_8xxx_crb_addr_transform(TIMR);
  58         qla4_8xxx_crb_addr_transform(SRE);
  59         qla4_8xxx_crb_addr_transform(SQN3);
  60         qla4_8xxx_crb_addr_transform(SQN2);
  61         qla4_8xxx_crb_addr_transform(SQN1);
  62         qla4_8xxx_crb_addr_transform(SQN0);
  63         qla4_8xxx_crb_addr_transform(SQS3);
  64         qla4_8xxx_crb_addr_transform(SQS2);
  65         qla4_8xxx_crb_addr_transform(SQS1);
  66         qla4_8xxx_crb_addr_transform(SQS0);
  67         qla4_8xxx_crb_addr_transform(RPMX7);
  68         qla4_8xxx_crb_addr_transform(RPMX6);
  69         qla4_8xxx_crb_addr_transform(RPMX5);
  70         qla4_8xxx_crb_addr_transform(RPMX4);
  71         qla4_8xxx_crb_addr_transform(RPMX3);
  72         qla4_8xxx_crb_addr_transform(RPMX2);
  73         qla4_8xxx_crb_addr_transform(RPMX1);
  74         qla4_8xxx_crb_addr_transform(RPMX0);
  75         qla4_8xxx_crb_addr_transform(ROMUSB);
  76         qla4_8xxx_crb_addr_transform(SN);
  77         qla4_8xxx_crb_addr_transform(QMN);
  78         qla4_8xxx_crb_addr_transform(QMS);
  79         qla4_8xxx_crb_addr_transform(PGNI);
  80         qla4_8xxx_crb_addr_transform(PGND);
  81         qla4_8xxx_crb_addr_transform(PGN3);
  82         qla4_8xxx_crb_addr_transform(PGN2);
  83         qla4_8xxx_crb_addr_transform(PGN1);
  84         qla4_8xxx_crb_addr_transform(PGN0);
  85         qla4_8xxx_crb_addr_transform(PGSI);
  86         qla4_8xxx_crb_addr_transform(PGSD);
  87         qla4_8xxx_crb_addr_transform(PGS3);
  88         qla4_8xxx_crb_addr_transform(PGS2);
  89         qla4_8xxx_crb_addr_transform(PGS1);
  90         qla4_8xxx_crb_addr_transform(PGS0);
  91         qla4_8xxx_crb_addr_transform(PS);
  92         qla4_8xxx_crb_addr_transform(PH);
  93         qla4_8xxx_crb_addr_transform(NIU);
  94         qla4_8xxx_crb_addr_transform(I2Q);
  95         qla4_8xxx_crb_addr_transform(EG);
  96         qla4_8xxx_crb_addr_transform(MN);
  97         qla4_8xxx_crb_addr_transform(MS);
  98         qla4_8xxx_crb_addr_transform(CAS2);
  99         qla4_8xxx_crb_addr_transform(CAS1);
 100         qla4_8xxx_crb_addr_transform(CAS0);
 101         qla4_8xxx_crb_addr_transform(CAM);
 102         qla4_8xxx_crb_addr_transform(C2C1);
 103         qla4_8xxx_crb_addr_transform(C2C0);
 104         qla4_8xxx_crb_addr_transform(SMB);
 105         qla4_8xxx_crb_addr_transform(OCM0);
 106         qla4_8xxx_crb_addr_transform(I2C0);
 107
 108         qla4_8xxx_crb_table_initialized = 1;
 109 }
 110
 111 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 112         {{{0, 0,         0,         0} } },             /* 0: PCI */
 113         {{{1, 0x0100000, 0x0102000, 0x120000},  /* 1: PCIE */
 114                 {1, 0x0110000, 0x0120000, 0x130000},
 115                 {1, 0x0120000, 0x0122000, 0x124000},
 116                 {1, 0x0130000, 0x0132000, 0x126000},
 117                 {1, 0x0140000, 0x0142000, 0x128000},
 118                 {1, 0x0150000, 0x0152000, 0x12a000},
 119                 {1, 0x0160000, 0x0170000, 0x110000},
 120                 {1, 0x0170000, 0x0172000, 0x12e000},
 121                 {0, 0x0000000, 0x0000000, 0x000000},
 122                 {0, 0x0000000, 0x0000000, 0x000000},
 123                 {0, 0x0000000, 0x0000000, 0x000000},
 124                 {0, 0x0000000, 0x0000000, 0x000000},
 125                 {0, 0x0000000, 0x0000000, 0x000000},
 126                 {0, 0x0000000, 0x0000000, 0x000000},
 127                 {1, 0x01e0000, 0x01e0800, 0x122000},
 128                 {0, 0x0000000, 0x0000000, 0x000000} } },
 129         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
 130         {{{0, 0,         0,         0} } },         /* 3: */
 131         {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
 132         {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
 133         {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
 134         {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
 135         {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
 136                 {0, 0x0000000, 0x0000000, 0x000000},
 137                 {0, 0x0000000, 0x0000000, 0x000000},
 138                 {0, 0x0000000, 0x0000000, 0x000000},
 139                 {0, 0x0000000, 0x0000000, 0x000000},
 140                 {0, 0x0000000, 0x0000000, 0x000000},
 141                 {0, 0x0000000, 0x0000000, 0x000000},
 142                 {0, 0x0000000, 0x0000000, 0x000000},
 143                 {0, 0x0000000, 0x0000000, 0x000000},
 144                 {0, 0x0000000, 0x0000000, 0x000000},
 145                 {0, 0x0000000, 0x0000000, 0x000000},
 146                 {0, 0x0000000, 0x0000000, 0x000000},
 147                 {0, 0x0000000, 0x0000000, 0x000000},
 148                 {0, 0x0000000, 0x0000000, 0x000000},
 149                 {0, 0x0000000, 0x0000000, 0x000000},
 150                 {1, 0x08f0000, 0x08f2000, 0x172000} } },
 151         {{{1, 0x0900000, 0x0902000, 0x174000},  /* 9: SQM1*/
 152                 {0, 0x0000000, 0x0000000, 0x000000},
 153                 {0, 0x0000000, 0x0000000, 0x000000},
 154                 {0, 0x0000000, 0x0000000, 0x000000},
 155                 {0, 0x0000000, 0x0000000, 0x000000},
 156                 {0, 0x0000000, 0x0000000, 0x000000},
 157                 {0, 0x0000000, 0x0000000, 0x000000},
 158                 {0, 0x0000000, 0x0000000, 0x000000},
 159                 {0, 0x0000000, 0x0000000, 0x000000},
 160                 {0, 0x0000000, 0x0000000, 0x000000},
 161                 {0, 0x0000000, 0x0000000, 0x000000},
 162                 {0, 0x0000000, 0x0000000, 0x000000},
 163                 {0, 0x0000000, 0x0000000, 0x000000},
 164                 {0, 0x0000000, 0x0000000, 0x000000},
 165                 {0, 0x0000000, 0x0000000, 0x000000},
 166                 {1, 0x09f0000, 0x09f2000, 0x176000} } },
 167         {{{0, 0x0a00000, 0x0a02000, 0x178000},  /* 10: SQM2*/
 168                 {0, 0x0000000, 0x0000000, 0x000000},
 169                 {0, 0x0000000, 0x0000000, 0x000000},
 170                 {0, 0x0000000, 0x0000000, 0x000000},
 171                 {0, 0x0000000, 0x0000000, 0x000000},
 172                 {0, 0x0000000, 0x0000000, 0x000000},
 173                 {0, 0x0000000, 0x0000000, 0x000000},
 174                 {0, 0x0000000, 0x0000000, 0x000000},
 175                 {0, 0x0000000, 0x0000000, 0x000000},
 176                 {0, 0x0000000, 0x0000000, 0x000000},
 177                 {0, 0x0000000, 0x0000000, 0x000000},
 178                 {0, 0x0000000, 0x0000000, 0x000000},
 179                 {0, 0x0000000, 0x0000000, 0x000000},
 180                 {0, 0x0000000, 0x0000000, 0x000000},
 181                 {0, 0x0000000, 0x0000000, 0x000000},
 182                 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 183         {{{0, 0x0b00000, 0x0b02000, 0x17c000},  /* 11: SQM3*/
 184                 {0, 0x0000000, 0x0000000, 0x000000},
 185                 {0, 0x0000000, 0x0000000, 0x000000},
 186                 {0, 0x0000000, 0x0000000, 0x000000},
 187                 {0, 0x0000000, 0x0000000, 0x000000},
 188                 {0, 0x0000000, 0x0000000, 0x000000},
 189                 {0, 0x0000000, 0x0000000, 0x000000},
 190                 {0, 0x0000000, 0x0000000, 0x000000},
 191                 {0, 0x0000000, 0x0000000, 0x000000},
 192                 {0, 0x0000000, 0x0000000, 0x000000},
 193                 {0, 0x0000000, 0x0000000, 0x000000},
 194                 {0, 0x0000000, 0x0000000, 0x000000},
 195                 {0, 0x0000000, 0x0000000, 0x000000},
 196                 {0, 0x0000000, 0x0000000, 0x000000},
 197                 {0, 0x0000000, 0x0000000, 0x000000},
 198                 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 199         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 200         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 201         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 202         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 203         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 204         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 205         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 206         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 207         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 208         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 209         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 210         {{{0, 0,         0,         0} } },     /* 23: */
 211         {{{0, 0,         0,         0} } },     /* 24: */
 212         {{{0, 0,         0,         0} } },     /* 25: */
 213         {{{0, 0,         0,         0} } },     /* 26: */
 214         {{{0, 0,         0,         0} } },     /* 27: */
 215         {{{0, 0,         0,         0} } },     /* 28: */
 216         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 217         {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 218         {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 219         {{{0} } },                              /* 32: PCI */
 220         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 221                 {1, 0x2110000, 0x2120000, 0x130000},
 222                 {1, 0x2120000, 0x2122000, 0x124000},
 223                 {1, 0x2130000, 0x2132000, 0x126000},
 224                 {1, 0x2140000, 0x2142000, 0x128000},
 225                 {1, 0x2150000, 0x2152000, 0x12a000},
 226                 {1, 0x2160000, 0x2170000, 0x110000},
 227                 {1, 0x2170000, 0x2172000, 0x12e000},
 228                 {0, 0x0000000, 0x0000000, 0x000000},
 229                 {0, 0x0000000, 0x0000000, 0x000000},
 230                 {0, 0x0000000, 0x0000000, 0x000000},
 231                 {0, 0x0000000, 0x0000000, 0x000000},
 232                 {0, 0x0000000, 0x0000000, 0x000000},
 233                 {0, 0x0000000, 0x0000000, 0x000000},
 234                 {0, 0x0000000, 0x0000000, 0x000000},
 235                 {0, 0x0000000, 0x0000000, 0x000000} } },
 236         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 237         {{{0} } },                              /* 35: */
 238         {{{0} } },                              /* 36: */
 239         {{{0} } },                              /* 37: */
 240         {{{0} } },                              /* 38: */
 241         {{{0} } },                              /* 39: */
 242         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 243         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 244         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 245         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 246         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 247         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 248         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 249         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 250         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 251         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 252         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 253         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 254         {{{0} } },                              /* 52: */
 255         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 256         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 257         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 258         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 259         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 260         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 261         {{{0} } },                              /* 59: I2C0 */
 262         {{{0} } },                              /* 60: I2C1 */
 263         {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
 264         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 265         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 266 };
 267
 268 /*
 269  * top 12 bits of crb internal address (hub, agent)
 270  */
 271 static unsigned qla4_8xxx_crb_hub_agt[64] = {
 272         0,
 273         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 274         QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 275         QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 276         0,
 277         QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 278         QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 279         QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 280         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 281         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 282         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 283         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 284         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 285         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 286         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 287         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 288         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 289         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 290         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 291         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 292         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 293         QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 294         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 295         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 296         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 297         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 298         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 299         0,
 300         QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 301         QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 302         0,
 303         QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 304         0,
 305         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 306         QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 307         0,
 308         0,
 309         0,
 310         0,
 311         0,
 312         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 313         0,
 314         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 315         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 316         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 317         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 318         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 319         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 320         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 321         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 322         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 323         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 324         0,
 325         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 326         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 327         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 328         QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 329         0,
 330         QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 331         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 332         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 333         0,
 334         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 335         0,
 336 };
 337
 338 /* Device states */
 339 static char *qdev_state[] = {
 340         "Unknown",
 341         "Cold",
 342         "Initializing",
 343         "Ready",
 344         "Need Reset",
 345         "Need Quiescent",
 346         "Failed",
 347         "Quiescent",
 348 };
 349
 350 /*
 351  * In: 'off' is offset from CRB space in 128M pci map
 352  * Out: 'off' is 2M pci map addr
 353  * side effect: lock crb window
 354  */
 355 static void
 356 qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
 357 {
 358         u32 win_read;
 359
 360         ha->crb_win = CRB_HI(*off);
 361         writel(ha->crb_win,
 362                 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 363
 364         /* Read back value to make sure write has gone through before trying
 365         * to use it. */
 366         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 367         if (win_read != ha->crb_win) {
 368                 DEBUG2(ql4_printk(KERN_INFO, ha,
 369                     "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
 370                     " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
 371         }
 372         *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 373 }
 374
 375 void
 376 qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
 377 {
 378         unsigned long flags = 0;
 379         int rv;
 380
 381         rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
 382
 383         BUG_ON(rv == -1);
 384
 385         if (rv == 1) {
 386                 write_lock_irqsave(&ha->hw_lock, flags);
 387                 qla4_82xx_crb_win_lock(ha);
 388                 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
 389         }
 390
 391         writel(data, (void __iomem *)off);
 392
 393         if (rv == 1) {
 394                 qla4_82xx_crb_win_unlock(ha);
 395                 write_unlock_irqrestore(&ha->hw_lock, flags);
 396         }
 397 }
 398
 399 int
 400 qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
 401 {
 402         unsigned long flags = 0;
 403         int rv;
 404         u32 data;
 405
 406         rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
 407
 408         BUG_ON(rv == -1);
 409
 410         if (rv == 1) {
 411                 write_lock_irqsave(&ha->hw_lock, flags);
 412                 qla4_82xx_crb_win_lock(ha);
 413                 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
 414         }
 415         data = readl((void __iomem *)off);
 416
 417         if (rv == 1) {
 418                 qla4_82xx_crb_win_unlock(ha);
 419                 write_unlock_irqrestore(&ha->hw_lock, flags);
 420         }
 421         return data;
 422 }
 423
 424 /* Minidump related functions */
 425 static int qla4_8xxx_md_rw_32(struct scsi_qla_host *ha, uint32_t off,
 426                               u32 data, uint8_t flag)
 427 {
 428         uint32_t win_read, off_value, rval = QLA_SUCCESS;
 429
 430         off_value  = off & 0xFFFF0000;
 431         writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 432
 433         /* Read back value to make sure write has gone through before trying
 434          * to use it.
 435          */
 436         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 437         if (win_read != off_value) {
 438                 DEBUG2(ql4_printk(KERN_INFO, ha,
 439                                   "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
 440                                    __func__, off_value, win_read, off));
 441                 return QLA_ERROR;
 442         }
 443
 444         off_value  = off & 0x0000FFFF;
 445
 446         if (flag)
 447                 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
 448                                               ha->nx_pcibase));
 449         else
 450                 rval = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
 451                                               ha->nx_pcibase));
 452
 453         return rval;
 454 }
 455
 456 #define CRB_WIN_LOCK_TIMEOUT 100000000
 457
 458 int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
 459 {
 460         int i;
 461         int done = 0, timeout = 0;
 462
 463         while (!done) {
 464                 /* acquire semaphore3 from PCI HW block */
 465                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 466                 if (done == 1)
 467                         break;
 468                 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 469                         return -1;
 470
 471                 timeout++;
 472
 473                 /* Yield CPU */
 474                 if (!in_interrupt())
 475                         schedule();
 476                 else {
 477                         for (i = 0; i < 20; i++)
 478                                 cpu_relax();    /*This a nop instr on i386*/
 479                 }
 480         }
 481         qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
 482         return 0;
 483 }
 484
 485 void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
 486 {
 487         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 488 }
 489
 490 #define IDC_LOCK_TIMEOUT 100000000
 491
 492 /**
 493  * qla4_82xx_idc_lock - hw_lock
 494  * @ha: pointer to adapter structure
 495  *
 496  * General purpose lock used to synchronize access to
 497  * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
 498  **/
 499 int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
 500 {
 501         int i;
 502         int done = 0, timeout = 0;
 503
 504         while (!done) {
 505                 /* acquire semaphore5 from PCI HW block */
 506                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 507                 if (done == 1)
 508                         break;
 509                 if (timeout >= IDC_LOCK_TIMEOUT)
 510                         return -1;
 511
 512                 timeout++;
 513
 514                 /* Yield CPU */
 515                 if (!in_interrupt())
 516                         schedule();
 517                 else {
 518                         for (i = 0; i < 20; i++)
 519                                 cpu_relax();    /*This a nop instr on i386*/
 520                 }
 521         }
 522         return 0;
 523 }
 524
 525 void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
 526 {
 527         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 528 }
 529
 530 int
 531 qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
 532 {
 533         struct crb_128M_2M_sub_block_map *m;
 534
 535         if (*off >= QLA82XX_CRB_MAX)
 536                 return -1;
 537
 538         if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
 539                 *off = (*off - QLA82XX_PCI_CAMQM) +
 540                     QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 541                 return 0;
 542         }
 543
 544         if (*off < QLA82XX_PCI_CRBSPACE)
 545                 return -1;
 546
 547         *off -= QLA82XX_PCI_CRBSPACE;
 548         /*
 549          * Try direct map
 550          */
 551
 552         m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
 553
 554         if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
 555                 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
 556                 return 0;
 557         }
 558
 559         /*
 560          * Not in direct map, use crb window
 561          */
 562         return 1;
 563 }
 564
 565 /*  PCI Windowing for DDR regions.  */
 566 #define QLA82XX_ADDR_IN_RANGE(addr, low, high)            \
 567         (((addr) <= (high)) && ((addr) >= (low)))
 568
 569 /*
 570 * check memory access boundary.
 571 * used by test agent. support ddr access only for now
 572 */
 573 static unsigned long
 574 qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
 575                 unsigned long long addr, int size)
 576 {
 577         if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 578             QLA82XX_ADDR_DDR_NET_MAX) ||
 579             !QLA82XX_ADDR_IN_RANGE(addr + size - 1,
 580             QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) ||
 581             ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
 582                 return 0;
 583         }
 584         return 1;
 585 }
 586
 587 static int qla4_8xxx_pci_set_window_warning_count;
 588
 589 static unsigned long
 590 qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
 591 {
 592         int window;
 593         u32 win_read;
 594
 595         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 596             QLA82XX_ADDR_DDR_NET_MAX)) {
 597                 /* DDR network side */
 598                 window = MN_WIN(addr);
 599                 ha->ddr_mn_window = window;
 600                 qla4_82xx_wr_32(ha, ha->mn_win_crb |
 601                     QLA82XX_PCI_CRBSPACE, window);
 602                 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
 603                     QLA82XX_PCI_CRBSPACE);
 604                 if ((win_read << 17) != window) {
 605                         ql4_printk(KERN_WARNING, ha,
 606                         "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
 607                         __func__, window, win_read);
 608                 }
 609                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 610         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 611                                 QLA82XX_ADDR_OCM0_MAX)) {
 612                 unsigned int temp1;
 613                 /* if bits 19:18&17:11 are on */
 614                 if ((addr & 0x00ff800) == 0xff800) {
 615                         printk("%s: QM access not handled.\n", __func__);
 616                         addr = -1UL;
 617                 }
 618
 619                 window = OCM_WIN(addr);
 620                 ha->ddr_mn_window = window;
 621                 qla4_82xx_wr_32(ha, ha->mn_win_crb |
 622                     QLA82XX_PCI_CRBSPACE, window);
 623                 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
 624                     QLA82XX_PCI_CRBSPACE);
 625                 temp1 = ((window & 0x1FF) << 7) |
 626                     ((window & 0x0FFFE0000) >> 17);
 627                 if (win_read != temp1) {
 628                         printk("%s: Written OCMwin (0x%x) != Read"
 629                             " OCMwin (0x%x)\n", __func__, temp1, win_read);
 630                 }
 631                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 632
 633         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
 634                                 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 635                 /* QDR network side */
 636                 window = MS_WIN(addr);
 637                 ha->qdr_sn_window = window;
 638                 qla4_82xx_wr_32(ha, ha->ms_win_crb |
 639                     QLA82XX_PCI_CRBSPACE, window);
 640                 win_read = qla4_82xx_rd_32(ha,
 641                      ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 642                 if (win_read != window) {
 643                         printk("%s: Written MSwin (0x%x) != Read "
 644                             "MSwin (0x%x)\n", __func__, window, win_read);
 645                 }
 646                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 647
 648         } else {
 649                 /*
 650                  * peg gdb frequently accesses memory that doesn't exist,
 651                  * this limits the chit chat so debugging isn't slowed down.
 652                  */
 653                 if ((qla4_8xxx_pci_set_window_warning_count++ < 8) ||
 654                     (qla4_8xxx_pci_set_window_warning_count%64 == 0)) {
 655                         printk("%s: Warning:%s Unknown address range!\n",
 656                             __func__, DRIVER_NAME);
 657                 }
 658                 addr = -1UL;
 659         }
 660         return addr;
 661 }
 662
 663 /* check if address is in the same windows as the previous access */
 664 static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
 665                 unsigned long long addr)
 666 {
 667         int window;
 668         unsigned long long qdr_max;
 669
 670         qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 671
 672         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 673             QLA82XX_ADDR_DDR_NET_MAX)) {
 674                 /* DDR network side */
 675                 BUG();  /* MN access can not come here */
 676         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 677              QLA82XX_ADDR_OCM0_MAX)) {
 678                 return 1;
 679         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
 680              QLA82XX_ADDR_OCM1_MAX)) {
 681                 return 1;
 682         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
 683             qdr_max)) {
 684                 /* QDR network side */
 685                 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
 686                 if (ha->qdr_sn_window == window)
 687                         return 1;
 688         }
 689
 690         return 0;
 691 }
 692
 693 static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
 694                 u64 off, void *data, int size)
 695 {
 696         unsigned long flags;
 697         void __iomem *addr;
 698         int ret = 0;
 699         u64 start;
 700         void __iomem *mem_ptr = NULL;
 701         unsigned long mem_base;
 702         unsigned long mem_page;
 703
 704         write_lock_irqsave(&ha->hw_lock, flags);
 705
 706         /*
 707          * If attempting to access unknown address or straddle hw windows,
 708          * do not access.
 709          */
 710         start = qla4_82xx_pci_set_window(ha, off);
 711         if ((start == -1UL) ||
 712             (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 713                 write_unlock_irqrestore(&ha->hw_lock, flags);
 714                 printk(KERN_ERR"%s out of bound pci memory access. "
 715                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 716                 return -1;
 717         }
 718
 719         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 720         if (!addr) {
 721                 write_unlock_irqrestore(&ha->hw_lock, flags);
 722                 mem_base = pci_resource_start(ha->pdev, 0);
 723                 mem_page = start & PAGE_MASK;
 724                 /* Map two pages whenever user tries to access addresses in two
 725                    consecutive pages.
 726                  */
 727                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 728                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 729                 else
 730                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 731
 732                 if (mem_ptr == NULL) {
 733                         *(u8 *)data = 0;
 734                         return -1;
 735                 }
 736                 addr = mem_ptr;
 737                 addr += start & (PAGE_SIZE - 1);
 738                 write_lock_irqsave(&ha->hw_lock, flags);
 739         }
 740
 741         switch (size) {
 742         case 1:
 743                 *(u8  *)data = readb(addr);
 744                 break;
 745         case 2:
 746                 *(u16 *)data = readw(addr);
 747                 break;
 748         case 4:
 749                 *(u32 *)data = readl(addr);
 750                 break;
 751         case 8:
 752                 *(u64 *)data = readq(addr);
 753                 break;
 754         default:
 755                 ret = -1;
 756                 break;
 757         }
 758         write_unlock_irqrestore(&ha->hw_lock, flags);
 759
 760         if (mem_ptr)
 761                 iounmap(mem_ptr);
 762         return ret;
 763 }
 764
 765 static int
 766 qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
 767                 void *data, int size)
 768 {
 769         unsigned long flags;
 770         void __iomem *addr;
 771         int ret = 0;
 772         u64 start;
 773         void __iomem *mem_ptr = NULL;
 774         unsigned long mem_base;
 775         unsigned long mem_page;
 776
 777         write_lock_irqsave(&ha->hw_lock, flags);
 778
 779         /*
 780          * If attempting to access unknown address or straddle hw windows,
 781          * do not access.
 782          */
 783         start = qla4_82xx_pci_set_window(ha, off);
 784         if ((start == -1UL) ||
 785             (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
 786                 write_unlock_irqrestore(&ha->hw_lock, flags);
 787                 printk(KERN_ERR"%s out of bound pci memory access. "
 788                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 789                 return -1;
 790         }
 791
 792         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 793         if (!addr) {
 794                 write_unlock_irqrestore(&ha->hw_lock, flags);
 795                 mem_base = pci_resource_start(ha->pdev, 0);
 796                 mem_page = start & PAGE_MASK;
 797                 /* Map two pages whenever user tries to access addresses in two
 798                    consecutive pages.
 799                  */
 800                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 801                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 802                 else
 803                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 804                 if (mem_ptr == NULL)
 805                         return -1;
 806
 807                 addr = mem_ptr;
 808                 addr += start & (PAGE_SIZE - 1);
 809                 write_lock_irqsave(&ha->hw_lock, flags);
 810         }
 811
 812         switch (size) {
 813         case 1:
 814                 writeb(*(u8 *)data, addr);
 815                 break;
 816         case 2:
 817                 writew(*(u16 *)data, addr);
 818                 break;
 819         case 4:
 820                 writel(*(u32 *)data, addr);
 821                 break;
 822         case 8:
 823                 writeq(*(u64 *)data, addr);
 824                 break;
 825         default:
 826                 ret = -1;
 827                 break;
 828         }
 829         write_unlock_irqrestore(&ha->hw_lock, flags);
 830         if (mem_ptr)
 831                 iounmap(mem_ptr);
 832         return ret;
 833 }
 834
 835 #define MTU_FUDGE_FACTOR 100
 836
 837 static unsigned long
 838 qla4_82xx_decode_crb_addr(unsigned long addr)
 839 {
 840         int i;
 841         unsigned long base_addr, offset, pci_base;
 842
 843         if (!qla4_8xxx_crb_table_initialized)
 844                 qla4_82xx_crb_addr_transform_setup();
 845
 846         pci_base = ADDR_ERROR;
 847         base_addr = addr & 0xfff00000;
 848         offset = addr & 0x000fffff;
 849
 850         for (i = 0; i < MAX_CRB_XFORM; i++) {
 851                 if (crb_addr_xform[i] == base_addr) {
 852                         pci_base = i << 20;
 853                         break;
 854                 }
 855         }
 856         if (pci_base == ADDR_ERROR)
 857                 return pci_base;
 858         else
 859                 return pci_base + offset;
 860 }
 861
 862 static long rom_max_timeout = 100;
 863 static long qla4_8xxx_rom_lock_timeout = 100;
 864
 865 static int
 866 qla4_82xx_rom_lock(struct scsi_qla_host *ha)
 867 {
 868         int i;
 869         int done = 0, timeout = 0;
 870
 871         while (!done) {
 872                 /* acquire semaphore2 from PCI HW block */
 873
 874                 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
 875                 if (done == 1)
 876                         break;
 877                 if (timeout >= qla4_8xxx_rom_lock_timeout)
 878                         return -1;
 879
 880                 timeout++;
 881
 882                 /* Yield CPU */
 883                 if (!in_interrupt())
 884                         schedule();
 885                 else {
 886                         for (i = 0; i < 20; i++)
 887                                 cpu_relax();    /*This a nop instr on i386*/
 888                 }
 889         }
 890         qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
 891         return 0;
 892 }
 893
 894 static void
 895 qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
 896 {
 897         qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
 898 }
 899
 900 static int
 901 qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
 902 {
 903         long timeout = 0;
 904         long done = 0 ;
 905
 906         while (done == 0) {
 907                 done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 908                 done &= 2;
 909                 timeout++;
 910                 if (timeout >= rom_max_timeout) {
 911                         printk("%s: Timeout reached  waiting for rom done",
 912                                         DRIVER_NAME);
 913                         return -1;
 914                 }
 915         }
 916         return 0;
 917 }
 918
 919 static int
 920 qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 921 {
 922         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
 923         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 924         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
 925         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
 926         if (qla4_82xx_wait_rom_done(ha)) {
 927                 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
 928                 return -1;
 929         }
 930         /* reset abyte_cnt and dummy_byte_cnt */
 931         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 932         udelay(10);
 933         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
 934
 935         *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
 936         return 0;
 937 }
 938
 939 static int
 940 qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 941 {
 942         int ret, loops = 0;
 943
 944         while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
 945                 udelay(100);
 946                 loops++;
 947         }
 948         if (loops >= 50000) {
 949                 ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
 950                            DRIVER_NAME);
 951                 return -1;
 952         }
 953         ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
 954         qla4_82xx_rom_unlock(ha);
 955         return ret;
 956 }
 957
 958 /**
 959  * This routine does CRB initialize sequence
 960  * to put the ISP into operational state
 961  **/
 962 static int
 963 qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
 964 {
 965         int addr, val;
 966         int i ;
 967         struct crb_addr_pair *buf;
 968         unsigned long off;
 969         unsigned offset, n;
 970
 971         struct crb_addr_pair {
 972                 long addr;
 973                 long data;
 974         };
 975
 976         /* Halt all the indiviual PEGs and other blocks of the ISP */
 977         qla4_82xx_rom_lock(ha);
 978
 979         /* disable all I2Q */
 980         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
 981         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
 982         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
 983         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
 984         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
 985         qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
 986
 987         /* disable all niu interrupts */
 988         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
 989         /* disable xge rx/tx */
 990         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
 991         /* disable xg1 rx/tx */
 992         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
 993         /* disable sideband mac */
 994         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
 995         /* disable ap0 mac */
 996         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
 997         /* disable ap1 mac */
 998         qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
 999
1000         /* halt sre */
1001         val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1002         qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1003
1004         /* halt epg */
1005         qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1006
1007         /* halt timers */
1008         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1009         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1010         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1011         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1012         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1013         qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1014
1015         /* halt pegs */
1016         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1017         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1018         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1019         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1020         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1021         msleep(5);
1022
1023         /* big hammer */
1024         if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1025                 /* don't reset CAM block on reset */
1026                 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1027         else
1028                 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1029
1030         qla4_82xx_rom_unlock(ha);
1031
1032         /* Read the signature value from the flash.
1033          * Offset 0: Contain signature (0xcafecafe)
1034          * Offset 4: Offset and number of addr/value pairs
1035          * that present in CRB initialize sequence
1036          */
1037         if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1038             qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
1039                 ql4_printk(KERN_WARNING, ha,
1040                         "[ERROR] Reading crb_init area: n: %08x\n", n);
1041                 return -1;
1042         }
1043
1044         /* Offset in flash = lower 16 bits
1045          * Number of enteries = upper 16 bits
1046          */
1047         offset = n & 0xffffU;
1048         n = (n >> 16) & 0xffffU;
1049
1050         /* number of addr/value pair should not exceed 1024 enteries */
1051         if (n  >= 1024) {
1052                 ql4_printk(KERN_WARNING, ha,
1053                     "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1054                     DRIVER_NAME, __func__, n);
1055                 return -1;
1056         }
1057
1058         ql4_printk(KERN_INFO, ha,
1059                 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
1060
1061         buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1062         if (buf == NULL) {
1063                 ql4_printk(KERN_WARNING, ha,
1064                     "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1065                 return -1;
1066         }
1067
1068         for (i = 0; i < n; i++) {
1069                 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1070                     qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1071                     0) {
1072                         kfree(buf);
1073                         return -1;
1074                 }
1075
1076                 buf[i].addr = addr;
1077                 buf[i].data = val;
1078         }
1079
1080         for (i = 0; i < n; i++) {
1081                 /* Translate internal CRB initialization
1082                  * address to PCI bus address
1083                  */
1084                 off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1085                     QLA82XX_PCI_CRBSPACE;
1086                 /* Not all CRB  addr/value pair to be written,
1087                  * some of them are skipped
1088                  */
1089
1090                 /* skip if LS bit is set*/
1091                 if (off & 0x1) {
1092                         DEBUG2(ql4_printk(KERN_WARNING, ha,
1093                             "Skip CRB init replay for offset = 0x%lx\n", off));
1094                         continue;
1095                 }
1096
1097                 /* skipping cold reboot MAGIC */
1098                 if (off == QLA82XX_CAM_RAM(0x1fc))
1099                         continue;
1100
1101                 /* do not reset PCI */
1102                 if (off == (ROMUSB_GLB + 0xbc))
1103                         continue;
1104
1105                 /* skip core clock, so that firmware can increase the clock */
1106                 if (off == (ROMUSB_GLB + 0xc8))
1107                         continue;
1108
1109                 /* skip the function enable register */
1110                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1111                         continue;
1112
1113                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1114                         continue;
1115
1116                 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1117                         continue;
1118
1119                 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1120                         continue;
1121
1122                 if (off == ADDR_ERROR) {
1123                         ql4_printk(KERN_WARNING, ha,
1124                             "%s: [ERROR] Unknown addr: 0x%08lx\n",
1125                             DRIVER_NAME, buf[i].addr);
1126                         continue;
1127                 }
1128
1129                 qla4_82xx_wr_32(ha, off, buf[i].data);
1130
1131                 /* ISP requires much bigger delay to settle down,
1132                  * else crb_window returns 0xffffffff
1133                  */
1134                 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1135                         msleep(1000);
1136
1137                 /* ISP requires millisec delay between
1138                  * successive CRB register updation
1139                  */
1140                 msleep(1);
1141         }
1142
1143         kfree(buf);
1144
1145         /* Resetting the data and instruction cache */
1146         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1147         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1148         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1149
1150         /* Clear all protocol processing engines */
1151         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1152         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1153         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1154         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1155         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1156         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1157         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1158         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1159
1160         return 0;
1161 }
1162
1163 static int
1164 qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1165 {
1166         int  i, rval = 0;
1167         long size = 0;
1168         long flashaddr, memaddr;
1169         u64 data;
1170         u32 high, low;
1171
1172         flashaddr = memaddr = ha->hw.flt_region_bootload;
1173         size = (image_start - flashaddr) / 8;
1174
1175         DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1176             ha->host_no, __func__, flashaddr, image_start));
1177
1178         for (i = 0; i < size; i++) {
1179                 if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1180                     (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
1181                     (int *)&high))) {
1182                         rval = -1;
1183                         goto exit_load_from_flash;
1184                 }
1185                 data = ((u64)high << 32) | low ;
1186                 rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1187                 if (rval)
1188                         goto exit_load_from_flash;
1189
1190                 flashaddr += 8;
1191                 memaddr   += 8;
1192
1193                 if (i % 0x1000 == 0)
1194                         msleep(1);
1195
1196         }
1197
1198         udelay(100);
1199
1200         read_lock(&ha->hw_lock);
1201         qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1202         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1203         read_unlock(&ha->hw_lock);
1204
1205 exit_load_from_flash:
1206         return rval;
1207 }
1208
1209 static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1210 {
1211         u32 rst;
1212
1213         qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1214         if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1215                 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1216                     __func__);
1217                 return QLA_ERROR;
1218         }
1219
1220         udelay(500);
1221
1222         /* at this point, QM is in reset. This could be a problem if there are
1223          * incoming d* transition queue messages. QM/PCIE could wedge.
1224          * To get around this, QM is brought out of reset.
1225          */
1226
1227         rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1228         /* unreset qm */
1229         rst &= ~(1 << 28);
1230         qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1231
1232         if (qla4_82xx_load_from_flash(ha, image_start)) {
1233                 printk("%s: Error trying to load fw from flash!\n", __func__);
1234                 return QLA_ERROR;
1235         }
1236
1237         return QLA_SUCCESS;
1238 }
1239
1240 int
1241 qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
1242                 u64 off, void *data, int size)
1243 {
1244         int i, j = 0, k, start, end, loop, sz[2], off0[2];
1245         int shift_amount;
1246         uint32_t temp;
1247         uint64_t off8, val, mem_crb, word[2] = {0, 0};
1248
1249         /*
1250          * If not MN, go check for MS or invalid.
1251          */
1252
1253         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1254                 mem_crb = QLA82XX_CRB_QDR_NET;
1255         else {
1256                 mem_crb = QLA82XX_CRB_DDR_NET;
1257                 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1258                         return qla4_82xx_pci_mem_read_direct(ha,
1259                                         off, data, size);
1260         }
1261
1262
1263         off8 = off & 0xfffffff0;
1264         off0[0] = off & 0xf;
1265         sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1266         shift_amount = 4;
1267
1268         loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1269         off0[1] = 0;
1270         sz[1] = size - sz[0];
1271
1272         for (i = 0; i < loop; i++) {
1273                 temp = off8 + (i << shift_amount);
1274                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1275                 temp = 0;
1276                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1277                 temp = MIU_TA_CTL_ENABLE;
1278                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1279                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1280                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1281
1282                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1283                         temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1284                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1285                                 break;
1286                 }
1287
1288                 if (j >= MAX_CTL_CHECK) {
1289                         printk_ratelimited(KERN_ERR
1290                                            "%s: failed to read through agent\n",
1291                                            __func__);
1292                         break;
1293                 }
1294
1295                 start = off0[i] >> 2;
1296                 end   = (off0[i] + sz[i] - 1) >> 2;
1297                 for (k = start; k <= end; k++) {
1298                         temp = qla4_82xx_rd_32(ha,
1299                                 mem_crb + MIU_TEST_AGT_RDDATA(k));
1300                         word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1301                 }
1302         }
1303
1304         if (j >= MAX_CTL_CHECK)
1305                 return -1;
1306
1307         if ((off0[0] & 7) == 0) {
1308                 val = word[0];
1309         } else {
1310                 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1311                 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1312         }
1313
1314         switch (size) {
1315         case 1:
1316                 *(uint8_t  *)data = val;
1317                 break;
1318         case 2:
1319                 *(uint16_t *)data = val;
1320                 break;
1321         case 4:
1322                 *(uint32_t *)data = val;
1323                 break;
1324         case 8:
1325                 *(uint64_t *)data = val;
1326                 break;
1327         }
1328         return 0;
1329 }
1330
1331 int
1332 qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
1333                 u64 off, void *data, int size)
1334 {
1335         int i, j, ret = 0, loop, sz[2], off0;
1336         int scale, shift_amount, startword;
1337         uint32_t temp;
1338         uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1339
1340         /*
1341          * If not MN, go check for MS or invalid.
1342          */
1343         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1344                 mem_crb = QLA82XX_CRB_QDR_NET;
1345         else {
1346                 mem_crb = QLA82XX_CRB_DDR_NET;
1347                 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1348                         return qla4_82xx_pci_mem_write_direct(ha,
1349                                         off, data, size);
1350         }
1351
1352         off0 = off & 0x7;
1353         sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1354         sz[1] = size - sz[0];
1355
1356         off8 = off & 0xfffffff0;
1357         loop = (((off & 0xf) + size - 1) >> 4) + 1;
1358         shift_amount = 4;
1359         scale = 2;
1360         startword = (off & 0xf)/8;
1361
1362         for (i = 0; i < loop; i++) {
1363                 if (qla4_82xx_pci_mem_read_2M(ha, off8 +
1364                     (i << shift_amount), &word[i * scale], 8))
1365                         return -1;
1366         }
1367
1368         switch (size) {
1369         case 1:
1370                 tmpw = *((uint8_t *)data);
1371                 break;
1372         case 2:
1373                 tmpw = *((uint16_t *)data);
1374                 break;
1375         case 4:
1376                 tmpw = *((uint32_t *)data);
1377                 break;
1378         case 8:
1379         default:
1380                 tmpw = *((uint64_t *)data);
1381                 break;
1382         }
1383
1384         if (sz[0] == 8)
1385                 word[startword] = tmpw;
1386         else {
1387                 word[startword] &=
1388                     ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1389                 word[startword] |= tmpw << (off0 * 8);
1390         }
1391
1392         if (sz[1] != 0) {
1393                 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1394                 word[startword+1] |= tmpw >> (sz[0] * 8);
1395         }
1396
1397         for (i = 0; i < loop; i++) {
1398                 temp = off8 + (i << shift_amount);
1399                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1400                 temp = 0;
1401                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1402                 temp = word[i * scale] & 0xffffffff;
1403                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1404                 temp = (word[i * scale] >> 32) & 0xffffffff;
1405                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1406                 temp = word[i*scale + 1] & 0xffffffff;
1407                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1408                     temp);
1409                 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1410                 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1411                     temp);
1412
1413                 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1414                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1415                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1416                 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1417
1418                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1419                         temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1420                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1421                                 break;
1422                 }
1423
1424                 if (j >= MAX_CTL_CHECK) {
1425                         if (printk_ratelimit())
1426                                 ql4_printk(KERN_ERR, ha,
1427                                            "%s: failed to read through agent\n",
1428                                            __func__);
1429                         ret = -1;
1430                         break;
1431                 }
1432         }
1433
1434         return ret;
1435 }
1436
1437 static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1438 {
1439         u32 val = 0;
1440         int retries = 60;
1441
1442         if (!pegtune_val) {
1443                 do {
1444                         val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
1445                         if ((val == PHAN_INITIALIZE_COMPLETE) ||
1446                             (val == PHAN_INITIALIZE_ACK))
1447                                 return 0;
1448                         set_current_state(TASK_UNINTERRUPTIBLE);
1449                         schedule_timeout(500);
1450
1451                 } while (--retries);
1452
1453                 if (!retries) {
1454                         pegtune_val = qla4_82xx_rd_32(ha,
1455                                 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1456                         printk(KERN_WARNING "%s: init failed, "
1457                                 "pegtune_val = %x\n", __func__, pegtune_val);
1458                         return -1;
1459                 }
1460         }
1461         return 0;
1462 }
1463
1464 static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
1465 {
1466         uint32_t state = 0;
1467         int loops = 0;
1468
1469         /* Window 1 call */
1470         read_lock(&ha->hw_lock);
1471         state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1472         read_unlock(&ha->hw_lock);
1473
1474         while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1475                 udelay(100);
1476                 /* Window 1 call */
1477                 read_lock(&ha->hw_lock);
1478                 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1479                 read_unlock(&ha->hw_lock);
1480
1481                 loops++;
1482         }
1483
1484         if (loops >= 30000) {
1485                 DEBUG2(ql4_printk(KERN_INFO, ha,
1486                     "Receive Peg initialization not complete: 0x%x.\n", state));
1487                 return QLA_ERROR;
1488         }
1489
1490         return QLA_SUCCESS;
1491 }
1492
1493 void
1494 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1495 {
1496         uint32_t drv_active;
1497
1498         drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1499         drv_active |= (1 << (ha->func_num * 4));
1500         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1501                    __func__, ha->host_no, drv_active);
1502         qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1503 }
1504
1505 void
1506 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1507 {
1508         uint32_t drv_active;
1509
1510         drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1511         drv_active &= ~(1 << (ha->func_num * 4));
1512         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1513                    __func__, ha->host_no, drv_active);
1514         qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1515 }
1516
1517 static inline int
1518 qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1519 {
1520         uint32_t drv_state, drv_active;
1521         int rval;
1522
1523         drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1524         drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1525         rval = drv_state & (1 << (ha->func_num * 4));
1526         if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1527                 rval = 1;
1528
1529         return rval;
1530 }
1531
1532 static inline void
1533 qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1534 {
1535         uint32_t drv_state;
1536
1537         drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1538         drv_state |= (1 << (ha->func_num * 4));
1539         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1540                    __func__, ha->host_no, drv_state);
1541         qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1542 }
1543
1544 static inline void
1545 qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1546 {
1547         uint32_t drv_state;
1548
1549         drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1550         drv_state &= ~(1 << (ha->func_num * 4));
1551         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1552                    __func__, ha->host_no, drv_state);
1553         qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1554 }
1555
1556 static inline void
1557 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1558 {
1559         uint32_t qsnt_state;
1560
1561         qsnt_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1562         qsnt_state |= (2 << (ha->func_num * 4));
1563         qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
1564 }
1565
1566
1567 static int
1568 qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1569 {
1570         int pcie_cap;
1571         uint16_t lnk;
1572
1573         /* scrub dma mask expansion register */
1574         qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1575
1576         /* Overwrite stale initialization register values */
1577         qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1578         qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1579         qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1580         qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1581
1582         if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
1583                 printk("%s: Error trying to start fw!\n", __func__);
1584                 return QLA_ERROR;
1585         }
1586
1587         /* Handshake with the card before we register the devices. */
1588         if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1589                 printk("%s: Error during card handshake!\n", __func__);
1590                 return QLA_ERROR;
1591         }
1592
1593         /* Negotiated Link width */
1594         pcie_cap = pci_pcie_cap(ha->pdev);
1595         pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
1596         ha->link_width = (lnk >> 4) & 0x3f;
1597
1598         /* Synchronize with Receive peg */
1599         return qla4_82xx_rcvpeg_ready(ha);
1600 }
1601
1602 static int
1603 qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
1604 {
1605         int rval = QLA_ERROR;
1606
1607         /*
1608          * FW Load priority:
1609          * 1) Operational firmware residing in flash.
1610          * 2) Fail
1611          */
1612
1613         ql4_printk(KERN_INFO, ha,
1614             "FW: Retrieving flash offsets from FLT/FDT ...\n");
1615         rval = qla4_8xxx_get_flash_info(ha);
1616         if (rval != QLA_SUCCESS)
1617                 return rval;
1618
1619         ql4_printk(KERN_INFO, ha,
1620             "FW: Attempting to load firmware from flash...\n");
1621         rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
1622
1623         if (rval != QLA_SUCCESS) {
1624                 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1625                     " FAILED...\n");
1626                 return rval;
1627         }
1628
1629         return rval;
1630 }
1631
1632 static void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
1633 {
1634         if (qla4_82xx_rom_lock(ha)) {
1635                 /* Someone else is holding the lock. */
1636                 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1637         }
1638
1639         /*
1640          * Either we got the lock, or someone
1641          * else died while holding it.
1642          * In either case, unlock.
1643          */
1644         qla4_82xx_rom_unlock(ha);
1645 }
1646
1647 static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
1648                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
1649                                 uint32_t **d_ptr)
1650 {
1651         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1652         struct qla82xx_minidump_entry_crb *crb_hdr;
1653         uint32_t *data_ptr = *d_ptr;
1654
1655         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1656         crb_hdr = (struct qla82xx_minidump_entry_crb *)entry_hdr;
1657         r_addr = crb_hdr->addr;
1658         r_stride = crb_hdr->crb_strd.addr_stride;
1659         loop_cnt = crb_hdr->op_count;
1660
1661         for (i = 0; i < loop_cnt; i++) {
1662                 r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0);
1663                 *data_ptr++ = cpu_to_le32(r_addr);
1664                 *data_ptr++ = cpu_to_le32(r_value);
1665                 r_addr += r_stride;
1666         }
1667         *d_ptr = data_ptr;
1668 }
1669
1670 static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
1671                                  struct qla82xx_minidump_entry_hdr *entry_hdr,
1672                                  uint32_t **d_ptr)
1673 {
1674         uint32_t addr, r_addr, c_addr, t_r_addr;
1675         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
1676         unsigned long p_wait, w_time, p_mask;
1677         uint32_t c_value_w, c_value_r;
1678         struct qla82xx_minidump_entry_cache *cache_hdr;
1679         int rval = QLA_ERROR;
1680         uint32_t *data_ptr = *d_ptr;
1681
1682         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1683         cache_hdr = (struct qla82xx_minidump_entry_cache *)entry_hdr;
1684
1685         loop_count = cache_hdr->op_count;
1686         r_addr = cache_hdr->read_addr;
1687         c_addr = cache_hdr->control_addr;
1688         c_value_w = cache_hdr->cache_ctrl.write_value;
1689
1690         t_r_addr = cache_hdr->tag_reg_addr;
1691         t_value = cache_hdr->addr_ctrl.init_tag_value;
1692         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
1693         p_wait = cache_hdr->cache_ctrl.poll_wait;
1694         p_mask = cache_hdr->cache_ctrl.poll_mask;
1695
1696         for (i = 0; i < loop_count; i++) {
1697                 qla4_8xxx_md_rw_32(ha, t_r_addr, t_value, 1);
1698
1699                 if (c_value_w)
1700                         qla4_8xxx_md_rw_32(ha, c_addr, c_value_w, 1);
1701
1702                 if (p_mask) {
1703                         w_time = jiffies + p_wait;
1704                         do {
1705                                 c_value_r = qla4_8xxx_md_rw_32(ha, c_addr,
1706                                                                 0, 0);
1707                                 if ((c_value_r & p_mask) == 0) {
1708                                         break;
1709                                 } else if (time_after_eq(jiffies, w_time)) {
1710                                         /* capturing dump failed */
1711                                         return rval;
1712                                 }
1713                         } while (1);
1714                 }
1715
1716                 addr = r_addr;
1717                 for (k = 0; k < r_cnt; k++) {
1718                         r_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0);
1719                         *data_ptr++ = cpu_to_le32(r_value);
1720                         addr += cache_hdr->read_ctrl.read_addr_stride;
1721                 }
1722
1723                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
1724         }
1725         *d_ptr = data_ptr;
1726         return QLA_SUCCESS;
1727 }
1728
1729 static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
1730                                 struct qla82xx_minidump_entry_hdr *entry_hdr)
1731 {
1732         struct qla82xx_minidump_entry_crb *crb_entry;
1733         uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
1734         uint32_t crb_addr;
1735         unsigned long wtime;
1736         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
1737         int i;
1738
1739         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1740         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1741                                                 ha->fw_dump_tmplt_hdr;
1742         crb_entry = (struct qla82xx_minidump_entry_crb *)entry_hdr;
1743
1744         crb_addr = crb_entry->addr;
1745         for (i = 0; i < crb_entry->op_count; i++) {
1746                 opcode = crb_entry->crb_ctrl.opcode;
1747                 if (opcode & QLA82XX_DBG_OPCODE_WR) {
1748                         qla4_8xxx_md_rw_32(ha, crb_addr,
1749                                            crb_entry->value_1, 1);
1750                         opcode &= ~QLA82XX_DBG_OPCODE_WR;
1751                 }
1752                 if (opcode & QLA82XX_DBG_OPCODE_RW) {
1753                         read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0);
1754                         qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1);
1755                         opcode &= ~QLA82XX_DBG_OPCODE_RW;
1756                 }
1757                 if (opcode & QLA82XX_DBG_OPCODE_AND) {
1758                         read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0);
1759                         read_value &= crb_entry->value_2;
1760                         opcode &= ~QLA82XX_DBG_OPCODE_AND;
1761                         if (opcode & QLA82XX_DBG_OPCODE_OR) {
1762                                 read_value |= crb_entry->value_3;
1763                                 opcode &= ~QLA82XX_DBG_OPCODE_OR;
1764                         }
1765                         qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1);
1766                 }
1767                 if (opcode & QLA82XX_DBG_OPCODE_OR) {
1768                         read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0);
1769                         read_value |= crb_entry->value_3;
1770                         qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1);
1771                         opcode &= ~QLA82XX_DBG_OPCODE_OR;
1772                 }
1773                 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
1774                         poll_time = crb_entry->crb_strd.poll_timeout;
1775                         wtime = jiffies + poll_time;
1776                         read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0);
1777
1778                         do {
1779                                 if ((read_value & crb_entry->value_2) ==
1780                                     crb_entry->value_1)
1781                                         break;
1782                                 else if (time_after_eq(jiffies, wtime)) {
1783                                         /* capturing dump failed */
1784                                         rval = QLA_ERROR;
1785                                         break;
1786                                 } else
1787                                         read_value = qla4_8xxx_md_rw_32(ha,
1788                                                                 crb_addr, 0, 0);
1789                         } while (1);
1790                         opcode &= ~QLA82XX_DBG_OPCODE_POLL;
1791                 }
1792
1793                 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
1794                         if (crb_entry->crb_strd.state_index_a) {
1795                                 index = crb_entry->crb_strd.state_index_a;
1796                                 addr = tmplt_hdr->saved_state_array[index];
1797                         } else {
1798                                 addr = crb_addr;
1799                         }
1800
1801                         read_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0);
1802                         index = crb_entry->crb_ctrl.state_index_v;
1803                         tmplt_hdr->saved_state_array[index] = read_value;
1804                         opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
1805                 }
1806
1807                 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
1808                         if (crb_entry->crb_strd.state_index_a) {
1809                                 index = crb_entry->crb_strd.state_index_a;
1810                                 addr = tmplt_hdr->saved_state_array[index];
1811                         } else {
1812                                 addr = crb_addr;
1813                         }
1814
1815                         if (crb_entry->crb_ctrl.state_index_v) {
1816                                 index = crb_entry->crb_ctrl.state_index_v;
1817                                 read_value =
1818                                         tmplt_hdr->saved_state_array[index];
1819                         } else {
1820                                 read_value = crb_entry->value_1;
1821                         }
1822
1823                         qla4_8xxx_md_rw_32(ha, addr, read_value, 1);
1824                         opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
1825                 }
1826
1827                 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
1828                         index = crb_entry->crb_ctrl.state_index_v;
1829                         read_value = tmplt_hdr->saved_state_array[index];
1830                         read_value <<= crb_entry->crb_ctrl.shl;
1831                         read_value >>= crb_entry->crb_ctrl.shr;
1832                         if (crb_entry->value_2)
1833                                 read_value &= crb_entry->value_2;
1834                         read_value |= crb_entry->value_3;
1835                         read_value += crb_entry->value_1;
1836                         tmplt_hdr->saved_state_array[index] = read_value;
1837                         opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
1838                 }
1839                 crb_addr += crb_entry->crb_strd.addr_stride;
1840         }
1841         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
1842         return rval;
1843 }
1844
1845 static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
1846                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
1847                                 uint32_t **d_ptr)
1848 {
1849         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1850         struct qla82xx_minidump_entry_rdocm *ocm_hdr;
1851         uint32_t *data_ptr = *d_ptr;
1852
1853         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1854         ocm_hdr = (struct qla82xx_minidump_entry_rdocm *)entry_hdr;
1855         r_addr = ocm_hdr->read_addr;
1856         r_stride = ocm_hdr->read_addr_stride;
1857         loop_cnt = ocm_hdr->op_count;
1858
1859         DEBUG2(ql4_printk(KERN_INFO, ha,
1860                           "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
1861                           __func__, r_addr, r_stride, loop_cnt));
1862
1863         for (i = 0; i < loop_cnt; i++) {
1864                 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
1865                 *data_ptr++ = cpu_to_le32(r_value);
1866                 r_addr += r_stride;
1867         }
1868         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
1869                 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
1870         *d_ptr = data_ptr;
1871 }
1872
1873 static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
1874                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
1875                                 uint32_t **d_ptr)
1876 {
1877         uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
1878         struct qla82xx_minidump_entry_mux *mux_hdr;
1879         uint32_t *data_ptr = *d_ptr;
1880
1881         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1882         mux_hdr = (struct qla82xx_minidump_entry_mux *)entry_hdr;
1883         r_addr = mux_hdr->read_addr;
1884         s_addr = mux_hdr->select_addr;
1885         s_stride = mux_hdr->select_value_stride;
1886         s_value = mux_hdr->select_value;
1887         loop_cnt = mux_hdr->op_count;
1888
1889         for (i = 0; i < loop_cnt; i++) {
1890                 qla4_8xxx_md_rw_32(ha, s_addr, s_value, 1);
1891                 r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0);
1892                 *data_ptr++ = cpu_to_le32(s_value);
1893                 *data_ptr++ = cpu_to_le32(r_value);
1894                 s_value += s_stride;
1895         }
1896         *d_ptr = data_ptr;
1897 }
1898
1899 static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
1900                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
1901                                 uint32_t **d_ptr)
1902 {
1903         uint32_t addr, r_addr, c_addr, t_r_addr;
1904         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
1905         uint32_t c_value_w;
1906         struct qla82xx_minidump_entry_cache *cache_hdr;
1907         uint32_t *data_ptr = *d_ptr;
1908
1909         cache_hdr = (struct qla82xx_minidump_entry_cache *)entry_hdr;
1910         loop_count = cache_hdr->op_count;
1911         r_addr = cache_hdr->read_addr;
1912         c_addr = cache_hdr->control_addr;
1913         c_value_w = cache_hdr->cache_ctrl.write_value;
1914
1915         t_r_addr = cache_hdr->tag_reg_addr;
1916         t_value = cache_hdr->addr_ctrl.init_tag_value;
1917         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
1918
1919         for (i = 0; i < loop_count; i++) {
1920                 qla4_8xxx_md_rw_32(ha, t_r_addr, t_value, 1);
1921                 qla4_8xxx_md_rw_32(ha, c_addr, c_value_w, 1);
1922                 addr = r_addr;
1923                 for (k = 0; k < r_cnt; k++) {
1924                         r_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0);
1925                         *data_ptr++ = cpu_to_le32(r_value);
1926                         addr += cache_hdr->read_ctrl.read_addr_stride;
1927                 }
1928                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
1929         }
1930         *d_ptr = data_ptr;
1931 }
1932
1933 static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
1934                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
1935                                 uint32_t **d_ptr)
1936 {
1937         uint32_t s_addr, r_addr;
1938         uint32_t r_stride, r_value, r_cnt, qid = 0;
1939         uint32_t i, k, loop_cnt;
1940         struct qla82xx_minidump_entry_queue *q_hdr;
1941         uint32_t *data_ptr = *d_ptr;
1942
1943         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1944         q_hdr = (struct qla82xx_minidump_entry_queue *)entry_hdr;
1945         s_addr = q_hdr->select_addr;
1946         r_cnt = q_hdr->rd_strd.read_addr_cnt;
1947         r_stride = q_hdr->rd_strd.read_addr_stride;
1948         loop_cnt = q_hdr->op_count;
1949
1950         for (i = 0; i < loop_cnt; i++) {
1951                 qla4_8xxx_md_rw_32(ha, s_addr, qid, 1);
1952                 r_addr = q_hdr->read_addr;
1953                 for (k = 0; k < r_cnt; k++) {
1954                         r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0);
1955                         *data_ptr++ = cpu_to_le32(r_value);
1956                         r_addr += r_stride;
1957                 }
1958                 qid += q_hdr->q_strd.queue_id_stride;
1959         }
1960         *d_ptr = data_ptr;
1961 }
1962
1963 #define MD_DIRECT_ROM_WINDOW            0x42110030
1964 #define MD_DIRECT_ROM_READ_BASE         0x42150000
1965
1966 static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
1967                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
1968                                 uint32_t **d_ptr)
1969 {
1970         uint32_t r_addr, r_value;
1971         uint32_t i, loop_cnt;
1972         struct qla82xx_minidump_entry_rdrom *rom_hdr;
1973         uint32_t *data_ptr = *d_ptr;
1974
1975         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1976         rom_hdr = (struct qla82xx_minidump_entry_rdrom *)entry_hdr;
1977         r_addr = rom_hdr->read_addr;
1978         loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
1979
1980         DEBUG2(ql4_printk(KERN_INFO, ha,
1981                           "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n",
1982                            __func__, r_addr, loop_cnt));
1983
1984         for (i = 0; i < loop_cnt; i++) {
1985                 qla4_8xxx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
1986                                    (r_addr & 0xFFFF0000), 1);
1987                 r_value = qla4_8xxx_md_rw_32(ha,
1988                                              MD_DIRECT_ROM_READ_BASE +
1989                                              (r_addr & 0x0000FFFF), 0, 0);
1990                 *data_ptr++ = cpu_to_le32(r_value);
1991                 r_addr += sizeof(uint32_t);
1992         }
1993         *d_ptr = data_ptr;
1994 }
1995
1996 #define MD_MIU_TEST_AGT_CTRL            0x41000090
1997 #define MD_MIU_TEST_AGT_ADDR_LO         0x41000094
1998 #define MD_MIU_TEST_AGT_ADDR_HI         0x41000098
1999
2000 static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
2001                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
2002                                 uint32_t **d_ptr)
2003 {
2004         uint32_t r_addr, r_value, r_data;
2005         uint32_t i, j, loop_cnt;
2006         struct qla82xx_minidump_entry_rdmem *m_hdr;
2007         unsigned long flags;
2008         uint32_t *data_ptr = *d_ptr;
2009
2010         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2011         m_hdr = (struct qla82xx_minidump_entry_rdmem *)entry_hdr;
2012         r_addr = m_hdr->read_addr;
2013         loop_cnt = m_hdr->read_data_size/16;
2014
2015         DEBUG2(ql4_printk(KERN_INFO, ha,
2016                           "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2017                           __func__, r_addr, m_hdr->read_data_size));
2018
2019         if (r_addr & 0xf) {
2020                 DEBUG2(ql4_printk(KERN_INFO, ha,
2021                                   "[%s]: Read addr 0x%x not 16 bytes alligned\n",
2022                                   __func__, r_addr));
2023                 return QLA_ERROR;
2024         }
2025
2026         if (m_hdr->read_data_size % 16) {
2027                 DEBUG2(ql4_printk(KERN_INFO, ha,
2028                                   "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2029                                   __func__, m_hdr->read_data_size));
2030                 return QLA_ERROR;
2031         }
2032
2033         DEBUG2(ql4_printk(KERN_INFO, ha,
2034                           "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2035                           __func__, r_addr, m_hdr->read_data_size, loop_cnt));
2036
2037         write_lock_irqsave(&ha->hw_lock, flags);
2038         for (i = 0; i < loop_cnt; i++) {
2039                 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
2040                 r_value = 0;
2041                 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
2042                 r_value = MIU_TA_CTL_ENABLE;
2043                 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
2044                 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
2045                 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
2046
2047                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2048                         r_value = qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL,
2049                                                      0, 0);
2050                         if ((r_value & MIU_TA_CTL_BUSY) == 0)
2051                                 break;
2052                 }
2053
2054                 if (j >= MAX_CTL_CHECK) {
2055                         printk_ratelimited(KERN_ERR
2056                                            "%s: failed to read through agent\n",
2057                                             __func__);
2058                         write_unlock_irqrestore(&ha->hw_lock, flags);
2059                         return QLA_SUCCESS;
2060                 }
2061
2062                 for (j = 0; j < 4; j++) {
2063                         r_data = qla4_8xxx_md_rw_32(ha,
2064                                                     MD_MIU_TEST_AGT_RDDATA[j],
2065                                                     0, 0);
2066                         *data_ptr++ = cpu_to_le32(r_data);
2067                 }
2068
2069                 r_addr += 16;
2070         }
2071         write_unlock_irqrestore(&ha->hw_lock, flags);
2072
2073         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
2074                           __func__, (loop_cnt * 16)));
2075
2076         *d_ptr = data_ptr;
2077         return QLA_SUCCESS;
2078 }
2079
2080 static void ql4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
2081                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
2082                                 int index)
2083 {
2084         entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
2085         DEBUG2(ql4_printk(KERN_INFO, ha,
2086                           "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2087                           ha->host_no, index, entry_hdr->entry_type,
2088                           entry_hdr->d_ctrl.entry_capture_mask));
2089 }
2090
2091 /**
2092  * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
2093  * @ha: pointer to adapter structure
2094  **/
2095 static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2096 {
2097         int num_entry_hdr = 0;
2098         struct qla82xx_minidump_entry_hdr *entry_hdr;
2099         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2100         uint32_t *data_ptr;
2101         uint32_t data_collected = 0;
2102         int i, rval = QLA_ERROR;
2103         uint64_t now;
2104         uint32_t timestamp;
2105
2106         if (!ha->fw_dump) {
2107                 ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
2108                            __func__, ha->host_no);
2109                 return rval;
2110         }
2111
2112         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2113                                                 ha->fw_dump_tmplt_hdr;
2114         data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
2115                                                 ha->fw_dump_tmplt_size);
2116         data_collected += ha->fw_dump_tmplt_size;
2117
2118         num_entry_hdr = tmplt_hdr->num_of_entries;
2119         ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
2120                    __func__, data_ptr);
2121         ql4_printk(KERN_INFO, ha,
2122                    "[%s]: no of entry headers in Template: 0x%x\n",
2123                    __func__, num_entry_hdr);
2124         ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
2125                    __func__, ha->fw_dump_capture_mask);
2126         ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
2127                    __func__, ha->fw_dump_size, ha->fw_dump_size);
2128
2129         /* Update current timestamp before taking dump */
2130         now = get_jiffies_64();
2131         timestamp = (u32)(jiffies_to_msecs(now) / 1000);
2132         tmplt_hdr->driver_timestamp = timestamp;
2133
2134         entry_hdr = (struct qla82xx_minidump_entry_hdr *)
2135                                         (((uint8_t *)ha->fw_dump_tmplt_hdr) +
2136                                          tmplt_hdr->first_entry_offset);
2137
2138         /* Walk through the entry headers - validate/perform required action */
2139         for (i = 0; i < num_entry_hdr; i++) {
2140                 if (data_collected >= ha->fw_dump_size) {
2141                         ql4_printk(KERN_INFO, ha,
2142                                    "Data collected: [0x%x], Total Dump size: [0x%x]\n",
2143                                    data_collected, ha->fw_dump_size);
2144                         return rval;
2145                 }
2146
2147                 if (!(entry_hdr->d_ctrl.entry_capture_mask &
2148                       ha->fw_dump_capture_mask)) {
2149                         entry_hdr->d_ctrl.driver_flags |=
2150                                                 QLA82XX_DBG_SKIPPED_FLAG;
2151                         goto skip_nxt_entry;
2152                 }
2153
2154                 DEBUG2(ql4_printk(KERN_INFO, ha,
2155                                   "Data collected: [0x%x], Dump size left:[0x%x]\n",
2156                                   data_collected,
2157                                   (ha->fw_dump_size - data_collected)));
2158
2159                 /* Decode the entry type and take required action to capture
2160                  * debug data
2161                  */
2162                 switch (entry_hdr->entry_type) {
2163                 case QLA82XX_RDEND:
2164                         ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2165                         break;
2166                 case QLA82XX_CNTRL:
2167                         rval = qla4_8xxx_minidump_process_control(ha,
2168                                                                   entry_hdr);
2169                         if (rval != QLA_SUCCESS) {
2170                                 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2171                                 goto md_failed;
2172                         }
2173                         break;
2174                 case QLA82XX_RDCRB:
2175                         qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
2176                                                          &data_ptr);
2177                         break;
2178                 case QLA82XX_RDMEM:
2179                         rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2180                                                                 &data_ptr);
2181                         if (rval != QLA_SUCCESS) {
2182                                 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2183                                 goto md_failed;
2184                         }
2185                         break;
2186                 case QLA82XX_BOARD:
2187                 case QLA82XX_RDROM:
2188                         qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
2189                                                          &data_ptr);
2190                         break;
2191                 case QLA82XX_L2DTG:
2192                 case QLA82XX_L2ITG:
2193                 case QLA82XX_L2DAT:
2194                 case QLA82XX_L2INS:
2195                         rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
2196                                                                 &data_ptr);
2197                         if (rval != QLA_SUCCESS) {
2198                                 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2199                                 goto md_failed;
2200                         }
2201                         break;
2202                 case QLA82XX_L1DAT:
2203                 case QLA82XX_L1INS:
2204                         qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
2205                                                            &data_ptr);
2206                         break;
2207                 case QLA82XX_RDOCM:
2208                         qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
2209                                                          &data_ptr);
2210                         break;
2211                 case QLA82XX_RDMUX:
2212                         qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
2213                                                          &data_ptr);
2214                         break;
2215                 case QLA82XX_QUEUE:
2216                         qla4_8xxx_minidump_process_queue(ha, entry_hdr,
2217                                                          &data_ptr);
2218                         break;
2219                 case QLA82XX_RDNOP:
2220                 default:
2221                         ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2222                         break;
2223                 }
2224
2225                 data_collected = (uint8_t *)data_ptr -
2226                                  ((uint8_t *)((uint8_t *)ha->fw_dump +
2227                                                 ha->fw_dump_tmplt_size));
2228 skip_nxt_entry:
2229                 /*  next entry in the template */
2230                 entry_hdr = (struct qla82xx_minidump_entry_hdr *)
2231                                 (((uint8_t *)entry_hdr) +
2232                                  entry_hdr->entry_size);
2233         }
2234
2235         if ((data_collected + ha->fw_dump_tmplt_size) != ha->fw_dump_size) {
2236                 ql4_printk(KERN_INFO, ha,
2237                            "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n",
2238                            data_collected, ha->fw_dump_size);
2239                 goto md_failed;
2240         }
2241
2242         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
2243                           __func__, i));
2244 md_failed:
2245         return rval;
2246 }
2247
2248 /**
2249  * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready.
2250  * @ha: pointer to adapter structure
2251  **/
2252 static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
2253 {
2254         char event_string[40];
2255         char *envp[] = { event_string, NULL };
2256
2257         switch (code) {
2258         case QL4_UEVENT_CODE_FW_DUMP:
2259                 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
2260                          ha->host_no);
2261                 break;
2262         default:
2263                 /*do nothing*/
2264                 break;
2265         }
2266
2267         kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
2268 }
2269
2270 /**
2271  * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
2272  * @ha: pointer to adapter structure
2273  *
2274  * Note: IDC lock must be held upon entry
2275  **/
2276 static int
2277 qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
2278 {
2279         int rval = QLA_ERROR;
2280         int i, timeout;
2281         uint32_t old_count, count;
2282         int need_reset = 0, peg_stuck = 1;
2283
2284         need_reset = qla4_8xxx_need_reset(ha);
2285
2286         old_count = qla4_82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2287
2288         for (i = 0; i < 10; i++) {
2289                 timeout = msleep_interruptible(200);
2290                 if (timeout) {
2291                         qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2292                            QLA82XX_DEV_FAILED);
2293                         return rval;
2294                 }
2295
2296                 count = qla4_82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2297                 if (count != old_count)
2298                         peg_stuck = 0;
2299         }
2300
2301         if (need_reset) {
2302                 /* We are trying to perform a recovery here. */
2303                 if (peg_stuck)
2304                         qla4_82xx_rom_lock_recovery(ha);
2305                 goto dev_initialize;
2306         } else  {
2307                 /* Start of day for this ha context. */
2308                 if (peg_stuck) {
2309                         /* Either we are the first or recovery in progress. */
2310                         qla4_82xx_rom_lock_recovery(ha);
2311                         goto dev_initialize;
2312                 } else {
2313                         /* Firmware already running. */
2314                         rval = QLA_SUCCESS;
2315                         goto dev_ready;
2316                 }
2317         }
2318
2319 dev_initialize:
2320         /* set to DEV_INITIALIZING */
2321         ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
2322         qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
2323
2324         /* Driver that sets device state to initializating sets IDC version */
2325         qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
2326
2327         qla4_82xx_idc_unlock(ha);
2328         if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
2329             !test_and_set_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
2330                 if (!qla4_8xxx_collect_md_data(ha)) {
2331                         qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
2332                 } else {
2333                         ql4_printk(KERN_INFO, ha, "Unable to collect minidump\n");
2334                         clear_bit(AF_82XX_FW_DUMPED, &ha->flags);
2335                 }
2336         }
2337         rval = qla4_82xx_try_start_fw(ha);
2338         qla4_82xx_idc_lock(ha);
2339
2340         if (rval != QLA_SUCCESS) {
2341                 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
2342                 qla4_8xxx_clear_drv_active(ha);
2343                 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
2344                 return rval;
2345         }
2346
2347 dev_ready:
2348         ql4_printk(KERN_INFO, ha, "HW State: READY\n");
2349         qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
2350
2351         return rval;
2352 }
2353
2354 /**
2355  * qla4_82xx_need_reset_handler - Code to start reset sequence
2356  * @ha: pointer to adapter structure
2357  *
2358  * Note: IDC lock must be held upon entry
2359  **/
2360 static void
2361 qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
2362 {
2363         uint32_t dev_state, drv_state, drv_active;
2364         uint32_t active_mask = 0xFFFFFFFF;
2365         unsigned long reset_timeout;
2366
2367         ql4_printk(KERN_INFO, ha,
2368                 "Performing ISP error recovery\n");
2369
2370         if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
2371                 qla4_82xx_idc_unlock(ha);
2372                 ha->isp_ops->disable_intrs(ha);
2373                 qla4_82xx_idc_lock(ha);
2374         }
2375
2376         if (!test_bit(AF_82XX_RST_OWNER, &ha->flags)) {
2377                 DEBUG2(ql4_printk(KERN_INFO, ha,
2378                                   "%s(%ld): reset acknowledged\n",
2379                                   __func__, ha->host_no));
2380                 qla4_8xxx_set_rst_ready(ha);
2381         } else {
2382                 active_mask = (~(1 << (ha->func_num * 4)));
2383         }
2384
2385         /* wait for 10 seconds for reset ack from all functions */
2386         reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
2387
2388         drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2389         drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2390
2391         ql4_printk(KERN_INFO, ha,
2392                 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2393                 __func__, ha->host_no, drv_state, drv_active);
2394
2395         while (drv_state != (drv_active & active_mask)) {
2396                 if (time_after_eq(jiffies, reset_timeout)) {
2397                         ql4_printk(KERN_INFO, ha,
2398                                    "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
2399                                    DRIVER_NAME, drv_state, drv_active);
2400                         break;
2401                 }
2402
2403                 /*
2404                  * When reset_owner times out, check which functions
2405                  * acked/did not ack
2406                  */
2407                 if (test_bit(AF_82XX_RST_OWNER, &ha->flags)) {
2408                         ql4_printk(KERN_INFO, ha,
2409                                    "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2410                                    __func__, ha->host_no, drv_state,
2411                                    drv_active);
2412                 }
2413                 qla4_82xx_idc_unlock(ha);
2414                 msleep(1000);
2415                 qla4_82xx_idc_lock(ha);
2416
2417                 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2418                 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2419         }
2420
2421         /* Clear RESET OWNER as we are not going to use it any further */
2422         clear_bit(AF_82XX_RST_OWNER, &ha->flags);
2423
2424         dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2425         ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
2426                    dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
2427
2428         /* Force to DEV_COLD unless someone else is starting a reset */
2429         if (dev_state != QLA82XX_DEV_INITIALIZING) {
2430                 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
2431                 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
2432                 qla4_8xxx_set_rst_ready(ha);
2433         }
2434 }
2435
2436 /**
2437  * qla4_8xxx_need_qsnt_handler - Code to start qsnt
2438  * @ha: pointer to adapter structure
2439  **/
2440 void
2441 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
2442 {
2443         qla4_82xx_idc_lock(ha);
2444         qla4_8xxx_set_qsnt_ready(ha);
2445         qla4_82xx_idc_unlock(ha);
2446 }
2447
2448 /**
2449  * qla4_8xxx_device_state_handler - Adapter state machine
2450  * @ha: pointer to host adapter structure.
2451  *
2452  * Note: IDC lock must be UNLOCKED upon entry
2453  **/
2454 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2455 {
2456         uint32_t dev_state;
2457         int rval = QLA_SUCCESS;
2458         unsigned long dev_init_timeout;
2459
2460         if (!test_bit(AF_INIT_DONE, &ha->flags)) {
2461                 qla4_82xx_idc_lock(ha);
2462                 qla4_8xxx_set_drv_active(ha);
2463                 qla4_82xx_idc_unlock(ha);
2464         }
2465
2466         dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2467         DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2468                           dev_state, dev_state < MAX_STATES ?
2469                           qdev_state[dev_state] : "Unknown"));
2470
2471         /* wait for 30 seconds for device to go ready */
2472         dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
2473
2474         qla4_82xx_idc_lock(ha);
2475         while (1) {
2476
2477                 if (time_after_eq(jiffies, dev_init_timeout)) {
2478                         ql4_printk(KERN_WARNING, ha,
2479                                    "%s: Device Init Failed 0x%x = %s\n",
2480                                    DRIVER_NAME,
2481                                    dev_state, dev_state < MAX_STATES ?
2482                                    qdev_state[dev_state] : "Unknown");
2483                         qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2484                                 QLA82XX_DEV_FAILED);
2485                 }
2486
2487                 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2488                 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2489                            dev_state, dev_state < MAX_STATES ?
2490                            qdev_state[dev_state] : "Unknown");
2491
2492                 /* NOTE: Make sure idc unlocked upon exit of switch statement */
2493                 switch (dev_state) {
2494                 case QLA82XX_DEV_READY:
2495                         goto exit;
2496                 case QLA82XX_DEV_COLD:
2497                         rval = qla4_8xxx_device_bootstrap(ha);
2498                         goto exit;
2499                 case QLA82XX_DEV_INITIALIZING:
2500                         qla4_82xx_idc_unlock(ha);
2501                         msleep(1000);
2502                         qla4_82xx_idc_lock(ha);
2503                         break;
2504                 case QLA82XX_DEV_NEED_RESET:
2505                         if (!ql4xdontresethba) {
2506                                 qla4_82xx_need_reset_handler(ha);
2507                                 /* Update timeout value after need
2508                                  * reset handler */
2509                                 dev_init_timeout = jiffies +
2510                                         (ha->nx_dev_init_timeout * HZ);
2511                         } else {
2512                                 qla4_82xx_idc_unlock(ha);
2513                                 msleep(1000);
2514                                 qla4_82xx_idc_lock(ha);
2515                         }
2516                         break;
2517                 case QLA82XX_DEV_NEED_QUIESCENT:
2518                         /* idc locked/unlocked in handler */
2519                         qla4_8xxx_need_qsnt_handler(ha);
2520                         break;
2521                 case QLA82XX_DEV_QUIESCENT:
2522                         qla4_82xx_idc_unlock(ha);
2523                         msleep(1000);
2524                         qla4_82xx_idc_lock(ha);
2525                         break;
2526                 case QLA82XX_DEV_FAILED:
2527                         qla4_82xx_idc_unlock(ha);
2528                         qla4xxx_dead_adapter_cleanup(ha);
2529                         rval = QLA_ERROR;
2530                         qla4_82xx_idc_lock(ha);
2531                         goto exit;
2532                 default:
2533                         qla4_82xx_idc_unlock(ha);
2534                         qla4xxx_dead_adapter_cleanup(ha);
2535                         rval = QLA_ERROR;
2536                         qla4_82xx_idc_lock(ha);
2537                         goto exit;
2538                 }
2539         }
2540 exit:
2541         qla4_82xx_idc_unlock(ha);
2542         return rval;
2543 }
2544
2545 int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
2546 {
2547         int retval;
2548
2549         /* clear the interrupt */
2550         writel(0, &ha->qla4_8xxx_reg->host_int);
2551         readl(&ha->qla4_8xxx_reg->host_int);
2552
2553         retval = qla4_8xxx_device_state_handler(ha);
2554
2555         if (retval == QLA_SUCCESS && !test_bit(AF_INIT_DONE, &ha->flags))
2556                 retval = qla4xxx_request_irqs(ha);
2557
2558         return retval;
2559 }
2560
2561 /*****************************************************************************/
2562 /* Flash Manipulation Routines                                               */
2563 /*****************************************************************************/
2564
2565 #define OPTROM_BURST_SIZE       0x1000
2566 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
2567
2568 #define FARX_DATA_FLAG  BIT_31
2569 #define FARX_ACCESS_FLASH_CONF  0x7FFD0000
2570 #define FARX_ACCESS_FLASH_DATA  0x7FF00000
2571
2572 static inline uint32_t
2573 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
2574 {
2575         return hw->flash_conf_off | faddr;
2576 }
2577
2578 static inline uint32_t
2579 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
2580 {
2581         return hw->flash_data_off | faddr;
2582 }
2583
2584 static uint32_t *
2585 qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
2586     uint32_t faddr, uint32_t length)
2587 {
2588         uint32_t i;
2589         uint32_t val;
2590         int loops = 0;
2591         while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
2592                 udelay(100);
2593                 cond_resched();
2594                 loops++;
2595         }
2596         if (loops >= 50000) {
2597                 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
2598                 return dwptr;
2599         }
2600
2601         /* Dword reads to flash. */
2602         for (i = 0; i < length/4; i++, faddr += 4) {
2603                 if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
2604                         ql4_printk(KERN_WARNING, ha,
2605                             "Do ROM fast read failed\n");
2606                         goto done_read;
2607                 }
2608                 dwptr[i] = __constant_cpu_to_le32(val);
2609         }
2610
2611 done_read:
2612         qla4_82xx_rom_unlock(ha);
2613         return dwptr;
2614 }
2615
2616 /**
2617  * Address and length are byte address
2618  **/
2619 static uint8_t *
2620 qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
2621                 uint32_t offset, uint32_t length)
2622 {
2623         qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
2624         return buf;
2625 }
2626
2627 static int
2628 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
2629 {
2630         const char *loc, *locations[] = { "DEF", "PCI" };
2631
2632         /*
2633          * FLT-location structure resides after the last PCI region.
2634          */
2635
2636         /* Begin with sane defaults. */
2637         loc = locations[0];
2638         *start = FA_FLASH_LAYOUT_ADDR_82;
2639
2640         DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
2641         return QLA_SUCCESS;
2642 }
2643
2644 static void
2645 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
2646 {
2647         const char *loc, *locations[] = { "DEF", "FLT" };
2648         uint16_t *wptr;
2649         uint16_t cnt, chksum;
2650         uint32_t start;
2651         struct qla_flt_header *flt;
2652         struct qla_flt_region *region;
2653         struct ql82xx_hw_data *hw = &ha->hw;
2654
2655         hw->flt_region_flt = flt_addr;
2656         wptr = (uint16_t *)ha->request_ring;
2657         flt = (struct qla_flt_header *)ha->request_ring;
2658         region = (struct qla_flt_region *)&flt[1];
2659         qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2660                         flt_addr << 2, OPTROM_BURST_SIZE);
2661         if (*wptr == __constant_cpu_to_le16(0xffff))
2662                 goto no_flash_data;
2663         if (flt->version != __constant_cpu_to_le16(1)) {
2664                 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
2665                         "version=0x%x length=0x%x checksum=0x%x.\n",
2666                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
2667                         le16_to_cpu(flt->checksum)));
2668                 goto no_flash_data;
2669         }
2670
2671         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
2672         for (chksum = 0; cnt; cnt--)
2673                 chksum += le16_to_cpu(*wptr++);
2674         if (chksum) {
2675                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
2676                         "version=0x%x length=0x%x checksum=0x%x.\n",
2677                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
2678                         chksum));
2679                 goto no_flash_data;
2680         }
2681
2682         loc = locations[1];
2683         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
2684         for ( ; cnt; cnt--, region++) {
2685                 /* Store addresses as DWORD offsets. */
2686                 start = le32_to_cpu(region->start) >> 2;
2687
2688                 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
2689                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
2690                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
2691
2692                 switch (le32_to_cpu(region->code) & 0xff) {
2693                 case FLT_REG_FDT:
2694                         hw->flt_region_fdt = start;
2695                         break;
2696                 case FLT_REG_BOOT_CODE_82:
2697                         hw->flt_region_boot = start;
2698                         break;
2699                 case FLT_REG_FW_82:
2700                 case FLT_REG_FW_82_1:
2701                         hw->flt_region_fw = start;
2702                         break;
2703                 case FLT_REG_BOOTLOAD_82:
2704                         hw->flt_region_bootload = start;
2705                         break;
2706                 case FLT_REG_ISCSI_PARAM:
2707                         hw->flt_iscsi_param =  start;
2708                         break;
2709                 case FLT_REG_ISCSI_CHAP:
2710                         hw->flt_region_chap =  start;
2711                         hw->flt_chap_size =  le32_to_cpu(region->size);
2712                         break;
2713                 }
2714         }
2715         goto done;
2716
2717 no_flash_data:
2718         /* Use hardcoded defaults. */
2719         loc = locations[0];
2720
2721         hw->flt_region_fdt      = FA_FLASH_DESCR_ADDR_82;
2722         hw->flt_region_boot     = FA_BOOT_CODE_ADDR_82;
2723         hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
2724         hw->flt_region_fw       = FA_RISC_CODE_ADDR_82;
2725         hw->flt_region_chap     = FA_FLASH_ISCSI_CHAP;
2726         hw->flt_chap_size       = FA_FLASH_CHAP_SIZE;
2727
2728 done:
2729         DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x "
2730             "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt,
2731             hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload,
2732             hw->flt_region_fw));
2733 }
2734
2735 static void
2736 qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
2737 {
2738 #define FLASH_BLK_SIZE_4K       0x1000
2739 #define FLASH_BLK_SIZE_32K      0x8000
2740 #define FLASH_BLK_SIZE_64K      0x10000
2741         const char *loc, *locations[] = { "MID", "FDT" };
2742         uint16_t cnt, chksum;
2743         uint16_t *wptr;
2744         struct qla_fdt_layout *fdt;
2745         uint16_t mid = 0;
2746         uint16_t fid = 0;
2747         struct ql82xx_hw_data *hw = &ha->hw;
2748
2749         hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2750         hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
2751
2752         wptr = (uint16_t *)ha->request_ring;
2753         fdt = (struct qla_fdt_layout *)ha->request_ring;
2754         qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2755             hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
2756
2757         if (*wptr == __constant_cpu_to_le16(0xffff))
2758                 goto no_flash_data;
2759
2760         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
2761             fdt->sig[3] != 'D')
2762                 goto no_flash_data;
2763
2764         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
2765             cnt++)
2766                 chksum += le16_to_cpu(*wptr++);
2767
2768         if (chksum) {
2769                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
2770                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
2771                     le16_to_cpu(fdt->version)));
2772                 goto no_flash_data;
2773         }
2774
2775         loc = locations[1];
2776         mid = le16_to_cpu(fdt->man_id);
2777         fid = le16_to_cpu(fdt->id);
2778         hw->fdt_wrt_disable = fdt->wrt_disable_bits;
2779         hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
2780         hw->fdt_block_size = le32_to_cpu(fdt->block_size);
2781
2782         if (fdt->unprotect_sec_cmd) {
2783                 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
2784                     fdt->unprotect_sec_cmd);
2785                 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
2786                     flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
2787                     flash_conf_addr(hw, 0x0336);
2788         }
2789         goto done;
2790
2791 no_flash_data:
2792         loc = locations[0];
2793         hw->fdt_block_size = FLASH_BLK_SIZE_64K;
2794 done:
2795         DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
2796                 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
2797                 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
2798                 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
2799                 hw->fdt_block_size));
2800 }
2801
2802 static void
2803 qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
2804 {
2805 #define QLA82XX_IDC_PARAM_ADDR      0x003e885c
2806         uint32_t *wptr;
2807
2808         if (!is_qla8022(ha))
2809                 return;
2810         wptr = (uint32_t *)ha->request_ring;
2811         qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2812                         QLA82XX_IDC_PARAM_ADDR , 8);
2813
2814         if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
2815                 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
2816                 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
2817         } else {
2818                 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
2819                 ha->nx_reset_timeout = le32_to_cpu(*wptr);
2820         }
2821
2822         DEBUG2(ql4_printk(KERN_DEBUG, ha,
2823                 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
2824         DEBUG2(ql4_printk(KERN_DEBUG, ha,
2825                 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
2826         return;
2827 }
2828
2829 int
2830 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
2831 {
2832         int ret;
2833         uint32_t flt_addr;
2834
2835         ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
2836         if (ret != QLA_SUCCESS)
2837                 return ret;
2838
2839         qla4_8xxx_get_flt_info(ha, flt_addr);
2840         qla4_82xx_get_fdt_info(ha);
2841         qla4_82xx_get_idc_param(ha);
2842
2843         return QLA_SUCCESS;
2844 }
2845
2846 /**
2847  * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
2848  * @ha: pointer to host adapter structure.
2849  *
2850  * Remarks:
2851  * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
2852  * not be available after successful return.  Driver must cleanup potential
2853  * outstanding I/O's after calling this funcion.
2854  **/
2855 int
2856 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
2857 {
2858         int status;
2859         uint32_t mbox_cmd[MBOX_REG_COUNT];
2860         uint32_t mbox_sts[MBOX_REG_COUNT];
2861
2862         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2863         memset(&mbox_sts, 0, sizeof(mbox_sts));
2864
2865         mbox_cmd[0] = MBOX_CMD_STOP_FW;
2866         status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
2867             &mbox_cmd[0], &mbox_sts[0]);
2868
2869         DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
2870             __func__, status));
2871         return status;
2872 }
2873
2874 /**
2875  * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
2876  * @ha: pointer to host adapter structure.
2877  **/
2878 int
2879 qla4_82xx_isp_reset(struct scsi_qla_host *ha)
2880 {
2881         int rval;
2882         uint32_t dev_state;
2883
2884         qla4_82xx_idc_lock(ha);
2885         dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2886
2887         if (dev_state == QLA82XX_DEV_READY) {
2888                 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
2889                 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2890                     QLA82XX_DEV_NEED_RESET);
2891                 set_bit(AF_82XX_RST_OWNER, &ha->flags);
2892         } else
2893                 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
2894
2895         qla4_82xx_idc_unlock(ha);
2896
2897         rval = qla4_8xxx_device_state_handler(ha);
2898
2899         qla4_82xx_idc_lock(ha);
2900         qla4_8xxx_clear_rst_ready(ha);
2901         qla4_82xx_idc_unlock(ha);
2902
2903         if (rval == QLA_SUCCESS) {
2904                 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
2905                 clear_bit(AF_FW_RECOVERY, &ha->flags);
2906         }
2907
2908         return rval;
2909 }
2910
2911 /**
2912  * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
2913  * @ha: pointer to host adapter structure.
2914  *
2915  **/
2916 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
2917 {
2918         uint32_t mbox_cmd[MBOX_REG_COUNT];
2919         uint32_t mbox_sts[MBOX_REG_COUNT];
2920         struct mbx_sys_info *sys_info;
2921         dma_addr_t sys_info_dma;
2922         int status = QLA_ERROR;
2923
2924         sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
2925                                       &sys_info_dma, GFP_KERNEL);
2926         if (sys_info == NULL) {
2927                 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
2928                     ha->host_no, __func__));
2929                 return status;
2930         }
2931
2932         memset(sys_info, 0, sizeof(*sys_info));
2933         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2934         memset(&mbox_sts, 0, sizeof(mbox_sts));
2935
2936         mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
2937         mbox_cmd[1] = LSDW(sys_info_dma);
2938         mbox_cmd[2] = MSDW(sys_info_dma);
2939         mbox_cmd[4] = sizeof(*sys_info);
2940
2941         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
2942             &mbox_sts[0]) != QLA_SUCCESS) {
2943                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
2944                     ha->host_no, __func__));
2945                 goto exit_validate_mac82;
2946         }
2947
2948         /* Make sure we receive the minimum required data to cache internally */
2949         if (mbox_sts[4] < offsetof(struct mbx_sys_info, reserved)) {
2950                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
2951                     " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
2952                 goto exit_validate_mac82;
2953
2954         }
2955
2956         /* Save M.A.C. address & serial_number */
2957         ha->port_num = sys_info->port_num;
2958         memcpy(ha->my_mac, &sys_info->mac_addr[0],
2959             min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
2960         memcpy(ha->serial_number, &sys_info->serial_number,
2961             min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
2962         memcpy(ha->model_name, &sys_info->board_id_str,
2963                min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
2964         ha->phy_port_cnt = sys_info->phys_port_cnt;
2965         ha->phy_port_num = sys_info->port_num;
2966         ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
2967
2968         DEBUG2(printk("scsi%ld: %s: "
2969             "mac %02x:%02x:%02x:%02x:%02x:%02x "
2970             "serial %s\n", ha->host_no, __func__,
2971             ha->my_mac[0], ha->my_mac[1], ha->my_mac[2],
2972             ha->my_mac[3], ha->my_mac[4], ha->my_mac[5],
2973             ha->serial_number));
2974
2975         status = QLA_SUCCESS;
2976
2977 exit_validate_mac82:
2978         dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
2979                           sys_info_dma);
2980         return status;
2981 }
2982
2983 /* Interrupt handling helpers. */
2984
2985 static int
2986 qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha)
2987 {
2988         uint32_t mbox_cmd[MBOX_REG_COUNT];
2989         uint32_t mbox_sts[MBOX_REG_COUNT];
2990
2991         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
2992
2993         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2994         memset(&mbox_sts, 0, sizeof(mbox_sts));
2995         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
2996         mbox_cmd[1] = INTR_ENABLE;
2997         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2998                 &mbox_sts[0]) != QLA_SUCCESS) {
2999                 DEBUG2(ql4_printk(KERN_INFO, ha,
3000                     "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
3001                     __func__, mbox_sts[0]));
3002                 return QLA_ERROR;
3003         }
3004         return QLA_SUCCESS;
3005 }
3006
3007 static int
3008 qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha)
3009 {
3010         uint32_t mbox_cmd[MBOX_REG_COUNT];
3011         uint32_t mbox_sts[MBOX_REG_COUNT];
3012
3013         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
3014
3015         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3016         memset(&mbox_sts, 0, sizeof(mbox_sts));
3017         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
3018         mbox_cmd[1] = INTR_DISABLE;
3019         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
3020             &mbox_sts[0]) != QLA_SUCCESS) {
3021                 DEBUG2(ql4_printk(KERN_INFO, ha,
3022                         "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
3023                         __func__, mbox_sts[0]));
3024                 return QLA_ERROR;
3025         }
3026
3027         return QLA_SUCCESS;
3028 }
3029
3030 void
3031 qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
3032 {
3033         qla4_8xxx_mbx_intr_enable(ha);
3034
3035         spin_lock_irq(&ha->hardware_lock);
3036         /* BIT 10 - reset */
3037         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
3038         spin_unlock_irq(&ha->hardware_lock);
3039         set_bit(AF_INTERRUPTS_ON, &ha->flags);
3040 }
3041
3042 void
3043 qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
3044 {
3045         if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
3046                 qla4_8xxx_mbx_intr_disable(ha);
3047
3048         spin_lock_irq(&ha->hardware_lock);
3049         /* BIT 10 - set */
3050         qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
3051         spin_unlock_irq(&ha->hardware_lock);
3052 }
3053
3054 struct ql4_init_msix_entry {
3055         uint16_t entry;
3056         uint16_t index;
3057         const char *name;
3058         irq_handler_t handler;
3059 };
3060
3061 static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = {
3062         { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT,
3063             "qla4xxx (default)",
3064             (irq_handler_t)qla4_8xxx_default_intr_handler },
3065         { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q,
3066             "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q },
3067 };
3068
3069 void
3070 qla4_8xxx_disable_msix(struct scsi_qla_host *ha)
3071 {
3072         int i;
3073         struct ql4_msix_entry *qentry;
3074
3075         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
3076                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
3077                 if (qentry->have_irq) {
3078                         free_irq(qentry->msix_vector, ha);
3079                         DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
3080                                 __func__, qla4_8xxx_msix_entries[i].name));
3081                 }
3082         }
3083         pci_disable_msix(ha->pdev);
3084         clear_bit(AF_MSIX_ENABLED, &ha->flags);
3085 }
3086
3087 int
3088 qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
3089 {
3090         int i, ret;
3091         struct msix_entry entries[QLA_MSIX_ENTRIES];
3092         struct ql4_msix_entry *qentry;
3093
3094         for (i = 0; i < QLA_MSIX_ENTRIES; i++)
3095                 entries[i].entry = qla4_8xxx_msix_entries[i].entry;
3096
3097         ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries));
3098         if (ret) {
3099                 ql4_printk(KERN_WARNING, ha,
3100                     "MSI-X: Failed to enable support -- %d/%d\n",
3101                     QLA_MSIX_ENTRIES, ret);
3102                 goto msix_out;
3103         }
3104         set_bit(AF_MSIX_ENABLED, &ha->flags);
3105
3106         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
3107                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
3108                 qentry->msix_vector = entries[i].vector;
3109                 qentry->msix_entry = entries[i].entry;
3110                 qentry->have_irq = 0;
3111                 ret = request_irq(qentry->msix_vector,
3112                     qla4_8xxx_msix_entries[i].handler, 0,
3113                     qla4_8xxx_msix_entries[i].name, ha);
3114                 if (ret) {
3115                         ql4_printk(KERN_WARNING, ha,
3116                             "MSI-X: Unable to register handler -- %x/%d.\n",
3117                             qla4_8xxx_msix_entries[i].index, ret);
3118                         qla4_8xxx_disable_msix(ha);
3119                         goto msix_out;
3120                 }
3121                 qentry->have_irq = 1;
3122                 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
3123                         __func__, qla4_8xxx_msix_entries[i].name));
3124         }
3125 msix_out:
3126         return ret;
3127 }