2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
46 #include "sata_promise.h"
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.04"
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE = 0x41, /* TBG mode */
56 PDC_FLASH_CTL = 0x44, /* Flash control register */
57 PDC_PCI_CTL = 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
62 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
64 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
65 (1<<8) | (1<<9) | (1<<10),
67 board_2037x = 0, /* FastTrak S150 TX2plus */
68 board_20319 = 1, /* FastTrak S150 TX4 */
69 board_20619 = 2, /* FastTrak TX4000 */
70 board_20771 = 3, /* FastTrak TX2300 */
71 board_2057x = 4, /* SATAII150 Tx2plus */
72 board_40518 = 5, /* SATAII150 Tx4 */
74 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
76 PDC_RESET = (1 << 11), /* HDMA reset */
78 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
79 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
84 struct pdc_port_priv {
89 struct pdc_host_priv {
93 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
94 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
95 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
96 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
97 static void pdc_eng_timeout(struct ata_port *ap);
98 static int pdc_port_start(struct ata_port *ap);
99 static void pdc_port_stop(struct ata_port *ap);
100 static void pdc_pata_phy_reset(struct ata_port *ap);
101 static void pdc_sata_phy_reset(struct ata_port *ap);
102 static void pdc_qc_prep(struct ata_queued_cmd *qc);
103 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
104 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
105 static void pdc_irq_clear(struct ata_port *ap);
106 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
107 static void pdc_host_stop(struct ata_host_set *host_set);
110 static struct scsi_host_template pdc_ata_sht = {
111 .module = THIS_MODULE,
113 .ioctl = ata_scsi_ioctl,
114 .queuecommand = ata_scsi_queuecmd,
115 .eh_timed_out = ata_scsi_timed_out,
116 .eh_strategy_handler = ata_scsi_error,
117 .can_queue = ATA_DEF_QUEUE,
118 .this_id = ATA_SHT_THIS_ID,
119 .sg_tablesize = LIBATA_MAX_PRD,
120 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
121 .emulated = ATA_SHT_EMULATED,
122 .use_clustering = ATA_SHT_USE_CLUSTERING,
123 .proc_name = DRV_NAME,
124 .dma_boundary = ATA_DMA_BOUNDARY,
125 .slave_configure = ata_scsi_slave_config,
126 .bios_param = ata_std_bios_param,
129 static const struct ata_port_operations pdc_sata_ops = {
130 .port_disable = ata_port_disable,
131 .tf_load = pdc_tf_load_mmio,
132 .tf_read = ata_tf_read,
133 .check_status = ata_check_status,
134 .exec_command = pdc_exec_command_mmio,
135 .dev_select = ata_std_dev_select,
137 .phy_reset = pdc_sata_phy_reset,
139 .qc_prep = pdc_qc_prep,
140 .qc_issue = pdc_qc_issue_prot,
141 .eng_timeout = pdc_eng_timeout,
142 .irq_handler = pdc_interrupt,
143 .irq_clear = pdc_irq_clear,
145 .scr_read = pdc_sata_scr_read,
146 .scr_write = pdc_sata_scr_write,
147 .port_start = pdc_port_start,
148 .port_stop = pdc_port_stop,
149 .host_stop = pdc_host_stop,
152 static const struct ata_port_operations pdc_pata_ops = {
153 .port_disable = ata_port_disable,
154 .tf_load = pdc_tf_load_mmio,
155 .tf_read = ata_tf_read,
156 .check_status = ata_check_status,
157 .exec_command = pdc_exec_command_mmio,
158 .dev_select = ata_std_dev_select,
160 .phy_reset = pdc_pata_phy_reset,
162 .qc_prep = pdc_qc_prep,
163 .qc_issue = pdc_qc_issue_prot,
164 .eng_timeout = pdc_eng_timeout,
165 .irq_handler = pdc_interrupt,
166 .irq_clear = pdc_irq_clear,
168 .port_start = pdc_port_start,
169 .port_stop = pdc_port_stop,
170 .host_stop = pdc_host_stop,
173 static const struct ata_port_info pdc_port_info[] = {
177 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
178 .pio_mask = 0x1f, /* pio0-4 */
179 .mwdma_mask = 0x07, /* mwdma0-2 */
180 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
181 .port_ops = &pdc_sata_ops,
187 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
188 .pio_mask = 0x1f, /* pio0-4 */
189 .mwdma_mask = 0x07, /* mwdma0-2 */
190 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
191 .port_ops = &pdc_sata_ops,
197 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
198 .pio_mask = 0x1f, /* pio0-4 */
199 .mwdma_mask = 0x07, /* mwdma0-2 */
200 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
201 .port_ops = &pdc_pata_ops,
207 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
208 .pio_mask = 0x1f, /* pio0-4 */
209 .mwdma_mask = 0x07, /* mwdma0-2 */
210 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
211 .port_ops = &pdc_sata_ops,
217 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
218 .pio_mask = 0x1f, /* pio0-4 */
219 .mwdma_mask = 0x07, /* mwdma0-2 */
220 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
221 .port_ops = &pdc_sata_ops,
227 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
228 .pio_mask = 0x1f, /* pio0-4 */
229 .mwdma_mask = 0x07, /* mwdma0-2 */
230 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
231 .port_ops = &pdc_sata_ops,
235 static const struct pci_device_id pdc_ata_pci_tbl[] = {
236 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
238 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
240 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
242 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
244 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
246 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
248 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
250 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
252 { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
255 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
257 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
259 { PCI_VENDOR_ID_PROMISE, 0x3515, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 { } /* terminate list */
277 static struct pci_driver pdc_ata_pci_driver = {
279 .id_table = pdc_ata_pci_tbl,
280 .probe = pdc_ata_init_one,
281 .remove = ata_pci_remove_one,
285 static int pdc_port_start(struct ata_port *ap)
287 struct device *dev = ap->host_set->dev;
288 struct pdc_port_priv *pp;
291 rc = ata_port_start(ap);
295 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
301 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
307 ap->private_data = pp;
319 static void pdc_port_stop(struct ata_port *ap)
321 struct device *dev = ap->host_set->dev;
322 struct pdc_port_priv *pp = ap->private_data;
324 ap->private_data = NULL;
325 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
331 static void pdc_host_stop(struct ata_host_set *host_set)
333 struct pdc_host_priv *hp = host_set->private_data;
335 ata_pci_host_stop(host_set);
341 static void pdc_reset_port(struct ata_port *ap)
343 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
347 for (i = 11; i > 0; i--) {
360 readl(mmio); /* flush */
363 static void pdc_sata_phy_reset(struct ata_port *ap)
369 static void pdc_pata_phy_reset(struct ata_port *ap)
371 /* FIXME: add cable detect. Don't assume 40-pin cable */
372 ap->cbl = ATA_CBL_PATA40;
373 ap->udma_mask &= ATA_UDMA_MASK_40C;
380 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
382 if (sc_reg > SCR_CONTROL)
384 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
388 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
391 if (sc_reg > SCR_CONTROL)
393 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
396 static void pdc_qc_prep(struct ata_queued_cmd *qc)
398 struct pdc_port_priv *pp = qc->ap->private_data;
403 switch (qc->tf.protocol) {
408 case ATA_PROT_NODATA:
409 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
410 qc->dev->devno, pp->pkt);
412 if (qc->tf.flags & ATA_TFLAG_LBA48)
413 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
415 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
417 pdc_pkt_footer(&qc->tf, pp->pkt, i);
425 static void pdc_eng_timeout(struct ata_port *ap)
427 struct ata_host_set *host_set = ap->host_set;
429 struct ata_queued_cmd *qc;
434 spin_lock_irqsave(&host_set->lock, flags);
436 qc = ata_qc_from_tag(ap, ap->active_tag);
438 switch (qc->tf.protocol) {
440 case ATA_PROT_NODATA:
441 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
442 drv_stat = ata_wait_idle(ap);
443 qc->err_mask |= __ac_err_mask(drv_stat);
447 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
449 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
450 ap->id, qc->tf.command, drv_stat);
452 qc->err_mask |= ac_err_mask(drv_stat);
456 spin_unlock_irqrestore(&host_set->lock, flags);
457 ata_eh_qc_complete(qc);
461 static inline unsigned int pdc_host_intr( struct ata_port *ap,
462 struct ata_queued_cmd *qc)
464 unsigned int handled = 0;
466 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
469 if (tmp & PDC_ERR_MASK) {
470 qc->err_mask |= AC_ERR_DEV;
474 switch (qc->tf.protocol) {
476 case ATA_PROT_NODATA:
477 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
483 ap->stats.idle_irq++;
490 static void pdc_irq_clear(struct ata_port *ap)
492 struct ata_host_set *host_set = ap->host_set;
493 void __iomem *mmio = host_set->mmio_base;
495 readl(mmio + PDC_INT_SEQMASK);
498 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
500 struct ata_host_set *host_set = dev_instance;
504 unsigned int handled = 0;
505 void __iomem *mmio_base;
509 if (!host_set || !host_set->mmio_base) {
510 VPRINTK("QUICK EXIT\n");
514 mmio_base = host_set->mmio_base;
516 /* reading should also clear interrupts */
517 mask = readl(mmio_base + PDC_INT_SEQMASK);
519 if (mask == 0xffffffff) {
520 VPRINTK("QUICK EXIT 2\n");
524 spin_lock(&host_set->lock);
526 mask &= 0xffff; /* only 16 tags possible */
528 VPRINTK("QUICK EXIT 3\n");
532 writel(mask, mmio_base + PDC_INT_SEQMASK);
534 for (i = 0; i < host_set->n_ports; i++) {
535 VPRINTK("port %u\n", i);
536 ap = host_set->ports[i];
537 tmp = mask & (1 << (i + 1));
539 !(ap->flags & ATA_FLAG_PORT_DISABLED)) {
540 struct ata_queued_cmd *qc;
542 qc = ata_qc_from_tag(ap, ap->active_tag);
543 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
544 handled += pdc_host_intr(ap, qc);
551 spin_unlock(&host_set->lock);
552 return IRQ_RETVAL(handled);
555 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
557 struct ata_port *ap = qc->ap;
558 struct pdc_port_priv *pp = ap->private_data;
559 unsigned int port_no = ap->port_no;
560 u8 seq = (u8) (port_no + 1);
562 VPRINTK("ENTER, ap %p\n", ap);
564 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
565 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
568 wmb(); /* flush PRD, pkt writes */
569 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
570 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
573 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
575 switch (qc->tf.protocol) {
577 case ATA_PROT_NODATA:
578 pdc_packet_start(qc);
581 case ATA_PROT_ATAPI_DMA:
589 return ata_qc_issue_prot(qc);
592 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
594 WARN_ON (tf->protocol == ATA_PROT_DMA ||
595 tf->protocol == ATA_PROT_NODATA);
600 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
602 WARN_ON (tf->protocol == ATA_PROT_DMA ||
603 tf->protocol == ATA_PROT_NODATA);
604 ata_exec_command(ap, tf);
608 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
610 port->cmd_addr = base;
611 port->data_addr = base;
613 port->error_addr = base + 0x4;
614 port->nsect_addr = base + 0x8;
615 port->lbal_addr = base + 0xc;
616 port->lbam_addr = base + 0x10;
617 port->lbah_addr = base + 0x14;
618 port->device_addr = base + 0x18;
620 port->status_addr = base + 0x1c;
621 port->altstatus_addr =
622 port->ctl_addr = base + 0x38;
626 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
628 void __iomem *mmio = pe->mmio_base;
629 struct pdc_host_priv *hp = pe->private_data;
630 int hotplug_offset = hp->hotplug_offset;
634 * Except for the hotplug stuff, this is voodoo from the
635 * Promise driver. Label this entire section
636 * "TODO: figure out why we do this"
639 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
640 tmp = readl(mmio + PDC_FLASH_CTL);
641 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
642 writel(tmp, mmio + PDC_FLASH_CTL);
644 /* clear plug/unplug flags for all ports */
645 tmp = readl(mmio + hotplug_offset);
646 writel(tmp | 0xff, mmio + hotplug_offset);
648 /* mask plug/unplug ints */
649 tmp = readl(mmio + hotplug_offset);
650 writel(tmp | 0xff0000, mmio + hotplug_offset);
652 /* reduce TBG clock to 133 Mhz. */
653 tmp = readl(mmio + PDC_TBG_MODE);
654 tmp &= ~0x30000; /* clear bit 17, 16*/
655 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
656 writel(tmp, mmio + PDC_TBG_MODE);
658 readl(mmio + PDC_TBG_MODE); /* flush */
661 /* adjust slew rate control register. */
662 tmp = readl(mmio + PDC_SLEW_CTL);
663 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
664 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
665 writel(tmp, mmio + PDC_SLEW_CTL);
668 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
670 static int printed_version;
671 struct ata_probe_ent *probe_ent = NULL;
672 struct pdc_host_priv *hp;
674 void __iomem *mmio_base;
675 unsigned int board_idx = (unsigned int) ent->driver_data;
676 int pci_dev_busy = 0;
679 if (!printed_version++)
680 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
683 * If this driver happens to only be useful on Apple's K2, then
684 * we should check that here as it has a normal Serverworks ID
686 rc = pci_enable_device(pdev);
690 rc = pci_request_regions(pdev, DRV_NAME);
696 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
698 goto err_out_regions;
699 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
701 goto err_out_regions;
703 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
704 if (probe_ent == NULL) {
706 goto err_out_regions;
709 probe_ent->dev = pci_dev_to_dev(pdev);
710 INIT_LIST_HEAD(&probe_ent->node);
712 mmio_base = pci_iomap(pdev, 3, 0);
713 if (mmio_base == NULL) {
715 goto err_out_free_ent;
717 base = (unsigned long) mmio_base;
719 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
722 goto err_out_free_ent;
725 /* Set default hotplug offset */
726 hp->hotplug_offset = PDC_SATA_PLUG_CSR;
727 probe_ent->private_data = hp;
729 probe_ent->sht = pdc_port_info[board_idx].sht;
730 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
731 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
732 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
733 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
734 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
736 probe_ent->irq = pdev->irq;
737 probe_ent->irq_flags = SA_SHIRQ;
738 probe_ent->mmio_base = mmio_base;
740 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
741 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
743 probe_ent->port[0].scr_addr = base + 0x400;
744 probe_ent->port[1].scr_addr = base + 0x500;
746 /* notice 4-port boards */
749 /* Override hotplug offset for SATAII150 */
750 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
753 probe_ent->n_ports = 4;
755 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
756 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
758 probe_ent->port[2].scr_addr = base + 0x600;
759 probe_ent->port[3].scr_addr = base + 0x700;
762 /* Override hotplug offset for SATAII150 */
763 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
766 probe_ent->n_ports = 2;
769 probe_ent->n_ports = 2;
772 probe_ent->n_ports = 4;
774 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
775 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
777 probe_ent->port[2].scr_addr = base + 0x600;
778 probe_ent->port[3].scr_addr = base + 0x700;
785 pci_set_master(pdev);
787 /* initialize adapter */
788 pdc_host_init(board_idx, probe_ent);
790 /* FIXME: Need any other frees than hp? */
791 if (!ata_device_add(probe_ent))
801 pci_release_regions(pdev);
804 pci_disable_device(pdev);
809 static int __init pdc_ata_init(void)
811 return pci_module_init(&pdc_ata_pci_driver);
815 static void __exit pdc_ata_exit(void)
817 pci_unregister_driver(&pdc_ata_pci_driver);
821 MODULE_AUTHOR("Jeff Garzik");
822 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
823 MODULE_LICENSE("GPL");
824 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
825 MODULE_VERSION(DRV_VERSION);
827 module_init(pdc_ata_init);
828 module_exit(pdc_ata_exit);