2 * sata_sx4.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware documentation available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
46 #include "sata_promise.h"
48 #define DRV_NAME "sata_sx4"
49 #define DRV_VERSION "0.8"
53 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
55 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
56 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
57 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
58 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
60 PDC_20621_SEQCTL = 0x400,
61 PDC_20621_SEQMASK = 0x480,
62 PDC_20621_GENERAL_CTL = 0x484,
63 PDC_20621_PAGE_SIZE = (32 * 1024),
65 /* chosen, not constant, values; we design our own DIMM mem map */
66 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
67 PDC_20621_DIMM_BASE = 0x00200000,
68 PDC_20621_DIMM_DATA = (64 * 1024),
69 PDC_DIMM_DATA_STEP = (256 * 1024),
70 PDC_DIMM_WINDOW_STEP = (8 * 1024),
71 PDC_DIMM_HOST_PRD = (6 * 1024),
72 PDC_DIMM_HOST_PKT = (128 * 0),
73 PDC_DIMM_HPKT_PRD = (128 * 1),
74 PDC_DIMM_ATA_PKT = (128 * 2),
75 PDC_DIMM_APKT_PRD = (128 * 3),
76 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
77 PDC_PAGE_WINDOW = 0x40,
78 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
79 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
80 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
82 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
84 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
87 board_20621 = 0, /* FastTrak S150 SX4 */
89 PDC_RESET = (1 << 11), /* HDMA reset */
92 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
94 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
95 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
96 PDC_MAX_DIMM_MODULE = 0x02,
97 PDC_I2C_CONTROL_OFFSET = 0x48,
98 PDC_I2C_ADDR_DATA_OFFSET = 0x4C,
99 PDC_DIMM0_CONTROL_OFFSET = 0x80,
100 PDC_DIMM1_CONTROL_OFFSET = 0x84,
101 PDC_SDRAM_CONTROL_OFFSET = 0x88,
102 PDC_I2C_WRITE = 0x00000000,
103 PDC_I2C_READ = 0x00000040,
104 PDC_I2C_START = 0x00000080,
105 PDC_I2C_MASK_INT = 0x00000020,
106 PDC_I2C_COMPLETE = 0x00010000,
107 PDC_I2C_NO_ACK = 0x00100000,
108 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
109 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
110 PDC_DIMM_SPD_ROW_NUM = 3,
111 PDC_DIMM_SPD_COLUMN_NUM = 4,
112 PDC_DIMM_SPD_MODULE_ROW = 5,
113 PDC_DIMM_SPD_TYPE = 11,
114 PDC_DIMM_SPD_FRESH_RATE = 12,
115 PDC_DIMM_SPD_BANK_NUM = 17,
116 PDC_DIMM_SPD_CAS_LATENCY = 18,
117 PDC_DIMM_SPD_ATTRIBUTE = 21,
118 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
119 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
120 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
121 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
122 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
123 PDC_CTL_STATUS = 0x08,
124 PDC_DIMM_WINDOW_CTLR = 0x0C,
125 PDC_TIME_CONTROL = 0x3C,
126 PDC_TIME_PERIOD = 0x40,
127 PDC_TIME_COUNTER = 0x44,
128 PDC_GENERAL_CTLR = 0x484,
129 PCI_PLL_INIT = 0x8A531824,
130 PCI_X_TCOUNT = 0xEE1E5CFF
134 struct pdc_port_priv {
135 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
140 struct pdc_host_priv {
141 void __iomem *dimm_mmio;
143 unsigned int doing_hdma;
144 unsigned int hdma_prod;
145 unsigned int hdma_cons;
147 struct ata_queued_cmd *qc;
149 unsigned long pkt_ofs;
154 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
155 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
156 static void pdc_eng_timeout(struct ata_port *ap);
157 static void pdc_20621_phy_reset (struct ata_port *ap);
158 static int pdc_port_start(struct ata_port *ap);
159 static void pdc_port_stop(struct ata_port *ap);
160 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
161 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
162 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
163 static void pdc20621_host_stop(struct ata_host_set *host_set);
164 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
165 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
166 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
167 u32 device, u32 subaddr, u32 *pdata);
168 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
169 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
170 #ifdef ATA_VERBOSE_DEBUG
171 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
172 void *psource, u32 offset, u32 size);
174 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
175 void *psource, u32 offset, u32 size);
176 static void pdc20621_irq_clear(struct ata_port *ap);
177 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
180 static struct scsi_host_template pdc_sata_sht = {
181 .module = THIS_MODULE,
183 .ioctl = ata_scsi_ioctl,
184 .queuecommand = ata_scsi_queuecmd,
185 .eh_timed_out = ata_scsi_timed_out,
186 .eh_strategy_handler = ata_scsi_error,
187 .can_queue = ATA_DEF_QUEUE,
188 .this_id = ATA_SHT_THIS_ID,
189 .sg_tablesize = LIBATA_MAX_PRD,
190 .max_sectors = ATA_MAX_SECTORS,
191 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
192 .emulated = ATA_SHT_EMULATED,
193 .use_clustering = ATA_SHT_USE_CLUSTERING,
194 .proc_name = DRV_NAME,
195 .dma_boundary = ATA_DMA_BOUNDARY,
196 .slave_configure = ata_scsi_slave_config,
197 .bios_param = ata_std_bios_param,
200 static const struct ata_port_operations pdc_20621_ops = {
201 .port_disable = ata_port_disable,
202 .tf_load = pdc_tf_load_mmio,
203 .tf_read = ata_tf_read,
204 .check_status = ata_check_status,
205 .exec_command = pdc_exec_command_mmio,
206 .dev_select = ata_std_dev_select,
207 .phy_reset = pdc_20621_phy_reset,
208 .qc_prep = pdc20621_qc_prep,
209 .qc_issue = pdc20621_qc_issue_prot,
210 .eng_timeout = pdc_eng_timeout,
211 .irq_handler = pdc20621_interrupt,
212 .irq_clear = pdc20621_irq_clear,
213 .port_start = pdc_port_start,
214 .port_stop = pdc_port_stop,
215 .host_stop = pdc20621_host_stop,
218 static const struct ata_port_info pdc_port_info[] = {
221 .sht = &pdc_sata_sht,
222 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
223 ATA_FLAG_SRST | ATA_FLAG_MMIO |
225 .pio_mask = 0x1f, /* pio0-4 */
226 .mwdma_mask = 0x07, /* mwdma0-2 */
227 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
228 .port_ops = &pdc_20621_ops,
233 static const struct pci_device_id pdc_sata_pci_tbl[] = {
234 { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
236 { } /* terminate list */
240 static struct pci_driver pdc_sata_pci_driver = {
242 .id_table = pdc_sata_pci_tbl,
243 .probe = pdc_sata_init_one,
244 .remove = ata_pci_remove_one,
248 static void pdc20621_host_stop(struct ata_host_set *host_set)
250 struct pci_dev *pdev = to_pci_dev(host_set->dev);
251 struct pdc_host_priv *hpriv = host_set->private_data;
252 void __iomem *dimm_mmio = hpriv->dimm_mmio;
254 pci_iounmap(pdev, dimm_mmio);
257 pci_iounmap(pdev, host_set->mmio_base);
260 static int pdc_port_start(struct ata_port *ap)
262 struct device *dev = ap->host_set->dev;
263 struct pdc_port_priv *pp;
266 rc = ata_port_start(ap);
270 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
275 memset(pp, 0, sizeof(*pp));
277 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
283 ap->private_data = pp;
295 static void pdc_port_stop(struct ata_port *ap)
297 struct device *dev = ap->host_set->dev;
298 struct pdc_port_priv *pp = ap->private_data;
300 ap->private_data = NULL;
301 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
307 static void pdc_20621_phy_reset (struct ata_port *ap)
310 ap->cbl = ATA_CBL_SATA;
315 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
317 unsigned int total_len)
320 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
321 u32 *buf32 = (u32 *) buf;
323 /* output ATA packet S/G table */
324 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
325 (PDC_DIMM_DATA_STEP * portno);
326 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
327 buf32[dw] = cpu_to_le32(addr);
328 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
330 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
331 PDC_20621_DIMM_BASE +
332 (PDC_DIMM_WINDOW_STEP * portno) +
334 buf32[dw], buf32[dw + 1]);
337 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
339 unsigned int total_len)
342 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
343 u32 *buf32 = (u32 *) buf;
345 /* output Host DMA packet S/G table */
346 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
347 (PDC_DIMM_DATA_STEP * portno);
349 buf32[dw] = cpu_to_le32(addr);
350 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
352 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
353 PDC_20621_DIMM_BASE +
354 (PDC_DIMM_WINDOW_STEP * portno) +
356 buf32[dw], buf32[dw + 1]);
359 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
360 unsigned int devno, u8 *buf,
364 u32 *buf32 = (u32 *) buf;
367 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
368 (PDC_DIMM_WINDOW_STEP * portno) +
370 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
372 i = PDC_DIMM_ATA_PKT;
377 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
378 buf[i++] = PDC_PKT_READ;
379 else if (tf->protocol == ATA_PROT_NODATA)
380 buf[i++] = PDC_PKT_NODATA;
383 buf[i++] = 0; /* reserved */
384 buf[i++] = portno + 1; /* seq. id */
385 buf[i++] = 0xff; /* delay seq. id */
387 /* dimm dma S/G, and next-pkt */
389 if (tf->protocol == ATA_PROT_NODATA)
392 buf32[dw] = cpu_to_le32(dimm_sg);
397 dev_reg = ATA_DEVICE_OBS;
399 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
402 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
405 /* device control register */
406 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
412 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
416 u32 tmp, *buf32 = (u32 *) buf;
418 unsigned int host_sg = PDC_20621_DIMM_BASE +
419 (PDC_DIMM_WINDOW_STEP * portno) +
421 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
422 (PDC_DIMM_WINDOW_STEP * portno) +
424 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
425 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
427 dw = PDC_DIMM_HOST_PKT >> 2;
430 * Set up Host DMA packet
432 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
436 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
437 tmp |= (0xff << 24); /* delay seq. id */
438 buf32[dw + 0] = cpu_to_le32(tmp);
439 buf32[dw + 1] = cpu_to_le32(host_sg);
440 buf32[dw + 2] = cpu_to_le32(dimm_sg);
443 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
444 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
452 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
454 struct scatterlist *sg;
455 struct ata_port *ap = qc->ap;
456 struct pdc_port_priv *pp = ap->private_data;
457 void __iomem *mmio = ap->host_set->mmio_base;
458 struct pdc_host_priv *hpriv = ap->host_set->private_data;
459 void __iomem *dimm_mmio = hpriv->dimm_mmio;
460 unsigned int portno = ap->port_no;
461 unsigned int i, idx, total_len = 0, sgt_len;
462 u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
464 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
466 VPRINTK("ata%u: ENTER\n", ap->id);
468 /* hard-code chip #0 */
469 mmio += PDC_CHIP0_OFS;
475 ata_for_each_sg(sg, qc) {
476 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
477 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
478 total_len += sg_dma_len(sg);
480 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
484 * Build ATA, host DMA packets
486 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
487 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
489 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
490 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
492 if (qc->tf.flags & ATA_TFLAG_LBA48)
493 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
495 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
497 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
499 /* copy three S/G tables and two packets to DIMM MMIO window */
500 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
501 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
502 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
504 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
506 /* force host FIFO dump */
507 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
509 readl(dimm_mmio); /* MMIO PCI posting flush */
511 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
514 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
516 struct ata_port *ap = qc->ap;
517 struct pdc_port_priv *pp = ap->private_data;
518 void __iomem *mmio = ap->host_set->mmio_base;
519 struct pdc_host_priv *hpriv = ap->host_set->private_data;
520 void __iomem *dimm_mmio = hpriv->dimm_mmio;
521 unsigned int portno = ap->port_no;
524 VPRINTK("ata%u: ENTER\n", ap->id);
526 /* hard-code chip #0 */
527 mmio += PDC_CHIP0_OFS;
529 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
531 if (qc->tf.flags & ATA_TFLAG_LBA48)
532 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
534 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
536 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
538 /* copy three S/G tables and two packets to DIMM MMIO window */
539 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
540 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
542 /* force host FIFO dump */
543 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
545 readl(dimm_mmio); /* MMIO PCI posting flush */
547 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
550 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
552 switch (qc->tf.protocol) {
554 pdc20621_dma_prep(qc);
556 case ATA_PROT_NODATA:
557 pdc20621_nodata_prep(qc);
564 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
568 struct ata_port *ap = qc->ap;
569 struct ata_host_set *host_set = ap->host_set;
570 void __iomem *mmio = host_set->mmio_base;
572 /* hard-code chip #0 */
573 mmio += PDC_CHIP0_OFS;
575 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
576 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
578 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
579 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
582 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
586 struct ata_port *ap = qc->ap;
587 struct pdc_host_priv *pp = ap->host_set->private_data;
588 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
590 if (!pp->doing_hdma) {
591 __pdc20621_push_hdma(qc, seq, pkt_ofs);
596 pp->hdma[idx].qc = qc;
597 pp->hdma[idx].seq = seq;
598 pp->hdma[idx].pkt_ofs = pkt_ofs;
602 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
604 struct ata_port *ap = qc->ap;
605 struct pdc_host_priv *pp = ap->host_set->private_data;
606 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
608 /* if nothing on queue, we're done */
609 if (pp->hdma_prod == pp->hdma_cons) {
614 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
615 pp->hdma[idx].pkt_ofs);
619 #ifdef ATA_VERBOSE_DEBUG
620 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
622 struct ata_port *ap = qc->ap;
623 unsigned int port_no = ap->port_no;
624 struct pdc_host_priv *hpriv = ap->host_set->private_data;
625 void *dimm_mmio = hpriv->dimm_mmio;
627 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
628 dimm_mmio += PDC_DIMM_HOST_PKT;
630 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
631 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
632 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
633 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
636 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
637 #endif /* ATA_VERBOSE_DEBUG */
639 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
641 struct ata_port *ap = qc->ap;
642 struct ata_host_set *host_set = ap->host_set;
643 unsigned int port_no = ap->port_no;
644 void __iomem *mmio = host_set->mmio_base;
645 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
646 u8 seq = (u8) (port_no + 1);
647 unsigned int port_ofs;
649 /* hard-code chip #0 */
650 mmio += PDC_CHIP0_OFS;
652 VPRINTK("ata%u: ENTER\n", ap->id);
654 wmb(); /* flush PRD, pkt writes */
656 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
658 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
659 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
662 pdc20621_dump_hdma(qc);
663 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
664 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
665 port_ofs + PDC_DIMM_HOST_PKT,
666 port_ofs + PDC_DIMM_HOST_PKT,
669 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
670 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
672 writel(port_ofs + PDC_DIMM_ATA_PKT,
673 (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
674 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
675 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
676 port_ofs + PDC_DIMM_ATA_PKT,
677 port_ofs + PDC_DIMM_ATA_PKT,
682 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
684 switch (qc->tf.protocol) {
686 case ATA_PROT_NODATA:
687 pdc20621_packet_start(qc);
690 case ATA_PROT_ATAPI_DMA:
698 return ata_qc_issue_prot(qc);
701 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
702 struct ata_queued_cmd *qc,
703 unsigned int doing_hdma,
706 unsigned int port_no = ap->port_no;
707 unsigned int port_ofs =
708 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
710 unsigned int handled = 0;
714 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
715 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
717 /* step two - DMA from DIMM to host */
719 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
720 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
721 /* get drive status; clear intr; complete txn */
722 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
724 pdc20621_pop_hdma(qc);
727 /* step one - exec ATA command */
729 u8 seq = (u8) (port_no + 1 + 4);
730 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
731 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
733 /* submit hdma pkt */
734 pdc20621_dump_hdma(qc);
735 pdc20621_push_hdma(qc, seq,
736 port_ofs + PDC_DIMM_HOST_PKT);
740 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
742 /* step one - DMA from host to DIMM */
744 u8 seq = (u8) (port_no + 1);
745 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
746 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
749 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
750 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
751 writel(port_ofs + PDC_DIMM_ATA_PKT,
752 (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
753 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
756 /* step two - execute ATA command */
758 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
759 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
760 /* get drive status; clear intr; complete txn */
761 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
763 pdc20621_pop_hdma(qc);
767 /* command completion, but no data xfer */
768 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
770 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
771 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
772 qc->err_mask |= ac_err_mask(status);
777 ap->stats.idle_irq++;
783 static void pdc20621_irq_clear(struct ata_port *ap)
785 struct ata_host_set *host_set = ap->host_set;
786 void __iomem *mmio = host_set->mmio_base;
788 mmio += PDC_CHIP0_OFS;
790 readl(mmio + PDC_20621_SEQMASK);
793 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
795 struct ata_host_set *host_set = dev_instance;
798 unsigned int i, tmp, port_no;
799 unsigned int handled = 0;
800 void __iomem *mmio_base;
804 if (!host_set || !host_set->mmio_base) {
805 VPRINTK("QUICK EXIT\n");
809 mmio_base = host_set->mmio_base;
811 /* reading should also clear interrupts */
812 mmio_base += PDC_CHIP0_OFS;
813 mask = readl(mmio_base + PDC_20621_SEQMASK);
814 VPRINTK("mask == 0x%x\n", mask);
816 if (mask == 0xffffffff) {
817 VPRINTK("QUICK EXIT 2\n");
820 mask &= 0xffff; /* only 16 tags possible */
822 VPRINTK("QUICK EXIT 3\n");
826 spin_lock(&host_set->lock);
828 for (i = 1; i < 9; i++) {
832 if (port_no >= host_set->n_ports)
835 ap = host_set->ports[port_no];
836 tmp = mask & (1 << i);
837 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
839 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
840 struct ata_queued_cmd *qc;
842 qc = ata_qc_from_tag(ap, ap->active_tag);
843 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
844 handled += pdc20621_host_intr(ap, qc, (i > 4),
849 spin_unlock(&host_set->lock);
851 VPRINTK("mask == 0x%x\n", mask);
855 return IRQ_RETVAL(handled);
858 static void pdc_eng_timeout(struct ata_port *ap)
861 struct ata_host_set *host_set = ap->host_set;
862 struct ata_queued_cmd *qc;
867 spin_lock_irqsave(&host_set->lock, flags);
869 qc = ata_qc_from_tag(ap, ap->active_tag);
871 switch (qc->tf.protocol) {
873 case ATA_PROT_NODATA:
874 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
875 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
879 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
881 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
882 ap->id, qc->tf.command, drv_stat);
884 qc->err_mask |= ac_err_mask(drv_stat);
888 spin_unlock_irqrestore(&host_set->lock, flags);
889 ata_eh_qc_complete(qc);
893 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
895 WARN_ON (tf->protocol == ATA_PROT_DMA ||
896 tf->protocol == ATA_PROT_NODATA);
901 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
903 WARN_ON (tf->protocol == ATA_PROT_DMA ||
904 tf->protocol == ATA_PROT_NODATA);
905 ata_exec_command(ap, tf);
909 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
911 port->cmd_addr = base;
912 port->data_addr = base;
914 port->error_addr = base + 0x4;
915 port->nsect_addr = base + 0x8;
916 port->lbal_addr = base + 0xc;
917 port->lbam_addr = base + 0x10;
918 port->lbah_addr = base + 0x14;
919 port->device_addr = base + 0x18;
921 port->status_addr = base + 0x1c;
922 port->altstatus_addr =
923 port->ctl_addr = base + 0x38;
927 #ifdef ATA_VERBOSE_DEBUG
928 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
929 u32 offset, u32 size)
935 void __iomem *mmio = pe->mmio_base;
936 struct pdc_host_priv *hpriv = pe->private_data;
937 void __iomem *dimm_mmio = hpriv->dimm_mmio;
939 /* hard-code chip #0 */
940 mmio += PDC_CHIP0_OFS;
943 window_size = 0x2000 * 4; /* 32K byte uchar size */
944 idx = (u16) (offset / window_size);
946 writel(0x01, mmio + PDC_GENERAL_CTLR);
947 readl(mmio + PDC_GENERAL_CTLR);
948 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
949 readl(mmio + PDC_DIMM_WINDOW_CTLR);
951 offset -= (idx * window_size);
953 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
954 (long) (window_size - offset);
955 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
960 for (; (long) size >= (long) window_size ;) {
961 writel(0x01, mmio + PDC_GENERAL_CTLR);
962 readl(mmio + PDC_GENERAL_CTLR);
963 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
964 readl(mmio + PDC_DIMM_WINDOW_CTLR);
965 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
967 psource += window_size;
973 writel(0x01, mmio + PDC_GENERAL_CTLR);
974 readl(mmio + PDC_GENERAL_CTLR);
975 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
976 readl(mmio + PDC_DIMM_WINDOW_CTLR);
977 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
984 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
985 u32 offset, u32 size)
991 void __iomem *mmio = pe->mmio_base;
992 struct pdc_host_priv *hpriv = pe->private_data;
993 void __iomem *dimm_mmio = hpriv->dimm_mmio;
995 /* hard-code chip #0 */
996 mmio += PDC_CHIP0_OFS;
999 window_size = 0x2000 * 4; /* 32K byte uchar size */
1000 idx = (u16) (offset / window_size);
1002 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1003 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1004 offset -= (idx * window_size);
1006 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1007 (long) (window_size - offset);
1008 memcpy_toio(dimm_mmio + offset / 4, psource, dist);
1009 writel(0x01, mmio + PDC_GENERAL_CTLR);
1010 readl(mmio + PDC_GENERAL_CTLR);
1014 for (; (long) size >= (long) window_size ;) {
1015 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1016 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1017 memcpy_toio(dimm_mmio, psource, window_size / 4);
1018 writel(0x01, mmio + PDC_GENERAL_CTLR);
1019 readl(mmio + PDC_GENERAL_CTLR);
1020 psource += window_size;
1021 size -= window_size;
1026 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1027 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1028 memcpy_toio(dimm_mmio, psource, size / 4);
1029 writel(0x01, mmio + PDC_GENERAL_CTLR);
1030 readl(mmio + PDC_GENERAL_CTLR);
1035 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
1036 u32 subaddr, u32 *pdata)
1038 void __iomem *mmio = pe->mmio_base;
1043 /* hard-code chip #0 */
1044 mmio += PDC_CHIP0_OFS;
1046 i2creg |= device << 24;
1047 i2creg |= subaddr << 16;
1049 /* Set the device and subaddress */
1050 writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1051 readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1053 /* Write Control to perform read operation, mask int */
1054 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1055 mmio + PDC_I2C_CONTROL_OFFSET);
1057 for (count = 0; count <= 1000; count ++) {
1058 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1059 if (status & PDC_I2C_COMPLETE) {
1060 status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1062 } else if (count == 1000)
1066 *pdata = (status >> 8) & 0x000000ff;
1071 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1074 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1075 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1081 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1091 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1097 void __iomem *mmio = pe->mmio_base;
1098 static const struct {
1101 } pdc_i2c_read_data [] = {
1102 { PDC_DIMM_SPD_TYPE, 11 },
1103 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1104 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1105 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1106 { PDC_DIMM_SPD_ROW_NUM, 3 },
1107 { PDC_DIMM_SPD_BANK_NUM, 17 },
1108 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1109 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1110 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1111 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1112 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1113 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1116 /* hard-code chip #0 */
1117 mmio += PDC_CHIP0_OFS;
1119 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1120 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1121 pdc_i2c_read_data[i].reg,
1122 &spd0[pdc_i2c_read_data[i].ofs]);
1124 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1125 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1126 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1127 data |= (((((spd0[29] > spd0[28])
1128 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1129 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1131 if (spd0[18] & 0x08)
1132 data |= ((0x03) << 14);
1133 else if (spd0[18] & 0x04)
1134 data |= ((0x02) << 14);
1135 else if (spd0[18] & 0x01)
1136 data |= ((0x01) << 14);
1141 Calculate the size of bDIMMSize (power of 2) and
1142 merge the DIMM size by program start/end address.
1145 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1146 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1147 data |= (((size / 16) - 1) << 16);
1150 writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1151 readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1156 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1160 void __iomem *mmio = pe->mmio_base;
1162 /* hard-code chip #0 */
1163 mmio += PDC_CHIP0_OFS;
1166 Set To Default : DIMM Module Global Control Register (0x022259F1)
1167 DIMM Arbitration Disable (bit 20)
1168 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1169 Refresh Enable (bit 17)
1173 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1174 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1176 /* Turn on for ECC */
1177 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1178 PDC_DIMM_SPD_TYPE, &spd0);
1180 data |= (0x01 << 16);
1181 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1182 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1183 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1186 /* DIMM Initialization Select/Enable (bit 18/19) */
1189 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1192 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
1193 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1194 if (!(data & (1<<19))) {
1204 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1206 int speed, size, length;
1207 u32 addr,spd0,pci_status;
1214 void __iomem *mmio = pe->mmio_base;
1216 /* hard-code chip #0 */
1217 mmio += PDC_CHIP0_OFS;
1219 /* Initialize PLL based upon PCI Bus Frequency */
1221 /* Initialize Time Period Register */
1222 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1223 time_period = readl(mmio + PDC_TIME_PERIOD);
1224 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1227 writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1228 readl(mmio + PDC_TIME_CONTROL);
1230 /* Wait 3 seconds */
1234 When timer is enabled, counter is decreased every internal
1238 tcount = readl(mmio + PDC_TIME_COUNTER);
1239 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1242 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1243 register should be >= (0xffffffff - 3x10^8).
1245 if(tcount >= PCI_X_TCOUNT) {
1246 ticks = (time_period - tcount);
1247 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1249 clock = (ticks / 300000);
1250 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1252 clock = (clock * 33);
1253 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1255 /* PLL F Param (bit 22:16) */
1256 fparam = (1400000 / clock) - 2;
1257 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1259 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1260 pci_status = (0x8a001824 | (fparam << 16));
1262 pci_status = PCI_PLL_INIT;
1264 /* Initialize PLL. */
1265 VPRINTK("pci_status: 0x%x\n", pci_status);
1266 writel(pci_status, mmio + PDC_CTL_STATUS);
1267 readl(mmio + PDC_CTL_STATUS);
1270 Read SPD of DIMM by I2C interface,
1271 and program the DIMM Module Controller.
1273 if (!(speed = pdc20621_detect_dimm(pe))) {
1274 printk(KERN_ERR "Detect Local DIMM Fail\n");
1275 return 1; /* DIMM error */
1277 VPRINTK("Local DIMM Speed = %d\n", speed);
1279 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1280 size = pdc20621_prog_dimm0(pe);
1281 VPRINTK("Local DIMM Size = %dMB\n",size);
1283 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1284 if (pdc20621_prog_dimm_global(pe)) {
1285 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1289 #ifdef ATA_VERBOSE_DEBUG
1291 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1292 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1294 '9','8','0','3','1','6','1','2',0,0};
1295 u8 test_parttern2[40] = {0};
1297 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1298 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1300 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1301 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1302 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1303 test_parttern2[1], &(test_parttern2[2]));
1304 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1306 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1307 test_parttern2[1], &(test_parttern2[2]));
1309 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1310 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1311 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1312 test_parttern2[1], &(test_parttern2[2]));
1316 /* ECC initiliazation. */
1318 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1319 PDC_DIMM_SPD_TYPE, &spd0);
1321 VPRINTK("Start ECC initialization\n");
1323 length = size * 1024 * 1024;
1324 while (addr < length) {
1325 pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1327 addr += sizeof(u32);
1329 VPRINTK("Finish ECC initialization\n");
1335 static void pdc_20621_init(struct ata_probe_ent *pe)
1338 void __iomem *mmio = pe->mmio_base;
1340 /* hard-code chip #0 */
1341 mmio += PDC_CHIP0_OFS;
1344 * Select page 0x40 for our 32k DIMM window
1346 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1347 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1348 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1353 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1355 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1356 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1360 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1362 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1363 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1366 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1368 static int printed_version;
1369 struct ata_probe_ent *probe_ent = NULL;
1371 void __iomem *mmio_base;
1372 void __iomem *dimm_mmio = NULL;
1373 struct pdc_host_priv *hpriv = NULL;
1374 unsigned int board_idx = (unsigned int) ent->driver_data;
1375 int pci_dev_busy = 0;
1378 if (!printed_version++)
1379 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1382 * If this driver happens to only be useful on Apple's K2, then
1383 * we should check that here as it has a normal Serverworks ID
1385 rc = pci_enable_device(pdev);
1389 rc = pci_request_regions(pdev, DRV_NAME);
1395 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1397 goto err_out_regions;
1398 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1400 goto err_out_regions;
1402 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1403 if (probe_ent == NULL) {
1405 goto err_out_regions;
1408 memset(probe_ent, 0, sizeof(*probe_ent));
1409 probe_ent->dev = pci_dev_to_dev(pdev);
1410 INIT_LIST_HEAD(&probe_ent->node);
1412 mmio_base = pci_iomap(pdev, 3, 0);
1413 if (mmio_base == NULL) {
1415 goto err_out_free_ent;
1417 base = (unsigned long) mmio_base;
1419 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1422 goto err_out_iounmap;
1424 memset(hpriv, 0, sizeof(*hpriv));
1426 dimm_mmio = pci_iomap(pdev, 4, 0);
1430 goto err_out_iounmap;
1433 hpriv->dimm_mmio = dimm_mmio;
1435 probe_ent->sht = pdc_port_info[board_idx].sht;
1436 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
1437 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
1438 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
1439 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
1440 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
1442 probe_ent->irq = pdev->irq;
1443 probe_ent->irq_flags = SA_SHIRQ;
1444 probe_ent->mmio_base = mmio_base;
1446 probe_ent->private_data = hpriv;
1447 base += PDC_CHIP0_OFS;
1449 probe_ent->n_ports = 4;
1450 pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1451 pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1452 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1453 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1455 pci_set_master(pdev);
1457 /* initialize adapter */
1458 /* initialize local dimm */
1459 if (pdc20621_dimm_init(probe_ent)) {
1461 goto err_out_iounmap_dimm;
1463 pdc_20621_init(probe_ent);
1465 /* FIXME: check ata_device_add return value */
1466 ata_device_add(probe_ent);
1471 err_out_iounmap_dimm: /* only get to this label if 20621 */
1473 pci_iounmap(pdev, dimm_mmio);
1475 pci_iounmap(pdev, mmio_base);
1479 pci_release_regions(pdev);
1482 pci_disable_device(pdev);
1487 static int __init pdc_sata_init(void)
1489 return pci_module_init(&pdc_sata_pci_driver);
1493 static void __exit pdc_sata_exit(void)
1495 pci_unregister_driver(&pdc_sata_pci_driver);
1499 MODULE_AUTHOR("Jeff Garzik");
1500 MODULE_DESCRIPTION("Promise SATA low-level driver");
1501 MODULE_LICENSE("GPL");
1502 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1503 MODULE_VERSION(DRV_VERSION);
1505 module_init(pdc_sata_init);
1506 module_exit(pdc_sata_exit);