drivers/scsi/stex.c

   1 /*
   2  * SuperTrak EX Series Storage Controller driver for Linux
   3  *
   4  *      Copyright (C) 2005-2009 Promise Technology Inc.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Written By:
  12  *              Ed Lin <promise_linux@promise.com>
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/kernel.h>
  19 #include <linux/delay.h>
  20 #include <linux/slab.h>
  21 #include <linux/time.h>
  22 #include <linux/pci.h>
  23 #include <linux/blkdev.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/spinlock.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30 #include <asm/byteorder.h>
  31 #include <scsi/scsi.h>
  32 #include <scsi/scsi_device.h>
  33 #include <scsi/scsi_cmnd.h>
  34 #include <scsi/scsi_host.h>
  35 #include <scsi/scsi_tcq.h>
  36 #include <scsi/scsi_dbg.h>
  37 #include <scsi/scsi_eh.h>
  38
  39 #define DRV_NAME "stex"
  40 #define ST_DRIVER_VERSION "4.6.0000.4"
  41 #define ST_VER_MAJOR            4
  42 #define ST_VER_MINOR            6
  43 #define ST_OEM                  0
  44 #define ST_BUILD_VER            4
  45
  46 enum {
  47         /* MU register offset */
  48         IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
  49         IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
  50         OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
  51         OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
  52         IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
  53         IIS     = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
  54         IIM     = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
  55         ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
  56         OIS     = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
  57         OIM     = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
  58
  59         YIOA_STATUS                             = 0x00,
  60         YH2I_INT                                = 0x20,
  61         YINT_EN                                 = 0x34,
  62         YI2H_INT                                = 0x9c,
  63         YI2H_INT_C                              = 0xa0,
  64         YH2I_REQ                                = 0xc0,
  65         YH2I_REQ_HI                             = 0xc4,
  66
  67         /* MU register value */
  68         MU_INBOUND_DOORBELL_HANDSHAKE           = (1 << 0),
  69         MU_INBOUND_DOORBELL_REQHEADCHANGED      = (1 << 1),
  70         MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = (1 << 2),
  71         MU_INBOUND_DOORBELL_HMUSTOPPED          = (1 << 3),
  72         MU_INBOUND_DOORBELL_RESET               = (1 << 4),
  73
  74         MU_OUTBOUND_DOORBELL_HANDSHAKE          = (1 << 0),
  75         MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
  76         MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = (1 << 2),
  77         MU_OUTBOUND_DOORBELL_BUSCHANGE          = (1 << 3),
  78         MU_OUTBOUND_DOORBELL_HASEVENT           = (1 << 4),
  79         MU_OUTBOUND_DOORBELL_REQUEST_RESET      = (1 << 27),
  80
  81         /* MU status code */
  82         MU_STATE_STARTING                       = 1,
  83         MU_STATE_STARTED                        = 2,
  84         MU_STATE_RESETTING                      = 3,
  85         MU_STATE_FAILED                         = 4,
  86
  87         MU_MAX_DELAY                            = 120,
  88         MU_HANDSHAKE_SIGNATURE                  = 0x55aaaa55,
  89         MU_HANDSHAKE_SIGNATURE_HALF             = 0x5a5a0000,
  90         MU_HARD_RESET_WAIT                      = 30000,
  91         HMU_PARTNER_TYPE                        = 2,
  92
  93         /* firmware returned values */
  94         SRB_STATUS_SUCCESS                      = 0x01,
  95         SRB_STATUS_ERROR                        = 0x04,
  96         SRB_STATUS_BUSY                         = 0x05,
  97         SRB_STATUS_INVALID_REQUEST              = 0x06,
  98         SRB_STATUS_SELECTION_TIMEOUT            = 0x0A,
  99         SRB_SEE_SENSE                           = 0x80,
 100
 101         /* task attribute */
 102         TASK_ATTRIBUTE_SIMPLE                   = 0x0,
 103         TASK_ATTRIBUTE_HEADOFQUEUE              = 0x1,
 104         TASK_ATTRIBUTE_ORDERED                  = 0x2,
 105         TASK_ATTRIBUTE_ACA                      = 0x4,
 106
 107         SS_STS_NORMAL                           = 0x80000000,
 108         SS_STS_DONE                             = 0x40000000,
 109         SS_STS_HANDSHAKE                        = 0x20000000,
 110
 111         SS_HEAD_HANDSHAKE                       = 0x80,
 112
 113         SS_H2I_INT_RESET                        = 0x100,
 114
 115         SS_I2H_REQUEST_RESET                    = 0x2000,
 116
 117         SS_MU_OPERATIONAL                       = 0x80000000,
 118
 119         STEX_CDB_LENGTH                         = 16,
 120         STATUS_VAR_LEN                          = 128,
 121
 122         /* sg flags */
 123         SG_CF_EOT                               = 0x80, /* end of table */
 124         SG_CF_64B                               = 0x40, /* 64 bit item */
 125         SG_CF_HOST                              = 0x20, /* sg in host memory */
 126         MSG_DATA_DIR_ND                         = 0,
 127         MSG_DATA_DIR_IN                         = 1,
 128         MSG_DATA_DIR_OUT                        = 2,
 129
 130         st_shasta                               = 0,
 131         st_vsc                                  = 1,
 132         st_yosemite                             = 2,
 133         st_seq                                  = 3,
 134         st_yel                                  = 4,
 135
 136         PASSTHRU_REQ_TYPE                       = 0x00000001,
 137         PASSTHRU_REQ_NO_WAKEUP                  = 0x00000100,
 138         ST_INTERNAL_TIMEOUT                     = 180,
 139
 140         ST_TO_CMD                               = 0,
 141         ST_FROM_CMD                             = 1,
 142
 143         /* vendor specific commands of Promise */
 144         MGT_CMD                                 = 0xd8,
 145         SINBAND_MGT_CMD                         = 0xd9,
 146         ARRAY_CMD                               = 0xe0,
 147         CONTROLLER_CMD                          = 0xe1,
 148         DEBUGGING_CMD                           = 0xe2,
 149         PASSTHRU_CMD                            = 0xe3,
 150
 151         PASSTHRU_GET_ADAPTER                    = 0x05,
 152         PASSTHRU_GET_DRVVER                     = 0x10,
 153
 154         CTLR_CONFIG_CMD                         = 0x03,
 155         CTLR_SHUTDOWN                           = 0x0d,
 156
 157         CTLR_POWER_STATE_CHANGE                 = 0x0e,
 158         CTLR_POWER_SAVING                       = 0x01,
 159
 160         PASSTHRU_SIGNATURE                      = 0x4e415041,
 161         MGT_CMD_SIGNATURE                       = 0xba,
 162
 163         INQUIRY_EVPD                            = 0x01,
 164
 165         ST_ADDITIONAL_MEM                       = 0x200000,
 166         ST_ADDITIONAL_MEM_MIN                   = 0x80000,
 167 };
 168
 169 struct st_sgitem {
 170         u8 ctrl;        /* SG_CF_xxx */
 171         u8 reserved[3];
 172         __le32 count;
 173         __le64 addr;
 174 };
 175
 176 struct st_ss_sgitem {
 177         __le32 addr;
 178         __le32 addr_hi;
 179         __le32 count;
 180 };
 181
 182 struct st_sgtable {
 183         __le16 sg_count;
 184         __le16 max_sg_count;
 185         __le32 sz_in_byte;
 186 };
 187
 188 struct st_msg_header {
 189         __le64 handle;
 190         u8 flag;
 191         u8 channel;
 192         __le16 timeout;
 193         u32 reserved;
 194 };
 195
 196 struct handshake_frame {
 197         __le64 rb_phy;          /* request payload queue physical address */
 198         __le16 req_sz;          /* size of each request payload */
 199         __le16 req_cnt;         /* count of reqs the buffer can hold */
 200         __le16 status_sz;       /* size of each status payload */
 201         __le16 status_cnt;      /* count of status the buffer can hold */
 202         __le64 hosttime;        /* seconds from Jan 1, 1970 (GMT) */
 203         u8 partner_type;        /* who sends this frame */
 204         u8 reserved0[7];
 205         __le32 partner_ver_major;
 206         __le32 partner_ver_minor;
 207         __le32 partner_ver_oem;
 208         __le32 partner_ver_build;
 209         __le32 extra_offset;    /* NEW */
 210         __le32 extra_size;      /* NEW */
 211         __le32 scratch_size;
 212         u32 reserved1;
 213 };
 214
 215 struct req_msg {
 216         __le16 tag;
 217         u8 lun;
 218         u8 target;
 219         u8 task_attr;
 220         u8 task_manage;
 221         u8 data_dir;
 222         u8 payload_sz;          /* payload size in 4-byte, not used */
 223         u8 cdb[STEX_CDB_LENGTH];
 224         u32 variable[0];
 225 };
 226
 227 struct status_msg {
 228         __le16 tag;
 229         u8 lun;
 230         u8 target;
 231         u8 srb_status;
 232         u8 scsi_status;
 233         u8 reserved;
 234         u8 payload_sz;          /* payload size in 4-byte */
 235         u8 variable[STATUS_VAR_LEN];
 236 };
 237
 238 struct ver_info {
 239         u32 major;
 240         u32 minor;
 241         u32 oem;
 242         u32 build;
 243         u32 reserved[2];
 244 };
 245
 246 struct st_frame {
 247         u32 base[6];
 248         u32 rom_addr;
 249
 250         struct ver_info drv_ver;
 251         struct ver_info bios_ver;
 252
 253         u32 bus;
 254         u32 slot;
 255         u32 irq_level;
 256         u32 irq_vec;
 257         u32 id;
 258         u32 subid;
 259
 260         u32 dimm_size;
 261         u8 dimm_type;
 262         u8 reserved[3];
 263
 264         u32 channel;
 265         u32 reserved1;
 266 };
 267
 268 struct st_drvver {
 269         u32 major;
 270         u32 minor;
 271         u32 oem;
 272         u32 build;
 273         u32 signature[2];
 274         u8 console_id;
 275         u8 host_no;
 276         u8 reserved0[2];
 277         u32 reserved[3];
 278 };
 279
 280 struct st_ccb {
 281         struct req_msg *req;
 282         struct scsi_cmnd *cmd;
 283
 284         void *sense_buffer;
 285         unsigned int sense_bufflen;
 286         int sg_count;
 287
 288         u32 req_type;
 289         u8 srb_status;
 290         u8 scsi_status;
 291         u8 reserved[2];
 292 };
 293
 294 struct st_hba {
 295         void __iomem *mmio_base;        /* iomapped PCI memory space */
 296         void *dma_mem;
 297         dma_addr_t dma_handle;
 298         size_t dma_size;
 299
 300         struct Scsi_Host *host;
 301         struct pci_dev *pdev;
 302
 303         struct req_msg * (*alloc_rq) (struct st_hba *);
 304         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 305         void (*send) (struct st_hba *, struct req_msg *, u16);
 306
 307         u32 req_head;
 308         u32 req_tail;
 309         u32 status_head;
 310         u32 status_tail;
 311
 312         struct status_msg *status_buffer;
 313         void *copy_buffer; /* temp buffer for driver-handled commands */
 314         struct st_ccb *ccb;
 315         struct st_ccb *wait_ccb;
 316         __le32 *scratch;
 317
 318         char work_q_name[20];
 319         struct workqueue_struct *work_q;
 320         struct work_struct reset_work;
 321         wait_queue_head_t reset_waitq;
 322         unsigned int mu_status;
 323         unsigned int cardtype;
 324         int msi_enabled;
 325         int out_req_cnt;
 326         u32 extra_offset;
 327         u16 rq_count;
 328         u16 rq_size;
 329         u16 sts_count;
 330 };
 331
 332 struct st_card_info {
 333         struct req_msg * (*alloc_rq) (struct st_hba *);
 334         int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
 335         void (*send) (struct st_hba *, struct req_msg *, u16);
 336         unsigned int max_id;
 337         unsigned int max_lun;
 338         unsigned int max_channel;
 339         u16 rq_count;
 340         u16 rq_size;
 341         u16 sts_count;
 342 };
 343
 344 static int msi;
 345 module_param(msi, int, 0);
 346 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
 347
 348 static const char console_inq_page[] =
 349 {
 350         0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
 351         0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,        /* "Promise " */
 352         0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,        /* "RAID Con" */
 353         0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,        /* "sole    " */
 354         0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,        /* "1.00    " */
 355         0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,        /* "SX/RSAF-" */
 356         0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,        /* "TE1.00  " */
 357         0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
 358 };
 359
 360 MODULE_AUTHOR("Ed Lin");
 361 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
 362 MODULE_LICENSE("GPL");
 363 MODULE_VERSION(ST_DRIVER_VERSION);
 364
 365 static void stex_gettime(__le64 *time)
 366 {
 367         struct timeval tv;
 368
 369         do_gettimeofday(&tv);
 370         *time = cpu_to_le64(tv.tv_sec);
 371 }
 372
 373 static struct status_msg *stex_get_status(struct st_hba *hba)
 374 {
 375         struct status_msg *status = hba->status_buffer + hba->status_tail;
 376
 377         ++hba->status_tail;
 378         hba->status_tail %= hba->sts_count+1;
 379
 380         return status;
 381 }
 382
 383 static void stex_invalid_field(struct scsi_cmnd *cmd,
 384                                void (*done)(struct scsi_cmnd *))
 385 {
 386         cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
 387
 388         /* "Invalid field in cdb" */
 389         scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
 390                                 0x0);
 391         done(cmd);
 392 }
 393
 394 static struct req_msg *stex_alloc_req(struct st_hba *hba)
 395 {
 396         struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
 397
 398         ++hba->req_head;
 399         hba->req_head %= hba->rq_count+1;
 400
 401         return req;
 402 }
 403
 404 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
 405 {
 406         return (struct req_msg *)(hba->dma_mem +
 407                 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
 408 }
 409
 410 static int stex_map_sg(struct st_hba *hba,
 411         struct req_msg *req, struct st_ccb *ccb)
 412 {
 413         struct scsi_cmnd *cmd;
 414         struct scatterlist *sg;
 415         struct st_sgtable *dst;
 416         struct st_sgitem *table;
 417         int i, nseg;
 418
 419         cmd = ccb->cmd;
 420         nseg = scsi_dma_map(cmd);
 421         BUG_ON(nseg < 0);
 422         if (nseg) {
 423                 dst = (struct st_sgtable *)req->variable;
 424
 425                 ccb->sg_count = nseg;
 426                 dst->sg_count = cpu_to_le16((u16)nseg);
 427                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 428                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 429
 430                 table = (struct st_sgitem *)(dst + 1);
 431                 scsi_for_each_sg(cmd, sg, nseg, i) {
 432                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 433                         table[i].addr = cpu_to_le64(sg_dma_address(sg));
 434                         table[i].ctrl = SG_CF_64B | SG_CF_HOST;
 435                 }
 436                 table[--i].ctrl |= SG_CF_EOT;
 437         }
 438
 439         return nseg;
 440 }
 441
 442 static int stex_ss_map_sg(struct st_hba *hba,
 443         struct req_msg *req, struct st_ccb *ccb)
 444 {
 445         struct scsi_cmnd *cmd;
 446         struct scatterlist *sg;
 447         struct st_sgtable *dst;
 448         struct st_ss_sgitem *table;
 449         int i, nseg;
 450
 451         cmd = ccb->cmd;
 452         nseg = scsi_dma_map(cmd);
 453         BUG_ON(nseg < 0);
 454         if (nseg) {
 455                 dst = (struct st_sgtable *)req->variable;
 456
 457                 ccb->sg_count = nseg;
 458                 dst->sg_count = cpu_to_le16((u16)nseg);
 459                 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
 460                 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
 461
 462                 table = (struct st_ss_sgitem *)(dst + 1);
 463                 scsi_for_each_sg(cmd, sg, nseg, i) {
 464                         table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
 465                         table[i].addr =
 466                                 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
 467                         table[i].addr_hi =
 468                                 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
 469                 }
 470         }
 471
 472         return nseg;
 473 }
 474
 475 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
 476 {
 477         struct st_frame *p;
 478         size_t count = sizeof(struct st_frame);
 479
 480         p = hba->copy_buffer;
 481         scsi_sg_copy_to_buffer(ccb->cmd, p, count);
 482         memset(p->base, 0, sizeof(u32)*6);
 483         *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
 484         p->rom_addr = 0;
 485
 486         p->drv_ver.major = ST_VER_MAJOR;
 487         p->drv_ver.minor = ST_VER_MINOR;
 488         p->drv_ver.oem = ST_OEM;
 489         p->drv_ver.build = ST_BUILD_VER;
 490
 491         p->bus = hba->pdev->bus->number;
 492         p->slot = hba->pdev->devfn;
 493         p->irq_level = 0;
 494         p->irq_vec = hba->pdev->irq;
 495         p->id = hba->pdev->vendor << 16 | hba->pdev->device;
 496         p->subid =
 497                 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
 498
 499         scsi_sg_copy_from_buffer(ccb->cmd, p, count);
 500 }
 501
 502 static void
 503 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 504 {
 505         req->tag = cpu_to_le16(tag);
 506
 507         hba->ccb[tag].req = req;
 508         hba->out_req_cnt++;
 509
 510         writel(hba->req_head, hba->mmio_base + IMR0);
 511         writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
 512         readl(hba->mmio_base + IDBL); /* flush */
 513 }
 514
 515 static void
 516 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
 517 {
 518         struct scsi_cmnd *cmd;
 519         struct st_msg_header *msg_h;
 520         dma_addr_t addr;
 521
 522         req->tag = cpu_to_le16(tag);
 523
 524         hba->ccb[tag].req = req;
 525         hba->out_req_cnt++;
 526
 527         cmd = hba->ccb[tag].cmd;
 528         msg_h = (struct st_msg_header *)req - 1;
 529         if (likely(cmd)) {
 530                 msg_h->channel = (u8)cmd->device->channel;
 531                 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
 532         }
 533         addr = hba->dma_handle + hba->req_head * hba->rq_size;
 534         addr += (hba->ccb[tag].sg_count+4)/11;
 535         msg_h->handle = cpu_to_le64(addr);
 536
 537         ++hba->req_head;
 538         hba->req_head %= hba->rq_count+1;
 539
 540         writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
 541         readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
 542         writel(addr, hba->mmio_base + YH2I_REQ);
 543         readl(hba->mmio_base + YH2I_REQ); /* flush */
 544 }
 545
 546 static int
 547 stex_slave_config(struct scsi_device *sdev)
 548 {
 549         sdev->use_10_for_rw = 1;
 550         sdev->use_10_for_ms = 1;
 551         blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
 552
 553         return 0;
 554 }
 555
 556 static int
 557 stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
 558 {
 559         struct st_hba *hba;
 560         struct Scsi_Host *host;
 561         unsigned int id, lun;
 562         struct req_msg *req;
 563         u16 tag;
 564
 565         host = cmd->device->host;
 566         id = cmd->device->id;
 567         lun = cmd->device->lun;
 568         hba = (struct st_hba *) &host->hostdata[0];
 569
 570         if (unlikely(hba->mu_status == MU_STATE_RESETTING))
 571                 return SCSI_MLQUEUE_HOST_BUSY;
 572
 573         switch (cmd->cmnd[0]) {
 574         case MODE_SENSE_10:
 575         {
 576                 static char ms10_caching_page[12] =
 577                         { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
 578                 unsigned char page;
 579
 580                 page = cmd->cmnd[2] & 0x3f;
 581                 if (page == 0x8 || page == 0x3f) {
 582                         scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
 583                                                  sizeof(ms10_caching_page));
 584                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 585                         done(cmd);
 586                 } else
 587                         stex_invalid_field(cmd, done);
 588                 return 0;
 589         }
 590         case REPORT_LUNS:
 591                 /*
 592                  * The shasta firmware does not report actual luns in the
 593                  * target, so fail the command to force sequential lun scan.
 594                  * Also, the console device does not support this command.
 595                  */
 596                 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
 597                         stex_invalid_field(cmd, done);
 598                         return 0;
 599                 }
 600                 break;
 601         case TEST_UNIT_READY:
 602                 if (id == host->max_id - 1) {
 603                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 604                         done(cmd);
 605                         return 0;
 606                 }
 607                 break;
 608         case INQUIRY:
 609                 if (lun >= host->max_lun) {
 610                         cmd->result = DID_NO_CONNECT << 16;
 611                         done(cmd);
 612                         return 0;
 613                 }
 614                 if (id != host->max_id - 1)
 615                         break;
 616                 if (!lun && !cmd->device->channel &&
 617                         (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
 618                         scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
 619                                                  sizeof(console_inq_page));
 620                         cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
 621                         done(cmd);
 622                 } else
 623                         stex_invalid_field(cmd, done);
 624                 return 0;
 625         case PASSTHRU_CMD:
 626                 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
 627                         struct st_drvver ver;
 628                         size_t cp_len = sizeof(ver);
 629
 630                         ver.major = ST_VER_MAJOR;
 631                         ver.minor = ST_VER_MINOR;
 632                         ver.oem = ST_OEM;
 633                         ver.build = ST_BUILD_VER;
 634                         ver.signature[0] = PASSTHRU_SIGNATURE;
 635                         ver.console_id = host->max_id - 1;
 636                         ver.host_no = hba->host->host_no;
 637                         cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
 638                         cmd->result = sizeof(ver) == cp_len ?
 639                                 DID_OK << 16 | COMMAND_COMPLETE << 8 :
 640                                 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 641                         done(cmd);
 642                         return 0;
 643                 }
 644         default:
 645                 break;
 646         }
 647
 648         cmd->scsi_done = done;
 649
 650         tag = cmd->request->tag;
 651
 652         if (unlikely(tag >= host->can_queue))
 653                 return SCSI_MLQUEUE_HOST_BUSY;
 654
 655         req = hba->alloc_rq(hba);
 656
 657         req->lun = lun;
 658         req->target = id;
 659
 660         /* cdb */
 661         memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
 662
 663         if (cmd->sc_data_direction == DMA_FROM_DEVICE)
 664                 req->data_dir = MSG_DATA_DIR_IN;
 665         else if (cmd->sc_data_direction == DMA_TO_DEVICE)
 666                 req->data_dir = MSG_DATA_DIR_OUT;
 667         else
 668                 req->data_dir = MSG_DATA_DIR_ND;
 669
 670         hba->ccb[tag].cmd = cmd;
 671         hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
 672         hba->ccb[tag].sense_buffer = cmd->sense_buffer;
 673
 674         if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
 675                 hba->ccb[tag].sg_count = 0;
 676                 memset(&req->variable[0], 0, 8);
 677         }
 678
 679         hba->send(hba, req, tag);
 680         return 0;
 681 }
 682
 683 static DEF_SCSI_QCMD(stex_queuecommand)
 684
 685 static void stex_scsi_done(struct st_ccb *ccb)
 686 {
 687         struct scsi_cmnd *cmd = ccb->cmd;
 688         int result;
 689
 690         if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
 691                 result = ccb->scsi_status;
 692                 switch (ccb->scsi_status) {
 693                 case SAM_STAT_GOOD:
 694                         result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
 695                         break;
 696                 case SAM_STAT_CHECK_CONDITION:
 697                         result |= DRIVER_SENSE << 24;
 698                         break;
 699                 case SAM_STAT_BUSY:
 700                         result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 701                         break;
 702                 default:
 703                         result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 704                         break;
 705                 }
 706         }
 707         else if (ccb->srb_status & SRB_SEE_SENSE)
 708                 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
 709         else switch (ccb->srb_status) {
 710                 case SRB_STATUS_SELECTION_TIMEOUT:
 711                         result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
 712                         break;
 713                 case SRB_STATUS_BUSY:
 714                         result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
 715                         break;
 716                 case SRB_STATUS_INVALID_REQUEST:
 717                 case SRB_STATUS_ERROR:
 718                 default:
 719                         result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
 720                         break;
 721         }
 722
 723         cmd->result = result;
 724         cmd->scsi_done(cmd);
 725 }
 726
 727 static void stex_copy_data(struct st_ccb *ccb,
 728         struct status_msg *resp, unsigned int variable)
 729 {
 730         if (resp->scsi_status != SAM_STAT_GOOD) {
 731                 if (ccb->sense_buffer != NULL)
 732                         memcpy(ccb->sense_buffer, resp->variable,
 733                                 min(variable, ccb->sense_bufflen));
 734                 return;
 735         }
 736
 737         if (ccb->cmd == NULL)
 738                 return;
 739         scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
 740 }
 741
 742 static void stex_check_cmd(struct st_hba *hba,
 743         struct st_ccb *ccb, struct status_msg *resp)
 744 {
 745         if (ccb->cmd->cmnd[0] == MGT_CMD &&
 746                 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
 747                 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
 748                         le32_to_cpu(*(__le32 *)&resp->variable[0]));
 749 }
 750
 751 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
 752 {
 753         void __iomem *base = hba->mmio_base;
 754         struct status_msg *resp;
 755         struct st_ccb *ccb;
 756         unsigned int size;
 757         u16 tag;
 758
 759         if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
 760                 return;
 761
 762         /* status payloads */
 763         hba->status_head = readl(base + OMR1);
 764         if (unlikely(hba->status_head > hba->sts_count)) {
 765                 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
 766                         pci_name(hba->pdev));
 767                 return;
 768         }
 769
 770         /*
 771          * it's not a valid status payload if:
 772          * 1. there are no pending requests(e.g. during init stage)
 773          * 2. there are some pending requests, but the controller is in
 774          *     reset status, and its type is not st_yosemite
 775          * firmware of st_yosemite in reset status will return pending requests
 776          * to driver, so we allow it to pass
 777          */
 778         if (unlikely(hba->out_req_cnt <= 0 ||
 779                         (hba->mu_status == MU_STATE_RESETTING &&
 780                          hba->cardtype != st_yosemite))) {
 781                 hba->status_tail = hba->status_head;
 782                 goto update_status;
 783         }
 784
 785         while (hba->status_tail != hba->status_head) {
 786                 resp = stex_get_status(hba);
 787                 tag = le16_to_cpu(resp->tag);
 788                 if (unlikely(tag >= hba->host->can_queue)) {
 789                         printk(KERN_WARNING DRV_NAME
 790                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 791                         continue;
 792                 }
 793
 794                 hba->out_req_cnt--;
 795                 ccb = &hba->ccb[tag];
 796                 if (unlikely(hba->wait_ccb == ccb))
 797                         hba->wait_ccb = NULL;
 798                 if (unlikely(ccb->req == NULL)) {
 799                         printk(KERN_WARNING DRV_NAME
 800                                 "(%s): lagging req\n", pci_name(hba->pdev));
 801                         continue;
 802                 }
 803
 804                 size = resp->payload_sz * sizeof(u32); /* payload size */
 805                 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 806                         size > sizeof(*resp))) {
 807                         printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
 808                                 pci_name(hba->pdev));
 809                 } else {
 810                         size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
 811                         if (size)
 812                                 stex_copy_data(ccb, resp, size);
 813                 }
 814
 815                 ccb->req = NULL;
 816                 ccb->srb_status = resp->srb_status;
 817                 ccb->scsi_status = resp->scsi_status;
 818
 819                 if (likely(ccb->cmd != NULL)) {
 820                         if (hba->cardtype == st_yosemite)
 821                                 stex_check_cmd(hba, ccb, resp);
 822
 823                         if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
 824                                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
 825                                 stex_controller_info(hba, ccb);
 826
 827                         scsi_dma_unmap(ccb->cmd);
 828                         stex_scsi_done(ccb);
 829                 } else
 830                         ccb->req_type = 0;
 831         }
 832
 833 update_status:
 834         writel(hba->status_head, base + IMR1);
 835         readl(base + IMR1); /* flush */
 836 }
 837
 838 static irqreturn_t stex_intr(int irq, void *__hba)
 839 {
 840         struct st_hba *hba = __hba;
 841         void __iomem *base = hba->mmio_base;
 842         u32 data;
 843         unsigned long flags;
 844
 845         spin_lock_irqsave(hba->host->host_lock, flags);
 846
 847         data = readl(base + ODBL);
 848
 849         if (data && data != 0xffffffff) {
 850                 /* clear the interrupt */
 851                 writel(data, base + ODBL);
 852                 readl(base + ODBL); /* flush */
 853                 stex_mu_intr(hba, data);
 854                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 855                 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
 856                         hba->cardtype == st_shasta))
 857                         queue_work(hba->work_q, &hba->reset_work);
 858                 return IRQ_HANDLED;
 859         }
 860
 861         spin_unlock_irqrestore(hba->host->host_lock, flags);
 862
 863         return IRQ_NONE;
 864 }
 865
 866 static void stex_ss_mu_intr(struct st_hba *hba)
 867 {
 868         struct status_msg *resp;
 869         struct st_ccb *ccb;
 870         __le32 *scratch;
 871         unsigned int size;
 872         int count = 0;
 873         u32 value;
 874         u16 tag;
 875
 876         if (unlikely(hba->out_req_cnt <= 0 ||
 877                         hba->mu_status == MU_STATE_RESETTING))
 878                 return;
 879
 880         while (count < hba->sts_count) {
 881                 scratch = hba->scratch + hba->status_tail;
 882                 value = le32_to_cpu(*scratch);
 883                 if (unlikely(!(value & SS_STS_NORMAL)))
 884                         return;
 885
 886                 resp = hba->status_buffer + hba->status_tail;
 887                 *scratch = 0;
 888                 ++count;
 889                 ++hba->status_tail;
 890                 hba->status_tail %= hba->sts_count+1;
 891
 892                 tag = (u16)value;
 893                 if (unlikely(tag >= hba->host->can_queue)) {
 894                         printk(KERN_WARNING DRV_NAME
 895                                 "(%s): invalid tag\n", pci_name(hba->pdev));
 896                         continue;
 897                 }
 898
 899                 hba->out_req_cnt--;
 900                 ccb = &hba->ccb[tag];
 901                 if (unlikely(hba->wait_ccb == ccb))
 902                         hba->wait_ccb = NULL;
 903                 if (unlikely(ccb->req == NULL)) {
 904                         printk(KERN_WARNING DRV_NAME
 905                                 "(%s): lagging req\n", pci_name(hba->pdev));
 906                         continue;
 907                 }
 908
 909                 ccb->req = NULL;
 910                 if (likely(value & SS_STS_DONE)) { /* normal case */
 911                         ccb->srb_status = SRB_STATUS_SUCCESS;
 912                         ccb->scsi_status = SAM_STAT_GOOD;
 913                 } else {
 914                         ccb->srb_status = resp->srb_status;
 915                         ccb->scsi_status = resp->scsi_status;
 916                         size = resp->payload_sz * sizeof(u32);
 917                         if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
 918                                 size > sizeof(*resp))) {
 919                                 printk(KERN_WARNING DRV_NAME
 920                                         "(%s): bad status size\n",
 921                                         pci_name(hba->pdev));
 922                         } else {
 923                                 size -= sizeof(*resp) - STATUS_VAR_LEN;
 924                                 if (size)
 925                                         stex_copy_data(ccb, resp, size);
 926                         }
 927                         if (likely(ccb->cmd != NULL))
 928                                 stex_check_cmd(hba, ccb, resp);
 929                 }
 930
 931                 if (likely(ccb->cmd != NULL)) {
 932                         scsi_dma_unmap(ccb->cmd);
 933                         stex_scsi_done(ccb);
 934                 } else
 935                         ccb->req_type = 0;
 936         }
 937 }
 938
 939 static irqreturn_t stex_ss_intr(int irq, void *__hba)
 940 {
 941         struct st_hba *hba = __hba;
 942         void __iomem *base = hba->mmio_base;
 943         u32 data;
 944         unsigned long flags;
 945
 946         spin_lock_irqsave(hba->host->host_lock, flags);
 947
 948         data = readl(base + YI2H_INT);
 949         if (data && data != 0xffffffff) {
 950                 /* clear the interrupt */
 951                 writel(data, base + YI2H_INT_C);
 952                 stex_ss_mu_intr(hba);
 953                 spin_unlock_irqrestore(hba->host->host_lock, flags);
 954                 if (unlikely(data & SS_I2H_REQUEST_RESET))
 955                         queue_work(hba->work_q, &hba->reset_work);
 956                 return IRQ_HANDLED;
 957         }
 958
 959         spin_unlock_irqrestore(hba->host->host_lock, flags);
 960
 961         return IRQ_NONE;
 962 }
 963
 964 static int stex_common_handshake(struct st_hba *hba)
 965 {
 966         void __iomem *base = hba->mmio_base;
 967         struct handshake_frame *h;
 968         dma_addr_t status_phys;
 969         u32 data;
 970         unsigned long before;
 971
 972         if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 973                 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
 974                 readl(base + IDBL);
 975                 before = jiffies;
 976                 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
 977                         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
 978                                 printk(KERN_ERR DRV_NAME
 979                                         "(%s): no handshake signature\n",
 980                                         pci_name(hba->pdev));
 981                                 return -1;
 982                         }
 983                         rmb();
 984                         msleep(1);
 985                 }
 986         }
 987
 988         udelay(10);
 989
 990         data = readl(base + OMR1);
 991         if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
 992                 data &= 0x0000ffff;
 993                 if (hba->host->can_queue > data) {
 994                         hba->host->can_queue = data;
 995                         hba->host->cmd_per_lun = data;
 996                 }
 997         }
 998
 999         h = (struct handshake_frame *)hba->status_buffer;
1000         h->rb_phy = cpu_to_le64(hba->dma_handle);
1001         h->req_sz = cpu_to_le16(hba->rq_size);
1002         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1003         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1004         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1005         stex_gettime(&h->hosttime);
1006         h->partner_type = HMU_PARTNER_TYPE;
1007         if (hba->extra_offset) {
1008                 h->extra_offset = cpu_to_le32(hba->extra_offset);
1009                 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1010         } else
1011                 h->extra_offset = h->extra_size = 0;
1012
1013         status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1014         writel(status_phys, base + IMR0);
1015         readl(base + IMR0);
1016         writel((status_phys >> 16) >> 16, base + IMR1);
1017         readl(base + IMR1);
1018
1019         writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1020         readl(base + OMR0);
1021         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1022         readl(base + IDBL); /* flush */
1023
1024         udelay(10);
1025         before = jiffies;
1026         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1027                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1028                         printk(KERN_ERR DRV_NAME
1029                                 "(%s): no signature after handshake frame\n",
1030                                 pci_name(hba->pdev));
1031                         return -1;
1032                 }
1033                 rmb();
1034                 msleep(1);
1035         }
1036
1037         writel(0, base + IMR0);
1038         readl(base + IMR0);
1039         writel(0, base + OMR0);
1040         readl(base + OMR0);
1041         writel(0, base + IMR1);
1042         readl(base + IMR1);
1043         writel(0, base + OMR1);
1044         readl(base + OMR1); /* flush */
1045         return 0;
1046 }
1047
1048 static int stex_ss_handshake(struct st_hba *hba)
1049 {
1050         void __iomem *base = hba->mmio_base;
1051         struct st_msg_header *msg_h;
1052         struct handshake_frame *h;
1053         __le32 *scratch;
1054         u32 data, scratch_size;
1055         unsigned long before;
1056         int ret = 0;
1057
1058         before = jiffies;
1059         while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) {
1060                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1061                         printk(KERN_ERR DRV_NAME
1062                                 "(%s): firmware not operational\n",
1063                                 pci_name(hba->pdev));
1064                         return -1;
1065                 }
1066                 msleep(1);
1067         }
1068
1069         msg_h = (struct st_msg_header *)hba->dma_mem;
1070         msg_h->handle = cpu_to_le64(hba->dma_handle);
1071         msg_h->flag = SS_HEAD_HANDSHAKE;
1072
1073         h = (struct handshake_frame *)(msg_h + 1);
1074         h->rb_phy = cpu_to_le64(hba->dma_handle);
1075         h->req_sz = cpu_to_le16(hba->rq_size);
1076         h->req_cnt = cpu_to_le16(hba->rq_count+1);
1077         h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1078         h->status_cnt = cpu_to_le16(hba->sts_count+1);
1079         stex_gettime(&h->hosttime);
1080         h->partner_type = HMU_PARTNER_TYPE;
1081         h->extra_offset = h->extra_size = 0;
1082         scratch_size = (hba->sts_count+1)*sizeof(u32);
1083         h->scratch_size = cpu_to_le32(scratch_size);
1084
1085         data = readl(base + YINT_EN);
1086         data &= ~4;
1087         writel(data, base + YINT_EN);
1088         writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1089         readl(base + YH2I_REQ_HI);
1090         writel(hba->dma_handle, base + YH2I_REQ);
1091         readl(base + YH2I_REQ); /* flush */
1092
1093         scratch = hba->scratch;
1094         before = jiffies;
1095         while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1096                 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1097                         printk(KERN_ERR DRV_NAME
1098                                 "(%s): no signature after handshake frame\n",
1099                                 pci_name(hba->pdev));
1100                         ret = -1;
1101                         break;
1102                 }
1103                 rmb();
1104                 msleep(1);
1105         }
1106
1107         memset(scratch, 0, scratch_size);
1108         msg_h->flag = 0;
1109         return ret;
1110 }
1111
1112 static int stex_handshake(struct st_hba *hba)
1113 {
1114         int err;
1115         unsigned long flags;
1116         unsigned int mu_status;
1117
1118         err = (hba->cardtype == st_yel) ?
1119                 stex_ss_handshake(hba) : stex_common_handshake(hba);
1120         spin_lock_irqsave(hba->host->host_lock, flags);
1121         mu_status = hba->mu_status;
1122         if (err == 0) {
1123                 hba->req_head = 0;
1124                 hba->req_tail = 0;
1125                 hba->status_head = 0;
1126                 hba->status_tail = 0;
1127                 hba->out_req_cnt = 0;
1128                 hba->mu_status = MU_STATE_STARTED;
1129         } else
1130                 hba->mu_status = MU_STATE_FAILED;
1131         if (mu_status == MU_STATE_RESETTING)
1132                 wake_up_all(&hba->reset_waitq);
1133         spin_unlock_irqrestore(hba->host->host_lock, flags);
1134         return err;
1135 }
1136
1137 static int stex_abort(struct scsi_cmnd *cmd)
1138 {
1139         struct Scsi_Host *host = cmd->device->host;
1140         struct st_hba *hba = (struct st_hba *)host->hostdata;
1141         u16 tag = cmd->request->tag;
1142         void __iomem *base;
1143         u32 data;
1144         int result = SUCCESS;
1145         unsigned long flags;
1146
1147         scmd_printk(KERN_INFO, cmd, "aborting command\n");
1148
1149         base = hba->mmio_base;
1150         spin_lock_irqsave(host->host_lock, flags);
1151         if (tag < host->can_queue &&
1152                 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1153                 hba->wait_ccb = &hba->ccb[tag];
1154         else
1155                 goto out;
1156
1157         if (hba->cardtype == st_yel) {
1158                 data = readl(base + YI2H_INT);
1159                 if (data == 0 || data == 0xffffffff)
1160                         goto fail_out;
1161
1162                 writel(data, base + YI2H_INT_C);
1163                 stex_ss_mu_intr(hba);
1164         } else {
1165                 data = readl(base + ODBL);
1166                 if (data == 0 || data == 0xffffffff)
1167                         goto fail_out;
1168
1169                 writel(data, base + ODBL);
1170                 readl(base + ODBL); /* flush */
1171
1172                 stex_mu_intr(hba, data);
1173         }
1174         if (hba->wait_ccb == NULL) {
1175                 printk(KERN_WARNING DRV_NAME
1176                         "(%s): lost interrupt\n", pci_name(hba->pdev));
1177                 goto out;
1178         }
1179
1180 fail_out:
1181         scsi_dma_unmap(cmd);
1182         hba->wait_ccb->req = NULL; /* nullify the req's future return */
1183         hba->wait_ccb = NULL;
1184         result = FAILED;
1185 out:
1186         spin_unlock_irqrestore(host->host_lock, flags);
1187         return result;
1188 }
1189
1190 static void stex_hard_reset(struct st_hba *hba)
1191 {
1192         struct pci_bus *bus;
1193         int i;
1194         u16 pci_cmd;
1195         u8 pci_bctl;
1196
1197         for (i = 0; i < 16; i++)
1198                 pci_read_config_dword(hba->pdev, i * 4,
1199                         &hba->pdev->saved_config_space[i]);
1200
1201         /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1202            secondary bus. Consult Intel 80331/3 developer's manual for detail */
1203         bus = hba->pdev->bus;
1204         pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1205         pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1206         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1207
1208         /*
1209          * 1 ms may be enough for 8-port controllers. But 16-port controllers
1210          * require more time to finish bus reset. Use 100 ms here for safety
1211          */
1212         msleep(100);
1213         pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1214         pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1215
1216         for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1217                 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1218                 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1219                         break;
1220                 msleep(1);
1221         }
1222
1223         ssleep(5);
1224         for (i = 0; i < 16; i++)
1225                 pci_write_config_dword(hba->pdev, i * 4,
1226                         hba->pdev->saved_config_space[i]);
1227 }
1228
1229 static int stex_yos_reset(struct st_hba *hba)
1230 {
1231         void __iomem *base;
1232         unsigned long flags, before;
1233         int ret = 0;
1234
1235         base = hba->mmio_base;
1236         writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1237         readl(base + IDBL); /* flush */
1238         before = jiffies;
1239         while (hba->out_req_cnt > 0) {
1240                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1241                         printk(KERN_WARNING DRV_NAME
1242                                 "(%s): reset timeout\n", pci_name(hba->pdev));
1243                         ret = -1;
1244                         break;
1245                 }
1246                 msleep(1);
1247         }
1248
1249         spin_lock_irqsave(hba->host->host_lock, flags);
1250         if (ret == -1)
1251                 hba->mu_status = MU_STATE_FAILED;
1252         else
1253                 hba->mu_status = MU_STATE_STARTED;
1254         wake_up_all(&hba->reset_waitq);
1255         spin_unlock_irqrestore(hba->host->host_lock, flags);
1256
1257         return ret;
1258 }
1259
1260 static void stex_ss_reset(struct st_hba *hba)
1261 {
1262         writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1263         readl(hba->mmio_base + YH2I_INT);
1264         ssleep(5);
1265 }
1266
1267 static int stex_do_reset(struct st_hba *hba)
1268 {
1269         struct st_ccb *ccb;
1270         unsigned long flags;
1271         unsigned int mu_status = MU_STATE_RESETTING;
1272         u16 tag;
1273
1274         spin_lock_irqsave(hba->host->host_lock, flags);
1275         if (hba->mu_status == MU_STATE_STARTING) {
1276                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1277                 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1278                         pci_name(hba->pdev));
1279                 return 0;
1280         }
1281         while (hba->mu_status == MU_STATE_RESETTING) {
1282                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1283                 wait_event_timeout(hba->reset_waitq,
1284                                    hba->mu_status != MU_STATE_RESETTING,
1285                                    MU_MAX_DELAY * HZ);
1286                 spin_lock_irqsave(hba->host->host_lock, flags);
1287                 mu_status = hba->mu_status;
1288         }
1289
1290         if (mu_status != MU_STATE_RESETTING) {
1291                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1292                 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1293         }
1294
1295         hba->mu_status = MU_STATE_RESETTING;
1296         spin_unlock_irqrestore(hba->host->host_lock, flags);
1297
1298         if (hba->cardtype == st_yosemite)
1299                 return stex_yos_reset(hba);
1300
1301         if (hba->cardtype == st_shasta)
1302                 stex_hard_reset(hba);
1303         else if (hba->cardtype == st_yel)
1304                 stex_ss_reset(hba);
1305
1306         spin_lock_irqsave(hba->host->host_lock, flags);
1307         for (tag = 0; tag < hba->host->can_queue; tag++) {
1308                 ccb = &hba->ccb[tag];
1309                 if (ccb->req == NULL)
1310                         continue;
1311                 ccb->req = NULL;
1312                 if (ccb->cmd) {
1313                         scsi_dma_unmap(ccb->cmd);
1314                         ccb->cmd->result = DID_RESET << 16;
1315                         ccb->cmd->scsi_done(ccb->cmd);
1316                         ccb->cmd = NULL;
1317                 }
1318         }
1319         spin_unlock_irqrestore(hba->host->host_lock, flags);
1320
1321         if (stex_handshake(hba) == 0)
1322                 return 0;
1323
1324         printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1325                 pci_name(hba->pdev));
1326         return -1;
1327 }
1328
1329 static int stex_reset(struct scsi_cmnd *cmd)
1330 {
1331         struct st_hba *hba;
1332
1333         hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1334
1335         shost_printk(KERN_INFO, cmd->device->host,
1336                      "resetting host\n");
1337
1338         return stex_do_reset(hba) ? FAILED : SUCCESS;
1339 }
1340
1341 static void stex_reset_work(struct work_struct *work)
1342 {
1343         struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1344
1345         stex_do_reset(hba);
1346 }
1347
1348 static int stex_biosparam(struct scsi_device *sdev,
1349         struct block_device *bdev, sector_t capacity, int geom[])
1350 {
1351         int heads = 255, sectors = 63;
1352
1353         if (capacity < 0x200000) {
1354                 heads = 64;
1355                 sectors = 32;
1356         }
1357
1358         sector_div(capacity, heads * sectors);
1359
1360         geom[0] = heads;
1361         geom[1] = sectors;
1362         geom[2] = capacity;
1363
1364         return 0;
1365 }
1366
1367 static struct scsi_host_template driver_template = {
1368         .module                         = THIS_MODULE,
1369         .name                           = DRV_NAME,
1370         .proc_name                      = DRV_NAME,
1371         .bios_param                     = stex_biosparam,
1372         .queuecommand                   = stex_queuecommand,
1373         .slave_configure                = stex_slave_config,
1374         .eh_abort_handler               = stex_abort,
1375         .eh_host_reset_handler          = stex_reset,
1376         .this_id                        = -1,
1377         .use_blk_tags                   = 1,
1378 };
1379
1380 static struct pci_device_id stex_pci_tbl[] = {
1381         /* st_shasta */
1382         { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1383                 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1384         { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1385                 st_shasta }, /* SuperTrak EX12350 */
1386         { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1387                 st_shasta }, /* SuperTrak EX4350 */
1388         { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1389                 st_shasta }, /* SuperTrak EX24350 */
1390
1391         /* st_vsc */
1392         { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1393
1394         /* st_yosemite */
1395         { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1396
1397         /* st_seq */
1398         { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1399
1400         /* st_yel */
1401         { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1402         { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1403         { }     /* terminate list */
1404 };
1405
1406 static struct st_card_info stex_card_info[] = {
1407         /* st_shasta */
1408         {
1409                 .max_id         = 17,
1410                 .max_lun        = 8,
1411                 .max_channel    = 0,
1412                 .rq_count       = 32,
1413                 .rq_size        = 1048,
1414                 .sts_count      = 32,
1415                 .alloc_rq       = stex_alloc_req,
1416                 .map_sg         = stex_map_sg,
1417                 .send           = stex_send_cmd,
1418         },
1419
1420         /* st_vsc */
1421         {
1422                 .max_id         = 129,
1423                 .max_lun        = 1,
1424                 .max_channel    = 0,
1425                 .rq_count       = 32,
1426                 .rq_size        = 1048,
1427                 .sts_count      = 32,
1428                 .alloc_rq       = stex_alloc_req,
1429                 .map_sg         = stex_map_sg,
1430                 .send           = stex_send_cmd,
1431         },
1432
1433         /* st_yosemite */
1434         {
1435                 .max_id         = 2,
1436                 .max_lun        = 256,
1437                 .max_channel    = 0,
1438                 .rq_count       = 256,
1439                 .rq_size        = 1048,
1440                 .sts_count      = 256,
1441                 .alloc_rq       = stex_alloc_req,
1442                 .map_sg         = stex_map_sg,
1443                 .send           = stex_send_cmd,
1444         },
1445
1446         /* st_seq */
1447         {
1448                 .max_id         = 129,
1449                 .max_lun        = 1,
1450                 .max_channel    = 0,
1451                 .rq_count       = 32,
1452                 .rq_size        = 1048,
1453                 .sts_count      = 32,
1454                 .alloc_rq       = stex_alloc_req,
1455                 .map_sg         = stex_map_sg,
1456                 .send           = stex_send_cmd,
1457         },
1458
1459         /* st_yel */
1460         {
1461                 .max_id         = 129,
1462                 .max_lun        = 256,
1463                 .max_channel    = 3,
1464                 .rq_count       = 801,
1465                 .rq_size        = 512,
1466                 .sts_count      = 801,
1467                 .alloc_rq       = stex_ss_alloc_req,
1468                 .map_sg         = stex_ss_map_sg,
1469                 .send           = stex_ss_send_cmd,
1470         },
1471 };
1472
1473 static int stex_set_dma_mask(struct pci_dev * pdev)
1474 {
1475         int ret;
1476
1477         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1478                 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
1479                 return 0;
1480         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1481         if (!ret)
1482                 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1483         return ret;
1484 }
1485
1486 static int stex_request_irq(struct st_hba *hba)
1487 {
1488         struct pci_dev *pdev = hba->pdev;
1489         int status;
1490
1491         if (msi) {
1492                 status = pci_enable_msi(pdev);
1493                 if (status != 0)
1494                         printk(KERN_ERR DRV_NAME
1495                                 "(%s): error %d setting up MSI\n",
1496                                 pci_name(pdev), status);
1497                 else
1498                         hba->msi_enabled = 1;
1499         } else
1500                 hba->msi_enabled = 0;
1501
1502         status = request_irq(pdev->irq, hba->cardtype == st_yel ?
1503                 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1504
1505         if (status != 0) {
1506                 if (hba->msi_enabled)
1507                         pci_disable_msi(pdev);
1508         }
1509         return status;
1510 }
1511
1512 static void stex_free_irq(struct st_hba *hba)
1513 {
1514         struct pci_dev *pdev = hba->pdev;
1515
1516         free_irq(pdev->irq, hba);
1517         if (hba->msi_enabled)
1518                 pci_disable_msi(pdev);
1519 }
1520
1521 static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1522 {
1523         struct st_hba *hba;
1524         struct Scsi_Host *host;
1525         const struct st_card_info *ci = NULL;
1526         u32 sts_offset, cp_offset, scratch_offset;
1527         int err;
1528
1529         err = pci_enable_device(pdev);
1530         if (err)
1531                 return err;
1532
1533         pci_set_master(pdev);
1534
1535         host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1536
1537         if (!host) {
1538                 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1539                         pci_name(pdev));
1540                 err = -ENOMEM;
1541                 goto out_disable;
1542         }
1543
1544         hba = (struct st_hba *)host->hostdata;
1545         memset(hba, 0, sizeof(struct st_hba));
1546
1547         err = pci_request_regions(pdev, DRV_NAME);
1548         if (err < 0) {
1549                 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1550                         pci_name(pdev));
1551                 goto out_scsi_host_put;
1552         }
1553
1554         hba->mmio_base = pci_ioremap_bar(pdev, 0);
1555         if ( !hba->mmio_base) {
1556                 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1557                         pci_name(pdev));
1558                 err = -ENOMEM;
1559                 goto out_release_regions;
1560         }
1561
1562         err = stex_set_dma_mask(pdev);
1563         if (err) {
1564                 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1565                         pci_name(pdev));
1566                 goto out_iounmap;
1567         }
1568
1569         hba->cardtype = (unsigned int) id->driver_data;
1570         ci = &stex_card_info[hba->cardtype];
1571         sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1572         if (hba->cardtype == st_yel)
1573                 sts_offset += (ci->sts_count+1) * sizeof(u32);
1574         cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1575         hba->dma_size = cp_offset + sizeof(struct st_frame);
1576         if (hba->cardtype == st_seq ||
1577                 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1578                 hba->extra_offset = hba->dma_size;
1579                 hba->dma_size += ST_ADDITIONAL_MEM;
1580         }
1581         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1582                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1583         if (!hba->dma_mem) {
1584                 /* Retry minimum coherent mapping for st_seq and st_vsc */
1585                 if (hba->cardtype == st_seq ||
1586                     (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1587                         printk(KERN_WARNING DRV_NAME
1588                                 "(%s): allocating min buffer for controller\n",
1589                                 pci_name(pdev));
1590                         hba->dma_size = hba->extra_offset
1591                                 + ST_ADDITIONAL_MEM_MIN;
1592                         hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1593                                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1594                 }
1595
1596                 if (!hba->dma_mem) {
1597                         err = -ENOMEM;
1598                         printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1599                                 pci_name(pdev));
1600                         goto out_iounmap;
1601                 }
1602         }
1603
1604         hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1605         if (!hba->ccb) {
1606                 err = -ENOMEM;
1607                 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1608                         pci_name(pdev));
1609                 goto out_pci_free;
1610         }
1611
1612         if (hba->cardtype == st_yel)
1613                 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1614         hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1615         hba->copy_buffer = hba->dma_mem + cp_offset;
1616         hba->rq_count = ci->rq_count;
1617         hba->rq_size = ci->rq_size;
1618         hba->sts_count = ci->sts_count;
1619         hba->alloc_rq = ci->alloc_rq;
1620         hba->map_sg = ci->map_sg;
1621         hba->send = ci->send;
1622         hba->mu_status = MU_STATE_STARTING;
1623
1624         if (hba->cardtype == st_yel)
1625                 host->sg_tablesize = 38;
1626         else
1627                 host->sg_tablesize = 32;
1628         host->can_queue = ci->rq_count;
1629         host->cmd_per_lun = ci->rq_count;
1630         host->max_id = ci->max_id;
1631         host->max_lun = ci->max_lun;
1632         host->max_channel = ci->max_channel;
1633         host->unique_id = host->host_no;
1634         host->max_cmd_len = STEX_CDB_LENGTH;
1635
1636         hba->host = host;
1637         hba->pdev = pdev;
1638         init_waitqueue_head(&hba->reset_waitq);
1639
1640         snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1641                  "stex_wq_%d", host->host_no);
1642         hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1643         if (!hba->work_q) {
1644                 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1645                         pci_name(pdev));
1646                 err = -ENOMEM;
1647                 goto out_ccb_free;
1648         }
1649         INIT_WORK(&hba->reset_work, stex_reset_work);
1650
1651         err = stex_request_irq(hba);
1652         if (err) {
1653                 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1654                         pci_name(pdev));
1655                 goto out_free_wq;
1656         }
1657
1658         err = stex_handshake(hba);
1659         if (err)
1660                 goto out_free_irq;
1661
1662         err = scsi_init_shared_tag_map(host, host->can_queue);
1663         if (err) {
1664                 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1665                         pci_name(pdev));
1666                 goto out_free_irq;
1667         }
1668
1669         pci_set_drvdata(pdev, hba);
1670
1671         err = scsi_add_host(host, &pdev->dev);
1672         if (err) {
1673                 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1674                         pci_name(pdev));
1675                 goto out_free_irq;
1676         }
1677
1678         scsi_scan_host(host);
1679
1680         return 0;
1681
1682 out_free_irq:
1683         stex_free_irq(hba);
1684 out_free_wq:
1685         destroy_workqueue(hba->work_q);
1686 out_ccb_free:
1687         kfree(hba->ccb);
1688 out_pci_free:
1689         dma_free_coherent(&pdev->dev, hba->dma_size,
1690                           hba->dma_mem, hba->dma_handle);
1691 out_iounmap:
1692         iounmap(hba->mmio_base);
1693 out_release_regions:
1694         pci_release_regions(pdev);
1695 out_scsi_host_put:
1696         scsi_host_put(host);
1697 out_disable:
1698         pci_disable_device(pdev);
1699
1700         return err;
1701 }
1702
1703 static void stex_hba_stop(struct st_hba *hba)
1704 {
1705         struct req_msg *req;
1706         struct st_msg_header *msg_h;
1707         unsigned long flags;
1708         unsigned long before;
1709         u16 tag = 0;
1710
1711         spin_lock_irqsave(hba->host->host_lock, flags);
1712         req = hba->alloc_rq(hba);
1713         if (hba->cardtype == st_yel) {
1714                 msg_h = (struct st_msg_header *)req - 1;
1715                 memset(msg_h, 0, hba->rq_size);
1716         } else
1717                 memset(req, 0, hba->rq_size);
1718
1719         if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) {
1720                 req->cdb[0] = MGT_CMD;
1721                 req->cdb[1] = MGT_CMD_SIGNATURE;
1722                 req->cdb[2] = CTLR_CONFIG_CMD;
1723                 req->cdb[3] = CTLR_SHUTDOWN;
1724         } else {
1725                 req->cdb[0] = CONTROLLER_CMD;
1726                 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1727                 req->cdb[2] = CTLR_POWER_SAVING;
1728         }
1729
1730         hba->ccb[tag].cmd = NULL;
1731         hba->ccb[tag].sg_count = 0;
1732         hba->ccb[tag].sense_bufflen = 0;
1733         hba->ccb[tag].sense_buffer = NULL;
1734         hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1735
1736         hba->send(hba, req, tag);
1737         spin_unlock_irqrestore(hba->host->host_lock, flags);
1738
1739         before = jiffies;
1740         while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1741                 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1742                         hba->ccb[tag].req_type = 0;
1743                         return;
1744                 }
1745                 msleep(1);
1746         }
1747 }
1748
1749 static void stex_hba_free(struct st_hba *hba)
1750 {
1751         stex_free_irq(hba);
1752
1753         destroy_workqueue(hba->work_q);
1754
1755         iounmap(hba->mmio_base);
1756
1757         pci_release_regions(hba->pdev);
1758
1759         kfree(hba->ccb);
1760
1761         dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1762                           hba->dma_mem, hba->dma_handle);
1763 }
1764
1765 static void stex_remove(struct pci_dev *pdev)
1766 {
1767         struct st_hba *hba = pci_get_drvdata(pdev);
1768
1769         scsi_remove_host(hba->host);
1770
1771         stex_hba_stop(hba);
1772
1773         stex_hba_free(hba);
1774
1775         scsi_host_put(hba->host);
1776
1777         pci_disable_device(pdev);
1778 }
1779
1780 static void stex_shutdown(struct pci_dev *pdev)
1781 {
1782         struct st_hba *hba = pci_get_drvdata(pdev);
1783
1784         stex_hba_stop(hba);
1785 }
1786
1787 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1788
1789 static struct pci_driver stex_pci_driver = {
1790         .name           = DRV_NAME,
1791         .id_table       = stex_pci_tbl,
1792         .probe          = stex_probe,
1793         .remove         = stex_remove,
1794         .shutdown       = stex_shutdown,
1795 };
1796
1797 static int __init stex_init(void)
1798 {
1799         printk(KERN_INFO DRV_NAME
1800                 ": Promise SuperTrak EX Driver version: %s\n",
1801                  ST_DRIVER_VERSION);
1802
1803         return pci_register_driver(&stex_pci_driver);
1804 }
1805
1806 static void __exit stex_exit(void)
1807 {
1808         pci_unregister_driver(&stex_pci_driver);
1809 }
1810
1811 module_init(stex_init);
1812 module_exit(stex_exit);