drivers/serial/bfin_5xx.c

   1 /*
   2  * Blackfin On-Chip Serial Driver
   3  *
   4  * Copyright 2006-2008 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  12 #define SUPPORT_SYSRQ
  13 #endif
  14
  15 #include <linux/module.h>
  16 #include <linux/ioport.h>
  17 #include <linux/gfp.h>
  18 #include <linux/io.h>
  19 #include <linux/init.h>
  20 #include <linux/console.h>
  21 #include <linux/sysrq.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/tty.h>
  24 #include <linux/tty_flip.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/dma-mapping.h>
  27
  28 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
  29         defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
  30 #include <linux/kgdb.h>
  31 #include <asm/irq_regs.h>
  32 #endif
  33
  34 #include <asm/gpio.h>
  35 #include <mach/bfin_serial_5xx.h>
  36
  37 #include <asm/dma.h>
  38 #include <asm/io.h>
  39 #include <asm/irq.h>
  40 #include <asm/cacheflush.h>
  41
  42 #ifdef CONFIG_SERIAL_BFIN_MODULE
  43 # undef CONFIG_EARLY_PRINTK
  44 #endif
  45
  46 #ifdef CONFIG_SERIAL_BFIN_MODULE
  47 # undef CONFIG_EARLY_PRINTK
  48 #endif
  49
  50 /* UART name and device definitions */
  51 #define BFIN_SERIAL_NAME        "ttyBF"
  52 #define BFIN_SERIAL_MAJOR       204
  53 #define BFIN_SERIAL_MINOR       64
  54
  55 static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
  56 static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource);
  57
  58 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
  59         defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
  60
  61 # ifndef CONFIG_SERIAL_BFIN_PIO
  62 #  error KGDB only support UART in PIO mode.
  63 # endif
  64
  65 static int kgdboc_port_line;
  66 static int kgdboc_break_enabled;
  67 #endif
  68 /*
  69  * Setup for console. Argument comes from the menuconfig
  70  */
  71 #define DMA_RX_XCOUNT           512
  72 #define DMA_RX_YCOUNT           (PAGE_SIZE / DMA_RX_XCOUNT)
  73
  74 #define DMA_RX_FLUSH_JIFFIES    (HZ / 50)
  75
  76 #ifdef CONFIG_SERIAL_BFIN_DMA
  77 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
  78 #else
  79 static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
  80 #endif
  81
  82 static void bfin_serial_reset_irda(struct uart_port *port);
  83
  84 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
  85         defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
  86 static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
  87 {
  88         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  89         if (uart->cts_pin < 0)
  90                 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  91
  92         /* CTS PIN is negative assertive. */
  93         if (UART_GET_CTS(uart))
  94                 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  95         else
  96                 return TIOCM_DSR | TIOCM_CAR;
  97 }
  98
  99 static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 100 {
 101         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
 102         if (uart->rts_pin < 0)
 103                 return;
 104
 105         /* RTS PIN is negative assertive. */
 106         if (mctrl & TIOCM_RTS)
 107                 UART_ENABLE_RTS(uart);
 108         else
 109                 UART_DISABLE_RTS(uart);
 110 }
 111
 112 /*
 113  * Handle any change of modem status signal.
 114  */
 115 static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
 116 {
 117         struct bfin_serial_port *uart = dev_id;
 118         unsigned int status;
 119
 120         status = bfin_serial_get_mctrl(&uart->port);
 121         uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
 122 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 123         uart->scts = 1;
 124         UART_CLEAR_SCTS(uart);
 125         UART_CLEAR_IER(uart, EDSSI);
 126 #endif
 127
 128         return IRQ_HANDLED;
 129 }
 130 #else
 131 static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
 132 {
 133         return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
 134 }
 135
 136 static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 137 {
 138 }
 139 #endif
 140
 141 /*
 142  * interrupts are disabled on entry
 143  */
 144 static void bfin_serial_stop_tx(struct uart_port *port)
 145 {
 146         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
 147 #ifdef CONFIG_SERIAL_BFIN_DMA
 148         struct circ_buf *xmit = &uart->port.state->xmit;
 149 #endif
 150
 151         while (!(UART_GET_LSR(uart) & TEMT))
 152                 cpu_relax();
 153
 154 #ifdef CONFIG_SERIAL_BFIN_DMA
 155         disable_dma(uart->tx_dma_channel);
 156         xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
 157         uart->port.icount.tx += uart->tx_count;
 158         uart->tx_count = 0;
 159         uart->tx_done = 1;
 160 #else
 161 #ifdef CONFIG_BF54x
 162         /* Clear TFI bit */
 163         UART_PUT_LSR(uart, TFI);
 164 #endif
 165         UART_CLEAR_IER(uart, ETBEI);
 166 #endif
 167 }
 168
 169 /*
 170  * port is locked and interrupts are disabled
 171  */
 172 static void bfin_serial_start_tx(struct uart_port *port)
 173 {
 174         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
 175         struct tty_struct *tty = uart->port.state->port.tty;
 176
 177 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 178         if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
 179                 uart->scts = 0;
 180                 uart_handle_cts_change(&uart->port, uart->scts);
 181         }
 182 #endif
 183
 184         /*
 185          * To avoid losting RX interrupt, we reset IR function
 186          * before sending data.
 187          */
 188         if (tty->termios->c_line == N_IRDA)
 189                 bfin_serial_reset_irda(port);
 190
 191 #ifdef CONFIG_SERIAL_BFIN_DMA
 192         if (uart->tx_done)
 193                 bfin_serial_dma_tx_chars(uart);
 194 #else
 195         UART_SET_IER(uart, ETBEI);
 196         bfin_serial_tx_chars(uart);
 197 #endif
 198 }
 199
 200 /*
 201  * Interrupts are enabled
 202  */
 203 static void bfin_serial_stop_rx(struct uart_port *port)
 204 {
 205         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
 206
 207         UART_CLEAR_IER(uart, ERBFI);
 208 }
 209
 210 /*
 211  * Set the modem control timer to fire immediately.
 212  */
 213 static void bfin_serial_enable_ms(struct uart_port *port)
 214 {
 215 }
 216
 217
 218 #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
 219 # define UART_GET_ANOMALY_THRESHOLD(uart)    ((uart)->anomaly_threshold)
 220 # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
 221 #else
 222 # define UART_GET_ANOMALY_THRESHOLD(uart)    0
 223 # define UART_SET_ANOMALY_THRESHOLD(uart, v)
 224 #endif
 225
 226 #ifdef CONFIG_SERIAL_BFIN_PIO
 227 static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
 228 {
 229         struct tty_struct *tty = NULL;
 230         unsigned int status, ch, flg;
 231         static struct timeval anomaly_start = { .tv_sec = 0 };
 232
 233         status = UART_GET_LSR(uart);
 234         UART_CLEAR_LSR(uart);
 235
 236         ch = UART_GET_CHAR(uart);
 237         uart->port.icount.rx++;
 238
 239 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
 240         defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
 241         if (kgdb_connected && kgdboc_port_line == uart->port.line
 242                 && kgdboc_break_enabled)
 243                 if (ch == 0x3) {/* Ctrl + C */
 244                         kgdb_breakpoint();
 245                         return;
 246                 }
 247
 248         if (!uart->port.state || !uart->port.state->port.tty)
 249                 return;
 250 #endif
 251         tty = uart->port.state->port.tty;
 252
 253         if (ANOMALY_05000363) {
 254                 /* The BF533 (and BF561) family of processors have a nice anomaly
 255                  * where they continuously generate characters for a "single" break.
 256                  * We have to basically ignore this flood until the "next" valid
 257                  * character comes across.  Due to the nature of the flood, it is
 258                  * not possible to reliably catch bytes that are sent too quickly
 259                  * after this break.  So application code talking to the Blackfin
 260                  * which sends a break signal must allow at least 1.5 character
 261                  * times after the end of the break for things to stabilize.  This
 262                  * timeout was picked as it must absolutely be larger than 1
 263                  * character time +/- some percent.  So 1.5 sounds good.  All other
 264                  * Blackfin families operate properly.  Woo.
 265                  */
 266                 if (anomaly_start.tv_sec) {
 267                         struct timeval curr;
 268                         suseconds_t usecs;
 269
 270                         if ((~ch & (~ch + 1)) & 0xff)
 271                                 goto known_good_char;
 272
 273                         do_gettimeofday(&curr);
 274                         if (curr.tv_sec - anomaly_start.tv_sec > 1)
 275                                 goto known_good_char;
 276
 277                         usecs = 0;
 278                         if (curr.tv_sec != anomaly_start.tv_sec)
 279                                 usecs += USEC_PER_SEC;
 280                         usecs += curr.tv_usec - anomaly_start.tv_usec;
 281
 282                         if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
 283                                 goto known_good_char;
 284
 285                         if (ch)
 286                                 anomaly_start.tv_sec = 0;
 287                         else
 288                                 anomaly_start = curr;
 289
 290                         return;
 291
 292  known_good_char:
 293                         status &= ~BI;
 294                         anomaly_start.tv_sec = 0;
 295                 }
 296         }
 297
 298         if (status & BI) {
 299                 if (ANOMALY_05000363)
 300                         if (bfin_revid() < 5)
 301                                 do_gettimeofday(&anomaly_start);
 302                 uart->port.icount.brk++;
 303                 if (uart_handle_break(&uart->port))
 304                         goto ignore_char;
 305                 status &= ~(PE | FE);
 306         }
 307         if (status & PE)
 308                 uart->port.icount.parity++;
 309         if (status & OE)
 310                 uart->port.icount.overrun++;
 311         if (status & FE)
 312                 uart->port.icount.frame++;
 313
 314         status &= uart->port.read_status_mask;
 315
 316         if (status & BI)
 317                 flg = TTY_BREAK;
 318         else if (status & PE)
 319                 flg = TTY_PARITY;
 320         else if (status & FE)
 321                 flg = TTY_FRAME;
 322         else
 323                 flg = TTY_NORMAL;
 324
 325         if (uart_handle_sysrq_char(&uart->port, ch))
 326                 goto ignore_char;
 327
 328         uart_insert_char(&uart->port, status, OE, ch, flg);
 329
 330  ignore_char:
 331         tty_flip_buffer_push(tty);
 332 }
 333
 334 static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
 335 {
 336         struct circ_buf *xmit = &uart->port.state->xmit;
 337
 338         if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
 339 #ifdef CONFIG_BF54x
 340                 /* Clear TFI bit */
 341                 UART_PUT_LSR(uart, TFI);
 342 #endif
 343                 /* Anomaly notes:
 344                  *  05000215 -  we always clear ETBEI within last UART TX
 345                  *              interrupt to end a string. It is always set
 346                  *              when start a new tx.
 347                  */
 348                 UART_CLEAR_IER(uart, ETBEI);
 349                 return;
 350         }
 351
 352         if (uart->port.x_char) {
 353                 UART_PUT_CHAR(uart, uart->port.x_char);
 354                 uart->port.icount.tx++;
 355                 uart->port.x_char = 0;
 356         }
 357
 358         while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
 359                 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
 360                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 361                 uart->port.icount.tx++;
 362                 SSYNC();
 363         }
 364
 365         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 366                 uart_write_wakeup(&uart->port);
 367 }
 368
 369 static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
 370 {
 371         struct bfin_serial_port *uart = dev_id;
 372
 373         spin_lock(&uart->port.lock);
 374         while (UART_GET_LSR(uart) & DR)
 375                 bfin_serial_rx_chars(uart);
 376         spin_unlock(&uart->port.lock);
 377
 378         return IRQ_HANDLED;
 379 }
 380
 381 static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
 382 {
 383         struct bfin_serial_port *uart = dev_id;
 384
 385 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 386         if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
 387                 uart->scts = 0;
 388                 uart_handle_cts_change(&uart->port, uart->scts);
 389         }
 390 #endif
 391         spin_lock(&uart->port.lock);
 392         if (UART_GET_LSR(uart) & THRE)
 393                 bfin_serial_tx_chars(uart);
 394         spin_unlock(&uart->port.lock);
 395
 396         return IRQ_HANDLED;
 397 }
 398 #endif
 399
 400 #ifdef CONFIG_SERIAL_BFIN_DMA
 401 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
 402 {
 403         struct circ_buf *xmit = &uart->port.state->xmit;
 404
 405         uart->tx_done = 0;
 406
 407         if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
 408                 uart->tx_count = 0;
 409                 uart->tx_done = 1;
 410                 return;
 411         }
 412
 413         if (uart->port.x_char) {
 414                 UART_PUT_CHAR(uart, uart->port.x_char);
 415                 uart->port.icount.tx++;
 416                 uart->port.x_char = 0;
 417         }
 418
 419         uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
 420         if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
 421                 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
 422         blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
 423                                         (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
 424         set_dma_config(uart->tx_dma_channel,
 425                 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
 426                         INTR_ON_BUF,
 427                         DIMENSION_LINEAR,
 428                         DATA_SIZE_8,
 429                         DMA_SYNC_RESTART));
 430         set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
 431         set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
 432         set_dma_x_modify(uart->tx_dma_channel, 1);
 433         SSYNC();
 434         enable_dma(uart->tx_dma_channel);
 435
 436         UART_SET_IER(uart, ETBEI);
 437 }
 438
 439 static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
 440 {
 441         struct tty_struct *tty = uart->port.state->port.tty;
 442         int i, flg, status;
 443
 444         status = UART_GET_LSR(uart);
 445         UART_CLEAR_LSR(uart);
 446
 447         uart->port.icount.rx +=
 448                 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
 449                 UART_XMIT_SIZE);
 450
 451         if (status & BI) {
 452                 uart->port.icount.brk++;
 453                 if (uart_handle_break(&uart->port))
 454                         goto dma_ignore_char;
 455                 status &= ~(PE | FE);
 456         }
 457         if (status & PE)
 458                 uart->port.icount.parity++;
 459         if (status & OE)
 460                 uart->port.icount.overrun++;
 461         if (status & FE)
 462                 uart->port.icount.frame++;
 463
 464         status &= uart->port.read_status_mask;
 465
 466         if (status & BI)
 467                 flg = TTY_BREAK;
 468         else if (status & PE)
 469                 flg = TTY_PARITY;
 470         else if (status & FE)
 471                 flg = TTY_FRAME;
 472         else
 473                 flg = TTY_NORMAL;
 474
 475         for (i = uart->rx_dma_buf.tail; ; i++) {
 476                 if (i >= UART_XMIT_SIZE)
 477                         i = 0;
 478                 if (i == uart->rx_dma_buf.head)
 479                         break;
 480                 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
 481                         uart_insert_char(&uart->port, status, OE,
 482                                 uart->rx_dma_buf.buf[i], flg);
 483         }
 484
 485  dma_ignore_char:
 486         tty_flip_buffer_push(tty);
 487 }
 488
 489 void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
 490 {
 491         int x_pos, pos;
 492
 493         dma_disable_irq(uart->tx_dma_channel);
 494         dma_disable_irq(uart->rx_dma_channel);
 495         spin_lock_bh(&uart->port.lock);
 496
 497         /* 2D DMA RX buffer ring is used. Because curr_y_count and
 498          * curr_x_count can't be read as an atomic operation,
 499          * curr_y_count should be read before curr_x_count. When
 500          * curr_x_count is read, curr_y_count may already indicate
 501          * next buffer line. But, the position calculated here is
 502          * still indicate the old line. The wrong position data may
 503          * be smaller than current buffer tail, which cause garbages
 504          * are received if it is not prohibit.
 505          */
 506         uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
 507         x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
 508         uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
 509         if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
 510                 uart->rx_dma_nrows = 0;
 511         x_pos = DMA_RX_XCOUNT - x_pos;
 512         if (x_pos == DMA_RX_XCOUNT)
 513                 x_pos = 0;
 514
 515         pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
 516         /* Ignore receiving data if new position is in the same line of
 517          * current buffer tail and small.
 518          */
 519         if (pos > uart->rx_dma_buf.tail ||
 520                 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
 521                 uart->rx_dma_buf.head = pos;
 522                 bfin_serial_dma_rx_chars(uart);
 523                 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
 524         }
 525
 526         spin_unlock_bh(&uart->port.lock);
 527         dma_enable_irq(uart->tx_dma_channel);
 528         dma_enable_irq(uart->rx_dma_channel);
 529
 530         mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
 531 }
 532
 533 static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
 534 {
 535         struct bfin_serial_port *uart = dev_id;
 536         struct circ_buf *xmit = &uart->port.state->xmit;
 537
 538 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 539         if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
 540                 uart->scts = 0;
 541                 uart_handle_cts_change(&uart->port, uart->scts);
 542         }
 543 #endif
 544
 545         spin_lock(&uart->port.lock);
 546         if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
 547                 disable_dma(uart->tx_dma_channel);
 548                 clear_dma_irqstat(uart->tx_dma_channel);
 549                 /* Anomaly notes:
 550                  *  05000215 -  we always clear ETBEI within last UART TX
 551                  *              interrupt to end a string. It is always set
 552                  *              when start a new tx.
 553                  */
 554                 UART_CLEAR_IER(uart, ETBEI);
 555                 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
 556                 uart->port.icount.tx += uart->tx_count;
 557
 558                 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 559                         uart_write_wakeup(&uart->port);
 560
 561                 bfin_serial_dma_tx_chars(uart);
 562         }
 563
 564         spin_unlock(&uart->port.lock);
 565         return IRQ_HANDLED;
 566 }
 567
 568 static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
 569 {
 570         struct bfin_serial_port *uart = dev_id;
 571         unsigned short irqstat;
 572         int x_pos, pos;
 573
 574         spin_lock(&uart->port.lock);
 575         irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
 576         clear_dma_irqstat(uart->rx_dma_channel);
 577
 578         uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
 579         x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
 580         uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
 581         if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
 582                 uart->rx_dma_nrows = 0;
 583
 584         pos = uart->rx_dma_nrows * DMA_RX_XCOUNT;
 585         if (pos > uart->rx_dma_buf.tail ||
 586                 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
 587                 uart->rx_dma_buf.head = pos;
 588                 bfin_serial_dma_rx_chars(uart);
 589                 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
 590         }
 591
 592         spin_unlock(&uart->port.lock);
 593
 594         return IRQ_HANDLED;
 595 }
 596 #endif
 597
 598 /*
 599  * Return TIOCSER_TEMT when transmitter is not busy.
 600  */
 601 static unsigned int bfin_serial_tx_empty(struct uart_port *port)
 602 {
 603         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
 604         unsigned short lsr;
 605
 606         lsr = UART_GET_LSR(uart);
 607         if (lsr & TEMT)
 608                 return TIOCSER_TEMT;
 609         else
 610                 return 0;
 611 }
 612
 613 static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
 614 {
 615         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
 616         u16 lcr = UART_GET_LCR(uart);
 617         if (break_state)
 618                 lcr |= SB;
 619         else
 620                 lcr &= ~SB;
 621         UART_PUT_LCR(uart, lcr);
 622         SSYNC();
 623 }
 624
 625 static int bfin_serial_startup(struct uart_port *port)
 626 {
 627         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
 628
 629 #ifdef CONFIG_SERIAL_BFIN_DMA
 630         dma_addr_t dma_handle;
 631
 632         if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
 633                 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
 634                 return -EBUSY;
 635         }
 636
 637         if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
 638                 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
 639                 free_dma(uart->rx_dma_channel);
 640                 return -EBUSY;
 641         }
 642
 643         set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
 644         set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
 645
 646         uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
 647         uart->rx_dma_buf.head = 0;
 648         uart->rx_dma_buf.tail = 0;
 649         uart->rx_dma_nrows = 0;
 650
 651         set_dma_config(uart->rx_dma_channel,
 652                 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
 653                                 INTR_ON_ROW, DIMENSION_2D,
 654                                 DATA_SIZE_8,
 655                                 DMA_SYNC_RESTART));
 656         set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
 657         set_dma_x_modify(uart->rx_dma_channel, 1);
 658         set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
 659         set_dma_y_modify(uart->rx_dma_channel, 1);
 660         set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
 661         enable_dma(uart->rx_dma_channel);
 662
 663         uart->rx_dma_timer.data = (unsigned long)(uart);
 664         uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
 665         uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
 666         add_timer(&(uart->rx_dma_timer));
 667 #else
 668 # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
 669         defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
 670         if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
 671                 kgdboc_break_enabled = 0;
 672         else {
 673 # endif
 674         if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
 675              "BFIN_UART_RX", uart)) {
 676                 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
 677                 return -EBUSY;
 678         }
 679
 680         if (request_irq
 681             (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
 682              "BFIN_UART_TX", uart)) {
 683                 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
 684                 free_irq(uart->port.irq, uart);
 685                 return -EBUSY;
 686         }
 687
 688 # ifdef CONFIG_BF54x
 689         {
 690                 /*
 691                  * UART2 and UART3 on BF548 share interrupt PINs and DMA
 692                  * controllers with SPORT2 and SPORT3. UART rx and tx
 693                  * interrupts are generated in PIO mode only when configure
 694                  * their peripheral mapping registers properly, which means
 695                  * request corresponding DMA channels in PIO mode as well.
 696                  */
 697                 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
 698
 699                 switch (uart->port.irq) {
 700                 case IRQ_UART3_RX:
 701                         uart_dma_ch_rx = CH_UART3_RX;
 702                         uart_dma_ch_tx = CH_UART3_TX;
 703                         break;
 704                 case IRQ_UART2_RX:
 705                         uart_dma_ch_rx = CH_UART2_RX;
 706                         uart_dma_ch_tx = CH_UART2_TX;
 707                         break;
 708                 default:
 709                         uart_dma_ch_rx = uart_dma_ch_tx = 0;
 710                         break;
 711                 };
 712
 713                 if (uart_dma_ch_rx &&
 714                         request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
 715                         printk(KERN_NOTICE"Fail to attach UART interrupt\n");
 716                         free_irq(uart->port.irq, uart);
 717                         free_irq(uart->port.irq + 1, uart);
 718                         return -EBUSY;
 719                 }
 720                 if (uart_dma_ch_tx &&
 721                         request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
 722                         printk(KERN_NOTICE "Fail to attach UART interrupt\n");
 723                         free_dma(uart_dma_ch_rx);
 724                         free_irq(uart->port.irq, uart);
 725                         free_irq(uart->port.irq + 1, uart);
 726                         return -EBUSY;
 727                 }
 728         }
 729 # endif
 730 # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
 731         defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
 732         }
 733 # endif
 734 #endif
 735
 736 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 737         if (uart->cts_pin >= 0) {
 738                 if (request_irq(gpio_to_irq(uart->cts_pin),
 739                         bfin_serial_mctrl_cts_int,
 740                         IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
 741                         IRQF_DISABLED, "BFIN_UART_CTS", uart)) {
 742                         uart->cts_pin = -1;
 743                         pr_info("Unable to attach BlackFin UART CTS interrupt. So, disable it.\n");
 744                 }
 745         }
 746         if (uart->rts_pin >= 0) {
 747                 gpio_request(uart->rts_pin, DRIVER_NAME);
 748                 gpio_direction_output(uart->rts_pin, 0);
 749         }
 750 #endif
 751 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 752         if (request_irq(uart->status_irq,
 753                 bfin_serial_mctrl_cts_int,
 754                 IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) {
 755                 pr_info("Unable to attach BlackFin UART Modem Status interrupt.\n");
 756         }
 757
 758         /* CTS RTS PINs are negative assertive. */
 759         UART_PUT_MCR(uart, ACTS);
 760         UART_SET_IER(uart, EDSSI);
 761 #endif
 762
 763         UART_SET_IER(uart, ERBFI);
 764         return 0;
 765 }
 766
 767 static void bfin_serial_shutdown(struct uart_port *port)
 768 {
 769         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
 770
 771 #ifdef CONFIG_SERIAL_BFIN_DMA
 772         disable_dma(uart->tx_dma_channel);
 773         free_dma(uart->tx_dma_channel);
 774         disable_dma(uart->rx_dma_channel);
 775         free_dma(uart->rx_dma_channel);
 776         del_timer(&(uart->rx_dma_timer));
 777         dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
 778 #else
 779 #ifdef CONFIG_BF54x
 780         switch (uart->port.irq) {
 781         case IRQ_UART3_RX:
 782                 free_dma(CH_UART3_RX);
 783                 free_dma(CH_UART3_TX);
 784                 break;
 785         case IRQ_UART2_RX:
 786                 free_dma(CH_UART2_RX);
 787                 free_dma(CH_UART2_TX);
 788                 break;
 789         default:
 790                 break;
 791         };
 792 #endif
 793         free_irq(uart->port.irq, uart);
 794         free_irq(uart->port.irq+1, uart);
 795 #endif
 796
 797 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 798         if (uart->cts_pin >= 0)
 799                 free_irq(gpio_to_irq(uart->cts_pin), uart);
 800         if (uart->rts_pin >= 0)
 801                 gpio_free(uart->rts_pin);
 802 #endif
 803 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
 804         if (UART_GET_IER(uart) & EDSSI)
 805                 free_irq(uart->status_irq, uart);
 806 #endif
 807 }
 808
 809 static void
 810 bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
 811                    struct ktermios *old)
 812 {
 813         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
 814         unsigned long flags;
 815         unsigned int baud, quot;
 816         unsigned short val, ier, lcr = 0;
 817
 818         switch (termios->c_cflag & CSIZE) {
 819         case CS8:
 820                 lcr = WLS(8);
 821                 break;
 822         case CS7:
 823                 lcr = WLS(7);
 824                 break;
 825         case CS6:
 826                 lcr = WLS(6);
 827                 break;
 828         case CS5:
 829                 lcr = WLS(5);
 830                 break;
 831         default:
 832                 printk(KERN_ERR "%s: word lengh not supported\n",
 833                         __func__);
 834         }
 835
 836         /* Anomaly notes:
 837          *  05000231 -  STOP bit is always set to 1 whatever the user is set.
 838          */
 839         if (termios->c_cflag & CSTOPB) {
 840                 if (ANOMALY_05000231)
 841                         printk(KERN_WARNING "STOP bits other than 1 is not "
 842                                 "supported in case of anomaly 05000231.\n");
 843                 else
 844                         lcr |= STB;
 845         }
 846         if (termios->c_cflag & PARENB)
 847                 lcr |= PEN;
 848         if (!(termios->c_cflag & PARODD))
 849                 lcr |= EPS;
 850         if (termios->c_cflag & CMSPAR)
 851                 lcr |= STP;
 852
 853         port->read_status_mask = OE;
 854         if (termios->c_iflag & INPCK)
 855                 port->read_status_mask |= (FE | PE);
 856         if (termios->c_iflag & (BRKINT | PARMRK))
 857                 port->read_status_mask |= BI;
 858
 859         /*
 860          * Characters to ignore
 861          */
 862         port->ignore_status_mask = 0;
 863         if (termios->c_iflag & IGNPAR)
 864                 port->ignore_status_mask |= FE | PE;
 865         if (termios->c_iflag & IGNBRK) {
 866                 port->ignore_status_mask |= BI;
 867                 /*
 868                  * If we're ignoring parity and break indicators,
 869                  * ignore overruns too (for real raw support).
 870                  */
 871                 if (termios->c_iflag & IGNPAR)
 872                         port->ignore_status_mask |= OE;
 873         }
 874
 875         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
 876         quot = uart_get_divisor(port, baud);
 877
 878         /* If discipline is not IRDA, apply ANOMALY_05000230 */
 879         if (termios->c_line != N_IRDA)
 880                 quot -= ANOMALY_05000230;
 881
 882         spin_lock_irqsave(&uart->port.lock, flags);
 883
 884         UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
 885
 886         /* Disable UART */
 887         ier = UART_GET_IER(uart);
 888         UART_DISABLE_INTS(uart);
 889
 890         /* Set DLAB in LCR to Access DLL and DLH */
 891         UART_SET_DLAB(uart);
 892
 893         UART_PUT_DLL(uart, quot & 0xFF);
 894         UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
 895         SSYNC();
 896
 897         /* Clear DLAB in LCR to Access THR RBR IER */
 898         UART_CLEAR_DLAB(uart);
 899
 900         UART_PUT_LCR(uart, lcr);
 901
 902         /* Enable UART */
 903         UART_ENABLE_INTS(uart, ier);
 904
 905         val = UART_GET_GCTL(uart);
 906         val |= UCEN;
 907         UART_PUT_GCTL(uart, val);
 908
 909         /* Port speed changed, update the per-port timeout. */
 910         uart_update_timeout(port, termios->c_cflag, baud);
 911
 912         spin_unlock_irqrestore(&uart->port.lock, flags);
 913 }
 914
 915 static const char *bfin_serial_type(struct uart_port *port)
 916 {
 917         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
 918
 919         return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
 920 }
 921
 922 /*
 923  * Release the memory region(s) being used by 'port'.
 924  */
 925 static void bfin_serial_release_port(struct uart_port *port)
 926 {
 927 }
 928
 929 /*
 930  * Request the memory region(s) being used by 'port'.
 931  */
 932 static int bfin_serial_request_port(struct uart_port *port)
 933 {
 934         return 0;
 935 }
 936
 937 /*
 938  * Configure/autoconfigure the port.
 939  */
 940 static void bfin_serial_config_port(struct uart_port *port, int flags)
 941 {
 942         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
 943
 944         if (flags & UART_CONFIG_TYPE &&
 945             bfin_serial_request_port(&uart->port) == 0)
 946                 uart->port.type = PORT_BFIN;
 947 }
 948
 949 /*
 950  * Verify the new serial_struct (for TIOCSSERIAL).
 951  * The only change we allow are to the flags and type, and
 952  * even then only between PORT_BFIN and PORT_UNKNOWN
 953  */
 954 static int
 955 bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
 956 {
 957         return 0;
 958 }
 959
 960 /*
 961  * Enable the IrDA function if tty->ldisc.num is N_IRDA.
 962  * In other cases, disable IrDA function.
 963  */
 964 static void bfin_serial_set_ldisc(struct uart_port *port, int ld)
 965 {
 966         int line = port->line;
 967         unsigned short val;
 968
 969         switch (ld) {
 970         case N_IRDA:
 971                 val = UART_GET_GCTL(&bfin_serial_ports[line]);
 972                 val |= (IREN | RPOLC);
 973                 UART_PUT_GCTL(&bfin_serial_ports[line], val);
 974                 break;
 975         default:
 976                 val = UART_GET_GCTL(&bfin_serial_ports[line]);
 977                 val &= ~(IREN | RPOLC);
 978                 UART_PUT_GCTL(&bfin_serial_ports[line], val);
 979         }
 980 }
 981
 982 static void bfin_serial_reset_irda(struct uart_port *port)
 983 {
 984         int line = port->line;
 985         unsigned short val;
 986
 987         val = UART_GET_GCTL(&bfin_serial_ports[line]);
 988         val &= ~(IREN | RPOLC);
 989         UART_PUT_GCTL(&bfin_serial_ports[line], val);
 990         SSYNC();
 991         val |= (IREN | RPOLC);
 992         UART_PUT_GCTL(&bfin_serial_ports[line], val);
 993         SSYNC();
 994 }
 995
 996 #ifdef CONFIG_CONSOLE_POLL
 997 /* Anomaly notes:
 998  *  05000099 -  Because we only use THRE in poll_put and DR in poll_get,
 999  *              losing other bits of UART_LSR is not a problem here.
1000  */
1001 static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
1002 {
1003         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1004
1005         while (!(UART_GET_LSR(uart) & THRE))
1006                 cpu_relax();
1007
1008         UART_CLEAR_DLAB(uart);
1009         UART_PUT_CHAR(uart, (unsigned char)chr);
1010 }
1011
1012 static int bfin_serial_poll_get_char(struct uart_port *port)
1013 {
1014         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1015         unsigned char chr;
1016
1017         while (!(UART_GET_LSR(uart) & DR))
1018                 cpu_relax();
1019
1020         UART_CLEAR_DLAB(uart);
1021         chr = UART_GET_CHAR(uart);
1022
1023         return chr;
1024 }
1025 #endif
1026
1027 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1028         defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1029 static void bfin_kgdboc_port_shutdown(struct uart_port *port)
1030 {
1031         if (kgdboc_break_enabled) {
1032                 kgdboc_break_enabled = 0;
1033                 bfin_serial_shutdown(port);
1034         }
1035 }
1036
1037 static int bfin_kgdboc_port_startup(struct uart_port *port)
1038 {
1039         kgdboc_port_line = port->line;
1040         kgdboc_break_enabled = !bfin_serial_startup(port);
1041         return 0;
1042 }
1043 #endif
1044
1045 static struct uart_ops bfin_serial_pops = {
1046         .tx_empty       = bfin_serial_tx_empty,
1047         .set_mctrl      = bfin_serial_set_mctrl,
1048         .get_mctrl      = bfin_serial_get_mctrl,
1049         .stop_tx        = bfin_serial_stop_tx,
1050         .start_tx       = bfin_serial_start_tx,
1051         .stop_rx        = bfin_serial_stop_rx,
1052         .enable_ms      = bfin_serial_enable_ms,
1053         .break_ctl      = bfin_serial_break_ctl,
1054         .startup        = bfin_serial_startup,
1055         .shutdown       = bfin_serial_shutdown,
1056         .set_termios    = bfin_serial_set_termios,
1057         .set_ldisc      = bfin_serial_set_ldisc,
1058         .type           = bfin_serial_type,
1059         .release_port   = bfin_serial_release_port,
1060         .request_port   = bfin_serial_request_port,
1061         .config_port    = bfin_serial_config_port,
1062         .verify_port    = bfin_serial_verify_port,
1063 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1064         defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1065         .kgdboc_port_startup    = bfin_kgdboc_port_startup,
1066         .kgdboc_port_shutdown   = bfin_kgdboc_port_shutdown,
1067 #endif
1068 #ifdef CONFIG_CONSOLE_POLL
1069         .poll_put_char  = bfin_serial_poll_put_char,
1070         .poll_get_char  = bfin_serial_poll_get_char,
1071 #endif
1072 };
1073
1074 static void __init bfin_serial_hw_init(void)
1075 {
1076 #ifdef CONFIG_SERIAL_BFIN_UART0
1077         peripheral_request(P_UART0_TX, DRIVER_NAME);
1078         peripheral_request(P_UART0_RX, DRIVER_NAME);
1079 #endif
1080
1081 #ifdef CONFIG_SERIAL_BFIN_UART1
1082         peripheral_request(P_UART1_TX, DRIVER_NAME);
1083         peripheral_request(P_UART1_RX, DRIVER_NAME);
1084
1085 # if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x)
1086         peripheral_request(P_UART1_RTS, DRIVER_NAME);
1087         peripheral_request(P_UART1_CTS, DRIVER_NAME);
1088 # endif
1089 #endif
1090
1091 #ifdef CONFIG_SERIAL_BFIN_UART2
1092         peripheral_request(P_UART2_TX, DRIVER_NAME);
1093         peripheral_request(P_UART2_RX, DRIVER_NAME);
1094 #endif
1095
1096 #ifdef CONFIG_SERIAL_BFIN_UART3
1097         peripheral_request(P_UART3_TX, DRIVER_NAME);
1098         peripheral_request(P_UART3_RX, DRIVER_NAME);
1099
1100 # if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x)
1101         peripheral_request(P_UART3_RTS, DRIVER_NAME);
1102         peripheral_request(P_UART3_CTS, DRIVER_NAME);
1103 # endif
1104 #endif
1105 }
1106
1107 static void __init bfin_serial_init_ports(void)
1108 {
1109         static int first = 1;
1110         int i;
1111
1112         if (!first)
1113                 return;
1114         first = 0;
1115
1116         bfin_serial_hw_init();
1117
1118         for (i = 0; i < nr_active_ports; i++) {
1119                 spin_lock_init(&bfin_serial_ports[i].port.lock);
1120                 bfin_serial_ports[i].port.uartclk   = get_sclk();
1121                 bfin_serial_ports[i].port.fifosize  = BFIN_UART_TX_FIFO_SIZE;
1122                 bfin_serial_ports[i].port.ops       = &bfin_serial_pops;
1123                 bfin_serial_ports[i].port.line      = i;
1124                 bfin_serial_ports[i].port.iotype    = UPIO_MEM;
1125                 bfin_serial_ports[i].port.membase   =
1126                         (void __iomem *)bfin_serial_resource[i].uart_base_addr;
1127                 bfin_serial_ports[i].port.mapbase   =
1128                         bfin_serial_resource[i].uart_base_addr;
1129                 bfin_serial_ports[i].port.irq       =
1130                         bfin_serial_resource[i].uart_irq;
1131                 bfin_serial_ports[i].status_irq     =
1132                         bfin_serial_resource[i].uart_status_irq;
1133                 bfin_serial_ports[i].port.flags     = UPF_BOOT_AUTOCONF;
1134 #ifdef CONFIG_SERIAL_BFIN_DMA
1135                 bfin_serial_ports[i].tx_done        = 1;
1136                 bfin_serial_ports[i].tx_count       = 0;
1137                 bfin_serial_ports[i].tx_dma_channel =
1138                         bfin_serial_resource[i].uart_tx_dma_channel;
1139                 bfin_serial_ports[i].rx_dma_channel =
1140                         bfin_serial_resource[i].uart_rx_dma_channel;
1141                 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
1142 #endif
1143 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1144         defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1145                 bfin_serial_ports[i].cts_pin        =
1146                         bfin_serial_resource[i].uart_cts_pin;
1147                 bfin_serial_ports[i].rts_pin        =
1148                         bfin_serial_resource[i].uart_rts_pin;
1149 #endif
1150         }
1151 }
1152
1153 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1154 /*
1155  * If the port was already initialised (eg, by a boot loader),
1156  * try to determine the current setup.
1157  */
1158 static void __init
1159 bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1160                            int *parity, int *bits)
1161 {
1162         unsigned short status;
1163
1164         status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1165         if (status == (ERBFI | ETBEI)) {
1166                 /* ok, the port was enabled */
1167                 u16 lcr, dlh, dll;
1168
1169                 lcr = UART_GET_LCR(uart);
1170
1171                 *parity = 'n';
1172                 if (lcr & PEN) {
1173                         if (lcr & EPS)
1174                                 *parity = 'e';
1175                         else
1176                                 *parity = 'o';
1177                 }
1178                 switch (lcr & 0x03) {
1179                         case 0: *bits = 5; break;
1180                         case 1: *bits = 6; break;
1181                         case 2: *bits = 7; break;
1182                         case 3: *bits = 8; break;
1183                 }
1184                 /* Set DLAB in LCR to Access DLL and DLH */
1185                 UART_SET_DLAB(uart);
1186
1187                 dll = UART_GET_DLL(uart);
1188                 dlh = UART_GET_DLH(uart);
1189
1190                 /* Clear DLAB in LCR to Access THR RBR IER */
1191                 UART_CLEAR_DLAB(uart);
1192
1193                 *baud = get_sclk() / (16*(dll | dlh << 8));
1194         }
1195         pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
1196 }
1197
1198 static struct uart_driver bfin_serial_reg;
1199
1200 static int __init
1201 bfin_serial_console_setup(struct console *co, char *options)
1202 {
1203         struct bfin_serial_port *uart;
1204         int baud = 57600;
1205         int bits = 8;
1206         int parity = 'n';
1207 # if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1208         defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1209         int flow = 'r';
1210 # else
1211         int flow = 'n';
1212 # endif
1213
1214         /*
1215          * Check whether an invalid uart number has been specified, and
1216          * if so, search for the first available port that does have
1217          * console support.
1218          */
1219         if (co->index == -1 || co->index >= nr_active_ports)
1220                 co->index = 0;
1221         uart = &bfin_serial_ports[co->index];
1222
1223         if (options)
1224                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1225         else
1226                 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1227
1228         return uart_set_options(&uart->port, co, baud, parity, bits, flow);
1229 }
1230 #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1231                                  defined (CONFIG_EARLY_PRINTK) */
1232
1233 #ifdef CONFIG_SERIAL_BFIN_CONSOLE
1234 static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1235 {
1236         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1237         while (!(UART_GET_LSR(uart) & THRE))
1238                 barrier();
1239         UART_PUT_CHAR(uart, ch);
1240         SSYNC();
1241 }
1242
1243 /*
1244  * Interrupts are disabled on entering
1245  */
1246 static void
1247 bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1248 {
1249         struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
1250         unsigned long flags;
1251
1252         spin_lock_irqsave(&uart->port.lock, flags);
1253         uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1254         spin_unlock_irqrestore(&uart->port.lock, flags);
1255
1256 }
1257
1258 static struct console bfin_serial_console = {
1259         .name           = BFIN_SERIAL_NAME,
1260         .write          = bfin_serial_console_write,
1261         .device         = uart_console_device,
1262         .setup          = bfin_serial_console_setup,
1263         .flags          = CON_PRINTBUFFER,
1264         .index          = -1,
1265         .data           = &bfin_serial_reg,
1266 };
1267
1268 static int __init bfin_serial_rs_console_init(void)
1269 {
1270         bfin_serial_init_ports();
1271         register_console(&bfin_serial_console);
1272
1273         return 0;
1274 }
1275 console_initcall(bfin_serial_rs_console_init);
1276
1277 #define BFIN_SERIAL_CONSOLE     &bfin_serial_console
1278 #else
1279 #define BFIN_SERIAL_CONSOLE     NULL
1280 #endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1281
1282
1283 #ifdef CONFIG_EARLY_PRINTK
1284 static __init void early_serial_putc(struct uart_port *port, int ch)
1285 {
1286         unsigned timeout = 0xffff;
1287         struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1288
1289         while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1290                 cpu_relax();
1291         UART_PUT_CHAR(uart, ch);
1292 }
1293
1294 static __init void early_serial_write(struct console *con, const char *s,
1295                                         unsigned int n)
1296 {
1297         struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1298         unsigned int i;
1299
1300         for (i = 0; i < n; i++, s++) {
1301                 if (*s == '\n')
1302                         early_serial_putc(&uart->port, '\r');
1303                 early_serial_putc(&uart->port, *s);
1304         }
1305 }
1306
1307 /*
1308  * This should have a .setup or .early_setup in it, but then things get called
1309  * without the command line options, and the baud rate gets messed up - so
1310  * don't let the common infrastructure play with things. (see calls to setup
1311  * & earlysetup in ./kernel/printk.c:register_console()
1312  */
1313 static struct __initdata console bfin_early_serial_console = {
1314         .name = "early_BFuart",
1315         .write = early_serial_write,
1316         .device = uart_console_device,
1317         .flags = CON_PRINTBUFFER,
1318         .index = -1,
1319         .data  = &bfin_serial_reg,
1320 };
1321
1322 struct console __init *bfin_earlyserial_init(unsigned int port,
1323                                                 unsigned int cflag)
1324 {
1325         struct bfin_serial_port *uart;
1326         struct ktermios t;
1327
1328         if (port == -1 || port >= nr_active_ports)
1329                 port = 0;
1330         bfin_serial_init_ports();
1331         bfin_early_serial_console.index = port;
1332         uart = &bfin_serial_ports[port];
1333         t.c_cflag = cflag;
1334         t.c_iflag = 0;
1335         t.c_oflag = 0;
1336         t.c_lflag = ICANON;
1337         t.c_line = port;
1338         bfin_serial_set_termios(&uart->port, &t, &t);
1339         return &bfin_early_serial_console;
1340 }
1341
1342 #endif /* CONFIG_EARLY_PRINTK */
1343
1344 static struct uart_driver bfin_serial_reg = {
1345         .owner                  = THIS_MODULE,
1346         .driver_name            = "bfin-uart",
1347         .dev_name               = BFIN_SERIAL_NAME,
1348         .major                  = BFIN_SERIAL_MAJOR,
1349         .minor                  = BFIN_SERIAL_MINOR,
1350         .nr                     = BFIN_UART_NR_PORTS,
1351         .cons                   = BFIN_SERIAL_CONSOLE,
1352 };
1353
1354 static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1355 {
1356         int i;
1357
1358         for (i = 0; i < nr_active_ports; i++) {
1359                 if (bfin_serial_ports[i].port.dev != &dev->dev)
1360                         continue;
1361                 uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1362         }
1363
1364         return 0;
1365 }
1366
1367 static int bfin_serial_resume(struct platform_device *dev)
1368 {
1369         int i;
1370
1371         for (i = 0; i < nr_active_ports; i++) {
1372                 if (bfin_serial_ports[i].port.dev != &dev->dev)
1373                         continue;
1374                 uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1375         }
1376
1377         return 0;
1378 }
1379
1380 static int bfin_serial_probe(struct platform_device *dev)
1381 {
1382         struct resource *res = dev->resource;
1383         int i;
1384
1385         for (i = 0; i < dev->num_resources; i++, res++)
1386                 if (res->flags & IORESOURCE_MEM)
1387                         break;
1388
1389         if (i < dev->num_resources) {
1390                 for (i = 0; i < nr_active_ports; i++, res++) {
1391                         if (bfin_serial_ports[i].port.mapbase != res->start)
1392                                 continue;
1393                         bfin_serial_ports[i].port.dev = &dev->dev;
1394                         uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1395                 }
1396         }
1397
1398         return 0;
1399 }
1400
1401 static int bfin_serial_remove(struct platform_device *dev)
1402 {
1403         int i;
1404
1405         for (i = 0; i < nr_active_ports; i++) {
1406                 if (bfin_serial_ports[i].port.dev != &dev->dev)
1407                         continue;
1408                 uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1409                 bfin_serial_ports[i].port.dev = NULL;
1410 #if defined(CONFIG_SERIAL_BFIN_CTSRTS)
1411                 gpio_free(bfin_serial_ports[i].cts_pin);
1412                 gpio_free(bfin_serial_ports[i].rts_pin);
1413 #endif
1414         }
1415
1416         return 0;
1417 }
1418
1419 static struct platform_driver bfin_serial_driver = {
1420         .probe          = bfin_serial_probe,
1421         .remove         = bfin_serial_remove,
1422         .suspend        = bfin_serial_suspend,
1423         .resume         = bfin_serial_resume,
1424         .driver         = {
1425                 .name   = "bfin-uart",
1426                 .owner  = THIS_MODULE,
1427         },
1428 };
1429
1430 static int __init bfin_serial_init(void)
1431 {
1432         int ret;
1433
1434         pr_info("Serial: Blackfin serial driver\n");
1435
1436         bfin_serial_init_ports();
1437
1438         ret = uart_register_driver(&bfin_serial_reg);
1439         if (ret == 0) {
1440                 ret = platform_driver_register(&bfin_serial_driver);
1441                 if (ret) {
1442                         pr_debug("uart register failed\n");
1443                         uart_unregister_driver(&bfin_serial_reg);
1444                 }
1445         }
1446         return ret;
1447 }
1448
1449 static void __exit bfin_serial_exit(void)
1450 {
1451         platform_driver_unregister(&bfin_serial_driver);
1452         uart_unregister_driver(&bfin_serial_reg);
1453 }
1454
1455
1456 module_init(bfin_serial_init);
1457 module_exit(bfin_serial_exit);
1458
1459 MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1460 MODULE_DESCRIPTION("Blackfin generic serial port driver");
1461 MODULE_LICENSE("GPL");
1462 MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
1463 MODULE_ALIAS("platform:bfin-uart");