2 * drivers/serial/rk2818_serial.h
4 * Copyright (C) 2010 ROCKCHIP, Inc.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef __DRIVERS_SERIAL_RK2818_SERIAL_H
17 #define __DRIVERS_SERIAL_RK2818_SERIAL_H
19 #define UART_RBR 0x0000 /* Receive Buffer Register */
20 #define UART_THR 0x0000 /* Transmit Holding Register */
21 #define UART_DLL 0x0000 /* Divisor Latch (Low) */
22 #define UART_DLH 0x0004 /* Divisor Latch (High) */
23 #define UART_IER 0x0004 /* Interrupt Enable Register */
24 #define UART_IIR 0x0008 /* Interrupt Identification Register */
25 #define UART_FCR 0x0008 /* FIFO Control Register */
26 #define UART_LCR 0x000C /* Line Control Register */
27 #define UART_MCR 0x0010 /* Modem Control Register */
28 #define UART_LSR 0x0014 /* [0x0000_0060] Line Status Register */
29 #define UART_MSR 0x0018 /* Modem Status Register */
30 #define UART_SCR 0x001c /* Scratchpad Register */
31 #define UART_SRBR(n) (0x0030+((n) * 4)) /* Shadow Receive Buffer Register */
32 #define UART_STHR(n) (0x0030+((n) * 4)) /* Shadow Transmit Holding Register */
33 #define UART_FAR 0x0070 /* FIFO Access Register */
34 #define UART_TFR 0x0074 /* Transmit FIFO Read */
35 #define UART_RFW 0x0078 /* Receive FIFO Write */
36 #define UART_USR 0x007C /* UART Status Register */
37 #define UART_TFL 0x0080 /* Transmit FIFO Level */
38 #define UART_RFL 0x0084 /* Receive FIFO Level */
39 #define UART_SRR 0x0088 /* Software Reset Register */
40 #define UART_SRTS 0x008C /* Shadow Request to Send */
41 #define UART_SBCR 0x0090 /* Shadow Break Control Register */
42 #define UART_SDMAM 0x0094 /* Shadow DMA Mode */
43 #define UART_SFE 0x0098 /* Shadow FIFO Enable */
44 #define UART_SRT 0x009C /* Shadow RCVR Trigger */
45 #define UART_STET 0x00A0 /* Shadow TX Empty Trigger */
46 #define UART_HTX 0x00A4 /* Halt TX */
47 #define UART_DMASA 0x00A8 /* DMA Software Acknowledge */
48 #define UART_CPR 0x00F4 /* Component Parameter Register */
49 #define UART_UCV 0x00F8 /* [0x3330_372a] UART Component Version */
50 #define UART_CTR 0x00FC /* [0x4457_0110] Component Type Register */
52 //#define UART_FCR 0x08
53 #define UART_FCR_FIFO_ENABLE (1<<0)
54 #define UART_FCR_CLEAR_RCVR (1<<1) /* Clear the RCVR FIFO */
55 #define UART_FCR_CLEAR_XMIT (1<<2) /* Clear the XMIT FIFO */
56 #define UART_FCR_DMA_SELECT (1<<3) /* For DMA applications */
57 #define UART_FCR_R_TRIG_00 0x00
58 #define UART_FCR_R_TRIG_01 0x40
59 #define UART_FCR_R_TRIG_10 0x80
60 #define UART_FCR_R_TRIG_11 0xc0
61 #define UART_FCR_T_TRIG_00 0x00
62 #define UART_FCR_T_TRIG_01 0x10
63 #define UART_FCR_T_TRIG_10 0x20
64 #define UART_FCR_T_TRIG_11 0x30
66 //#define UART_LCR 0x0c
67 #define LCR_DLA_EN (1<<7)
68 #define BREAK_CONTROL_BIT (1<<6)
69 #define EVEN_PARITY_SELECT (1<<4)
70 #define EVEN_PARITY (1<<4)
71 #define ODD_PARITY (0)
72 #define PARITY_DISABLED (0)
73 #define PARITY_ENABLED (1<<3)
74 #define ONE_STOP_BIT (0)
75 #define ONE_HALF_OR_TWO_BIT (1<<2)
76 #define LCR_WLS_5 (0x00)
77 #define LCR_WLS_6 (0x01)
78 #define LCR_WLS_7 (0x02)
79 #define LCR_WLS_8 (0x03)
80 #define UART_DATABIT_MASK (0x03)
82 /* Detail UART_IER Register Description */
83 #define UART_IER_THRE_MODE_INT_ENABLE 1<<7
84 #define UART_IER_MODEM_STATUS_INT_ENABLE 1<<3
85 #define UART_IER_RECV_LINE_STATUS_INT_ENABLE 1<<2
86 #define UART_IER_SEND_EMPTY_INT_ENABLE 1<<1
87 #define UART_IER_RECV_DATA_AVAIL_INT_ENABLE 1<<0
90 /* Detail UART_IIR Register Description */
91 #define UART_IIR_FIFO_DISABLE 0x00
92 #define UART_IIR_FIFO_ENABLE 0x03
93 #define UART_IIR_INT_ID_MASK 0x0F
94 #define UART_IIR_MODEM_STATUS 0x00
95 #define UART_IIR_NO_INTERRUPT_PENDING 0x01
96 #define UART_IIR_THR_EMPTY 0x02
97 #define UART_IIR_RECV_AVAILABLE 0x04
98 #define UART_IIR_RECV_LINE_STATUS 0x06
99 #define UART_IIR_BUSY_DETECT 0x07
100 #define UART_IIR_CHAR_TIMEOUT 0x0C
102 //#define UART_MCR 0x10
103 /* Modem Control Register */
104 #define UART_SIR_ENABLE (1 << 6)
105 #define UART_MCR_AFCEN (1 << 5) /* Auto Flow Control Mode enabled */
106 #define UART_MCR_URLB (1 << 4) /* Loop-back mode */
107 #define UART_MCR_UROUT2 (1 << 3) /* OUT2 signal */
108 #define UART_MCR_UROUT1 (1 << 2) /* OUT1 signal */
109 #define UART_MCR_URRTS (1 << 1) /* Request to Send */
110 #define UART_MCR_URDTR (1 << 0) /* Data Terminal Ready */
112 //#define UART_MSR 0x18
113 /* Modem Status Register */
114 #define UART_MSR_URDCD (1 << 7) /* Data Carrier Detect */
115 #define UART_MSR_URRI (1 << 6) /* Ring Indicator */
116 #define UART_MSR_URDSR (1 << 5) /* Data Set Ready */
117 #define UART_MSR_URCTS (1 << 4) /* Clear to Send */
118 #define UART_MSR_URDDCD (1 << 3) /* Delta Data Carrier Detect */
119 #define UART_MSR_URTERI (1 << 2) /* Trailing Edge Ring Indicator */
120 #define UART_MSR_URDDST (1 << 1) /* Delta Data Set Ready */
121 #define UART_MSR_URDCTS (1 << 0) /* Delta Clear to Send */
123 /* Detail UART_USR Register Description */
124 #define UART_RECEIVE_FIFO_FULL (1<<4)
125 #define UART_RECEIVE_FIFO_NOT_FULL (0)
126 #define UART_RECEIVE_FIFO_EMPTY (0)
127 #define UART_RECEIVE_FIFO_NOT_EMPTY (1<<3)
128 #define UART_TRANSMIT_FIFO_NOT_EMPTY (0)
129 #define UART_TRANSMIT_FIFO_EMPTY (1<<2)
130 #define UART_TRANSMIT_FIFO_FULL (0)
131 #define UART_TRANSMIT_FIFO_NOT_FULL (1<<1)
132 #define UART_USR_BUSY (1)
134 /*UART_LSR Line Status Register*/
135 #define UART_BREAK_INT_BIT (1<<4)/*break Interrupt bit*/
137 #endif /* __DRIVERS_SERIAL_RK2818_SERIAL_H */