drivers/serial/rk29_serial.c

   1 /*
   2  * drivers/serial/rk29_serial.c - driver for rk29 serial device and console
   3  *
   4  * Copyright (C) 2010 ROCKCHIP, Inc.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16
  17 #if defined(CONFIG_SERIAL_RK29_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  18 #define SUPPORT_SYSRQ
  19 #endif
  20
  21 #include <linux/hrtimer.h>
  22 #include <linux/module.h>
  23 #include <linux/io.h>
  24 #include <linux/ioport.h>
  25 #include <linux/irq.h>
  26 #include <linux/init.h>
  27 #include <linux/console.h>
  28 #include <linux/tty.h>
  29 #include <linux/tty_flip.h>
  30 #include <linux/serial_core.h>
  31 #include <linux/serial.h>
  32 #include <linux/clk.h>
  33 #include <linux/platform_device.h>
  34 #include <mach/iomux.h>
  35 #include <mach/gpio.h>
  36 #include <mach/board.h>
  37 #include "rk2818_serial.h"
  38
  39 #define DBG_PORT    0
  40 #if 0
  41 #define DBG(msg...)     printk(msg);
  42 #else
  43 #define DBG(...)
  44 #endif
  45 /*
  46  * We wrap our port structure around the generic uart_port.
  47  */
  48 struct rk29_port {
  49         struct uart_port        uart;
  50         char                    name[16];
  51         struct clk              *clk;
  52         unsigned int            imr;
  53 };
  54
  55 #define UART_TO_RK29(uart_port) ((struct rk29_port *) uart_port)
  56 #define RK29_SERIAL_MAJOR        TTY_MAJOR
  57 #define RK29_SERIAL_MINOR        64
  58
  59
  60 static inline void rk29_uart_write(struct uart_port *port, unsigned int val,
  61                              unsigned int off)
  62 {
  63         __raw_writel(val, port->membase + off);
  64 }
  65
  66 static inline unsigned int rk29_uart_read(struct uart_port *port, unsigned int off)
  67 {
  68         return __raw_readl(port->membase + off);
  69 }
  70
  71 static int rk29_set_baud_rate(struct uart_port *port, unsigned int baud)
  72 {
  73         unsigned int uartTemp;
  74
  75         rk29_uart_write(port,rk29_uart_read(port,UART_LCR) | LCR_DLA_EN,UART_LCR);
  76     uartTemp = port->uartclk / (16 * baud);
  77     rk29_uart_write(port,uartTemp & 0xff,UART_DLL);
  78     rk29_uart_write(port,(uartTemp>>8) & 0xff,UART_DLH);
  79     rk29_uart_write(port,rk29_uart_read(port,UART_LCR) & (~LCR_DLA_EN),UART_LCR);
  80         return baud;
  81 }
  82
  83 /*
  84  * ÅÐ¶Ï·¢ËÍ»º³åÇøÊÇ·ñÎª¿Õ
  85  *ÏÈÒÔFIFO´ò¿ª×ö£¬ºóÃæ¿ÉÒÔ×ö³ÉFIFO¹Ø»òFIFO¿ª¡£
  86  */
  87 static u_int rk29_serial_tx_empty(struct uart_port *port)
  88 {
  89     int timeout = 10000000;
  90     while(!(rk29_uart_read(port,UART_USR)&UART_TRANSMIT_FIFO_EMPTY))
  91         if(timeout-- ==0)
  92             break;
  93         cpu_relax();
  94         if(rk29_uart_read(port,UART_USR)&UART_TRANSMIT_FIFO_EMPTY)
  95         {
  96         return (1);///1£º¿Õ
  97         }else{
  98         return (0);///0:·Ç¿Õ
  99         }
 100 }
 101
 102 /*
 103  * Power / Clock management.
 104  */
 105 static void rk29_serial_pm(struct uart_port *port, unsigned int state,
 106                             unsigned int oldstate)
 107 {
 108         struct rk29_port *rk29_port = UART_TO_RK29(port);
 109
 110         switch (state) {
 111         case 0:
 112                 /*
 113                  * Enable the peripheral clock for this serial port.
 114                  * This is called on uart_open() or a resume event.
 115                  */
 116                 clk_enable(rk29_port->clk);
 117                 break;
 118         case 3:
 119                 /*
 120                  * Disable the peripheral clock for this serial port.
 121                  * This is called on uart_close() or a suspend event.
 122                  */
 123                 clk_disable(rk29_port->clk);
 124                 break;
 125         default:
 126                 printk(KERN_ERR "rk29_serial: unknown pm %d\n", state);
 127         }
 128 }
 129
 130 /*
 131  * Return string describing the specified port
 132  */
 133 static const char *rk29_serial_type(struct uart_port *port)
 134 {
 135         return (port->type == PORT_RK29) ? "RK29_SERIAL" : NULL;
 136 }
 137
 138 static void rk29_serial_enable_ms(struct uart_port *port)
 139 {
 140   #ifdef DEBUG_LHH
 141   printk("Enter::%s\n",__FUNCTION__);
 142   #endif
 143 }
 144
 145 /* no modem control lines */
 146 static unsigned int rk29_serial_get_mctrl(struct uart_port *port)
 147 {
 148         unsigned int result = 0;
 149         unsigned int status;
 150
 151         status = rk29_uart_read(port,UART_MSR);
 152         if (status & UART_MSR_URCTS)
 153         {
 154                 result = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 155                 printk("UART_GET_MSR:0x%x\n",result);
 156         }else{
 157                 result = TIOCM_CAR | TIOCM_DSR;
 158                 printk("UART_GET_MSR:0x%x\n",result);
 159         }
 160         return result;
 161 }
 162
 163 static void rk29_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 164 {
 165         #ifdef DEBUG_LHH
 166         printk("Enter::%s\n",__FUNCTION__);
 167         #endif
 168 }
 169
 170 /*
 171  * Stop transmitting.
 172  */
 173 static void rk29_serial_stop_tx(struct uart_port *port)
 174 {
 175         #ifdef DEBUG_LHH
 176         printk("Enter::%s\n",__FUNCTION__);
 177         #endif
 178 }
 179
 180 /*
 181  * Start transmitting.
 182  */
 183 static void rk29_serial_start_tx(struct uart_port *port)
 184 {
 185         struct circ_buf *xmit = &port->state->xmit;
 186
 187     if(DBG_PORT == port->line) {
 188         DBG("TX:");
 189     }
 190
 191         while(!(uart_circ_empty(xmit)))
 192         {
 193                 while (!(rk29_uart_read(port,UART_USR) & UART_TRANSMIT_FIFO_NOT_FULL)){
 194             rk29_uart_write(port,UART_IER_RECV_DATA_AVAIL_INT_ENABLE|UART_IER_SEND_EMPTY_INT_ENABLE,UART_IER);
 195             return;
 196         }
 197         rk29_uart_write(port,xmit->buf[xmit->tail],UART_THR);
 198
 199         if(DBG_PORT == port->line) {
 200             DBG("0x%x, ", xmit->buf[xmit->tail]);
 201         }
 202
 203                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 204                 port->icount.tx++;
 205         }
 206         if((uart_circ_empty(xmit)))
 207                 rk29_uart_write(port,UART_IER_RECV_DATA_AVAIL_INT_ENABLE,UART_IER);
 208         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 209                 uart_write_wakeup(port);
 210
 211     if(DBG_PORT == port->line) {
 212         DBG("\n");
 213     }
 214 }
 215
 216 /*
 217  * Stop receiving - port is in process of being closed.
 218  */
 219 static void rk29_serial_stop_rx(struct uart_port *port)
 220 {
 221     #ifdef DEBUG_LHH
 222     printk("Enter::%s\n",__FUNCTION__);
 223     #endif
 224 }
 225
 226 /*
 227  * Control the transmission of a break signal
 228  */
 229 static void rk29_serial_break_ctl(struct uart_port *port, int break_state)
 230 {
 231     unsigned int temp;
 232     temp = rk29_uart_read(port,UART_LCR);
 233     if (break_state != 0)
 234         temp = temp & (~BREAK_CONTROL_BIT);/* start break */
 235         else
 236         temp = temp | BREAK_CONTROL_BIT; /* stop break */
 237     rk29_uart_write(port,temp,UART_LCR);
 238 }
 239
 240
 241 /*
 242  * Characters received (called from interrupt handler)
 243  */
 244 static void rk29_rx_chars(struct uart_port *port)
 245 {
 246         unsigned int ch, flag;
 247
 248     if(DBG_PORT == port->line) {
 249         DBG("RX:");
 250     }
 251
 252         while((rk29_uart_read(port,UART_USR) & UART_RECEIVE_FIFO_NOT_EMPTY) == UART_RECEIVE_FIFO_NOT_EMPTY)
 253         {
 254                 u32 lsr = rk29_uart_read(port, UART_LSR);
 255             ch = rk29_uart_read(port,UART_RBR);
 256             flag = TTY_NORMAL;
 257                 port->icount.rx++;
 258                 if (lsr & UART_BREAK_INT_BIT) {
 259                         port->icount.brk++;
 260                         if (uart_handle_break(port))
 261                                 continue;
 262                 }
 263 #if 1
 264                 if (uart_handle_sysrq_char(port, ch))
 265                 {
 266                         continue;
 267                 }
 268 #endif
 269                 uart_insert_char(port, 0, 0, ch, flag);
 270
 271         if(DBG_PORT == port->line) {
 272             DBG("0x%x, ", ch);
 273         }
 274         }
 275         tty_flip_buffer_push(port->state->port.tty);
 276
 277     if(DBG_PORT == port->line) {
 278         DBG("\n");
 279     }
 280 }
 281
 282 /*
 283  * Interrupt handler
 284  */
 285 static irqreturn_t rk29_uart_interrupt(int irq, void *dev_id)
 286 {
 287         struct uart_port *port = dev_id;
 288         unsigned int status, pending;
 289
 290         spin_lock(&port->lock);
 291         status = rk29_uart_read(port,UART_IIR);
 292         pending = status & 0x0f;
 293     if((pending == UART_IIR_RECV_AVAILABLE) || (pending == UART_IIR_CHAR_TIMEOUT))
 294                 rk29_rx_chars(port);
 295         if(pending == UART_IIR_THR_EMPTY)
 296                 rk29_serial_start_tx(port);
 297         spin_unlock(&port->lock);
 298         return IRQ_HANDLED;
 299 }
 300
 301 /*
 302  * Disable the port
 303  */
 304 static void rk29_serial_shutdown(struct uart_port *port)
 305 {
 306         struct rk29_port *rk29_port = UART_TO_RK29(port);
 307         rk29_uart_write(port,0x00,UART_IER);
 308         rk29_uart_write(port, UART_FCR_FIFO_ENABLE |
 309                 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, UART_FCR);
 310         //rk29_uart_write(port, 0, UART_FCR);
 311         clk_disable(rk29_port->clk);
 312         free_irq(port->irq, port);
 313 }
 314 /*
 315  * Perform initialization and enable port for reception
 316  */
 317 static int rk29_serial_startup(struct uart_port *port)
 318 {
 319         struct rk29_port *rk29_port = UART_TO_RK29(port);
 320         struct tty_struct *tty = port->state->port.tty;
 321         int retval;
 322         DBG("%s\n",__FUNCTION__);
 323
 324         if(2 == port->line)
 325         {
 326                 rk29_mux_api_set(GPIO2B1_UART2SOUT_NAME, GPIO2L_UART2_SOUT);
 327                 rk29_mux_api_set(GPIO2B0_UART2SIN_NAME, GPIO2L_UART2_SIN);
 328         }
 329         else if(0 == port->line)
 330         {
 331                 rk29_mux_api_set(GPIO1B7_UART0SOUT_NAME, GPIO1L_UART0_SOUT);
 332                 rk29_mux_api_set(GPIO1B6_UART0SIN_NAME, GPIO1L_UART0_SIN);
 333         }
 334         else if(3 == port->line)
 335         {
 336                 rk29_mux_api_set(GPIO2B3_UART3SOUT_NAME, GPIO2L_UART3_SOUT);
 337                 rk29_mux_api_set(GPIO2B2_UART3SIN_NAME, GPIO2L_UART3_SIN);
 338         }
 339
 340         retval = request_irq(port->irq,rk29_uart_interrupt,IRQF_SHARED,
 341                      tty ? tty->name : "rk29_serial",port);
 342         if(retval)
 343         {
 344                 printk("\nrk29_serial_startup err \n");
 345                 rk29_serial_shutdown(port);
 346                 return  retval;
 347         }
 348         clk_enable(rk29_port->clk);
 349 #if 0
 350         if(port->irq == IRQ_NR_UART0)
 351         rk29_uart_write(port,0xf7,UART_FCR);    //enable and clear fifo if busy while starting
 352         else
 353         rk29_uart_write(port,0xf1,UART_FCR);    //enable fifo
 354         rk29_uart_write(port,0x01,UART_SFE);
 355         rk29_uart_write(port,UART_IER_RECV_DATA_AVAIL_INT_ENABLE,UART_IER);  //enable uart recevice IRQ
 356 #else
 357         //lw modify on 110309
 358         /*
 359          * Clear the FIFO buffers and disable them.
 360          */
 361         rk29_uart_write(port, UART_FCR_FIFO_ENABLE, UART_FCR);
 362         rk29_uart_write(port, UART_FCR_FIFO_ENABLE |
 363                         UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, UART_FCR);
 364         rk29_uart_write(port, 0, UART_FCR);
 365
 366         /*
 367          * Clear the interrupt registers.
 368          */
 369         (void) rk29_uart_read(port, UART_LSR);
 370         (void) rk29_uart_read(port, UART_RBR);
 371         (void) rk29_uart_read(port, UART_IIR);
 372         (void) rk29_uart_read(port, UART_MSR);
 373
 374         /*
 375          * And clear the user registers.
 376          */
 377         (void) rk29_uart_read(port, UART_USR);
 378
 379 #endif
 380         return 0;
 381 }
 382
 383 /*
 384  * Change the port parameters
 385  */
 386 static void rk29_serial_set_termios(struct uart_port *port, struct ktermios *termios,
 387                               struct ktermios *old)
 388 {
 389     unsigned long flags;
 390     unsigned int mode, baud;
 391         unsigned int umcon,fcr;
 392         spin_lock_irqsave(&port->lock, flags);
 393     /* Get current mode register */
 394     mode = rk29_uart_read(port,UART_LCR) & (BREAK_CONTROL_BIT | EVEN_PARITY_SELECT | PARITY_ENABLED
 395                        | ONE_HALF_OR_TWO_BIT | UART_DATABIT_MASK);
 396
 397     baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
 398     /* byte size */
 399     switch (termios->c_cflag & CSIZE) {
 400     case CS5:
 401         mode |= LCR_WLS_5;
 402         break;
 403     case CS6:
 404         mode |= LCR_WLS_6;
 405         break;
 406     case CS7:
 407         mode |= LCR_WLS_7;
 408         break;
 409     default:
 410         mode |= LCR_WLS_8;
 411         break;
 412     }
 413
 414     /* stop bits */
 415     if (termios->c_cflag & CSTOPB)
 416         mode |= ONE_STOP_BIT;
 417
 418     /* parity */
 419     if (termios->c_cflag & PARENB)
 420     {
 421         mode |= PARITY_ENABLED;
 422         if (termios->c_cflag & PARODD)
 423             mode |= ODD_PARITY;
 424         else
 425             mode |= EVEN_PARITY;
 426     }
 427
 428         int timeout = 10000000;
 429         while(rk29_uart_read(port,UART_USR)&UART_USR_BUSY){
 430         if(timeout-- == 0){
 431         printk("rk29_serial_set_termios uart timeout,irq=%d,ret=0x%x\n",port->irq,rk29_uart_read(port,UART_USR));
 432         break;
 433         }
 434         cpu_relax();
 435         }
 436
 437         rk29_uart_write(port,mode,UART_LCR);
 438         baud = rk29_set_baud_rate(port, baud);
 439         uart_update_timeout(port, termios->c_cflag, baud);
 440
 441         /*
 442          * enable FIFO and interrupt
 443          */
 444         if(termios->c_cflag & CRTSCTS)
 445         {
 446                 /*¿ªÆôuart0Ó²¼þÁ÷¿Ø*/
 447                 printk("start CRTSCTS control and baudrate is %d,irq=%d\n",baud,port->irq);
 448                 if(2 == port->line)
 449                 {
 450                         rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N);
 451                         rk29_mux_api_set(GPIO2A6_UART2CTSN_NAME, GPIO2L_UART2_CTS_N);
 452                 }
 453                 else if(0 == port->line)
 454                 {
 455                         rk29_mux_api_set(GPIO1C1_UART0RTSN_SDMMC1WRITEPRT_NAME, GPIO1H_UART0_RTS_N);
 456                         rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_UART0_CTS_N);
 457                 }
 458                 else if(3 == port->line)
 459                 {
 460                         rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_UART3_RTS_N);
 461                         rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_UART3_CTS_N);
 462                 }
 463
 464                 umcon=rk29_uart_read(port,UART_MCR);
 465                 umcon |= UART_MCR_AFCEN;
 466                 umcon |= UART_MCR_URRTS;
 467                 umcon &=~UART_SIR_ENABLE;
 468                 rk29_uart_write(port,umcon,UART_MCR);
 469                 printk("UART_GET_MCR umcon=0x%x\n",umcon);
 470         }
 471         mode = mode | LCR_DLA_EN;
 472
 473 #if 1
 474         //lw modify on 110309
 475         fcr = UART_FCR_FIFO_ENABLE | UART_FCR_R_TRIG_10 | UART_FCR_T_TRIG_10;
 476         rk29_uart_write(port,  fcr,  UART_FCR);
 477         rk29_uart_write(port,0x01,UART_SFE);
 478         rk29_uart_write(port,UART_IER_RECV_DATA_AVAIL_INT_ENABLE,UART_IER);  //enable uart recevice IRQ
 479         printk("%s:fcr=0x%x,irq=%d\n",__FUNCTION__,fcr,port->irq);
 480 #endif
 481
 482         spin_unlock_irqrestore(&port->lock, flags);
 483
 484 }
 485
 486
 487 static void rk29_serial_release_port(struct uart_port *port)
 488 {
 489     struct platform_device *pdev = to_platform_device(port->dev);
 490         struct resource *resource;
 491         resource_size_t size;
 492
 493         resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 494         if (unlikely(!resource))
 495                 return;
 496         size = resource->end - resource->start + 1;
 497
 498         release_mem_region(port->mapbase, size);
 499         iounmap(port->membase);
 500         port->membase = NULL;
 501 }
 502
 503 static int rk29_serial_request_port(struct uart_port *port)
 504 {
 505         struct platform_device *pdev = to_platform_device(port->dev);
 506         struct resource *resource;
 507         resource_size_t size;
 508
 509         resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 510         if (unlikely(!resource))
 511                 return -ENXIO;
 512         size = resource->end - resource->start + 1;
 513
 514         if (unlikely(!request_mem_region(port->mapbase, size, "rk29_serial")))
 515                 return -EBUSY;
 516
 517         port->membase = ioremap(port->mapbase, size);
 518         if (!port->membase) {
 519                 release_mem_region(port->mapbase, size);
 520                 return -EBUSY;
 521         }
 522
 523         return 0;
 524 }
 525
 526 /*
 527  * Configure/autoconfigure the port.
 528  */
 529 static void rk29_serial_config_port(struct uart_port *port, int flags)
 530 {
 531         if (flags & UART_CONFIG_TYPE) {
 532                 port->type = PORT_RK29;
 533                 rk29_serial_request_port(port);
 534         }
 535 }
 536
 537 /*
 538  * Verify the new serial_struct (for TIOCSSERIAL).
 539  */
 540 static int rk29_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
 541 {
 542         int ret = 0;
 543         if (ser->type != PORT_UNKNOWN && ser->type != PORT_RK29)
 544                 ret = -EINVAL;
 545         if (port->irq != ser->irq)
 546                 ret = -EINVAL;
 547         if (ser->io_type != SERIAL_IO_MEM)
 548                 ret = -EINVAL;
 549         if (port->uartclk / 16 != ser->baud_base)
 550                 ret = -EINVAL;
 551         if ((void *)port->mapbase != ser->iomem_base)
 552                 ret = -EINVAL;
 553         if (port->iobase != ser->port)
 554                 ret = -EINVAL;
 555         if (ser->hub6 != 0)
 556                 ret = -EINVAL;
 557         return ret;
 558 }
 559
 560 #ifdef CONFIG_CONSOLE_POLL
 561 /*
 562  * Console polling routines for writing and reading from the uart while
 563  * in an interrupt or debug context.
 564  */
 565
 566 static int rk29_serial_poll_get_char(struct uart_port *port)
 567 {
 568         while (!((rk29_uart_read(port, UART_USR) & UART_RECEIVE_FIFO_NOT_EMPTY) == UART_RECEIVE_FIFO_NOT_EMPTY))
 569                 barrier();
 570         return rk29_uart_read(port, UART_RBR);
 571 }
 572
 573 static void rk29_serial_poll_put_char(struct uart_port *port, unsigned char c)
 574 {
 575         while (!(rk29_uart_read(port, UART_USR) & UART_TRANSMIT_FIFO_NOT_FULL))
 576                 barrier();
 577         rk29_uart_write(port, c, UART_THR);
 578 }
 579 #endif /* CONFIG_CONSOLE_POLL */
 580
 581 static struct uart_ops rk29_uart_pops = {
 582         .tx_empty = rk29_serial_tx_empty,
 583         .set_mctrl = rk29_serial_set_mctrl,
 584         .get_mctrl = rk29_serial_get_mctrl,
 585         .stop_tx = rk29_serial_stop_tx,
 586         .start_tx = rk29_serial_start_tx,
 587         .stop_rx = rk29_serial_stop_rx,
 588         .enable_ms = rk29_serial_enable_ms,
 589         .break_ctl = rk29_serial_break_ctl,
 590         .startup = rk29_serial_startup,
 591         .shutdown = rk29_serial_shutdown,
 592         .set_termios = rk29_serial_set_termios,
 593         .type = rk29_serial_type,
 594         .release_port = rk29_serial_release_port,
 595         .request_port = rk29_serial_request_port,
 596         .config_port = rk29_serial_config_port,
 597         .verify_port = rk29_serial_verify_port,
 598         .pm = rk29_serial_pm,
 599 #ifdef CONFIG_CONSOLE_POLL
 600         .poll_get_char = rk29_serial_poll_get_char,
 601         .poll_put_char = rk29_serial_poll_put_char,
 602 #endif
 603 };
 604
 605
 606 static struct rk29_port rk29_uart_ports[] = {
 607         {
 608                 .uart = {
 609                         .iotype = UPIO_MEM,
 610                         .ops = &rk29_uart_pops,
 611                         .flags = UPF_BOOT_AUTOCONF,
 612                         .fifosize = 32,
 613                         .line = 0,
 614                 },
 615         },
 616         {
 617                 .uart = {
 618                         .iotype = UPIO_MEM,
 619                         .ops = &rk29_uart_pops,
 620                         .flags = UPF_BOOT_AUTOCONF,
 621                         .fifosize = 32,
 622                         .line = 1,
 623                 },
 624         },
 625         {
 626                 .uart = {
 627                         .iotype = UPIO_MEM,
 628                         .ops = &rk29_uart_pops,
 629                         .flags = UPF_BOOT_AUTOCONF,
 630                         .fifosize = 32,
 631                         .line = 2,
 632                 },
 633         },
 634         {
 635                 .uart = {
 636                         .iotype = UPIO_MEM,
 637                         .ops = &rk29_uart_pops,
 638                         .flags = UPF_BOOT_AUTOCONF,
 639                         .fifosize = 32,
 640                         .line = 3,
 641                 },
 642         },
 643 };
 644
 645 #define UART_NR ARRAY_SIZE(rk29_uart_ports)
 646
 647 static inline struct uart_port *get_port_from_line(unsigned int line)
 648 {
 649         return &rk29_uart_ports[line].uart;
 650 }
 651
 652 #ifdef CONFIG_SERIAL_RK29_CONSOLE
 653 static void rk29_console_putchar(struct uart_port *port, int ch)
 654 {
 655     while (!(rk29_uart_read(port,UART_USR) & UART_TRANSMIT_FIFO_NOT_FULL))
 656                 cpu_relax();
 657         rk29_uart_write(port,ch,UART_THR);
 658 }
 659
 660 /*
 661  * Interrupts are disabled on entering
 662  */
 663 static void rk29_console_write(struct console *co, const char *s, u_int count)
 664 {
 665         struct uart_port *port;
 666         struct rk29_port *rk29_port;
 667
 668         BUG_ON(co->index < 0 || co->index >= UART_NR);
 669
 670         port = get_port_from_line(co->index);
 671         rk29_port = UART_TO_RK29(port);
 672
 673         spin_lock(&port->lock);
 674         uart_console_write(port, s, count, rk29_console_putchar);
 675         spin_unlock(&port->lock);
 676 }
 677
 678 static int __init rk29_console_setup(struct console *co, char *options)
 679 {
 680         struct uart_port *port;
 681         int baud, flow, bits, parity;
 682
 683         if (unlikely(co->index >= UART_NR || co->index < 0))
 684                 return -ENXIO;
 685
 686         port = get_port_from_line(co->index);
 687
 688         if (unlikely(!port->membase))
 689                 return -ENXIO;
 690
 691         port->cons = co;
 692
 693         //rk29_init_clock(port);
 694
 695         if (options)
 696                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 697
 698         bits = 8;
 699         parity = 'n';
 700         flow = 'n';
 701         rk29_uart_write(port,rk29_uart_read(port,UART_LCR) | LCR_WLS_8 | PARITY_DISABLED | ONE_STOP_BIT,UART_LCR);      /* 8N1 */
 702         if (baud < 300 || baud > 115200)
 703                 baud = 115200;
 704         rk29_set_baud_rate(port, baud);
 705
 706         printk(KERN_INFO "rk29_serial: console setup on port %d\n", port->line);
 707
 708         /* clear rx fifo, else will blocked on set_termios (always busy) */
 709         while ((rk29_uart_read(port, UART_USR) & UART_RECEIVE_FIFO_NOT_EMPTY) == UART_RECEIVE_FIFO_NOT_EMPTY)
 710                 rk29_uart_read(port, UART_RBR);
 711
 712         return uart_set_options(port, co, baud, parity, bits, flow);
 713 }
 714
 715 static struct uart_driver rk29_uart_driver;
 716
 717 static struct console rk29_console = {
 718         .name = "ttyS",
 719         .write = rk29_console_write,
 720         .device = uart_console_device,
 721         .setup = rk29_console_setup,
 722         .flags = CON_PRINTBUFFER,
 723         .index = 1,
 724         .data = &rk29_uart_driver,
 725 };
 726
 727 #define RK29_CONSOLE    (&rk29_console)
 728
 729 #else
 730 #define RK29_CONSOLE    NULL
 731 #endif
 732
 733 static struct uart_driver rk29_uart_driver = {
 734         .owner = THIS_MODULE,
 735         .driver_name = "rk29_serial",
 736         .dev_name = "ttyS",
 737         .nr = UART_NR,
 738         .cons = RK29_CONSOLE,
 739         .major          = RK29_SERIAL_MAJOR,
 740         .minor          = RK29_SERIAL_MINOR,
 741 };
 742
 743 static int __devinit rk29_serial_probe(struct platform_device *pdev)
 744 {
 745         struct rk29_port *rk29_port;
 746         struct resource *resource;
 747         struct uart_port *port;
 748     //struct rk29_serial_platform_data *pdata = pdev->dev.platform_data;
 749
 750         if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
 751                 return -ENXIO;
 752
 753         printk(KERN_INFO "rk29_serial: detected port %d\n", pdev->id);
 754
 755         //if (pdata && pdata->io_init)
 756                 //pdata->io_init();
 757
 758         port = get_port_from_line(pdev->id);
 759         port->dev = &pdev->dev;
 760         rk29_port = UART_TO_RK29(port);
 761
 762         rk29_port->clk = clk_get(&pdev->dev, "uart");
 763         if (unlikely(IS_ERR(rk29_port->clk)))
 764                 return PTR_ERR(rk29_port->clk);
 765         port->uartclk = 24000000; ///clk_get_rate(rk29_port->clk);
 766
 767         resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 768         if (unlikely(!resource))
 769                 return -ENXIO;
 770         port->mapbase = resource->start;
 771
 772         port->irq = platform_get_irq(pdev, 0);
 773         if (unlikely(port->irq < 0))
 774                 return -ENXIO;
 775
 776         platform_set_drvdata(pdev, port);
 777
 778         return uart_add_one_port(&rk29_uart_driver, port);
 779 }
 780
 781 static int __devexit rk29_serial_remove(struct platform_device *pdev)
 782 {
 783         struct rk29_port *rk29_port = platform_get_drvdata(pdev);
 784
 785         clk_put(rk29_port->clk);
 786
 787         return 0;
 788 }
 789
 790 static struct platform_driver rk29_platform_driver = {
 791         .remove = rk29_serial_remove,
 792         .driver = {
 793                 .name = "rk29_serial",
 794                 .owner = THIS_MODULE,
 795         },
 796 };
 797
 798 static int __init rk29_serial_init(void)
 799 {
 800         int ret;
 801         ret = uart_register_driver(&rk29_uart_driver);
 802         if (unlikely(ret))
 803                 return ret;
 804
 805         ret = platform_driver_probe(&rk29_platform_driver, rk29_serial_probe);
 806         if (unlikely(ret))
 807                 uart_unregister_driver(&rk29_uart_driver);
 808
 809         printk(KERN_INFO "rk29_serial: driver initialized\n");
 810
 811         return ret;
 812 }
 813
 814 static void __exit rk29_serial_exit(void)
 815 {
 816         #ifdef CONFIG_SERIAL_RK29_CONSOLE
 817         unregister_console(&rk29_console);
 818         #endif
 819         platform_driver_unregister(&rk29_platform_driver);
 820         uart_unregister_driver(&rk29_uart_driver);
 821 }
 822
 823 /*
 824  * While this can be a module, if builtin it's most likely the console
 825  * So let's leave module_exit but move module_init to an earlier place
 826  */
 827 arch_initcall(rk29_serial_init);
 828 module_exit(rk29_serial_exit);
 829
 830 MODULE_AUTHOR("lhh lhh@rock-chips.com");
 831 MODULE_DESCRIPTION("Rockchip rk29 Serial port driver");
 832 MODULE_LICENSE("GPL");
 833
 834