1 #include <linux/module.h>
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2 #include <linux/kernel.h>
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3 #include <linux/errno.h>
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4 #include <linux/string.h>
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5 #include <linux/mm.h>
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6 #include <linux/slab.h>
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7 #include <linux/delay.h>
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8 #include <linux/device.h>
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9 #include <linux/init.h>
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10 #include <linux/dma-mapping.h>
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11 #include <linux/interrupt.h>
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12 #include <linux/platform_device.h>
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13 #include <linux/clk.h>
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14 #include <linux/backlight.h>
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15 #include <linux/timer.h>
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16 #include <linux/time.h>
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17 #include <linux/wait.h>
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18 #include <linux/earlysuspend.h>
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19 #include <linux/cpufreq.h>
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20 #include <linux/wakelock.h>
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23 #include <asm/div64.h>
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24 #include <asm/uaccess.h>
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27 #include <mach/iomux.h>
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28 #include <mach/gpio.h>
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29 #include <mach/board.h>
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30 #include <mach/rk29_iomap.h>
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31 #include <mach/pmu.h>
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33 void __iomem *rank0_vir_base; // virtual basic address of lcdc register
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34 struct clk *smc_clk = NULL;
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35 struct clk *smc_axi_clk = NULL;
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36 void __iomem *reg_vir_base; // virtual basic address of lcdc register
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38 int smc0_enable(int enable)
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41 clk_enable(smc_axi_clk);
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42 clk_enable(smc_clk);
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43 __raw_writel(__raw_readl(RK29_GRF_BASE+0xbc) | 0x2000 , (RK29_GRF_BASE+0xbc));
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45 __raw_writel((0x801), (reg_vir_base+0x18));
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46 __raw_writel(0x00400000, (reg_vir_base+0x10));
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47 __raw_writel((15 | (14<<8) | (15<<4) | (5<<11) ), (reg_vir_base+0x14));
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48 //__raw_writel((15 | (10<<8) | (15<<4) | (7<<11) ), (reg_vir_base+0x14));
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50 __raw_writel(0x00400000, (reg_vir_base+0x10));
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52 clk_disable(smc_axi_clk);
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53 clk_disable(smc_clk);
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58 int smc0_init(u8 **base_addr)
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60 u32 reg_phy_base; // physical basic address of lcdc register
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61 u32 len; // physical map length of lcdc register
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62 struct resource *mem;
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64 u32 rank0_phy_base; // physical basic address of lcdc register
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65 u32 rank0_len; // physical map length of lcdc register
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66 struct resource *rank0_mem;
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68 printk(" %s %d \n",__FUNCTION__, __LINE__);
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70 if(smc_axi_clk == NULL)smc_axi_clk = clk_get(NULL, "aclk_smc");
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71 if(smc_clk == NULL)smc_clk = clk_get(NULL, "smc");
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73 rank0_phy_base = 0x11000000; //0x12000000;//
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75 rank0_mem = request_mem_region(rank0_phy_base, rank0_len, "smc_rank0");
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76 if (rank0_mem == NULL)
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78 printk("failed to get rank0 memory region [%d]\n",__LINE__);
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81 rank0_vir_base = ioremap(rank0_phy_base, rank0_len);
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82 if (rank0_vir_base == NULL)
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84 printk("ioremap() of rank0 failed\n");
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87 //*base_addr = rank0_vir_base;
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89 reg_phy_base = RK29_SMC_PHYS;
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91 mem = request_mem_region(reg_phy_base, len, "smc reg");
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94 printk("failed to get memory region [%d]\n",__LINE__);
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97 reg_vir_base = ioremap(reg_phy_base, len);
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98 if (reg_vir_base == NULL)
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100 printk("ioremap() of registers failed\n");
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105 rk29_mux_api_set(GPIO0B7_EBCGDOE_SMCOEN_NAME, GPIO0L_SMC_OE_N);
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106 rk29_mux_api_set(GPIO0B6_EBCSDSHR_SMCBLSN1_HOSTINT_NAME, GPIO0L_SMC_BLS_N_1 );
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107 rk29_mux_api_set(GPIO0B5_EBCVCOM_SMCBLSN0_NAME, GPIO0L_SMC_BLS_N_0 );
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108 rk29_mux_api_set(GPIO0B4_EBCBORDER1_SMCWEN_NAME, GPIO0L_SMC_WE_N);
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110 rk29_mux_api_set(GPIO0B3_EBCBORDER0_SMCADDR3_HOSTDATA3_NAME, GPIO0L_SMC_ADDR3);
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111 rk29_mux_api_set(GPIO0B2_EBCSDCE2_SMCADDR2_HOSTDATA2_NAME, GPIO0L_SMC_ADDR2);
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112 rk29_mux_api_set(GPIO0B1_EBCSDCE1_SMCADDR1_HOSTDATA1_NAME, GPIO0L_SMC_ADDR1);
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113 rk29_mux_api_set(GPIO0B0_EBCSDCE0_SMCADDR0_HOSTDATA0_NAME, GPIO0L_SMC_ADDR0);
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115 rk29_mux_api_set(GPIO1A1_SMCCSN0_NAME, GPIO1L_SMC_CSN0);
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116 // rk29_mux_api_set(GPIO1A1_SMCCSN0_NAME, GPIO1L_GPIO1A1);
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118 // if(gpio_request(RK29_PIN1_PA1, NULL) != 0)
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120 // gpio_free(RK29_PIN1_PA1);
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121 // printk(">>>>>> RK29_PIN1_PA1 gpio_request err \n ");
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123 // gpio_direction_output(RK29_PIN1_PA1, GPIO_LOW);
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125 rk29_mux_api_set(GPIO1A2_SMCCSN1_NAME, GPIO1L_SMC_CSN1);
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126 rk29_mux_api_set(GPIO0D0_EBCSDOE_SMCADVN_NAME, GPIO0H_SMC_ADV_N);
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128 rk29_mux_api_set(GPIO5C0_EBCSDDO0_SMCDATA0_NAME, GPIO5H_SMC_DATA0);
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129 rk29_mux_api_set(GPIO5C1_EBCSDDO1_SMCDATA1_NAME, GPIO5H_SMC_DATA1);
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130 rk29_mux_api_set(GPIO5C2_EBCSDDO2_SMCDATA2_NAME, GPIO5H_SMC_DATA2);
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131 rk29_mux_api_set(GPIO5C3_EBCSDDO3_SMCDATA3_NAME, GPIO5H_SMC_DATA3);
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132 rk29_mux_api_set(GPIO5C4_EBCSDDO4_SMCDATA4_NAME, GPIO5H_SMC_DATA4);
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133 rk29_mux_api_set(GPIO5C5_EBCSDDO5_SMCDATA5_NAME, GPIO5H_SMC_DATA5);
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134 rk29_mux_api_set(GPIO5C6_EBCSDDO6_SMCDATA6_NAME, GPIO5H_SMC_DATA6);
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135 rk29_mux_api_set(GPIO5C7_EBCSDDO7_SMCDATA7_NAME, GPIO5H_SMC_DATA7);
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137 rk29_mux_api_set(GPIO0C0_EBCGDSP_SMCDATA8_NAME, GPIO0H_SMC_DATA8);
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138 rk29_mux_api_set(GPIO0C1_EBCGDR1_SMCDATA9_NAME, GPIO0H_SMC_DATA9);
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139 rk29_mux_api_set(GPIO0C2_EBCSDCE0_SMCDATA10_NAME, GPIO0H_SMC_DATA10);
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140 rk29_mux_api_set(GPIO0C3_EBCSDCE1_SMCDATA11_NAME, GPIO0H_SMC_DATA11);
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141 rk29_mux_api_set(GPIO0C4_EBCSDCE2_SMCDATA12_NAME, GPIO0H_SMC_DATA12);
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142 rk29_mux_api_set(GPIO0C5_EBCSDCE3_SMCDATA13_NAME, GPIO0H_SMC_DATA13);
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143 rk29_mux_api_set(GPIO0C6_EBCSDCE4_SMCDATA14_NAME, GPIO0H_SMC_DATA14);
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144 rk29_mux_api_set(GPIO0C7_EBCSDCE5_SMCDATA15_NAME, GPIO0H_SMC_DATA15);
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152 int smc0_write(u32 addr, u16 data)
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154 // __raw_writel(data, rank0_vir_base + addr);
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155 u16 *p = rank0_vir_base + addr;
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162 //printk("%s addr=%x, data = %x, read date = %x\n",__FUNCTION__,addr,data,readdata);
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166 int smc0_read(u32 addr)
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168 u16 * p = rank0_vir_base + addr;
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169 int readdata = *p;
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171 //printk("%s addr=%x, read date = %x\n",__FUNCTION__,addr,readdata);
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172 return readdata;//__raw_readl(rank0_vir_base + addr);
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175 void smc0_exit(void)
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